Light-emitting device
The semiconductor structure with specific wiring and insulating layer configurations addresses uneven light emission intensity in light emitting elements, achieving uniform light distribution and enhanced efficiency.
Patent Information
- Application Number
- JP2024042151
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-03-18
- Publication Date
- 2025-10-01
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Figure 2025142663000001_ABST
Abstract
Description
[Technical Field]
[0001] The present disclosure relates to light-emitting devices. [Background technology]
[0002] A light emitting device has been proposed in which two active regions connected in series to each other are provided on one substrate (see Patent Document 1). [Prior art documents] [Patent documents]
[0003] [Patent Document 1] Special Publication No. 2015-533022 Summary of the Invention [Problem to be solved by the invention]
[0004] Conventional light emitting elements are prone to uneven distribution of light emission intensity.
[0005] An object of the present disclosure is to provide a light-emitting element that can reduce bias in the emission intensity distribution. [Means for solving the problem]
[0006] According to one aspect of the disclosed technique, a light-emitting element is a semiconductor structure including a conductive substrate, a conductive member disposed on the substrate, a first insulating layer disposed on the conductive member, and a first light-emitting portion and a second light-emitting portion disposed apart from each other on the first insulating layer, wherein each of the first light-emitting portion and the second light-emitting portion has a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer; a first wiring electrically connected to the first semiconductor layer of the first light-emitting portion; a layer, a second wiring electrically connected to the first semiconductor layer of the second light-emitting portion, a third wiring electrically connected to the second semiconductor layer of the second light-emitting portion, and a pad electrode disposed above the substrate and spaced apart from the semiconductor structure in a planar view and electrically connected to the first wiring, wherein the second light-emitting portion is surrounded by the first light-emitting portion in a planar view, the first insulating layer has a first opening overlapping the second light-emitting portion in a planar view, the third wiring is in contact with the conductive member through the first opening, and the first wiring and the second wiring are not in contact with the conductive member. [Effects of the Invention]
[0007] According to the present disclosure, it is possible to provide a light-emitting element capable of reducing bias in the emission intensity distribution. [Brief explanation of the drawings]
[0008] [Figure 1] FIG. 2 is a top view showing some of the components of the light-emitting device according to the embodiment. [Figure 2] 1 is a cross-sectional view showing a light-emitting element according to an embodiment. [Figure 3] FIG. 10 is a cross-sectional view showing a light-emitting element according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION
[0009] Hereinafter, embodiments for carrying out the present disclosure will be described with reference to the drawings. The following description is intended to embody the technical idea of the present disclosure, and unless otherwise specified, the present disclosure is not limited to the following description.
[0010] In each drawing, components having the same function may be designated by the same reference numeral. For convenience, the embodiments may be shown separately to facilitate explanation or understanding of key points. However, partial substitution or combination of configurations shown in different embodiments or examples is possible. In the embodiments shown later, differences from the previously shown embodiments will be mainly described, and overlapping descriptions of commonalities with the previously shown embodiments may be omitted. The size and positional relationships of components shown in each drawing may be exaggerated for clarity. To avoid overly complex drawings, some elements may be omitted, or end views showing only the cut surface may be used as cross-sectional views. Furthermore, from an arbitrary point, the +Z side may be referred to as the upper side, upper side, or top, and the -Z side may be referred to as the lower side, lower side, or bottom. Viewing in a direction along the Z direction is referred to as a "planar view."
[0011] The embodiment relates to a light-emitting device. Fig. 1 is a top view showing some of the components of the light-emitting device according to the embodiment. Fig. 2 is a cross-sectional view showing the light-emitting device according to the embodiment. Fig. 2 corresponds to a cross-sectional view taken along line II-II in Fig. 1.
[0012] The light-emitting element 1 of the embodiment has a substrate 10, a conductive member 20, a first insulating layer 30, a second insulating layer 40, a third insulating layer 50, a pad electrode 61, light-reflective conductive layers 71 and 72, a semiconductor structure 100, a first wiring 210, a second wiring 220, and a third wiring 230.
[0013] The substrate 10 is conductive. The shape of the substrate 10 in a plan view is square. When the shape of the substrate 10 in a plan view is square, the length of one side of the substrate 10 is, for example, 500 μm or more and 3000 μm or less. In a plan view, the substrate 10 has vertices 11, 12, 13, and 14. The vertex 11 is a vertex on the −X side and −Y side of the center of the substrate 10. The vertex 12 is a vertex on the +X side and −Y side of the center of the substrate 10. The vertex 13 is a vertex on the +X side and +Y side of the center of the substrate 10. The vertex 14 is a vertex on the −X side and +Y side of the center of the substrate 10. The substrate 10 can be, for example, a conductive silicon substrate. The thickness of the substrate 10 is, for example, 100 μm or more and 1000 μm or less.
[0014] As shown in FIG. 2, the conductive member 20 is disposed on the substrate 10. The conductive member 20 includes a metal layer such as solder. The thickness of the conductive member 20 is, for example, 3 μm or more and 10 μm or less. The substrate 10 and the conductive member 20 are electrically connected to each other. The first insulating layer 30 is disposed on the conductive member 20. The first insulating layer 30 is, for example, a layer including at least one of silicon oxide, silicon nitride, and silicon oxynitride. The first wiring 210, the second wiring 220, and the third wiring 230 are disposed on the first insulating layer 30. The thickness of the first insulating layer 30 is, for example, 0.1 μm or more and 2 μm or less.
[0015] As shown in FIG. 1, the first wiring 210 is arranged along the outer edge of the substrate 10. The outer shape of the first wiring 210 in a plan view is substantially rectangular. The first wiring 210 has an opening 211 that is substantially rectangular in a plan view. The first wiring 210 has a connection portion 215 near the vertex 11. A pad electrode 61 is connected to the connection portion 215.
[0016] As shown in FIG. 1, in a plan view, the second wiring 220 is arranged inside the opening 211 of the first wiring 210. In a plan view, the outer shape of the second wiring 220 is a rectangular shape in which the corners corresponding to the portions where the pad electrodes 61 are arranged are curved toward the center of the substrate 10. The second wiring 220 has an opening 221. The second wiring 220 may have a plurality of openings 221. The opening 221 has a circular shape in a plan view.
[0017] 1, in plan view, the third wiring 230 is disposed inside the opening 221 of the second wiring 220. The third wiring 230 has a circular shape in plan view.
[0018] The first wiring 210, the second wiring 220, and the third wiring 230 are made of metal. For example, Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, Ru, W, or other simple metals, or alloys containing these metals as their main components, can be suitably used for the first wiring 210, the second wiring 220, and the third wiring 230. The first wiring 210, the second wiring 220, and the third wiring 230 are made of, for example, an Al alloy. The first wiring 210, the second wiring 220, and the third wiring 230 may have a single-layer structure consisting of one of these metal layers, or may have a multilayer structure consisting of multiple layers stacked together. The thickness of the first wiring 210, the second wiring 220, and the third wiring 230 is, for example, 0.3 μm or more and 3 μm or less.
[0019] As shown in FIG. 2, the second insulating layer 40 is disposed on the first insulating layer 30 so as to cover the first wiring 210, the second wiring 220, and the third wiring 230. The second insulating layer 40 is, for example, a layer containing at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second insulating layer 40 has an opening 41, a plurality of openings 42 as second openings, an opening 43, and a plurality of openings 44. The openings 41, 42, 43, and 44 penetrate the second insulating layer 40. The thickness of the second insulating layer 40 is, for example, not less than 0.1 μm and not more than 2 μm.
[0020] As shown in FIGS. 1 and 2 , the opening 41 is disposed inside the outer edge of the first wiring 210 in a plan view. The opening 42 is disposed inside the outer edge of the second wiring 220 in a plan view. The opening 42 has a circular shape in a plan view. When the opening 42 has a circular shape in a plan view, the diameter of the opening 42 is 2 μm or more and 20 μm or less. The multiple openings 42 are disposed along the outer edge of the substrate 10 in a plan view. The opening 43 is disposed inside the outer edge of the second wiring 220, away from the opening 42 in a plan view. The opening 44 is disposed inside the outer edge of the third wiring 230 in a plan view. The opening 44 has a circular shape in a plan view. When the opening 44 has a circular shape in a plan view, the diameter of the opening 44 is 2 μm or more and 20 μm or less.
[0021] As shown in FIG. 2 , the light-reflective conductive layer 71 is disposed on the second insulating layer 40, away from the opening 42 in a cross-sectional view, and overlaps with a portion of the first wiring 210 and a portion of the second wiring 220. The light-reflective conductive layer 71 is electrically connected to the first wiring 210 through the opening 41. The light-reflective conductive layer 71 has a plurality of openings 71a in a plan view. In a plan view, the opening 42 is disposed inside the opening 71a of the light-reflective conductive layer 71. The opening 71a of the light-reflective conductive layer 71 has a circular shape in a plan view. The light-reflective conductive layer 72 is disposed on the second insulating layer 40, away from the opening 44 in a cross-sectional view, and overlaps with a portion of the second wiring 220 and a portion of the third wiring 230. The light-reflective conductive layer 72 is electrically connected to the second wiring 220 through the opening 43. The light-reflective conductive layer 72 has a plurality of openings 72a in a plan view. In plan view, the opening 42 is disposed inside the opening 72a of the light-reflective conductive layer 72. The opening 72a of the light-reflective conductive layer 72 has a circular shape in plan view. The light-reflective conductive layers 71 and 72 are made of a metal. For example, a single metal such as Ag, Al, Ni, Ti, Pt, Ta, Ru, or Au, or an alloy containing these metals as a main component, can be suitably used for the light-reflective conductive layers 71 and 72. The light-reflective conductive layers 71 and 72 may have a single-layer structure consisting of one of these metal layers, or a multilayer structure consisting of multiple layers. The thickness of the light-reflective conductive layer 71 is, for example, 0.05 μm or more and 1 μm or less.
[0022] As shown in FIG. 2, the semiconductor structure 100 is disposed on the second insulating layer 40 and the light-reflective conductive layers 71 and 72. The semiconductor structure 100 includes a first light-emitting section 110 and a second light-emitting section 120. The first light-emitting section 110 has a substantially rectangular shape in a plan view with an opening 119. The first light-emitting section 110 is disposed along the outer edge of the substrate 10 in a plan view. In a plan view, the second light-emitting section 120 is disposed inside the opening 119 of the first light-emitting section 110 and is surrounded by the first light-emitting section 110 in a plan view. The thickness of the semiconductor structure 100 is, for example, 1 μm or more and 10 μm or less.
[0023] The first light-emitting section 110 has a p-type semiconductor layer 111 as a first semiconductor layer, an n-type semiconductor layer 112 as a second semiconductor layer, and a light-emitting layer 113. The light-emitting layer 113 is disposed between the p-type semiconductor layer 111 and the n-type semiconductor layer 112. The p-type semiconductor layer 111 is disposed on the light-reflective conductive layer 71 and the second insulating layer 40, away from the opening 42 in a planar view, and the light-emitting layer 113 is disposed on the p-type semiconductor layer 111. The light-reflective conductive layer 71 and the p-type semiconductor layer 111 are electrically connected. The n-type semiconductor layer 112 is disposed on the second wiring 220, the light-emitting layer 113, and the second insulating layer 40. The outer shape of the n-type semiconductor layer 112 is approximately rectangular in a planar view. The n-type semiconductor layer 112 has an opening that is approximately rectangular in a planar view. The n-type semiconductor layer 112 is disposed along the outer edge of the substrate 10 in a planar view. The upper surface of n-type semiconductor layer 112, which is located on the opposite side to light emitting layer 113, has a plurality of protrusions. The protrusions of n-type semiconductor layer 112 are arranged in portions that overlap light emitting layer 113 in a plan view. The shape of the protrusions of n-type semiconductor layer 112 in a cross-sectional view is, for example, triangular.
[0024] The second light-emitting section 120 has a p-type semiconductor layer 121 as a first semiconductor layer, an n-type semiconductor layer 122 as a second semiconductor layer, and a light-emitting layer 123. The light-emitting layer 123 is disposed between the p-type semiconductor layer 121 and the n-type semiconductor layer 122. The p-type semiconductor layer 121 is disposed on the light-reflective conductive layer 72 and the second insulating layer 40, away from the opening 44 in a planar view, and the light-emitting layer 123 is disposed on the p-type semiconductor layer 121. The light-reflective conductive layer 72 and the p-type semiconductor layer 121 are electrically connected. The n-type semiconductor layer 122 is disposed on the third wiring 230, the light-emitting layer 123, and the second insulating layer 40. The n-type semiconductor layer 122 is disposed inside the opening of the n-type semiconductor layer 112 and is surrounded by the n-type semiconductor layer 112 in a planar view. The upper surface of the n-type semiconductor layer 122, located on the opposite side to the light-emitting layer 123, has multiple protrusions. The convex portion of n-type semiconductor layer 122 is disposed in a portion that overlaps with light emitting layer 123 in a plan view. The convex portion of n-type semiconductor layer 122 has, for example, a triangular shape in a cross-sectional view.
[0025] The first light-emitting section 110 and the second light-emitting section 120 are arranged apart from each other. The first light-emitting section 110 and the second light-emitting section 120 are electrically connected by conductive members such as a first wiring 210, a second wiring 220, and a third wiring 230.
[0026] The material of the p-type semiconductor layers 111 and 121, the material of the n-type semiconductor layers 112 and 122, and the material of the light emitting layers 113 and 123 can be, for example, a nitride semiconductor. X Al Y Ga 1-X-Y The term "nitride semiconductor" includes semiconductors of all compositions in which the composition ratios x and y in the chemical formula represented by N (0≦X, 0≦Y, X+Y<1) are varied within their respective ranges. Furthermore, the term "nitride semiconductor" also includes semiconductors in the above chemical formula that further contain a Group V element other than N (nitrogen), and semiconductors that further contain various elements added to control various physical properties such as conductivity type. The p-type semiconductor layers 111 and 121, the n-type semiconductor layers 112 and 122, and the light-emitting layers 113 and 123 may each have a single-layer structure or a stacked structure having multiple semiconductor layers with different semiconductor compositions and film thicknesses. In particular, the light-emitting layers 113 and 123 preferably have a single quantum well or multiple quantum well structure in which thin semiconductor layers that generate quantum effects are stacked. The n-type semiconductor layers 112 and 122 have a semiconductor layer containing n-type impurities. Examples of n-type impurities include Si, Ge, and the like. The p-type semiconductor layers 111 and 121 have a semiconductor layer containing p-type impurities. Examples of p-type impurities include Mg, Zn, and the like. The peak wavelength of the light emitted by light-emitting layer 113 is the same as the peak wavelength of the light emitted by light-emitting layer 123. The peak wavelength of the light emitted by light-emitting layers 113 and 123 is, for example, 210 nm or more and 580 nm or less. Note that the peak wavelength of the light emitted by light-emitting layer 113 may be different from the peak wavelength of the light emitted by light-emitting layer 123.
[0027] The first wiring 210 is electrically connected to the p-type semiconductor layer 111 of the first light emitting section 110 through the opening 41. The second wiring 220 is electrically connected to the n-type semiconductor layer 112 of the first light emitting section 110 through the opening 42, and is electrically connected to the p-type semiconductor layer 121 of the second light emitting section 120 through the opening 43. The third wiring 230 is electrically connected to the n-type semiconductor layer 122 of the second light emitting section 120 through the opening 44.
[0028] As shown in FIG. 2 , the third insulating layer 50 is disposed to cover the semiconductor structure 100 and the second insulating layer 40. The third insulating layer 50 is, for example, a layer containing at least one of silicon oxide, silicon nitride, and silicon oxynitride. The upper surfaces of the third insulating layer 50 that overlap the n-type semiconductor layers 112 and 122 have a shape that reflects the shape of the convex portions on the upper surfaces of the n-type semiconductor layers 112 and 122 in a cross-sectional view. The stack of the second insulating layer 40 and the third insulating layer 50 has an opening 51. The opening 51 penetrates the stack of the second insulating layer 40 and the third insulating layer 50. The opening 51 reaches the connection portion 215 of the first wiring 210. The thickness of the third insulating layer 50 is, for example, 0.01 μm or more and 2 μm or less.
[0029] The pad electrode 61 is disposed on the connection portion 215 inside the opening 51. The pad electrode 61 is electrically connected to the connection portion 215. That is, the pad electrode 61 is separated from the semiconductor structure 100 in a plan view and electrically connected to the first wiring 210. By disposing the pad electrode 61 separated from the semiconductor structure 100 in a plan view, absorption of light from the semiconductor structure 100 by the pad electrode 61 can be reduced. As shown in FIG. 1, only the pad electrode 61 functioning as an n-side pad electrode is disposed above the substrate 10, and no pad electrode functioning as a p-side pad electrode is disposed above the substrate 10, with the substrate 10 serving as the p-side electrode. This allows for a larger area of the light-emitting portion and easier acquisition of high light output compared to a case where an n-side pad electrode and a p-side pad electrode are disposed above the substrate 10. As shown in FIG. 2, the first insulating layer 30 is disposed between the connection portion 215 and the conductive member 20. That is, the first insulating layer 30 is disposed between the pad electrode 61 and the conductive member 20.
[0030] As shown in FIG. 2, the first insulating layer 30 has an opening 31 as a first opening. The opening 31 penetrates the first insulating layer 30. The opening 31 overlaps the second light-emitting section 120 in a planar view. The opening 31 further overlaps the third wiring 230 in a planar view. A portion of the conductive member 20 is disposed inside the opening 31, and the conductive member 20 is in contact with the third wiring 230. In other words, the third wiring 230 is electrically connected to the conductive member 20 through the opening 31. On the other hand, the first wiring 210 and the second wiring 220 are not in contact with the conductive member 20.
[0031] In this embodiment, the first insulating layer 30 has an opening 31 that overlaps the second light-emitting portion 120 in a planar view, and the third wiring 230 is electrically connected to the conductive member 20 through the opening 31, and the conductive member 20 is electrically connected to the conductive substrate 10. That is, the third wiring 230 is electrically connected to the substrate 10 through the opening 31. By passing a current between the pad electrode 61 and the substrate 10, the first light-emitting portion 110 and the second light-emitting portion 120 emit light.
[0032] Furthermore, in this embodiment, the second light-emitting portion 120 is surrounded by the first light-emitting portion 110 in a planar view. Therefore, the shape of the non-light-emitting portion between the first light-emitting portion 110 and the second light-emitting portion 120 in a planar view is a single closed curve with no end portions, and the second light-emitting portion 120 is located on both sides of the first light-emitting portion 110 in any in-plane direction parallel to the top surface of the substrate 10. This reduces the difference between the light-emitting intensity of the first light-emitting portion 110 and the light-emitting intensity of the second light-emitting portion 120, thereby reducing the bias in the light-emitting intensity distribution of the light-emitting element 1. For example, if the first light-emitting portion 110 and the second light-emitting portion 120 are arranged with the diagonal line of the substrate 10 as their boundary and pad electrodes are arranged at two of the four corners of the substrate 10 located diagonally, the distance between the pad electrodes in a planar view becomes large, and the light-emitting intensity distribution is likely to be biased toward the light-emitting portion on either side of the pad electrode. Furthermore, heat generated in the semiconductor structure 100 is easily transferred to the conductive member 20 and the substrate 10 through the opening 31, improving heat dissipation.
[0033] By arranging the multiple openings 42 along the outer edge of the substrate 10 in a plan view, it becomes easier for current to flow uniformly in the n-type semiconductor layer 112, making it possible to further reduce bias in the emission intensity distribution. The multiple openings may also be arranged so as to surround the second light emitting section 120 in a plan view. In this case, it becomes easier for current to flow uniformly in the n-type semiconductor layer 112, making it possible to further reduce bias in the emission intensity distribution.
[0034] Next, a modified example of the embodiment will be described. Fig. 3 is a cross-sectional view showing a light emitting device according to a modified example of the embodiment.
[0035] 3 , in the light-emitting element 2 according to the modified example of the embodiment, the second insulating layer 40 has an opening 45 as a third opening located between the first light-emitting section 110 and the second light-emitting section 120 in a plan view. For example, in a plan view, the opening 45 is surrounded by the first light-emitting section 110, and the second light-emitting section 120 is surrounded by the opening 45. A part of the second wiring 220 is disposed within the opening 45.
[0036] The other configurations of the modified example are basically the same as those of the above embodiment.
[0037] The same effect as that of the embodiment can be obtained by the modified example. Furthermore, a part of the light emitted from the light emitting layers 113 and 123 is reflected by the second wiring 220 in the opening 45 and is emitted to the outside without being absorbed by the n-type semiconductor layers 112 and 122. Therefore, the light extraction efficiency can be improved.
[0038] The above describes in detail preferred embodiments, but the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.
[0039] The present specification includes the following embodiments. 1. a conductive substrate; a conductive member disposed on the substrate; a first insulating layer disposed on the conductive member; a semiconductor structure including a first light emitting portion and a second light emitting portion spaced apart from each other on the first insulating layer, wherein each of the first light emitting portion and the second light emitting portion has a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer; a first wiring electrically connected to the first semiconductor layer of the first light emitting portion; a second wiring electrically connected to the second semiconductor layer of the first light emitting portion and the first semiconductor layer of the second light emitting portion; a third wiring electrically connected to the second semiconductor layer of the second light emitting portion; a pad electrode disposed above the substrate and spaced apart from the semiconductor structure in a plan view and electrically connected to the first wiring; and the second light-emitting portion is surrounded by the first light-emitting portion in a plan view, the first insulating layer has a first opening that overlaps with the second light emitting portion in a plan view; the third wiring is in contact with the conductive member through the first opening, The light-emitting element, wherein the first wiring and the second wiring are not in contact with the conductive member. 2. a second insulating layer disposed between the first light-emitting section and the second wiring, and between the second light-emitting section and the second wiring; the second insulating layer has a plurality of second openings that reach the second semiconductor layer of the first light emitting unit, the plurality of second openings are arranged to surround the second light-emitting unit in a plan view, 2. The light-emitting element according to 1, wherein the second wiring is electrically connected to the second semiconductor layer of the first light-emitting portion through the plurality of second openings. 3. a second insulating layer disposed between the first light-emitting section and the second wiring, and between the second light-emitting section and the second wiring; the second insulating layer has a plurality of second openings that reach the second semiconductor layer of the first light emitting unit, the plurality of second openings are arranged along an outer edge of the substrate in a plan view, 3. The light-emitting element according to 1 or 2 above, wherein the second wiring is electrically connected to the second semiconductor layer of the first light-emitting portion through the plurality of second openings. 4. the second insulating layer has a third opening located between the first light emitting portion and the second light emitting portion in a plan view; 4. The light-emitting element according to claim 3, wherein a portion of the second wiring is disposed within the third opening. [Explanation of symbols]
[0040] 1: Light emitting element 10: Circuit board 20: Conductive material 30: First insulating layer 31: Opening 40: Second insulating layer 41, 42, 43, 44: Openings 50: Third insulating layer 61: Pad electrode 71, 72: Light-reflective conductive layer 100: Semiconductor structure 110: First light-emitting part 120: Second light-emitting part 111, 121: p-type semiconductor layer 112, 122: n-type semiconductor layer 113, 123: Light-emitting layer 210: 1st wiring 220: 2nd wiring 230: 3rd wiring
Claims
1. a conductive substrate; a conductive member disposed on the substrate; a first insulating layer disposed on the conductive member; a semiconductor structure including a first light emitting portion and a second light emitting portion spaced apart from each other on the first insulating layer, wherein each of the first light emitting portion and the second light emitting portion has a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer; a first wiring electrically connected to the first semiconductor layer of the first light emitting portion; a second wiring electrically connected to the second semiconductor layer of the first light emitting portion and the first semiconductor layer of the second light emitting portion; a third wiring electrically connected to the second semiconductor layer of the second light emitting portion; a pad electrode disposed above the substrate and spaced apart from the semiconductor structure in a plan view and electrically connected to the first wiring; and the second light-emitting portion is surrounded by the first light-emitting portion in a plan view, the first insulating layer has a first opening that overlaps with the second light emitting portion in a plan view; the third wiring is in contact with the conductive member through the first opening, The light-emitting element, wherein the first wiring and the second wiring are not in contact with the conductive member.
2. a second insulating layer disposed between the first light emitting section and the second wiring, and the second insulating layer has a plurality of second openings that reach the second semiconductor layer of the first light emitting section, the plurality of second openings are arranged to surround the second light-emitting unit in a plan view, The light-emitting element according to claim 1 , wherein the second wiring is electrically connected to the second semiconductor layer of the first light-emitting portion through the plurality of second openings.
3. a second insulating layer disposed between the first light emitting section and the second wiring, and the second insulating layer has a plurality of second openings that reach the second semiconductor layer of the first light emitting section, the plurality of second openings are arranged along an outer edge of the substrate in a plan view, The light-emitting element according to claim 1 , wherein the second wiring is electrically connected to the second semiconductor layer of the first light-emitting portion through the plurality of second openings.
4. the second insulating layer has a third opening located between the first light emitting portion and the second light emitting portion in a plan view; The light-emitting element according to claim 3 , wherein a portion of the second wiring is disposed within the third opening.
Citation Information
Patent Citations
Optoelectronic semiconductor chip having multiple active regions arranged side by side.
JP2015533022A