Storage device

Abstract

To provide a storage device capable of reducing the number of redundancy lines to be used.SOLUTION: A storage device according to an embodiment includes: a plurality of first wirings 111 each extending in a first direction; a plurality of second wirings 112 each extending in a second direction intersecting the first direction; a plurality of memory cells 120 provided between the plurality of first wirings and the plurality of second wirings, each of the plurality of memory cells including a resistance change memory element and a switching element connected in series; and an address allocation circuit 301 that allocates an address to the plurality of first wirings. When the plurality of first wirings include a first short wire and a second short wire that are short-circuited to each other, the address allocation circuit allocates a common address to the first short wire and the second short wire.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] FIELD OF THE INVENTION An embodiment of the present invention relates to a storage device. [Background technology]

[0002] 2. Description of the Related Art A memory device has been proposed in which a plurality of resistance change memory elements such as magnetoresistive effect elements are integrated on a semiconductor substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2023 / 0015040 Summary of the Invention [Problem to be solved by the invention]

[0004] To provide a storage device capable of reducing the number of redundancy lines used. [Means for solving the problem]

[0005] A memory device according to an embodiment includes a plurality of first wirings each extending in a first direction, a plurality of second wirings each extending in a second direction intersecting the first direction, a plurality of memory cells provided between the plurality of first wirings and the plurality of second wirings, each including a resistance change memory element and a switching element connected in series, and an address assignment circuit that assigns addresses to the plurality of first wirings, and when the plurality of first wirings include a first short wiring and a second short wiring that are short-circuited to each other, the address assignment circuit assigns a common address to the first short wiring and the second short wiring. [Brief explanation of the drawings]

[0006] [Figure 1]FIG. 1 is a block diagram showing a configuration of a storage device according to an embodiment. [Figure 2] 1 is a perspective view schematically showing the configuration of a memory cell array unit included in a memory device according to an embodiment. [Figure 3] 1 is a cross-sectional view schematically showing the basic configuration of a magnetoresistive effect element included in a memory cell array section of a memory device according to an embodiment. [Figure 4] 1 is a cross-sectional view schematically showing the basic configuration of a selector included in a memory cell array unit of a memory device according to an embodiment. [Figure 5] 1 is a diagram schematically illustrating the configuration of a memory cell array unit, a drive circuit, and an address assignment circuit included in a memory device according to an embodiment. [Figure 6] 1 is a diagram illustrating a schematic configuration example of a connection relationship setting circuit and the like included in an address assignment circuit of a storage device according to an embodiment. [Figure 7] 1 is a diagram illustrating a schematic configuration example of a connection relationship setting circuit and the like included in an address assignment circuit of a storage device according to an embodiment. [Figure 8] 1 is a diagram illustrating a schematic configuration example of a connection relationship setting circuit and the like included in an address assignment circuit of a storage device according to an embodiment. [Figure 9] 1 is a diagram illustrating a schematic configuration example of a connection relationship setting circuit and the like included in an address assignment circuit of a storage device according to an embodiment. [Figure 10] 10 is a flowchart showing the operation of the storage device according to the embodiment. [Figure 11] 10A and 10B are diagrams illustrating a detection process for a short circuit defect in the memory device according to the embodiment. [Figure 12] FIG. 10 is a block diagram showing the configuration of a modified example of the storage device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment will be described with reference to the drawings.

[0008] FIG. 1 is a block diagram showing the configuration of a storage device according to an embodiment.

[0009] The memory device shown in FIG. 1 includes a memory cell array unit 100, a drive circuit 200, an address assignment circuit 300, a detection processing circuit 400, and a redundancy control circuit 500.

[0010] FIG. 2 is a perspective view showing a schematic configuration of the memory cell array unit 100. As shown in FIG.

[0011] 2, the memory cell array unit 100 includes a plurality of lower interconnections 110L each extending in the X direction, a plurality of upper interconnections 110U each extending in the Y direction, and a plurality of memory cells 120 provided between the plurality of lower interconnections 110L and the plurality of upper interconnections 110U. One of the lower interconnections 110L and the upper interconnections 110U corresponds to a word line, and the other of the lower interconnections 110L and the upper interconnections 110U corresponds to a bit line.

[0012] Each of the plurality of memory cells 120 includes a magnetoresistive effect element (resistance change memory element) 121 and a selector (switching element) 122 connected in series. The magnetoresistive effect element 121 and the selector 122 are stacked in the Z direction. In the example shown in FIG. 2, the magnetoresistive effect element 121 is provided on the upper layer side of the selector 122, but the magnetoresistive effect element 121 may also be provided on the lower layer side of the selector 122.

[0013] The X, Y, and Z directions intersect with each other, specifically, the X, Y, and Z directions are perpendicular to each other.

[0014] FIG. 3 is a cross-sectional view schematically showing the basic configuration of the magnetoresistive element 121. As shown in FIG.

[0015] As shown in FIG. 3, the magnetoresistive effect element 121 includes a memory layer (first magnetic layer) 121a, a reference layer (second magnetic layer) 121b, and a tunnel barrier layer (non-magnetic layer) 121c, and has a structure in which the memory layer 121a, the reference layer 121b, and the tunnel barrier layer 121c are stacked in the Z direction.

[0016] The memory layer 121a is a ferromagnetic layer with a variable magnetization direction. The reference layer 121b is a ferromagnetic layer with a fixed magnetization direction. The tunnel barrier layer 121c is an insulating layer provided between the memory layer 121a and the reference layer 121b. The variable magnetization direction means that the magnetization direction changes with a predetermined write current. The fixed magnetization direction means that the magnetization direction does not change with a predetermined write current.

[0017] When the magnetization direction of the storage layer 121a is parallel to the magnetization direction of the reference layer 121b, the magnetoresistive element 121 exhibits a low-resistance state having a relatively low resistance, and when the magnetization direction of the storage layer 121a is antiparallel to the magnetization direction of the reference layer 121b, the magnetoresistive element 121 exhibits a high-resistance state having a relatively high resistance. Therefore, the magnetoresistive element 121 can store binary data according to its resistance state.

[0018] The magnetoresistive effect element 121 shown in FIG. 3 is a bottom-free type magnetoresistive effect element in which the memory layer 121a is located below the reference layer 121b, but a top-free type magnetoresistive effect element in which the memory layer 121a is located above the reference layer 121b may also be used.

[0019] FIG. 4 is a cross-sectional view showing a schematic basic configuration of the selector 122. As shown in FIG.

[0020] The selector 122 is a two-terminal switching element including a lower electrode 122a, an upper electrode 122b, and a selector material layer 122c, and has the characteristic of transitioning from an off state to an on state when the voltage applied between the two terminals (between the lower electrode 122a and the upper electrode 122b) becomes equal to or greater than a threshold voltage.

[0021] When a voltage is applied between the selected lower wiring 110L and the selected upper wiring 110U, and a voltage equal to or greater than the threshold voltage is applied to the selected selector 122 included in the selected memory cell 120, a current flows through the selected magnetoresistance effect element 121 connected in series to the selected selector 122, making it possible to read or write from or to the selected magnetoresistance effect element 121.

[0022] FIG. 5 is a diagram showing a schematic configuration of the memory cell array unit 100, the drive circuit 200, and the address assignment circuit 300. As shown in FIG.

[0023] 5, the memory cell array unit 100 includes a plurality of first wirings 111, a plurality of second wirings 112, and a plurality of memory cells 120 connected between the plurality of first wirings 111 and the plurality of second wirings 112. The first wirings 111 correspond to one of the lower wirings 110L and the upper wirings 110U shown in FIG. 2, and the second wirings 112 correspond to the other of the lower wirings 110L and the upper wirings 110U shown in FIG. 2. The memory cells 120 correspond to the memory cells 120 shown in FIG. 2.

[0024] The plurality of first wirings 111 include a plurality of normal wirings 111a and at least one redundancy line 111b. Similarly, the plurality of second wirings 112 include a plurality of normal wirings 112a and at least one redundancy line 112b. The plurality of memory cells 120 include a plurality of normal memory cells 120a and a plurality of redundancy memory cells 120b.

[0025] The plurality of normal wirings 111a are regular first wirings 111. At least one redundancy line 111b is a first wiring 111 other than the plurality of normal wirings 111a, and, like the normal redundancy line, is a spare first wiring 111 used when a defective wiring is included among the plurality of normal wirings 111a. In this embodiment, at least one redundancy line 111b is used when a short-circuit wiring that is short-circuited with each other is included among the plurality of normal wirings 111a.

[0026] The plurality of normal wirings 112a and at least one redundancy line 112b are similar to the plurality of normal wirings 111a and at least one redundancy line 111b described above.

[0027] All of the at least one redundancy line 111b is provided in an area 101b outside the area 101a in which the plurality of normal wirings 111a are provided, and all of the at least one redundancy line 112b is provided in an area 102b outside the area 102a in which the plurality of normal wirings 112a are provided.

[0028] The driving circuit 200 includes a driving circuit 201 and a driving circuit 202. The driving circuit 201 generates driving signals to be supplied to the memory cells 120 via a plurality of first wirings 111, and the driving circuit 202 generates driving signals to be supplied to the memory cells 120 via a plurality of second wirings 112.

[0029] By supplying a selection signal from the driver circuit 201 to the selected first wiring 111 and supplying a selection signal from the driver circuit 202 to the selected second wiring 112, the selected memory cell 120 connected between the selected first wiring 111 and the selected second wiring 112 is turned on, making it possible to write or read data to or from the selected memory cell 120.

[0030] The address assignment circuit 300 includes an address assignment circuit 301 and an address assignment circuit 302. The address assignment circuit 301 is provided between the drive circuit 201 and the plurality of first wirings 111, and assigns addresses to the plurality of first wirings 111. The address assignment circuit 302 is provided between the drive circuit 202 and the plurality of second wirings 112, and assigns addresses to the plurality of second wirings 112.

[0031] In this embodiment, when a plurality of short-circuiting wirings that are short-circuited to each other are included among a plurality of first wirings 111, the address assignment circuit 301 assigns a common address to the plurality of short-circuiting wirings. Specifically, when a plurality of normal wirings 111a include a plurality of short-circuiting wirings that are short-circuited to each other, the address assignment circuit 301 assigns a common address to the plurality of short-circuiting wirings. Because a short-circuit defect is an inter-line defect (bridge defect) that occurs between adjacent first wirings 111, the plurality of short-circuiting wirings are first wirings 111 that are continuously arranged.

[0032] Similarly, when a plurality of shorting wires that are short-circuited to each other are included among a plurality of second wirings 112, the address assignment circuit 302 assigns a common address to the plurality of shorting wires. Specifically, when a plurality of normal wirings 112a include a plurality of shorting wires that are short-circuited to each other, the address assignment circuit 302 assigns a common address to the plurality of shorting wires. Regarding the second wirings 112, the plurality of shorting wires are second wirings 112 that are arranged continuously.

[0033] Below, we will explain an example configuration and functions of the address assignment circuit 300. Note that, for simplicity of explanation, the address assignment circuit 301 will be explained below, but the address assignment circuit 302 also has the same configuration and functions as the address assignment circuit 301.

[0034] 6 and 7 are diagrams each showing a schematic configuration example of the connection relationship setting circuit 301a etc. included in the address assignment circuit 301. Fig. 6 shows a case where the plurality of first wirings 111 (specifically, the plurality of normal wirings 111a) does not include short-circuiting wirings that are short-circuited to each other. Fig. 7 shows a case where the plurality of first wirings 111 (specifically, the plurality of normal wirings 111a) includes short-circuiting wirings that are short-circuited to each other.

[0035] As shown in Figures 6 and 7, the connection relationship setting circuit 301a includes a plurality of input terminals Ta (Ta1 to Ta8), a plurality of output terminals Tb (Tb1 to Tb10), and a plurality of connection members Cn, and sets the connection relationships between the plurality of input terminals Ta and the plurality of output terminals Tb.

[0036] The plurality of input terminals Ta receive drive signals, which are supplied to the plurality of memory cells 120 via the plurality of first wirings 111. The drive signals are supplied to the plurality of input terminals Ta from a drive circuit 201 shown in FIG. 5. The plurality of output terminals Tb output the drive signals input to the plurality of input terminals Ta to the plurality of first wirings 111. The connection relationship between the plurality of input terminals Ta and the plurality of output terminals Tb is set appropriately by a plurality of connection members Cn.

[0037] The connection relationship setting circuit 301a includes, for example, a plurality of fuses, and by adjusting the connection relationships using the plurality of fuses, it is possible to set the connection relationships between a plurality of input terminals Ta and a plurality of output terminals Tb.

[0038] 6, when the plurality of normal wirings 111a does not include any short-circuited wirings, the plurality of input terminals Ta1 to Ta8 are connected to the plurality of output terminals Tb1 to Tb8 via the plurality of connection members Cn, respectively, and the output terminals Tb9 and Tb10 are not used. That is, only the normal wiring 111a is used, and the redundancy line 111b is not used.

[0039] 7, when the plurality of normal wirings 111a includes short-circuited wirings that are shorted to each other, a common address is assigned to the plurality of short-circuited wirings (two short-circuited wirings in the example of FIG. 7). That is, a common address is assigned to two adjacent short-circuited wirings (two adjacent normal wirings 111a) that are short-circuited by a short portion ST, and a common drive signal is supplied to the two adjacent short-circuited wirings.

[0040] Specifically, in the example shown in FIG. 7, one of the two shorting wires is designated as a first shorting wire, and the other of the two shorting wires is designated as a second shorting wire, and an output terminal Tb5 provided for the first shorting wire among the plurality of output terminals Tb1 to Tb8 is connected to one input terminal Ta4 among the plurality of input terminals Ta1 to Ta8, but the output terminal Tb4 provided for the second shorting wire among the plurality of output terminals Tb1 to Tb8 is not connected to the one input terminal Ta4.

[0041] The two shorting wires (first and second shorting wires) described above are electrically connected to each other by the shorting portion ST. Therefore, a common address is assigned to the two shorting wires by the input terminal Ta4, and a common drive signal is supplied to the two shorting wires.

[0042] 7, the input terminal Ta8 is connected to the output terminal Tb9 provided for the redundancy line 111b, so that the drive signal input to the input terminal Ta8 is supplied to the redundancy line 111b connected to the output terminal Tb9.

[0043] As can be seen from the above, in this embodiment, instead of using two redundancy lines 111b instead of two short wirings, a common address is assigned to the two short wirings, thereby reducing the number of redundancy lines 111b used for redundancy processing.

[0044] Here, a memory cell provided between a first shorting wire and one second wire is referred to as a first memory cell, and a memory cell provided between a second shorting wire and the one second wire is referred to as a second memory cell. As described above, in this embodiment, a common address is assigned to the first and second shorting wires. Therefore, when a common drive signal (selection signal) is supplied to the first and second shorting wires, both the first and second memory cells are selectable. Because the first and second memory cells are controlled by a common address, both the first and second memory cells must not be selected, and only one of the first and second memory cells must be selected. In this embodiment, it is possible to select only one of the first and second memory cells for the following reasons.

[0045] The selection voltage (threshold voltage) of a memory cell varies from one memory cell to another. Therefore, only the memory cell with the lower threshold voltage of the first or second memory cell is selected as the usable memory cell. Specifically, during the forming process performed during initial setting, only one of the first or second memory cell is selected and the forming process is performed, and when writing or reading, only the memory cell that has undergone the forming process functions as the usable memory cell.

[0046] FIG. 8 is a diagram showing a schematic diagram of another example of the configuration of the connection relationship setting circuit 301a and the like included in the address assignment circuit 301. In FIG.

[0047] 8, an output terminal Tb5 provided for a first short-circuit wire among the plurality of output terminals Tb1 to Tb8 is connected to one input terminal Ta4 among the plurality of input terminals Ta1 to Ta8, and an output terminal Tb4 provided for a second short-circuit wire among the plurality of output terminals Tb1 to Tb8 is also connected to the one input terminal Ta4. Other basic configurations are the same as those shown in FIG.

[0048] In this example, similarly to the example of FIG. 7, a common address is assigned to two adjacent shorting wires (first and second shorting wires) by the input terminal Ta4, and a common drive signal is supplied to the two adjacent shorting wires.

[0049] In this example, both the output terminal Tb5 provided for the first shorting wire and the output terminal Tb4 provided for the second shorting wire are connected to one input terminal Ta4, so that a common drive signal can be more reliably supplied to the two shorting wires (first and second shorting wires).

[0050] FIG. 9 is a diagram showing a schematic diagram of still another example of the configuration of the connection relationship setting circuit 301a and the like included in the address assignment circuit 301. In FIG.

[0051] 9, three consecutively arranged first wirings 111 are shorted to each other. That is, a third short wiring that is shorted to the first and second short wirings is further included among the multiple first wirings 111. Specifically, the first short wiring and the second short wiring that are adjacent to each other are shorted by a short portion ST1, and the first short wiring and the third short wiring that are adjacent to each other are shorted by a short portion ST2.

[0052] In this example, a common address is assigned to three consecutively arranged short wirings (first, second and third short wirings) by input terminal Ta4, and a common drive signal is supplied to the three consecutively arranged short wirings.

[0053] In this example, the input terminal Ta7 is connected to the output terminal Tb9, and the input terminal Ta8 is connected to the output terminal Tb10. As a result, the drive signal input to the input terminal Ta7 is supplied to the redundancy line 111b connected to the output terminal Tb9, and the drive signal input to the input terminal Ta8 is supplied to the redundancy line 111b connected to the output terminal Tb10.

[0054] In the example shown in FIG. 9, the output terminal Tb5 provided for the first short wiring is connected to the input terminal Ta4, and the output terminal Tb4 provided for the second short wiring and the output terminal Tb6 provided for the third short wiring are not connected to the input terminal Ta4, but two or more of the output terminals Tb4, Tb5, and Tb6 may be connected to the input terminal Ta4.

[0055] Returning to the explanation of Figure 1, the memory device shown in Figure 1 has the detection processing circuit 400 and the redundancy control circuit 500 built into the same integrated circuit chip 1000 that also includes the memory cell array section 100, the drive circuit 200, and the address assignment circuit 300.

[0056] The detection processing circuit 400 performs detection processing for short-circuit defects in the plurality of first wirings 111 (specifically, the plurality of normal wirings 111a) and detection processing for short-circuit defects in the plurality of second wirings 112 (specifically, the plurality of normal wirings 112a).

[0057] Specifically, the detection processing circuit 400 detects whether or not the plurality of first wirings 111 includes short-circuited wirings that are shorted to each other, and if short-circuited wirings are included, detects which wirings among the plurality of first wirings 111 are shorted (detects the position of the short-circuited wiring). The same applies to the plurality of second wirings 112.

[0058] The above-described detection processing operations performed by detection processing circuit 400 can be performed after integrated circuit chip 1000 is packaged.

[0059] The redundancy control circuit 500 performs redundancy control. Specifically, the redundancy control circuit 500 controls the operation of setting the connection relationships performed by the connection relationship setting circuit 301a included in the address assignment circuit 301 based on the detection result of the detection processing circuit 400. That is, the redundancy control circuit 500 controls the operation of setting the connection relationships between the multiple input terminals Ta and the multiple output terminals Tb in the connection relationship setting circuit 301a. The address assignment circuit 302 is also controlled by the redundancy control circuit 500 in the same way.

[0060] The above-described redundancy control operations performed by redundancy control circuit 500 can be performed after integrated circuit chip 1000 is packaged.

[0061] Next, the operation of this embodiment will be described with reference to the flowchart shown in Fig. 10. Specifically, the initial setting operation of the memory device described above will be described. Note that, for simplicity of explanation, the operation for the first wiring 111 will be described as an example, but the same operation is also performed for the second wiring 112.

[0062] First, after the integrated circuit chip 1000 is packaged, a detection process for short-circuit defects is performed by the detection processing circuit 400 (S11). That is, a self-test for short-circuit defects is performed within the integrated circuit chip 1000.

[0063] 11 is a diagram showing a detection process for a short circuit defect. Specifically, it is a diagram showing the potentials (a1, a2) of the selected first wiring 111 and the potential (b) of the selected second wiring 112 when a current is passed between the selected first wiring 111 and the selected second wiring 112.

[0064] When there is no short circuit defect, a normal current flows between the selected first wiring 111 and the selected second wiring 112 via the selected memory cell, ensuring a potential rise in the selected first wiring 111, resulting in a characteristic like (a1). On the other hand, when there is a short circuit defect, a current flows between adjacent shorted wirings (between the selected first wiring 111 and the unselected first wiring 111 adjacent to the selected first wiring 111), preventing a potential rise in the selected first wiring 111, resulting in a characteristic like (a2). Therefore, it is possible to detect a short circuit defect by detecting the potential of the selected first wiring 111.

[0065] Next, it is determined whether or not a short circuit defect is detected (S12).

[0066] If no short circuit defect is detected, the connection relationship setting circuit 301a is in the state shown in FIG. 6, and the initial setting operation ends without performing redundancy processing.

[0067] If a short circuit defect is detected, it is determined whether the number of redundancy lines 111b will overflow (S13). That is, if the number of shorted wirings is large, the number of redundancy lines 111b will be insufficient. In such a case, it is determined that an overflow state has occurred, and the initial setting operation is terminated without performing redundancy processing.

[0068] If the number of redundancy lines 111b does not overflow, the redundancy processing as already described is performed (S14), and the process returns to step S11 to perform the detection processing for short-circuit defects again.

[0069] As described above, in this embodiment, instead of replacing all short wirings with redundancy lines as in the conventional method, a common address is assigned to multiple short wirings that are shorted to each other, making it possible to reduce the number of redundancy lines used for redundancy processing.

[0070] FIG. 12 is a block diagram showing the configuration of a modified example of the storage device according to this embodiment.

[0071] In the above-described embodiment, the detection processing circuit 400 and the redundancy control circuit 500 were built into the integrated circuit chip 1000 which included the memory cell array section 100, the drive circuit 200 and the address allocation circuit 300, but in this modified example, the detection processing circuit 400 and the redundancy control circuit 500 are not built into the integrated circuit chip 1000 but are provided in the external controller 2000.

[0072] In this modification, the basic configurations of the memory cell array unit 100, the drive circuit 200, and the address assignment circuit 300 are the same as those in the above-described embodiment. Furthermore, the operations performed by the detection processing circuit 400 and the redundancy control circuit 500 are also the same as those in the above-described embodiment. Therefore, in this modification, it is possible to obtain the same effects as those in the above-described embodiment.

[0073] In the above-described embodiment and modified example, an example has been shown in which the detection process and redundancy process for short-circuit defects are performed after the integrated circuit chip 1000 is packaged, but these processes may also be performed before packaging. Specifically, the above-described processes may be performed before the multiple integrated circuit chips 1000 are separated from the semiconductor wafer, and then the multiple integrated circuit chips 1000 may be separated from the semiconductor wafer and packaged.

[0074] 6 to 9 is used as the address assignment circuit 301, other structures may be used as long as they are capable of assigning a common address to a plurality of short-circuiting wirings when the plurality of first wirings 111 include a plurality of short-circuiting wirings that are short-circuited to each other. The same applies to the address assignment circuit 302.

[0075] Furthermore, in the above-described embodiment, a magnetoresistive effect element is used as the resistance change memory element, but other resistance change memory elements may also be used.

[0076] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0077] 100...Memory cell array section 101a, 102a...areas where normal wiring is provided 101b, 102b...outer area 110L...Lower wiring 110U...Upper wiring 111...first wiring 111a...normal wiring 111b...redundancy wiring 112...second wiring 112a...normal wiring 112b...redundancy wiring 120...Memory cell 120a...Normal memory cell 120b...Redundancy memory cell 121...Magnetoresistive effect element (resistance change memory element) 122...Selector (switching element) 200, 201, 202...Drive circuits 300, 301, 302...Address assignment circuits 301a...Connection relationship setting circuit 400...detection processing circuit 500...redundancy control circuit 1000...Integrated circuit chip 2000...External controller Ta, Ta1 to Ta8...input terminals Tb, Tb1 to Tb10...output terminals Cn...Connection part ST, ST1, ST2...Short part

Claims

1. a plurality of first wirings each extending in a first direction; a plurality of second wirings each extending in a second direction intersecting the first direction; a plurality of memory cells provided between the plurality of first wirings and the plurality of second wirings, each including a resistance change memory element and a switching element connected in series; an address assignment circuit that assigns addresses to the plurality of first wirings; A storage device comprising: When the plurality of first wirings includes a first short wiring and a second short wiring that are short-circuited to each other, the address assignment circuit assigns a common address to the first short wiring and the second short wiring.

1. A storage device comprising:

2. a plurality of input terminals to which drive signals are inputted, the drive signals being supplied to the plurality of memory cells via the plurality of first wirings; a plurality of output terminals that output the drive signals input to the plurality of input terminals to the plurality of first wirings; Furthermore, The address assignment circuit includes a connection relationship setting circuit that sets connection relationships between the plurality of input terminals and the plurality of output terminals.

2. The storage device according to claim 1.

3. The connection relationship setting circuit connects a first output terminal provided for the first short wiring among the plurality of output terminals to one input terminal among the plurality of input terminals, and does not connect a second output terminal provided for the second short wiring among the plurality of output terminals to the one input terminal.

3. The storage device according to claim 2.

4. The connection relationship setting circuit connects a first output terminal provided for the first short wiring among the plurality of output terminals to one input terminal among the plurality of input terminals, and connects a second output terminal provided for the second short wiring among the plurality of output terminals to the one input terminal.

3. The storage device according to claim 2.

5. When the plurality of first wirings further includes a third short wiring that is shorted to the first and second short wirings, the address assignment circuit assigns a common address to the first, second, and third short wirings.

2. The storage device according to claim 1.

6. A memory cell provided between the first short wiring and one of the second wirings among the plurality of memory cells is defined as a first memory cell, and a memory cell provided between the second short wiring and one of the second wirings among the plurality of memory cells is defined as a second memory cell, and one of the first memory cell and the second memory cell functions as an available cell.

2. The storage device according to claim 1.

7. The plurality of first wirings include a plurality of normal wirings and at least one redundancy wiring that is used when short-circuit wirings that are short-circuited to each other are included in the plurality of normal wirings.

2. The storage device according to claim 1.

8. The at least one redundancy line is provided in an area outside an area in which the plurality of normal lines are provided.

8. The storage device according to claim 7.

9. The chip includes the plurality of first wirings, the plurality of second wirings, the plurality of memory cells, and the address assignment circuit, and further includes a detection processing circuit that performs detection processing for short-circuit defects of the plurality of first wirings.

2. The storage device according to claim 1.

10. The detection process performed by the detection processing circuit can be performed after the chip is packaged.

10. The storage device according to claim 9.

11. The chip includes the plurality of first wirings, the plurality of second wirings, the plurality of memory cells, and the address assignment circuit, and further includes a redundancy control circuit for performing redundancy control.

2. The storage device according to claim 1.

12. The redundancy control performed by the redundancy control circuit can be performed after the chip is packaged. The storage device according to claim 11 .

13. The resistance change memory element and the switching element are stacked in a third direction intersecting the first and second directions.

2. The storage device according to claim 1.

14. The resistance change memory element is a magnetoresistive effect element.

2. The storage device according to claim 1.

15. The switching element is a two-terminal switching element that has the characteristic of transitioning from an off state to an on state when the voltage applied between the two terminals becomes equal to or greater than a threshold voltage.

2. The storage device according to claim 1.

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