Semiconductor device

Abstract

To provide a DC conversion circuit having high reliability.SOLUTION: A semiconductor device includes an induction element that generates an electromotive force according to a change in a flowing current, a transistor that has a gate, a source, and a drain and that controls generation of an electromotive force in the induction element by turning on or off, a rectifying element which is in conduction state when the transistor is off, and a control circuit that controls the on state or the off state of the transistor, and the transistor has an oxide semiconductor layer having a hydrogen concentration of 5×1019 atoms / cm3 or less as a channel formation layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] 1. Field of the Invention An embodiment of the present invention relates to a DC converter circuit and a power supply circuit. [Background technology]

[0002] In recent years, in various electronic devices, for example, it has become necessary to change the power supply voltage from a voltage with large voltage fluctuations to a stable value. When generating a DC voltage of a certain value, or when multiple different power supply voltages are required, A circuit that converts a voltage into a DC voltage of another value (also called a DC conversion circuit or DC-DC converter) ) is used.

[0003] The DC conversion circuit is configured using, for example, a coil, a diode, and a transistor. There is a non-insulated DC converter circuit (for example, Patent Document 1). The switching circuit has the advantages of a small circuit area and low manufacturing costs. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 58-086868 Summary of the Invention [Problem to be solved by the invention]

[0005] However, conventional DC converter circuits have the problem of low reliability. For example, a DC converter circuit handles a relatively high voltage, so When a high voltage above a certain value is applied to a transistor (e.g., a thin film transistor) This may cause dielectric breakdown of the transistor.

[0006] An object of one embodiment of the present invention is to improve the reliability of a DC converter circuit. [Means for solving the problem]

[0007] One aspect of the present invention is to obtain a highly purified product by removing as many impurities as possible that act as electron donors. It is an intrinsic or substantially intrinsic semiconductor that has been oxidized and has a higher energy gap than silicon semiconductors. DC converter using transistors with oxide semiconductors having large jumps in their channel formation layers This improves the reliability of the DC conversion circuit. The energy gap of the oxide semiconductor used in one embodiment is, for example, 2 eV or more, preferably is set to 2.5 eV or more, more preferably 3 eV or more.

[0008] Note that the term "high purification" refers to removing hydrogen from the oxide semiconductor layer as much as possible and By supplying oxygen to the oxide semiconductor layer, defects due to oxygen deficiency in the oxide semiconductor layer can be reduced. It is a concept that includes both.

[0009] The hydrogen concentration in the oxide semiconductor is 5×10 19 / cm 3 Below 5x, preferably 10 18 / cm 3 Less than or equal to 5 × 10 17 / cm 3 or less, or 1 x 10 16 / cm 3 In addition, hydrogen or OH groups contained in the oxide semiconductor are removed. The carrier concentration is 1×10 12 / cm 3 Less than 1 x 10 11 / cm 3 less than is.

[0010] The oxide semiconductor layer is made of a quaternary metal oxide, In-Sn-Ga-Zn-O, or a ternary metal oxide. Metal oxide films such as In-Ga-Zn-O, In-Sn-Zn-O, and In-Al-Zn- O film, Sn-Ga-Zn-O film, Al-Ga-Zn-O film, Sn-Al-Zn-O film, Binary metal oxide films such as In-Zn-O, Sn-Zn-O, Al-Zn-O, and Zn -Mg-O film, Sn-Mg-O film, In-Mg-O film, In-Sn-O film, and In-O film The insulating film can be formed using an oxide semiconductor film such as a Sn—O film or a Zn—O film. The oxide semiconductor film may contain SiO2. n-Ga-Zn-O film is a material made of indium (In), tin (Sn), gallium (Ga), and zinc The term "oxide film containing (Zn)" refers to an oxide film containing (Zn), and the stoichiometric ratio is not particularly important.

[0011] The oxide semiconductor layer is InMO3(ZnO) m The membrane is formed using (m>0) Here, M is one or more selected from Ga, Al, Mn and Co. For example, M can be Ga, Ga and Al, Ga and Mn, or Ga and Co. InMO3(ZnO) m Oxide semiconductors with a structure represented by (m>0) Among the oxide films, the oxide semiconductor having a structure containing Ga as M is the above-mentioned In-Ga-Zn-O This is called an oxide semiconductor, and the film is also called an In-Ga-Zn-O film.

[0012] In this way, by using a highly purified oxide semiconductor for a channel formation region of a transistor, For example, when the drain voltage is in the range of 1V to 10V, When the voltage is in the range of 0V or less, the off-state current (gate-source voltage The current that flows between the source and drain when -13 A or less, or off current density The value obtained by dividing the off-state current by the channel width of the transistor is 100 aA (a (atom) is 1 0 -18 ) / μm or less, preferably 10 aA / μm or less, and more preferably 1 aA / μm or less.

[0013] A highly purified oxide semiconductor layer with a sufficiently reduced hydrogen concentration is used as the channel formation layer. By using transistors with high reliability, a highly reliable DC conversion circuit can be realized. do.

[0014] One aspect of the present invention is a semiconductor device that includes an inductive element that generates an electromotive force in response to a change in the flowing current, a gate, a switch, and a The inductive element has a source and a drain, and is turned on or off to The transistor that controls the generation of electromotive force and the transistor that is in a conductive state when the transistor is in an off state and a control circuit that controls the on / off state of the transistor, The transistor and the channel formation layer have a hydrogen concentration of 5×10 19 atoms / cm 3 The following is a DC converter circuit including an oxide semiconductor layer.

[0015] In one embodiment of the present invention, the control circuit is configured to receive the voltage at the second terminal of the inductive element as an input signal. A signal is input, the input signal is compared with a reference voltage, and a pulse is generated according to the comparison result. A hysteresis loop that outputs a pulse signal with a set width to the gate of a transistor as an output signal. The configuration may include a comparator.

[0016] In one embodiment of the present invention, the hysteresis comparator is configured using a logic circuit. The channel formation layer has a hydrogen concentration of 5×10 19 atoms / cm 3 is The transistor may be formed using a transistor including an oxide semiconductor layer.

[0017] One aspect of the present invention is a method for manufacturing a semiconductor device having a first terminal and a second terminal, wherein a current flows through the first terminal and the second terminal. It has an inductive element that generates an electromotive force in response to changes in current, a gate, a source, and a drain. By being turned on or off, the generation of electromotive force in the inductive element is controlled. A transistor, a rectifying element that is in a conductive state when the transistor is in an off state, and a transistor and a control circuit for controlling the on / off state of the motor, and the control circuit receives an input signal A signal, which is the voltage at the second terminal of the inductive element, is input, and the input signal and the reference voltage are The output signal is a pulse signal with a pulse width set according to the comparison result. It is a DC conversion circuit having a hysteresis comparator that outputs to the gate of the inverter.

[0018] In one embodiment of the present invention, the transistor has a channel formation layer having a hydrogen concentration of 5×10 1 9 atoms / cm 3 It may be the following:

[0019] One aspect of the present invention is a coil having a first terminal and a second terminal, and the voltage of the second terminal is the output voltage. The transistor has a gate, a source, and a drain, and either the source or the drain is a coil. a transistor electrically connected to the first terminal of the transistor, and an input voltage is applied to the other of the source and drain. A transistor has a first electrode and a second electrode, and the first electrode is electrically connected to the second terminal of the coil. a capacitor element having a low power supply voltage applied to its second electrode, and an anode and a cathode a low power supply voltage is applied to the anode, and the cathode is connected to the source and drain of the transistor. The second terminal of the coil is connected to the diode electrically connected to one of the terminals. The voltage at the second terminal of the coil is input, and a pulse signal with a duty ratio set according to the voltage at the second terminal of the coil is generated. a hysteresis comparator that outputs the signal to the gate of the transistor as an output signal. The transistor is equipped with a channel-forming layer with a hydrogen concentration of 5×10 19 atoms / cm 3 The following is a DC converter circuit including an oxide semiconductor layer.

[0020] In one embodiment of the present invention, a hysteresis comparator includes a first input terminal, a second input terminal, a first reference voltage is applied to the first input terminal, and a second reference voltage is applied to the second input terminal. a first comparator to which the voltage of the second terminal of the coil is input as an input signal; a first input terminal, a second input terminal, and an output terminal, and a coil A second capacitor is connected to the second terminal of the first capacitor, and a second reference voltage is applied to the second input terminal of the second capacitor. a first comparator having an input terminal and an output terminal, the input terminal being connected to the output terminal of the first comparator; a first inverter electrically connected to the second inverter, the first inverter having an input terminal and an output terminal, the input terminal being connected to the second inverter; a second inverter electrically connected to the output terminal of the comparator; and a first input terminal; a first inverter having a second input terminal and an output terminal, the first input terminal being connected to the output terminal of the first inverter; a first NOR transistor electrically connected to the output terminal of the first NOR transistor; a gate, a first input terminal, a second input terminal, and an output terminal, the first input terminal being a The second input terminal is electrically connected to the output terminal of the first NOR gate, and the second input terminal is electrically connected to the output terminal of the second inverter. the output terminal is electrically connected to the second input terminal of the first NOR gate; and a second NOR gate connected to the first NOR gate.

[0021] In one embodiment of the present invention, a first comparator, a second comparator, a first inverter , the second inverter, the first NOR gate, and the second NOR gate are transistors The transistor includes a gate, a source, a drain, and a channel forming layer. Hydrogen concentration is 5×10 19 atoms / cm 3 The present invention has a structure including an oxide semiconductor layer having the following structure. It is also possible.

[0022] In one aspect of the present invention, the capacitance element is an electric double layer capacitor, a redox capacitor, Alternatively, it may be a lithium ion capacitor.

[0023] One embodiment of the present invention is a DC converter circuit according to the present invention, comprising: a storage device electrically connected to the DC converter circuit; and a power supply circuit having a power supply device.

[0024] In one embodiment of the present invention, the power storage device includes a photoelectric conversion device, a lithium ion secondary battery, and a lithium ion secondary battery. The capacitor may be any one or more of a lithium ion capacitor. [Effects of the Invention]

[0025] According to one embodiment of the present invention, the reliability of a DC converter circuit can be improved. [Brief explanation of the drawings]

[0026] [Figure 1] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a DC conversion circuit. [Figure 2] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a DC conversion circuit. [Figure 3] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a DC conversion circuit. [Figure 4] FIG. 1 is a circuit diagram showing an example of a circuit configuration of a hysteresis comparator. [Figure 5] 10 is a timing chart for explaining an example of the operation of a hysteresis comparator. [Figure 6] 1A and 1B are diagrams illustrating a transistor. [Figure 7] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 8] 1A and 1B are diagrams illustrating a transistor. [Figure 9] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 10] 1A and 1B are diagrams illustrating a transistor. [Figure 11] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 12] FIG. 10 is a longitudinal cross-sectional view of an inverted staggered transistor including an oxide semiconductor. [Figure 13] 13 is an energy band diagram (schematic diagram) taken along the line AA' in FIG. 12. [Figure 14] 1A shows a state in which a positive potential (+Vg) is applied to the gate electrode 1001. FIG. 1B shows a state in which a negative potential (-Vg) is applied to the gate electrode 1001. [Figure 15] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). [Figure 16] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 17] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 18] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 19] 1A and 1B are diagrams illustrating a transistor. [Figure 20] FIG. 2 is a diagram illustrating a power supply circuit. [Figure 21]1A to 1C illustrate electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0027] An example of an embodiment of the present invention will be described below with reference to the drawings. The present invention is not limited to the above description, and the embodiments and details thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications can be made to the above. The present invention should not be construed as being limited to the description of the embodiments.

[0028] (Embodiment 1) In this embodiment, an example of a DC converter circuit according to one embodiment of the present invention will be described.

[0029] An example of the configuration of the DC converter circuit according to this embodiment will be described with reference to FIG. 1 is a circuit diagram showing an example of the configuration of a DC converter circuit according to the present embodiment.

[0030] The DC converter circuit shown in FIG. 1 includes an inductive element 101, a transistor 102, and a rectifying element (RC T) 103.

[0031] In this specification, a transistor is defined as a transistor having at least a gate, a source, and a drain. As the transistor, for example, an insulating gate transistor can be used. do.

[0032] The term "gate" refers to a gate electrode and a part or the whole of a gate wiring. This means that the gate electrode of at least one transistor is electrically connected to another electrode or another wiring. The gate electrode and the gate wiring are not distinguished from each other and are referred to as the same. The conductive layer may have a function as a gate electrode and a gate wiring.

[0033] The source refers to the source electrode and part or all of the source wiring. The source wiring is a conductive layer that functions as a source. A wiring that electrically connects the source electrode of a transistor to another electrode or wiring. In addition, the source electrode and the source wiring are not distinguished from each other, and one conductive layer is used for both the source electrode and the source wiring. It can also be configured to function as a signal wiring.

[0034] The drain refers to the drain electrode and part or all of the drain wiring. The electrode refers to a conductive layer that functions as a drain. To electrically connect the drain electrode of one transistor to another electrode or another wiring In addition, the drain electrode and the drain wiring are not distinguished from each other and a single conductive layer is used. It may also be configured to function as a drain electrode and drain wiring.

[0035] In this specification, the source and drain of a transistor are used to determine the structure and operation of the transistor. Since they are interchangeable depending on the operating conditions, it is difficult to determine which is the source or drain. Therefore, in this document (specification, claims, drawings, etc.), Either the source or the drain is referred to as one of the source and the drain, and the other is referred to as the source. and the other end of the drain.

[0036] The induction element 101 generates an electromotive force in response to changes in the current flowing through it due to electromagnetic induction. As shown in FIG. 1, the inductive element 101 has a first terminal and a second terminal. The inductive element 101 may be, for example, a coil.

[0037] The transistor 102 is turned on or off to control the inductive element 101. The transistor 102 has a function of controlling the generation of electromotive force. , one of the source and the drain is connected to either the first terminal or the second terminal of the inductive element 101. are electrically connected.

[0038] Generally, voltage refers to the difference in potential between two points (also called the potential difference). However, voltage and potential values ​​are often expressed in volts (V) in circuit diagrams and other similar situations. Therefore, in this specification, unless otherwise specified, The potential difference between the potential at this point and the reference potential (also called the reference potential) is used as the voltage at that point. There are cases where this happens.

[0039] In this specification, the signal may be an analog signal using, for example, a voltage or a digital signal. For example, a signal using a voltage (also called a voltage signal) can be: It is preferred to use a signal having at least a first voltage state and a second voltage state, e.g. For example, a high voltage state is used as the first voltage state and a low voltage state is used as the second voltage state. A digital signal having a voltage state can be used. Voltage V H or simply V H The voltage at low level is called voltage V L or simply V L and The voltages of the first voltage state and the second voltage state are also referred to as the respective values ​​of the signals. The voltage in the first voltage state may differ depending on the signal and may be affected by noise, etc. The voltage in the first voltage state and the voltage in the second voltage state do not have to be constant, but may be within a certain range. stomach.

[0040] For example, as shown in FIG. 1, the rectifying element 103 has a first terminal and a second terminal. Either the first terminal or the second terminal of the inductive element 101 is connected to either the first terminal or the second terminal of the inductive element 101. are electrically connected.

[0041] The rectifying element 103 may be, for example, a diode. For example, a PN diode or a PIN diode can be used. The transistor 102 may be applied to the transistor having a gate and a drain. The use of a transistor with its inputs electrically connected (also called diode-connected) As a diode-connected transistor, the function as a channel forming layer can be and a hydrogen concentration in a channel formation layer is 5×10 19 atoms / c m 3 Less than or equal to 5 x 10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 and the carrier concentration is 1×10 12 / cm 3 Less than, preferred 1×10 11 / cm 3 A transistor having less than 1000 .mu.m can be used.

[0042] Furthermore, the DC converter circuit shown in Figure 1 has a function to determine which terminal receives the input voltage and which terminal outputs the voltage. For example, the first and second terminals of the inductive element 101 are An input voltage is applied to the other of the first and second terminals of the rectifying element 103, and a voltage is output from the other of the first and second terminals of the rectifying element 103. When a current flows from the first terminal to the second terminal of the rectifying element 103, the direct current shown in FIG. The current converter circuit functions as a boost circuit. An input voltage is applied to the other terminal of the inductive element 101, and the voltage at the other terminal of the first terminal and the second terminal of the inductive element 101 is When a current flows from the first terminal to the second terminal of the rectifying element 103, the output voltage is The DC converter circuit functions as a step-down circuit.

[0043] Furthermore, in the DC converter circuit of this embodiment, the on and off states of the transistor 102 are The DC converter circuit of this embodiment can be configured to have a control circuit for controlling the DC converter. An example of the configuration will be described with reference to FIG. 2. In the DC conversion circuit shown in FIG. For parts with the same configuration as the DC converter circuit shown in Fig. 1, the explanation of the DC converter circuit shown in Fig. 1 will be used as appropriate. To quote.

[0044] The DC conversion circuit shown in FIG. 2 includes a control circuit 104 in addition to the configuration shown in FIG.

[0045] The control circuit 104 has a function of controlling the on / off state of the transistor 102. The control circuit 104 receives the output voltage of the DC converter as an input signal, and The ripple of the output voltage of the The pulse signal is output to the gate of the transistor 102. The transistor 102 is turned on or off by the pulse signal. The off state is controlled.

[0046] The control circuit 104 is configured using, for example, a hysteresis comparator. The comparator is configured using, for example, a plurality of logic circuits, each of which has the following configuration: For example, the transistor is configured using a channel forming layer. and the hydrogen concentration in the oxide semiconductor layer is 5×10 19 atoms / cm 3 Less than or equal to 5 x 10 18 atoms / cm 3 Below are some more preferred Or 5 x 10 17 atoms / cm 3 and the carrier concentration is 1×10 12 / cm 3 Less than 1 x 10 11 / cm 3 It is also possible to use transistors with a This reduces voltage fluctuations due to transistor leakage current in each logic circuit. Therefore, the voltage state of the pulse signal can be stabilized. The control circuit 104 is configured by combining a hysteresis comparator with another arithmetic circuit. It is preferable.

[0047] As shown in FIGS. 1 and 2, an example of a DC converter circuit according to the present embodiment includes a transistor and an inductor. The configuration includes a conductive element and a rectifying element.

[0048] The DC converter circuit of this embodiment has a structure including a capacitance element for smoothing the output voltage. By providing a capacitance element, the output voltage can be made close to a constant value. Cut.

[0049] Furthermore, in one example of the DC converter circuit of this embodiment, a transistor has a channel forming layer and and the oxide semiconductor layer has a hydrogen concentration of 5×1019 a toms / cm 3 Less than or equal to 5 x 10 18 atoms / cm 3 The following are more preferred: Kuha 5 x 10 17 atoms / cm 3 and the carrier concentration is 1×10 12 / cm 3 Less than 1 x 10 11 / cm 3 The transistors used must be less than The transistor has the following advantages compared to, for example, a conventional transistor using silicon: It has a low off-state current and a high dielectric strength. Therefore, it is used as a transistor that configures a DC conversion circuit. This allows the transistor to operate even when a high voltage is applied between its terminals. This can prevent damage to the capacitor.

[0050] Next, as an example of the operation of the DC converter circuit of this embodiment, the operation of the DC converter circuit shown in FIG. An example of this will be described.

[0051] As a DC conversion method of the DC conversion circuit of this embodiment, for example, a nonlinear control method is used. The nonlinear control scheme can alternate the state of the transistor 102 between an on state and an off state. By switching between them, the voltage input to the DC converter circuit is converted into a pulse signal, and In this case, the output voltage is generated using a pulse signal. The state is set by, for example, the duty ratio of the pulse signal input to the gate. The pulse signal input to the transistor 102 is generated by using, for example, the output voltage of a DC converter circuit. is generated.

[0052] An example of the operation of the DC converter circuit shown in FIG. 2 can be mainly divided into periods T1 and T2. , the input is made by alternately performing the operation in the period T1 and the operation in the period T2. The voltage is increased or decreased during each period, as explained below.

[0053] During the period T1, the transistor 102 is turned on in response to the pulse signal, and the rectifying element 10 3 is in a non-conducting state. Also, depending on the value of the input voltage input to the DC conversion circuit, the inductive element A current flows through inductive element 101. At this time, electromotive force V1 is generated in inductive element 101.

[0054] During the period T2, the transistor 102 is turned off in response to the pulse signal. In the conductive element 101, in order to suppress the change in its own magnetic field, an electromotive force in the opposite direction to the electromotive force V1 is generated. V2 is generated, and the rectifying element 103 is turned on. When this happens, the output voltage of the DC converter shown in Figure 2 changes. The voltage value is the value at which the input voltage value has changed. The output voltage value is the value at which the input voltage value has changed between the periods T1 and T2. T2, in other words, it is determined by the duty ratio of the pulse signal. In periods T1 and T2, if the output voltage is greater than the desired value, the duty cycle of the pulse signal is The ratio is set to be low by the control circuit 104. Also, if the output voltage is lower than the desired value, If the duty ratio of the pulse signal is smaller than the predetermined value, the duty ratio of the pulse signal is set to be higher by the control circuit 104. In this way, in the DC converter circuit shown in FIG. 2, the output voltage for each unit period is set by the control circuit. By feeding back to 104, the output voltage after feedback is made to approach the desired value. It can be done.

[0055] As described above, the DC converter circuit of this embodiment is an example of a DC converter circuit that converts a pulse signal input from a control circuit into a The transistor electrically connected to the inductive element 101 is turned on in accordance with the duty ratio of the signal. and off states to convert the input voltage to a different value to generate an output voltage. This allows the circuit to function as a voltage step-up circuit or a voltage step-down circuit.

[0056] (Embodiment 2) In this embodiment, an example of a DC converter circuit according to one embodiment of the present invention will be described. The conversion method of the conversion circuit is typically the linear method or the switching method. The DC converter circuit of this type has excellent conversion efficiency and is therefore suitable for reducing the power consumption of electronic devices. In the embodiment, a switching type, particularly a chopper type DC conversion circuit will be described. .

[0057] An example of the configuration of the DC converter circuit according to this embodiment will be described with reference to FIG. 1 is a circuit diagram showing an example of the configuration of a DC converter circuit according to the present embodiment.

[0058] The DC conversion circuit shown in FIG. 3 includes a coil 201, a transistor 202, and a diode 203. a capacitance element 204, and a hysteresis comparator (also called HCMP) 205. Prepare.

[0059] The coil 201 has a first terminal and a second terminal. The coil 201 functions as an inductive element. It has.

[0060] The transistor 202 has one of its source and drain electrically connected to the first terminal of the coil 201. Connected.

[0061] The transistor 202 is, for example, a semiconductor device having a function as a channel formation layer. and the hydrogen concentration in the channel forming layer is 5×10 19 atoms / cm 3 Below, preferably 5×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 and the carrier concentration is 1×10 12 / cm 3 Less than 1 x 10 11 / c m 3 A transistor having less than 1000 .mu.m can be used.

[0062] The diode 203 has an anode and a cathode, and the anode is connected to a low power supply voltage (voltage VSS or simply VSS) is applied, and the cathode is electrically connected to the first terminal of the coil 201. The diode 203 functions as a rectifying element.

[0063] The diode 203 may be, for example, a PN diode or a PIN diode. In addition, a transistor applicable to the transistor 202, for example, a diode The connected transistor can also be used as a diode 203. The transistor may be, for example, a transistor including an oxide semiconductor having a function as a channel formation layer. the hydrogen concentration in the oxide semiconductor layer is 5×10 19 atoms / cm 3 The following is preferably is 5 x 10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / c m 3 and the carrier concentration is 1×10 12 / cm 3Less than 1 x 10 11 / cm 3 A transistor having less than 1000 .mu.m can be used.

[0064] The capacitor 204 is provided between a first electrode, a second electrode, and the first electrode and the second electrode. a dielectric layer formed on the first electrode, the first electrode being electrically connected to the second terminal of the coil 201; A low power supply voltage is applied to the second electrode. The capacitor 204 functions as a smoothing capacitor. , has the function of smoothing the voltage of node N2 shown in FIG.

[0065] The capacitor 204 is formed using, for example, the oxide semiconductor layer used in the transistor 202. MIS capacitor, electric double layer capacitor, redox capacitor, or lithium ion capacitor In the DC converter circuit according to one embodiment of the present invention, By alternately switching the transistor 202 on and off, a voltage boosting operation or To perform the step-down operation, the charge / discharge rate of the capacitor 204 to which the stepped-up or stepped-down voltage is applied is If the voltage is low, the voltage step-up or step-down operation may be delayed. By using a lithium ion capacitor, which is considered to be fast, the delay in voltage step-up or step-down operation is reduced. Furthermore, the present invention is not limited to the lithium ion capacitor, and the capacitance element 2 04, other alkali metal ions or alkaline earth metal ions are used as mobile ions. For example, a sodium ion capacitor may be used. This reduces the manufacturing cost. It is preferable that the capacitance of the capacitor 204 is large. By increasing the capacitance of the capacitor 204, the Therefore, the output voltage of the DC converter circuit can be smoothed.

[0066] The hysteresis comparator 205 receives the output voltage of the DC converter circuit shown in FIG. The voltage is input, the ripple of the input signal is detected, and the duty ratio is adjusted according to the detected ripple. The set pulse signal is generated, and the generated pulse signal is used as a control signal to drive the transistor 20 It has the function of outputting to gate 2.

[0067] The hysteresis comparator 205 is configured using a logic circuit, and the entire logic circuit This allows the number of steps to be reduced. can be reduced.

[0068] Here, the circuit of the hysteresis comparator (hysteresis comparator 205) shown in FIG. An example of the circuit configuration will be described with reference to FIG. 4. FIG. 4 shows the hysteresis comparator shown in FIG. FIG. 1 is a circuit diagram showing an example of a circuit configuration of a regulator.

[0069] The hysteresis comparator shown in FIG. 4 includes a comparator 221, a comparator 222, and , inverter 223, inverter 224, NOR gate 225, and NOR gate 22 6 and are equipped with.

[0070] The comparator 221 has a first input terminal, a second input terminal, and an output terminal. A reference high voltage (reference voltage Vref H Or simply Vref H (also called) is given A signal S22 is input to the second input terminal.

[0071] The comparator 222 has a first input terminal, a second input terminal, and an output terminal. A signal S22 is input to the input terminal, and a low voltage (reference voltage Vre f L Or simply Vref L The reference voltage Vref L The value of is the base Sub-voltage Vref H is less than the value of

[0072] The inverter 223 has an input terminal and an output terminal. The input terminal is connected to the output terminal of the comparator 221. The power terminal is electrically connected to the power terminal.

[0073] The inverter 224 has an input terminal and an output terminal. The input terminal is connected to the output terminal of the comparator 222. The power terminal is electrically connected to the power terminal.

[0074] The NOR gate 225 has a first input terminal, a second input terminal, and an output terminal. The input terminal is electrically connected to the output terminal of the inverter 223. The connection point between the first input terminal of the inverter 5 and the output terminal of the inverter 223 is referred to as a node S.

[0075] NOR gate 226 has a first input terminal, a second input terminal, and an output terminal. The input terminal is electrically connected to the output terminal of the NOR gate 225, and the second input terminal is an inverter. The output terminal is electrically connected to the second input of NOR gate 225. The first input terminal of the NOR gate 226 is electrically connected to the inverter 2 The connection point with the output terminal of 24 is node R.

[0076] The comparator 221, the comparator 222, the inverter 223, and the inverter 224 , the NOR gate 225, and the NOR gate 226 are each formed by using, for example, transistors. The transistor is provided with, for example, an oxide semiconductor having a function as a channel forming layer. The oxide semiconductor layer has a hydrogen concentration of 5×10 19 atoms / cm 3 Below, I prefer Or 5 x 10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 and the carrier concentration is 1×10 12 / cm 3 Less than 1 x 10 1 1 / cm 3 In this embodiment, a transistor having a capacitance of less than 100 Ω can be used. It is also possible to configure each logic circuit using only transistors of the same conductivity type. By using only transistors of the same conductivity type to configure each logic circuit, the manufacturing process is simplified. It can be simplified.

[0077] As shown in Figure 4, the hysteresis comparator shown in Figure 3 has two comparators. The voltage of the signal input to each of the two comparators is (the output voltage of the DC conversion circuit shown in Figure 3) and the reference voltage (reference voltage Vref H or base Sub-voltage Vref L ) and generates a pulse signal with a duty ratio set according to the comparison result. Output the number.

[0078] Next, an example of the operation of the hysteresis comparator shown in FIG. 4 will be described.

[0079] An example of the operation of the hysteresis comparator shown in Figure 4 is shown in Figure 3, which is input as an input signal. The voltage at node N2 (voltage V N2 or simply VN2 (also called) is the reference voltage Vref H twist If high (V N2 >Vref H ), voltage V N2 is the reference voltage Vref L Higher, reference voltage Vref H If lower (Vref H >V N2 >Vref L ), voltage V N2 is the reference voltage V ref L If lower (Vref L >V N2 ) can be divided into two cases. This will be explained below.

[0080] V N2 >Vref H When the potential of node S is V H The potential of node R becomes V L become At this time, the potential of node Q becomes V L The output of the hysteresis comparator shown in Figure 4 is Signal (Signal OUT HCMP ) will be at a low level.

[0081] Vref H >V N2 >Vref L When the potential of node S is V L and the potential of node R V L In this case, node Q maintains the state of node Q in the previous period. For example, if the potential of node Q is V H In this case, the potential of node Q is V H and The output signal of the hysteresis comparator also remains high, and The potential of the Q terminal is V L When the potential of node Q is V L The signal remains OUTHCMP Moro It remains at the same level.

[0082] Vref L >V N2 When the potential of node S is V L The potential of node R becomes V H become At this time, the potential of node Q is V H The output signal of the hysteresis comparator becomes It becomes an uneven level.

[0083] Furthermore, an example of the operation of the hysteresis comparator of this embodiment will be explained with reference to FIG. FIG. 5 illustrates an example of the operation of the hysteresis comparator according to this embodiment. This is a timing chart for setting the voltage V N2 , the voltage of node S (V NS Also called , the voltage at node R (V NR ) and the waveform of the output signal of the hysteresis comparator are shown respectively.

[0084] As shown in Figure 5, for example, the voltage V N2 If is a triangular wave, Vref L >V N2 During The voltage of the node S is kept at a low level. L >V N2 to Vref L <V N2 When this happens, the voltage at node R goes from high to low, and Vref H >V N2 >Vref L During this time, the signal OUT HCMP is maintained at a high level. f H >V N2 >Vref L From V N2 >Vref HWhen this happens, the voltage at node S goes low. The signal OUT HCMP V goes from high to low. N 2>Vref H During this time, the voltage at node S is maintained at a high level. N2 >V ref H to Vref H >V N2 When this happens, the voltage at node S changes from high to low. Furthermore, Vref H >V N2 >Vref L During this time, the signal OUT HCMP is low level In this way, the voltage V N2 A pulse signal based on The above is an example of the operation of the hysteresis comparator shown in Figure 4.

[0085] As shown in FIGS. 2 to 4, an example of the DC converter circuit of this embodiment is an inductive A coil that functions as a conducting element and a transistor that functions as a switching element. a capacitor that functions as a smoothing capacitor; a diode that functions as a rectifying element; a hysteresis comparator that controls the on or off state of the transistor; , and the configuration is provided with:

[0086] Furthermore, an example of the DC converter circuit of this embodiment is an oxide film having a function as a channel forming layer. The oxide semiconductor layer has a hydrogen concentration of 5×10 19 atoms / cm 3 below , preferably 5 x 10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 at oms / cm 3and the carrier concentration is 1×10 12 / cm 3 Less than 1x, preferably 10 11 / cm 3 The transistor may have a capacitance of less than 100 Ω. Compared to conventional silicon-based transistors, for example, the transistors have a low off-state current and high insulating properties. Therefore, by using it as a transistor that configures a DC conversion circuit, Even when a high voltage is applied between the terminals of the transistor, the breakdown of the transistor can be suppressed. This can be done.

[0087] Next, an example of the operation of the DC converter circuit shown in FIG. 3 will be described.

[0088] The DC conversion method of the DC converter circuit of this embodiment is a pulse width modulation control method. The example of the operation of the DC converter circuit shown in 3 can be divided into a period T51 and a period T52. The operation in the period T51 and the operation in the period T52 are alternately repeated. The respective periods are explained below.

[0089] During the period T51, the trigger is turned on in accordance with the pulse signal input from the hysteresis comparator 205. The transistor 202 is turned on, and the voltage at the node N1 rises to the input voltage of the DC converter circuit shown in FIG. The voltage at node N1 becomes equal to the voltage at node N2, and diode 203 becomes non-conductive. When the voltage becomes equal to the input voltage, a current flows through the coil 201. At 1, an electromotive force is generated.

[0090] During the period T52, the transistor is turned on by the pulse signal input from the hysteresis comparator 205. At this time, the coil 201 generates a magnetic field To suppress the change, an electromotive force V2 is generated in the opposite direction to the electromotive force V1, and diode 203 becomes conductive, and current flows through the diode 203 and the coil 201. By repeating the periods T51 and T52, the voltage at the node N2 decreases. The output voltage of the DC converter shown in FIG. 3 is smaller than the input voltage. The ratio of the length of the period T51 to the length of the period T52, in other words, the duty ratio of the pulse signal, is determined. For example, in periods T51 and T52, if the output voltage is greater than the desired value, the pulse The duty cycle of the signal is set low by the hysteresis comparator 205. If the output voltage is lower than the desired value, the duty cycle of the pulse signal is adjusted by the hysteresis loop. It is set high by the lysis comparator 205. Thus, the In the DC conversion circuit, the output voltage for each unit period is fed to the hysteresis comparator 205. By backing up the output voltage, the output voltage can be adjusted to the desired value in the following period. do.

[0091] As shown in FIG. 3, an example of the DC converter circuit of this embodiment is a DC converter circuit that receives an input from a control circuit. A transistor electrically connected to the first terminal of the coil is turned on in response to the duty ratio of the input pulse signal. The transistor is alternately switched on and off to convert the input voltage to a voltage of a different value. By generating an output voltage, it can function as a voltage step-up circuit or a voltage step-down circuit.

[0092] This embodiment mode can be appropriately combined with or replaced with other embodiment modes. do.

[0093] (Embodiment 3) This embodiment can be applied to the transistors that configure the DC converter circuit disclosed in this specification. An example of a transistor is shown below.

[0094] One embodiment of a transistor and a manufacturing method of the transistor of this embodiment will be described with reference to FIGS. and explain.

[0095] 6(A) and 6(B) show examples of the planar and cross-sectional structures of a transistor. The transistor 410 shown is one of the top-gate transistors.

[0096] FIG. 6A is a plan view of a transistor 410 having a top-gate structure, and FIG. 6B is a plan view of a transistor 410 having a top-gate structure. FIG. 10 is a cross-sectional view taken along line C1-C2 of (A).

[0097] The transistor 410 includes an insulating layer 407, an oxide semiconductor layer 408, and a gate insulating layer 409 over a substrate 400 having an insulating surface. the layer 412, the source electrode layer 415a, the drain electrode layer 415b, the gate insulating layer 402, and The gate electrode layer 411 is included, the wiring layer 414a is in contact with the source electrode layer 415a, and the drain electrode The wiring layer 414b contacts the pole layer 415b.

[0098] 6A and 6B, the transistor 410 is a transistor having a single gate structure. The transistor in this embodiment will be described using a transistor having a channel formation region. A transistor having a multi-gate structure may be used.

[0099] 7A to 7E, a process of manufacturing a transistor 410 on a substrate 400 will be described. Explain.

[0100] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least In both cases, it is necessary for the substrate 4 to have heat resistance to the extent that it can withstand the heat treatment. 00 is a glass substrate such as barium borosilicate glass or aluminoborosilicate glass. can be used.

[0101] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. Alternatively, a substrate made of an insulating material may be used. Alternatively, a crystallized glass substrate or the like may be used. In addition, a plastic substrate or the like can also be used as appropriate. A semiconductor substrate of the type described above can also be used.

[0102] First, an insulating layer 407 is formed as a base film on a substrate 400 having an insulating surface. 07 includes a silicon oxide layer and a silicon oxynitride layer (SiO x N y Also called, however, x>y>0), an oxide insulating layer such as an aluminum oxide layer or an aluminum oxynitride layer The insulating layer 407 is preferably formed by plasma CVD or sputtering. However, it is necessary to prevent a large amount of hydrogen from being contained in the insulating layer 407. To achieve this, the insulating layer 407 is preferably formed by a sputtering method.

[0103] In this embodiment, a silicon oxide layer is formed as the insulating layer 407 by a sputtering method. The substrate 400 is transferred to a processing chamber, where hydrogen and moisture are removed and a high-purity sputter containing oxygen is applied. A targeting gas is introduced, and a silicon semiconductor target is used to oxidize the insulating layer 407. A silicon layer is formed on the substrate 400. When the insulating layer 407 is formed, the substrate 400 The temperature may be room temperature or heated.

[0104] In this embodiment, for example, quartz (preferably The substrate temperature was 108°C, and the distance between the substrate and the target (TS distance) was 60 mm, pressure 0.4 Pa, high frequency power 1.5 kW, oxygen and argon (oxygen flow rate 25 RF sputtering was performed under an atmosphere of argon (25 sccm, argon flow rate 25 sccm = 1:1). A silicon oxide film is formed. The thickness of the silicon oxide film is 100 nm. Instead of quartz (preferably synthetic quartz), silicon dioxide is used as a target for forming a silicon oxide film. A silicon target can be used as the sputtering gas. Alternatively, a mixed gas of oxygen and argon can be used.

[0105] When the insulating layer 407 is formed using any of the above materials and methods, It is preferable to form the insulating layer 407 while removing residual moisture. This is to prevent the inclusion of hydroxyl groups or moisture.

[0106] In order to remove the residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. Examples of adsorption type vacuum pumps include cryopumps, ion pumps, and titanium It is preferable to use a sublimation pump. As an exhaust means, for example, a turbine A cryopump equipped with a cold trap can be used. In the film-forming chamber that has been evacuated, for example, hydrogen atoms and compounds containing hydrogen atoms (such as water) are present. Since the gas is exhausted, the gas contained in the insulating layer 407 formed by forming a film in the film forming chamber is The concentration of impurities (especially hydrogen) can be reduced.

[0107] The sputtering gas used in forming the insulating layer 407 is hydrogen, water, or hydroxide. High purity, with impurities such as bases or hydrides removed to concentrations of ppm or ppb. It is preferable to use a gas.

[0108] In addition, the sputtering method uses RF sputtering, which uses a high frequency power source for the sputtering power source. sputtering method, DC sputtering method using a DC power supply, or pulsed bias method The RF sputtering method is mainly used for forming insulating films. DC sputtering is mainly used to deposit metal films.

[0109] In addition, the sputtering equipment is a multi-target sputtering system that can install multiple targets of different materials. Multi-target sputtering equipment is a device that deposits different material films in the same chamber. It is possible to deposit layers or to deposit films by discharging multiple types of materials simultaneously in the same chamber. can.

[0110] The sputtering device is a magnetron with a magnet mechanism inside the chamber. Sputtering equipment that uses the sputtering method and microwaves that do not use glow discharge There is a sputtering device that uses the ECR sputtering method using generated plasma. .

[0111] In addition, in the sputtering method, a target material and a sputtering gas component are mixed during film formation. Reactive sputtering is a method of forming thin films of these compounds by chemically reacting them with each other. One method is bias sputtering, in which a voltage is also applied to the substrate.

[0112] The insulating layer 407 may have a laminated structure, for example, a nitride insulating layer and a The nitride insulating layer may have a stacked structure with an oxide insulating layer. , silicon oxynitride (SiN x O y (x>y>0) layer, aluminum nitride An oxide insulating layer can be an aluminum layer, an aluminum nitride oxide layer, or the like. a silicon oxynitride layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer etc. can be used.

[0113] For example, a high-purity sputtering gas containing nitrogen and from which hydrogen and moisture have been removed is introduced. A silicon nitride layer is formed on the substrate using a cone target, and an oxide layer is formed on the silicon nitride layer. In this case, as with the silicon oxide layer, the remaining silicon in the processing chamber is It is preferable to form the silicon nitride layer while removing moisture.

[0114] When forming the silicon nitride layer, the substrate 400 may also be heated.

[0115] When a silicon nitride layer and a silicon oxide layer are stacked as the insulating layer 407, forming a silicon nitride layer and a silicon oxide layer using a common silicon target in First, a sputtering gas containing nitrogen is introduced to the silicon wafers installed in the processing chamber. A silicon nitride layer is formed using a silicon nitride target, and then the sputtering gas is changed to a gas containing oxygen. Switch to sputtering gas and form silicon oxide layer using the same silicon target This allows the silicon nitride layer and the silicon oxide layer to be formed without exposing the substrate 400 to the atmosphere. Since the silicon nitride layer can be formed continuously, impurities such as hydrogen and moisture on the surface of the silicon nitride layer can be prevented. This can prevent the adsorption of

[0116] Next, an oxide semiconductor film is formed over the insulating layer 407 to a thickness of 2 nm to 200 nm.

[0117] In order to prevent hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor film as much as possible, As a pretreatment, the substrate 400 on which the insulating layer 407 is formed is placed in a preheating chamber of a sputtering device. The substrate 400 is preheated at 1000 K to desorb impurities such as hydrogen and moisture adsorbed on the substrate 400 and then exhausted. As the exhaust means provided in the preheating chamber, for example, a cryopump is preferable. It is preferable to omit this preheating process. This may be performed on the substrate 400 before the formation of the gate insulating layer 402 to be formed later, or on the substrate 400 before the formation of the gate insulating layer 402 to be formed later. The same process was carried out on the substrate 400 on which the source electrode layer 415a and the drain electrode layer 415b had been formed. That's fine.

[0118] Before the oxide semiconductor film was formed by a sputtering method, argon gas was introduced. Reverse sputtering is performed to generate plasma, and the film formed during film formation adhered to the surface of the insulating layer 407 is It is preferable to remove the powdery material (also called particles or dust) that is generated. This means that no voltage is applied to the target side, and a high frequency power supply is used on the substrate side in an argon atmosphere. This is a method of modifying the surface by applying a voltage to generate plasma near the substrate. Instead of the argon atmosphere, nitrogen, helium, oxygen, etc. may be used.

[0119] The oxide semiconductor film can be formed by a sputtering method. Examples of such films include In-Sn-Ga-Zn-O, which is a quaternary metal oxide, and ternary metal oxide, In-Ga-Zn-O film, In-Sn-Zn-O film, In-Al-Zn-O film, Sn- Ga-Zn-O film, Al-Ga-Zn-O film, Sn-Al-Zn-O film, and binary metal oxide film In-Zn-O film, Sn-Zn-O film, Al-Zn-O film, Zn-Mg-O film, which are oxides , Sn-Mg-O film, In-Mg-O film, In-Sn-O film, In-O film, Sn-O film In addition, an oxide semiconductor film such as a Zn—O film can be used. SiO2 may be included.

[0120] In addition, as an oxide semiconductor film, InMO3(ZnO) m Using a membrane expressed as (m>0) Here, M can be one or more selected from Ga, Al, Mn, and Co. Indicates a metal element. For example, M can be Ga, Ga and Al, Ga and Mn, or Ga and C. Examples include o.

[0121] In this embodiment, as an example, an oxide semiconductor film is formed using an In—Ga—Zn—O-based metal oxide substrate. The oxide semiconductor film is formed by a sputtering method using a target. Typically, under an atmosphere of argon, oxygen, or a rare gas (typically argon) and oxygen. The film can be formed by sputtering in a nitrogen-mixed atmosphere. When using the ring method, a target containing 2% to 10% by weight of SiO2 is used. Film formation may also be performed.

[0122] The sputtering gas used in forming the oxide semiconductor film may be hydrogen, water, a hydroxyl group, or a fluorine-containing gas. is a high-purity gas in which impurities such as hydrides have been removed to concentrations of ppm or ppb. It is preferable to use

[0123] The oxide semiconductor film is formed by sputtering using a target containing In, Ga and a metal oxide target containing Zn (composition ratio: In2O3:Ga2O3:Zn O=1:1:1 [mol%] or In:Ga:Zn=1:1:0.5 [atom%]) It should be noted that the total volume of the metal oxide target to be produced is The volume ratio (also called the filling rate) of the volume of the material excluding the space occupied by voids, etc. is 90 % or more, preferably 95% or more. A metal oxide target with a high filling rate is used. As a result, the formed oxide semiconductor film becomes a dense film.

[0124] In this embodiment, as an example, the substrate is held in a processing chamber maintained in a reduced pressure state. The remaining moisture in the metal is removed and a sputtering gas from which hydrogen and moisture have been removed is introduced. An oxide semiconductor film is formed on the substrate 400 using an oxide as a target. To remove the residue, it is preferable to use an adsorption type vacuum pump. Examples of pumps include cryopumps, ion pumps, and titanium sublimation pumps. It is preferable to use a turbo pump with a cold trap as an exhaust means. The deposition chamber evacuated using a cryopump can be, for example, , hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (more preferably compounds containing carbon atoms) Since the oxides formed by film formation in the film formation chamber are exhausted, The concentration of impurities contained in the oxide semiconductor film can be reduced. It may also be heated.

[0125] An example of film formation conditions is: substrate temperature is room temperature, the distance between the substrate and the target is 60 mm, and the pressure is 0. 4 Pa, direct current (DC) power supply 0.5 kW, oxygen and argon (oxygen flow rate 15 sccm: argon The conditions were as follows: a 30 sccm (30 sccm) atmosphere; a pulsed direct current (DC) power supply was used; When used, particles can be reduced and the film thickness distribution can be made uniform. The thickness of the oxide semiconductor film is preferably 5 nm to 30 nm. Since the thickness varies depending on the oxide semiconductor material used, it is sufficient to select an appropriate thickness depending on the material. .

[0126] Next, the oxide semiconductor film is subjected to a first photolithography process to form an island-shaped oxide semiconductor layer 41 2 (see FIG. 7A). The resist mask may be formed by an ink-jet method. When the film is formed by this method, the manufacturing cost can be reduced.

[0127] The oxide semiconductor film may be etched by dry etching or wet etching. The oxide semiconductor film can be etched by dry etching. Both dry etching and wet etching may be used.

[0128] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, for example For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0129] In addition, the etching gas used in dry etching is a gas containing fluorine (fluorine-based Gases such as carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), hydrogen bromide (HBr), or oxygen (O2), or These gases are made by adding rare gases such as helium (He) and argon (Ar). can be used.

[0130] Dry etching methods include, for example, parallel plate RIE (Reactive Ion Etching) tching) method, ICP (Inductively Coupled Plasma) (Inductively coupled plasma) etching method can be used. Etching to the desired processed shape. In order to be able to perform etching, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) The amount of power applied, the temperature of the electrode on the substrate side, etc. are adjusted appropriately.

[0131] The etching solution used for wet etching is, for example, a mixture of phosphoric acid, acetic acid, and nitric acid. In addition, the etching solution used for wet etching is I TO07N (manufactured by Kanto Chemical Co., Ltd.) may also be used.

[0132] In addition, the etching solution after wet etching contains the material removed by etching. The waste etching solution containing the removed material is purified and The material removed by etching may be reused. By recovering and reusing materials such as indium contained in the oxide semiconductor layer from the waste liquid, This allows for efficient use of resources and reduces manufacturing costs.

[0133] In addition, during etching, the desired processing shape can be etched according to the material. The etching conditions (etching solution, etching time, temperature, etc.) are adjusted appropriately.

[0134] In this embodiment, as an example, a solution of a mixture of phosphoric acid, acetic acid, and nitric acid is used as the etching solution. The oxide semiconductor film was processed into an island-shaped oxide semiconductor layer 412 by wet etching. do.

[0135] Next, first heat treatment is performed on the oxide semiconductor layer 412. The temperature of the first heat treatment is 400 The temperature is set to 750°C or higher, preferably 400°C or higher but lower than the strain point of the substrate. The substrate is placed in an electric furnace, which is one of heat treatment apparatuses, and the oxide semiconductor layer is heated in a nitrogen atmosphere. After heat treatment at 450°C for 1 hour in an atmosphere, the sample was oxidized without contact with the air. This first heat treatment prevents water and hydrogen from entering the oxide semiconductor layer, thereby obtaining an oxide semiconductor layer. In this way, the oxide semiconductor layer 412 can be dehydrated or dehydrogenated.

[0136] The atmosphere may be switched to oxygen when the temperature of the heat treatment device is lowered from the heat treatment temperature. When the temperature is lowered and the atmosphere is switched to oxygen, oxygen is replenished to the oxygen vacancies in the oxide semiconductor layer. Oxygen vacancies generate carriers, but when they disappear, the carriers become significantly Therefore, an oxide semiconductor layer with an extremely low carrier concentration can be obtained.

[0137] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat radiation from a heat source such as a resistance heating element. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas such as a rare gas such as argon or nitrogen that does not react with the material to be treated by heat treatment. A gas is used.

[0138] In the first heat treatment, the substrate is placed in an inert gas heated to 650°C to 700°C. After heating for several minutes, the substrate is removed from the inert gas heated to a high temperature and subjected to the GRTA process. GRTA treatment allows high-temperature heat treatment in a short time.

[0139] In the first heat treatment, the atmosphere during the heat treatment (nitrogen, helium, neon, or rare gases such as argon) does not contain water, hydrogen, etc., or The purity of nitrogen or rare gases such as helium, neon, or argon introduced into the treatment equipment , 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. It is preferable to keep the impurity concentration at 1 ppm or less, preferably 0.1 ppm or less.

[0140] The first heat treatment is performed on an oxide semiconductor film before it is processed into an island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is taken out of the heating device and A lithography process is carried out.

[0141] The heat treatment that has the effect of dehydrating and dehydrogenating the oxide semiconductor layer is performed by the oxide semiconductor layer formation. After that, a source electrode layer and a drain electrode layer are stacked on the oxide semiconductor layer, and then a source electrode After forming the gate insulating layer on the gate electrode layer and the drain electrode layer, stomach.

[0142] Next, a conductive film is formed over the insulating layer 407 and the oxide semiconductor layer 412. The conductive film may be formed by sputtering or vacuum deposition. an element selected from chromium, copper, tantalum, titanium, molybdenum, and tungsten, An alloy containing the element as the main component, or an alloy film combining the above elements, etc. can be used. The conductive film can be made of manganese, magnesium, zirconium, beryllium, Alternatively, a material selected from one or more of aluminum and yttrium may be used. The film may have a single layer structure or a laminated structure of two or more layers. A single layer structure of aluminum film containing aluminum alloy is also available. Two-layer structure with titanium film laminated on aluminum film, titanium film and aluminum film overlapping the titanium film. Examples include a three-layer structure with an aluminum film and a titanium film on top of that. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium A film made of a single or multiple combinations of elements selected from the group consisting of aluminum, alloy film, or nitride film is used. That's fine.

[0143] Next, a resist mask is formed over the conductive film by a second photolithography process. After etching to form the source electrode layer 415a and the drain electrode layer 415b, The resist mask is removed (see FIG. 7B). The drain electrode layer 415b preferably has a tapered edge. As a result, a gate insulating layer is stacked on the source electrode layer 415a and the drain electrode layer 415b. This is preferable because it improves the covering property of the film.

[0144] In this embodiment, a titanium film having a thickness of 150 nm is formed by sputtering. A resist mask is formed on the titanium film, and the titanium film is selectively etched to form the source electrode. A layer 415a and a drain electrode layer 415b are formed.

[0145] Note that when the conductive film is etched, the oxide semiconductor layer 412 is removed, and the insulating layer The conductive film and the oxide semiconductor film are selected based on their materials and etching conditions so that the conductive film and the oxide semiconductor film 407 are not exposed. Adjust the conditions accordingly.

[0146] In this embodiment, as an example, a titanium film is used as the conductive film and an I oxide semiconductor film is used as the oxide semiconductor film. An n-Ga-Zn-O oxide semiconductor film was used, and ammonia water (ammonia) was used as an etchant. A mixture of ammonia, water, and hydrogen peroxide is used.

[0147] Note that in the second photolithography step, only a part of the oxide semiconductor layer is etched. In some cases, the oxide semiconductor layer 412 may have a groove (a recess). 15a, a resist mask for forming the drain electrode layer 415b is formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, manufacturing costs can be reduced.

[0148] The exposure to light when forming the resist mask in the second photolithography process is done using ultraviolet light or KrF laser. The source electrode layers adjacent to each other on the oxide semiconductor layer 412 are exposed to the laser beam or ArF laser beam. The width of the gap between the end of the drain electrode layer and the bottom end of the drain electrode layer determines the channel width of the transistor to be formed later. When exposure is performed for a channel length L of less than 25 nm, the channel length L is determined by the Extreme ultraviolet rays have extremely short wavelengths of up to several tens of nanometers. The exposure is performed when forming a resist mask in the second photolithography process. Line exposure has high resolution and a large depth of focus. It is also possible to set the channel length L to 10 nm or more and 1000 nm or less, and the operating speed of the circuit can be improved. This allows for faster switching speeds and extremely small off-state current values, resulting in low power consumption. This can also be achieved.

[0149] Next, the insulating layer 407, the oxide semiconductor layer 412, the source electrode layer 415a, and the drain electrode layer 415b are A gate insulating layer 402 is formed on 15b (see FIG. 7C).

[0150] The gate insulating layer 402 is formed by depositing silicon oxide using a plasma CVD method or a sputtering method. a silicon layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer The gate insulating layer 402 can be formed as a single layer or a stacked layer. In order to prevent a large amount of SiO 2 from being contained, the gate insulating layer 402 is formed by sputtering. When a silicon oxide film is formed by sputtering, for example, For example, a silicon target or a quartz target is used as the target, and Oxygen or a mixed gas of oxygen and argon is used.

[0151] The gate insulating layer 402 may be, for example, HfO x (x>0) can also be used. The gate insulating layer 402 is made of HfO x By using the above, from the oxide semiconductor layer side The leakage current flowing toward the gate electrode can be reduced.

[0152] The gate insulating layer 402 is also covered with an oxide film from the source electrode layer 415a and the drain electrode layer 415b side. Alternatively, a silicon oxide layer and a silicon nitride layer may be stacked. A silicon oxide (SiO) layer with a thickness of 5 nm to 300 nm is used as an insulating layer. x (x>0) and forming a second gate insulating layer on the first gate insulating layer by sputtering. Silicon nitride layer (SiN) with a thickness of 50 nm to 200 nm y (y>0)) to form a film The gate insulating layer may have a thickness of 100 nm. Pa, high frequency power supply 1.5 kW, oxygen and argon (oxygen flow rate 25 sccm: argon flow rate An oxide film with a thickness of 100 nm was deposited by RF sputtering under a 25 sccm (1:1) atmosphere. A silicon layer is formed.

[0153] Next, a resist mask is formed by a third photolithography process, and selective etching is performed. A part of the gate insulating layer 402 is removed by etching to form a source electrode layer 415a and a drain electrode layer 415b. Openings 421a and 421b are formed that reach the layer 415b (see FIG. 7(D)).

[0154] Next, a conductive film is formed over the gate insulating layer 402 and the openings 421a and 421b, and then: The gate electrode layer 411, the wiring layer 414a, and the wiring layer 41 The resist mask 4b may be formed by an ink jet method. If the mask is formed by an inkjet method, the manufacturing cost can be reduced.

[0155] The gate electrode layer 411, the wiring layer 414a, and the wiring layer 414b are made of molybdenum, titanium, and the like. Tantalum, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. It is formed by using any metal material or alloy material containing these as the main component, in a single layer or laminated form. It is possible.

[0156] For example, a two-layer stack structure of a gate electrode layer 411, a wiring layer 414a, and a wiring layer 414b is used. For example, a two-layer structure with a molybdenum layer laminated on an aluminum layer, or a molybdenum layer laminated on a copper layer Two-layer structure with a butane layer laminated on top of a copper layer, and two-layer structure with a titanium nitride layer or tantalum nitride layer laminated on top of a copper layer. A layer structure or a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated is preferred. The three-layer laminate structure is a tungsten layer or a tungsten nitride layer and an aluminum layer. A layer of aluminum-silicon alloy or aluminum-titanium alloy and a layer of titanium nitride or titanium It is preferable that the gate electrode has a laminated structure in which a light-transmitting conductive film is used. A light-transmitting gate electrode layer 411 and wiring layers 414a and 414b can also be formed. The conductive film may be, for example, a transparent conductive oxide.

[0157] In this embodiment, as an example, a titanium film having a thickness of 150 nm is formed by sputtering. A gate electrode layer 411, a wiring layer 414a, and a wiring layer 41 Form 4b.

[0158] Next, a second heat treatment (preferably 200 In this embodiment, the nitrogen is A second heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour. Even if the second heat treatment is performed after forming a protective insulating layer or a planarizing insulating layer on the transistor 410, good.

[0159] Through the above steps, the oxide semiconductor layer 41 in which the concentrations of hydrogen, moisture, hydrides, and hydroxides are reduced is obtained. 7E, a transistor 410 having the same structure as in FIG.

[0160] A protective insulating layer or a planarization insulating layer for planarization may be provided over the transistor 410. For example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, The silicon nitride oxide layer or the aluminum oxide layer can be formed as a single layer or a stacked layer. do.

[0161] The planarization insulating layer may be made of polyimide, acrylic, benzocyclobutene, or polyamide. Heat-resistant organic materials such as epoxy can be used. Other materials include low-k materials, siloxane resins, PSG (phosphor glass), and B It is possible to use PSG (phosphorus boron glass) and other materials. A planarization insulating layer may be formed by stacking a plurality of insulating films.

[0162] The siloxane resin is a Si—O— compound formed using a siloxane material as a starting material. Siloxane resins correspond to resins containing Si bonds. The organic group may contain a fluoro group. It may be possible.

[0163] The method for forming the planarizing insulating layer is not particularly limited, and may be a sputtering method, a SO G method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen Printing methods such as doctor knife, roller printing, and offset printing can also be used. The coating can be formed using a roll coater, curtain coater, knife coater, or the like.

[0164] When forming the oxide semiconductor film as described above, residual moisture in the atmosphere during film formation is removed. This allows the concentration of hydrogen and hydride in the oxide semiconductor film to be reduced, and This makes it possible to stabilize the characteristics of the star.

[0165] As described above, in a DC converter circuit including a transistor including an oxide semiconductor layer, It is possible to provide a highly reliable DC converter circuit having stable electrical characteristics.

[0166] This embodiment mode can be combined with or replaced with any of the other embodiment modes as appropriate.

[0167] (Fourth embodiment) This embodiment can be applied to the transistors that configure the DC converter circuit disclosed in this specification. Other examples of transistors will be described. Note that the same parts as those in the third embodiment or parts having similar functions will be described. The steps and operations may be the same as those in the third embodiment, and the repeated explanations will be omitted as appropriate. Detailed explanations of the same parts will also be omitted as appropriate.

[0168] One embodiment of a transistor and a manufacturing method of the transistor of this embodiment will be described with reference to FIGS. and explain.

[0169] 8(A) and (B) show examples of the planar and cross-sectional structures of a transistor. The transistor 460 shown is one of the top-gate transistors.

[0170] FIG. 8A is a plan view of a transistor 460 having a top-gate structure, and FIG. FIG. 8(B) is a cross-sectional view taken along line D1-D2 in FIG. 8(A).

[0171] The transistor 460 includes an insulating layer 457, a source electrode layer 458, a gate insulating layer 459 ... and the electrode layer 465a1, 465a2 which will be either the drain electrode layer, an oxide semiconductor the layer 462, the electrode layer 465b which will be the other of the source and drain electrode layers, and the wiring layer 468 , a gate insulating layer 452, a gate electrode layer 461 (461a, 461b), and an electrode layer 46 5a (465a1, 465a2) are electrically connected to the wiring layer 464 via the wiring layer 468. Although not shown, the electrode layer 465b is also provided on the gate insulating layer 452. Electrical connection is made to the wiring layer in the opening.

[0172] Hereinafter, a process of manufacturing a transistor 460 on a substrate 450 will be described with reference to FIGS. 9A to 9E. Explain.

[0173] First, an insulating layer 457 serving as a base film is formed over a substrate 450 having an insulating surface.

[0174] In this embodiment, the substrate 450 is transferred to a processing chamber, where hydrogen and moisture are removed and oxygen-containing High purity sputtering gas is introduced and a silicon target or quartz (preferably synthetic quartz) is used. Using the above, a silicon oxide film was deposited on the substrate 450 as an example of an insulating layer 457 by sputtering. The sputtering gas is oxygen or a mixture of oxygen and argon. A mixed gas is used.

[0175] In this embodiment, for example, the purity is 6N, and quartz (preferably synthetic quartz) is used as the target. The substrate temperature was 108°C, and the distance between the substrate and the target (TS distance) was 60 mm. , pressure 0.4 Pa, high frequency power supply 1.5 kW, oxygen and argon (oxygen flow rate 25 sccm: Silicon oxide was deposited by RF sputtering under an argon atmosphere (flow rate 25 sccm = 1:1). The thickness of the silicon oxide film is 100 nm. Instead of quartz, a silicon target is used as a target for depositing silicon oxide film. A cot can be used.

[0176] When the insulating layer 457 is formed using any of the above materials and methods, It is preferable to form the insulating layer 457 while removing residual moisture. This is to prevent the inclusion of acid groups or moisture.

[0177] In order to remove the residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. Examples of adsorption type vacuum pumps include cryopumps, ion pumps, and titanium pumps. It is preferable to use a sublimation pump. A cryopump equipped with a cold trap can be used. The film-forming chamber that has been evacuated contains, for example, hydrogen atoms and compounds containing hydrogen atoms (such as water). Since the gas is exhausted, the concentration of impurities contained in the insulating layer 457 is can be reduced.

[0178] The sputtering gas used in forming the insulating layer 457 may be hydrogen, water, a hydroxyl group, or High-purity gas in which impurities such as hydrides have been removed to concentrations of ppm or ppb. It is preferable to use

[0179] The insulating layer 457 may have a laminated structure. For example, the insulating layer 457 may have a nitride insulating layer and an oxide insulating layer from the substrate 450 side. The nitride insulating layer may be a laminated structure in which it is laminated with a silicon nitride insulating layer. a silicon nitride layer, a silicon oxide nitride layer, an aluminum nitride layer, or an aluminum oxide nitride layer, etc. The oxide insulating layer can be a silicon oxide layer, a silicon oxynitride layer, or an oxide An aluminum layer, an aluminum oxynitride layer, or the like can be used.

[0180] For example, a high-purity sputtering gas containing nitrogen and from which hydrogen and moisture have been removed is introduced. A silicon nitride layer is formed on the substrate using a cone target, and an oxide layer is formed on the silicon nitride layer. In this case, as with the silicon oxide layer, the remaining silicon in the processing chamber is It is preferable to form the silicon nitride layer while removing moisture.

[0181] Next, a conductive film is formed over the insulating layer 457 and is then subjected to a first photolithography process. A resist mask is formed on the electrode layers 465a1 and 465a2, and selective etching is performed. After forming the electrode layers 465a1 and 465b2, the resist mask is removed (see FIG. 9A). Although 65a2 is shown as being divided in the cross-sectional view, it is a continuous film. When the ends of the source electrode layer and the drain electrode layer are tapered, the gate insulating layer stacked thereon can be formed in a tapered shape. This is preferable because it improves the covering property of the film.

[0182] The material of the electrode layers 465a1 and 465a2 may be aluminum, chromium, copper, tantalum, An element selected from titanium, molybdenum, and tungsten, or an alloy containing the above elements as the main component Alternatively, an alloy film combining the above elements can be used. Materials for 5a1 and 465a2 include manganese, magnesium, zirconium, and beryllium. Alternatively, a material selected from one or more of aluminum and yttrium may be used. The film may have a single layer structure or a laminated structure of two or more layers. A single layer structure of aluminum film containing silicon is also available. A two-layer structure in which a titanium film is laminated on an aluminum film, and a titanium film and an aluminum film are laminated on top of the titanium film. Examples include a three-layer structure in which a titanium film is deposited on top of a tungsten film. , aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, A film of a single or a combination of elements selected from scandium, It is also possible to use an alloy film in which several elements are combined, or a nitride film in which one or more of the elements are combined. good.

[0183] In this embodiment, the electrode layers 465a1 and 465a2 are formed by sputtering to a thickness of 15 A 0 nm titanium film is formed.

[0184] Next, an oxide semiconductor film is formed over the insulating layer 457 to a thickness of 2 nm to 200 nm.

[0185] Next, an oxide semiconductor film is formed, and an island-shaped oxide semiconductor is formed by a second photolithography process. The oxide semiconductor film is processed into a layer 462 (see FIG. 9B). The film is formed by sputtering using a Ga-Zn-O metal oxide target.

[0186] In this embodiment, as an example, the substrate is held in a processing chamber maintained in a reduced pressure state. The remaining moisture in the metal is removed and a sputtering gas from which hydrogen and moisture have been removed is introduced. An oxide semiconductor film is formed on the substrate 450 using an oxide as a target. To remove the residue, it is preferable to use an adsorption type vacuum pump. Examples of pumps include cryopumps, ion pumps, and titanium sublimation pumps. As an exhaust means, a turbo pump equipped with a cold trap is preferably used. The deposition chamber evacuated using a cryopump can be filled with, for example, water. Compounds containing hydrogen atoms, such as water (H2O), are more preferably compounds containing carbon atoms. Since the gases such as fluorine and fluorine are exhausted from the deposition chamber, the oxide semiconductor film is formed in the deposition chamber. The concentration of impurities contained in the oxide semiconductor film can be reduced. .

[0187] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, or High purity impurities such as acid groups or hydrides have been removed to concentrations of ppm or ppb. It is preferable to use a high-temperature gas.

[0188] An example of film formation conditions is: substrate temperature is room temperature, the distance between the substrate and the target is 60 mm, and the pressure is 0. 4 Pa, direct current (DC) power supply 0.5 kW, oxygen and argon (oxygen flow rate 15 sccm: argon The conditions were as follows: a 30 sccm (30 sccm) atmosphere; a pulsed direct current (DC) power supply was used; When used, particles can be reduced and the film thickness distribution can be made uniform. The thickness of the oxide semiconductor film is preferably 5 nm to 30 nm. Since the thickness varies depending on the oxide semiconductor material used, it is sufficient to select an appropriate thickness depending on the material. .

[0189] In this embodiment, as an example, a solution of a mixture of phosphoric acid, acetic acid, and nitric acid is used as the etching solution. The oxide semiconductor film was processed into an island-shaped oxide semiconductor layer 462 by wet etching. do.

[0190] Next, first heat treatment is performed on the oxide semiconductor layer 462. The first heat treatment is performed at a temperature of 400 The temperature is set to 750°C or higher, preferably 400°C or higher but lower than the strain point of the substrate. The substrate is placed in an electric furnace, which is one of heat treatment apparatuses, and the oxide semiconductor layer is heated in a nitrogen atmosphere. After heat treatment at 450°C for 1 hour in an atmosphere, the sample was oxidized without contact with the air. This first heat treatment prevents water and hydrogen from entering the oxide semiconductor layer, thereby obtaining an oxide semiconductor layer. In this way, the oxide semiconductor layer 462 can be dehydrated or dehydrogenated.

[0191] The atmosphere may be switched to oxygen when the temperature of the heat treatment device is lowered from the heat treatment temperature. When the temperature is lowered and the atmosphere is switched to oxygen, oxygen is replenished to the oxygen vacancies in the oxide semiconductor layer. Oxygen vacancies generate carriers, but when they disappear, the number of carriers decreases significantly. In this way, an oxide semiconductor layer with an extremely low carrier concentration can be obtained.

[0192] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat radiation from a heat source such as a resistance heating element. The apparatus may be equipped with a device for heating the object to be treated by irradiation. For example, a GRTA apparatus, an LR apparatus, etc. For example, a 65°C RTA apparatus can be used as the first heat treatment. The substrate is placed in an inert gas atmosphere heated to a temperature between 0°C and 700°C, and after heating for several minutes, the substrate is GRTA can also be performed by moving the plate and removing it from the inert gas heated to a high temperature. The use of this method makes it possible to perform high-temperature heat treatment in a short time.

[0193] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. The purity of rare gases such as helium, neon, and argon is 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., 1 ppm or less, preferably It is preferable to keep the concentration below 0.1 ppm.

[0194] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. The substrate is taken out and subjected to a photolithography process.

[0195] The heat treatment that has the effect of dehydrating and dehydrogenating the oxide semiconductor layer is performed by the oxide semiconductor layer formation. After the formation, a source electrode layer and a drain electrode layer are further laminated on the oxide semiconductor layer, and then the source electrode layer is After forming the gate insulating layer on the source electrode layer and the drain electrode layer, It is also possible.

[0196] Next, a conductive film is formed over the insulating layer 457 and the oxide semiconductor layer 462, and then a conductive film is formed by a third photolithography process. A resist mask is formed on the conductive film by a lithography process, and selective etching is performed to form the conductive film. After the electrode layer 465b and the wiring layer 468 are formed, the resist mask is removed (see FIG. 9(C)). The electrode layer 465b and the wiring layer 468 are made of the same material and process as the electrode layers 465a1 and 465a2. It is sufficient to form it in this order.

[0197] In this embodiment, as an example, a titanium film having a thickness of 150 nm is formed by sputtering. Then, a resist mask is formed on the titanium film by a third photolithography process. The electrode layer 465b and the wiring layer 468 are formed by etching. Since the same titanium film is used for the pole layers 465a1, 465a2 and the electrode layer 465b, The etching selectivity between 465a1, 465a2 and the electrode layer 465b is not good. Therefore, the electrode layers 465a1 and 465a2 are etched when the electrode layer 465b is etched. The wiring layer 468 is formed on the electrode layer 465a2 that is not covered with the oxide semiconductor layer 462 so as to prevent the wiring layer 468 from being covered with the oxide semiconductor layer 462. The electrode layers 465a1, 465a2 and the electrode layer 465b are provided with a thin film in an etching process. When a different material having a high selectivity is used, the electrode layer 465a2 is The protective wiring layer 468 does not necessarily have to be provided.

[0198] Note that the conductive film is etched so that the oxide semiconductor layer 462 is not removed. The materials and etching conditions for the oxide semiconductor film and the oxide semiconductor film are adjusted as appropriate.

[0199] In this embodiment, as an example, a titanium film is used as the conductive film and an I oxide semiconductor film is used as the oxide semiconductor film. An n-Ga-Zn-O oxide semiconductor film was used, and ammonia water (ammonia) was used as an etchant. A mixture of ammonia, water, and hydrogen peroxide is used.

[0200] Note that in the third photolithography step, part of the oxide semiconductor layer 462 is etched. In this case, the oxide semiconductor layer 462 may have a groove (depression). b. A resist mask for forming the wiring layer 468 may be formed by an ink-jet method. When a resist mask is formed using the inkjet method, no photomask is used, so manufacturing Costs can be reduced.

[0201] Next, the insulating layer 457, the oxide semiconductor layer 462, the electrode layers 465a1 and 465a2, and the electrode layer 465a1 are 65b, a gate insulating layer 452 is formed on the wiring layer 468.

[0202] The gate insulating layer 452 is formed by depositing silicon oxide using a plasma CVD method or a sputtering method. a silicon layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer The gate insulating layer 452 can be formed as a single layer or a stacked layer. In order to prevent a large amount of SiO 2 from being contained, the gate insulating layer 452 is formed by sputtering. When a silicon oxide film is formed by sputtering, for example, For example, a silicon target or a quartz target is used as the target, and the sputtering gas The heating is carried out using oxygen or a mixed gas of oxygen and argon.

[0203] The gate insulating layer 452 may be, for example, HfO x Gate HfO as insulating layer 452 x By using the above, the gate electrode can be formed from the oxide semiconductor layer side. This can reduce the leakage current flowing toward the

[0204] The gate insulating layer 452 is made of silicon oxide from the electrode layer 465a1, 465a2, and electrode layer 465b side. It is also possible to use a structure in which a silicon layer and a silicon nitride layer are stacked. The pressure was 0.4 Pa, the high frequency power was 1.5 kW, and oxygen and argon (oxygen flow rate 25 sccm) A 1000-membrane film was deposited by RF sputtering under an argon atmosphere (flow rate: 25 sccm = 1:1). Form a 0 nm silicon oxide layer.

[0205] Next, a resist mask is formed by a fourth photolithography process, and selective etching is performed. A part of the gate insulating layer 452 is removed by etching to form an opening 423 that reaches the wiring layer 468. Although not shown, when the opening 423 is formed, the electrode layer 465b In this embodiment, for example, an opening to the electrode layer 465b may be formed. Furthermore, an example in which an interlayer insulating layer is formed after laminating, and an electrically connecting wiring layer is formed in the opening is also available. do.

[0206] Next, a conductive film is formed over the gate insulating layer 452 and the opening 423, and then a fifth photolithography is performed. A gate electrode layer 461 (461a, 461b) and a wiring layer 464 are formed by a photolithography process. The resist mask may be formed by an ink-jet method. Forming it by the coujet method can reduce manufacturing costs.

[0207] Also, a conductive layer for forming the gate electrode layer 461 (461a, 461b) and the wiring layer 464 is formed. The film is made of molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, A single layer is made of metal materials such as zinc and scandium, or alloy materials that contain these as the main components. Alternatively, it can be formed by laminating.

[0208] In this embodiment, as an example, a titanium film having a thickness of 150 nm is formed by sputtering. Then, gate electrode layers 461a and 461b and wiring layer 46 are formed by a fifth photolithography method. Form 4.

[0209] Next, a second heat treatment (preferably 200 In this embodiment, the nitrogen is A second heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour. This may be performed after forming a protective insulating layer or a planarizing insulating layer.

[0210] Through the above steps, the oxide semiconductor layer 46 in which the concentrations of hydrogen, moisture, hydrides, and hydroxides are reduced is obtained. A transistor 460 having 2 can be formed (see FIG. 9E).

[0211] A protective insulating layer or a planarization insulating layer for planarization may be provided over the transistor 460. Although not shown, the gate insulating layer 452, the protective insulating layer, and the planarizing insulating layer are covered with the electrode layer 46. An opening is formed in the insulating layer 460, reaching the insulating layer 460b, and a wiring layer is formed in the opening to be electrically connected to the electrode layer 465b. Complete.

[0212] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0213] As described above, when forming an oxide semiconductor film, it is necessary to remove residual moisture in the atmosphere during film formation. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced. This can stabilize the oxide semiconductor film.

[0214] As described above, in a DC converter circuit including a transistor including an oxide semiconductor layer, It is possible to provide a highly reliable DC converter circuit having stable electrical characteristics.

[0215] (Embodiment 5) This embodiment can be applied to a transistor included in a DC converter circuit according to one embodiment of the present invention. An example of such a transistor will be described. The components or parts having similar functions and steps are the same as those in the third or fourth embodiment. The detailed explanation of the same points will be omitted as appropriate. do.

[0216] An example of a transistor of this embodiment will be described with reference to FIGS.

[0217] 10(A) and 10(B) show examples of cross-sectional structures of transistors. The transistors 425 and 426 have a structure in which an oxide semiconductor layer is sandwiched between a conductive layer and a gate electrode layer. It is one of the transistors.

[0218] In addition, in FIGS. 10(A) and 10(B), a silicon substrate is used as the substrate. Transistors 425 and 426 are provided on an insulating layer 422 provided on a plate 420. It is being done.

[0219] In FIG. 10A, an insulating layer 422 and an insulating layer 407 are provided on a silicon substrate 420. A conductive layer 427 is provided between the oxide semiconductor layer 412 and the conductive layer 427 so as to overlap with at least the entire oxide semiconductor layer 412. do.

[0220] 10B, the conductive layer between the insulating layer 422 and the insulating layer 407 is the conductive layer 424. The oxide semiconductor layer 412 is processed by etching so as to have a thickness including at least a channel region. This is an example that overlaps with part of the

[0221] The conductive layers 427 and 424 can be made of any metal material that can withstand the heat treatment temperature in the subsequent process. Commonly, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium or an alloy containing the above elements or a combination of the above elements An alloy film or a nitride containing the above-mentioned element as a component can be used. 427 and 424 may be a single layer structure or a laminated structure, for example, a single layer of tungsten or a nitride layer. The tungsten nitride layer may have a laminated structure in which a tungsten nitride layer and a tungsten layer are laminated.

[0222] The conductive layers 427 and 424 have potentials different from the gate electrode layers 41 of the transistors 425 and 426. It may be the same as or different from the first gate electrode layer, and may also function as the second gate electrode layer. The potential of the conductive layers 427 and 424 may be a fixed potential such as GND or 0V. stomach.

[0223] The conductive layers 427 and 424 control the electrical characteristics of the transistors 425 and 426. can be done.

[0224] In addition, the present invention is not limited to the structure in which the second gate electrode layer is formed by providing a conductive layer. For example, when a semiconductor substrate is used as the substrate, the substrate is thermally oxidized to form a film on the substrate. The formed region can also function as a second gate electrode layer.

[0225] This embodiment mode can be combined with or replaced with any of the other embodiment modes as appropriate.

[0226] (Sixth embodiment) In this embodiment, a transistor that can be used in a DC converter circuit according to one embodiment of the present invention will be described. An example of a transistor that can be used will be described below.

[0227] An example of a transistor and a manufacturing method of the transistor of this embodiment will be described with reference to FIGS. explain.

[0228] An example of a method for manufacturing a transistor is shown in FIGS. The transistor shown in Figure 1 has a bottom gate structure and is also called an inverted staggered transistor. cormorant.

[0229] The transistor 390 has a single gate structure. The transistor is a multi-gate transistor having a plurality of channel formation regions. That's fine.

[0230] 11A to 11E, a process for fabricating a transistor 390 on a substrate 394 will be described. Explain the process.

[0231] First, a conductive film is formed on a substrate 394 having an insulating surface, and then a first photolithography is performed. A resist mask is formed on the conductive film by a process, and the conductive film is selectively etched. In this way, a gate electrode layer 391 is formed. Note that the end of the gate electrode layer 391 is tapered. When the end of the gate electrode layer 391 is tapered, the gate electrode layer 391 can be easily stacked on top of the gate electrode layer 391. The resist mask is formed by the inkjet method. If the resist mask is formed by an inkjet method, the manufacturing cost can be reduced. .

[0232] There is no significant limitation on the substrate that can be used for the substrate 394 having an insulating surface, but at least In any case, the substrate 394 must have heat resistance to a degree that it can withstand the heat treatment. For example, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass is used. It can be used.

[0233] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. Alternatively, a substrate made of an insulating material may be used. Alternatively, a substrate made of a crystallized glass may be used. A semiconductor substrate such as silicon may also be used as the substrate. A solid substrate may also be used.

[0234] In addition, an insulating film serving as a base film may be provided between the substrate 394 and the gate electrode layer 391. The base film has a function of preventing the diffusion of impurity elements from the substrate 394, and is a silicon nitride film, an oxide film, or the like. a silicon nitride film, a silicon oxide nitride film, or a silicon oxynitride film; It can be formed by a laminated structure of films.

[0235] The material of the gate electrode layer 391 is molybdenum, titanium, chromium, tantalum, or tungsten. Metallic materials such as zinc, aluminum, copper, neodymium, scandium, etc., or materials containing these as the main components The insulating film 10 can be formed as a single layer or a stacked layer using an alloy material.

[0236] For example, the two-layer stack structure of the gate electrode layer 391 is a molybdenum layer stacked on an aluminum layer. Two-layer laminated structure with a molybdenum layer on a copper layer, two-layer structure with a titanium nitride layer on a copper layer Two-layer structure with a titanium nitride layer or a tantalum nitride layer laminated, and a titanium nitride layer and a molybdenum layer laminated or a two-layer structure in which a tungsten nitride layer and a tungsten layer are laminated. The three-layer laminated structure is preferably a tungsten layer or a tungsten nitride layer and an aluminum layer. A layer of aluminum-silicon alloy or aluminum-titanium alloy, a layer of titanium nitride or titanium, It is preferable that the gate electrode be formed by stacking a light-transmitting conductive film. A layer 391 can also be formed. As the light-transmitting conductive film, a light-transmitting conductive oxide can be used. Examples of such things can be given.

[0237] Next, a gate insulating layer 397 is formed on the gate electrode layer 391 .

[0238] Here, the oxide semiconductor (high-temperature) that has been made i-type or substantially i-type by removing impurities is Since the gate electrode (a purified oxide semiconductor) is extremely sensitive to the interface state and the interface charge, The interface between the gate insulating layer and the highly purified oxide semiconductor layer is important. The insulating layer (GI) is required to be of high quality.

[0239] For example, high density plasma CVD using microwaves (2.45 GHz) produces dense, high dielectric strength films. It is preferable to form a highly purified oxide semiconductor layer and a high-quality gate insulating film. By closely contacting the gate insulating layer, the interface state can be reduced and the interface characteristics can be improved. The high density plasma device used here is 1×10 11 / cm 3 Any device capable of achieving the above plasma density can be used.

[0240] For example, a microwave power of 3 kW to 6 kW is applied to generate plasma, and the insulating film is formed. The chamber is filled with monosilane gas (SiH4) and nitrous oxide (N2 O) and rare gas are introduced to generate high-density plasma under a pressure of 10 Pa to 30 Pa. An insulating film is formed on a substrate having an insulating surface such as a silicon dioxide gas. Nitrous oxide (N2O) and rare gases are introduced without exposing the insulating film to the atmosphere. Plasma treatment may be performed. At least nitrous oxide (N2O) and rare gases are introduced to provide insulation. The plasma treatment on the film surface is carried out after the insulating film is formed. The flow ratio of silane gas (SiH4) to nitrous oxide (N2O) is 1:10 to 1:20. The rare gas introduced into the chamber is helium, argon, Lipton, xenon, etc. can be used, but argon is the most inexpensive. It is preferable that:

[0241] Of course, if a good insulating film can be formed as the gate insulating layer 397, sputtering is also possible. Other film formation methods such as the ring method and plasma CVD method can be applied. The insulating film is one whose film quality and interface characteristics with the oxide semiconductor are improved by heat treatment. In any case, it goes without saying that the quality of the film as a gate insulating film is good. Any material may be used as long as it can reduce the interface state density with the oxide semiconductor and form a good interface.

[0242] For example, at 85°C, 2 x 10 6 V / cm, 12-hour gate bias thermal stress test (B In the T test, when impurities are added to an oxide semiconductor, the impurities and the oxide semiconductor The bonds between the main component of the compound are broken by a strong electric field (B: bias) and high temperature (T: temperature), The dangling bonds induce a drift in the threshold voltage (Vth). The transistor used in the DC converter circuit of one embodiment of the present invention is a transistor containing an oxide semiconductor. In order to improve the interface characteristics with the gate insulating layer, hydrogen and water must be removed as much as possible. This makes it possible to obtain a stable transistor even in BT tests.

[0243] The gate insulating layer 397 may be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. a silicon nitride layer, a silicon oxide nitride layer, or an aluminum oxide layer, formed as a single layer or a stacked layer; can be done.

[0244] The gate insulating layer 397 may be formed of, for example, HfO x Gate HfO as insulating layer 397 x By using the above, the gate electrode can be formed from the oxide semiconductor layer side. This can reduce the leakage current flowing toward the

[0245] The gate insulating layer 397 may have a structure in which a silicon oxide layer and a silicon nitride layer are stacked. In this embodiment, as an example, a high density microwave is generated at a pressure of 30 Pa and a microwave power of 6 kW. A silicon oxynitride layer with a thickness of 100 nm is formed by plasma CVD. The flow rate ratio of monosilane gas (SiH4) and nitrous oxide (N2O) introduced into the chamber is: The range is 1:10 to 1:200.

[0246] In addition, the gate insulating layer 397 and the oxide semiconductor film 393 contain hydrogen, a hydroxyl group, and moisture as much as possible. In order to prevent the gate electrode layer 391 from being broken, the substrate on which the gate electrode layer 391 is formed is treated as a pre-treatment for the film formation. 394, or the substrate 394 on which the gate insulating layer 397 has been formed, is pre-sputtered by a sputtering device. Preheating is performed in a preheating chamber to remove impurities such as hydrogen and moisture adsorbed on the substrate 394, and then exhaust The preheating temperature is preferably 100°C or higher and 400°C or lower. The temperature is 150°C or more and 300°C or less. The exhaust means provided in the preheating chamber may be, for example: A cryopump is preferable. However, this preheating process can be omitted. The preheating was performed after forming the source electrode layer and the drain electrode layer before forming the oxide insulating layer. Substrate 394 may be treated similarly.

[0247] Next, an oxide semiconductor film 393 with a thickness of 2 nm to 200 nm is formed over the gate insulating layer 397. (See FIG. 11(A)).

[0248] Note that before the oxide semiconductor film 393 was formed, argon gas was introduced to generate plasma. Then, particles adhering to the surface of the gate insulating layer 397 are removed by reverse sputtering. It is preferable to remove it.

[0249] The oxide semiconductor film 393 is formed by, for example, a sputtering method. Examples include quaternary metal oxide films such as In-Sn-Ga-Zn-O and ternary metal oxide films. In-Ga-Zn-O film, In-Sn-Zn-O film, In-Al-Zn-O film, S n-Ga-Zn-O film, Al-Ga-Zn-O film, Sn-Al-Zn-O film, and binary metal Metal oxide films such as In-Zn-O, Sn-Zn-O, Al-Zn-O, and Zn-Mg- O film, Sn-Mg-O film, In-Mg-O film, In-Sn-O film, In-O film, Sn- Oxide semiconductor films such as O films and Zn—O films can be used. The film may contain SiO2.

[0250] The oxide semiconductor film 393 is made of InMO3(ZnO). m (m>0) Here, M is one or more selected from Ga, Al, Mn, and Co. indicates multiple metal elements. For example, M can be Ga, Ga and Al, Ga and Mn, or G Examples include a and Co.

[0251] In this embodiment, as an example, the oxide semiconductor film 393 is formed of an In—Ga—Zn—O-based metal oxide. The oxide semiconductor film 393 is formed by a sputtering method using an oxide target. , in a rare gas (typically argon) atmosphere, in an oxygen atmosphere, or in a rare gas (typically argon) atmosphere. It can be formed by sputtering in an atmosphere of fluorine and oxygen. When using a sputtering method, a target containing 2% to 10% by weight of SiO2 The film may be formed using the following.

[0252] In addition, an oxide semiconductor film 393 is formed by a sputtering method using an oxide semiconductor film. A target of a metal oxide containing zinc oxide as a main component can be used. Other examples of such targets include metal oxide targets (compositions) containing In, Ga, and Zn. The composition ratio is In2O3:Ga2O3:ZnO=1:1:1 [mol%], In:Ga Zn=1:1:0.5[atom%]) can be used as a metal oxide target. The filling rate of the metal oxide target is 90% or more, preferably 95% or more. By using the oxide semiconductor film, the oxide semiconductor film formed becomes dense.

[0253] In this embodiment, as an example, the substrate is held in a processing chamber maintained in a reduced pressure state. The process is heated to room temperature or a temperature below 400° C. Then, hydrogen is introduced into the process chamber while removing the remaining moisture. A sputtering gas from which moisture has been removed is introduced, and a metal oxide is used as a target to sputter the substrate. An oxide semiconductor film 393 is formed on the substrate 394. In order to remove residual moisture in the treatment chamber, It is preferable to use an adsorption type vacuum pump. It is preferable to use a lion pump, an ion pump, or a titanium sublimation pump. As the exhaust means, for example, a turbo pump equipped with a cold trap is used. The film formation chamber evacuated using a cryopump contains, for example, hydrogen atoms, water (H2 O) and other compounds containing hydrogen atoms (and more preferably compounds containing carbon atoms) are excluded. Therefore, by forming the oxide semiconductor film in the deposition chamber, the concentration of impurities contained in the oxide semiconductor film is reduced. In addition, the cryopump removes the moisture remaining in the processing chamber while the By performing sputtering, the substrate temperature during the deposition of the oxide semiconductor film 393 can be adjusted from room temperature to The temperature can be from 100°C to less than 400°C.

[0254] An example of the film formation conditions is a distance between the substrate and the target of 60 mm, a pressure of 0.6 Pa, and a direct current ( The conditions are DC power supply 0.5kW and oxygen atmosphere (oxygen flow rate 100%). In addition, by using a pulsed direct current (DC) power supply, particles can be reduced and the film thickness distribution becomes uniform. The thickness of the oxide semiconductor film is preferably 5 nm to 30 nm. Note that the appropriate thickness of the oxide semiconductor film varies depending on the oxide semiconductor material used. The thickness may be selected appropriately depending on the material.

[0255] Next, the oxide semiconductor film is subjected to a second photolithography process to form an island-shaped oxide semiconductor layer 39 9 (see FIG. 11B). The resist mask may be formed by an ink-jet method. Forming it by the PET method can reduce manufacturing costs.

[0256] In addition, when a contact hole is formed in the gate insulating layer 397, the process is performed using an oxide semiconductor This can be done when layer 399 is formed.

[0257] Note that the oxide semiconductor film 393 can be etched by dry etching or wafer etching. The oxide semiconductor film 393 can be etched by hot etching. Both dry etching and wet etching may be used.

[0258] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, for example For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0259] In addition, the etching gas used in dry etching is a gas containing fluorine (fluorine-based Gases such as carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), hydrogen bromide (HBr), or oxygen (O2), or These gases are made by adding rare gases such as helium (He) and argon (Ar). can be used.

[0260] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired processed shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0261] The etching solution used for wet etching is, for example, a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0262] In addition, after wet etching, the etching solution is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium and other components contained in the oxide semiconductor layer may be extracted from the waste liquid after etching. By recovering and reusing materials, we can make effective use of resources and reduce costs. do.

[0263] In addition, during etching, the desired processing shape can be etched according to the material. The etching conditions (etching solution, etching time, temperature, etc.) are adjusted appropriately.

[0264] In this embodiment, reverse sputtering is performed before forming a conductive film in the next step, and oxidation is performed. Resist residues adhering to the surfaces of the compound semiconductor layer 399 and the gate insulating layer 397 are removed. It is preferable to do so.

[0265] Next, a conductive film is formed over the gate insulating layer 397 and the oxide semiconductor layer 399. The conductive film can be formed by sputtering or vacuum deposition. an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; Alternatively, an alloy containing the above elements or an alloy film made of a combination of the above elements may be used. The conductive film can be made of manganese, magnesium, zirconium, or the like. Alternatively, a material selected from one or more of the following may be used: SiO 2 , beryllium, and yttrium. The conductive film may have a single layer structure or a stacked structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon can be used. The titanium film is laminated on the aluminum film, or the titanium film is laminated on the titanium film. Examples include a three-layer structure in which an aluminum film is laminated on top of the aluminum film and a Ti film is then formed on top of that. In addition, titanium, tantalum, tungsten, molybdenum, chromium, nickel, a film of a single element selected from the group consisting of chromium, chromium, and scandium, or a combination of multiple elements; or an alloy film in which a plurality of elements are combined, or a nitride film in which a single element or a plurality of elements are combined It may be used.

[0266] Next, a resist mask is formed over the conductive film by a third photolithography process. After etching the source electrode layer 395a and the drain electrode layer 395b, Remove the dysplasia mask (see Figure 11(C)).

[0267] The third photolithography process involves exposure to ultraviolet light or KrF laser light when forming a resist mask. The source electrode layer is formed on the oxide semiconductor layer 399. The width of the gap between the end of the drain electrode layer and the bottom end of the drain electrode layer determines the channel width of the transistor to be formed later. When exposure is performed for a channel length L of less than 25 nm, the channel length L is determined by the Extreme ultraviolet rays have extremely short wavelengths of up to several tens of nanometers. The third photolithography step is performed using ultraviolet light to form a resist mask. Line exposure has high resolution and a large depth of focus. It is also possible to set the channel length L to 10 nm or more and 1000 nm or less, and the operating speed of the circuit can be improved. This allows for faster switching speeds and extremely small off-state current values, which also contributes to lower power consumption. can be done.

[0268] Note that the conductive film is etched so that the oxide semiconductor layer 399 is not removed. The materials and etching conditions for the oxide semiconductor film and the oxide semiconductor film are adjusted as appropriate.

[0269] In this embodiment, for example, a titanium film is used as the conductive film, and the oxide semiconductor layer 399 is An In-Ga-Zn-O oxide semiconductor layer was used as the etchant, and ammonium hydrogen peroxide was used as the etchant. Use water (a mixture of ammonia, water, and hydrogen peroxide).

[0270] Note that in the third photolithography step, part of the oxide semiconductor layer 399 is etched. In this case, the oxide semiconductor layer 399 may have a groove (a recess). 395a, a resist mask for forming the drain electrode layer 395b is formed by ink-jet printing. If the resist mask is formed by an ink-jet method, the manufacturing cost can be reduced. Cut.

[0271] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, The resist mask is formed by a multi-tone mask, which is an exposure mask that allows the incident light to have multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0272] Plasma treatment with gases such as N2O, N2, or Ar removes exposed oxide semiconductor. It is also possible to remove adsorbed water and the like attached to the surface of the conductor layer. Also, a mixed gas of oxygen and argon is used. The plasma treatment may be carried out using

[0273] When plasma treatment is performed, a protective film that is in contact with a part of the oxide semiconductor layer is formed without being exposed to the air. An oxide insulating layer 396 is formed as an oxide insulating layer to be an insulating layer (see FIG. 11D). In this embodiment, the oxide semiconductor layer 399 is a source electrode layer 395a and a drain electrode layer 395b. In a region where the oxide semiconductor layer 399 does not overlap with the oxide insulating layer 396, Form it as follows.

[0274] In this embodiment, the oxide insulating layer 396 includes an island-shaped oxide semiconductor layer 399, a source electrode The substrate 394 on which the electrode layer 395a and the drain electrode layer 395b have been formed is heated at room temperature or below 100°C. The gas is heated to a temperature of 1000 K, and hydrogen and moisture are removed. A high-purity sputtering gas containing oxygen is introduced. A silicon oxide layer containing defects is formed using a silicon semiconductor target.

[0275] In this embodiment, for example, a silicon target having a purity of 6N and doped with boron is used. The distance between the substrate and the target (TS distance) was set to 89 m. m, pressure 0.4 Pa, direct current (DC) power 6 kW, oxygen (oxygen flow rate 100%) atmosphere The silicon oxide film is formed by pulse DC sputtering. The thickness is set to 300 nm. In addition, a silicon oxide film is formed instead of a silicon target. Quartz (preferably synthetic quartz) can be used as the target for sputtering. The deposition gas may be, for example, oxygen or a mixed gas of oxygen and argon.

[0276] When the oxide insulating layer 396 is formed using any of the above materials and methods, It is preferable to deposit the oxide insulating layer 396 while removing residual moisture in the chamber. In order to prevent hydrogen, hydroxyl groups, or moisture from being contained in the oxide insulating layer 399 and the oxide insulating layer 396, is.

[0277] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. Examples of adsorption type vacuum pumps include cryopumps, ion pumps, and titanium sublimation pumps. It is preferable to use a displacement pump. As an exhaust means, a turbo pump with a A cryopump equipped with a dust trap can be used. The chamber is evacuated, for example, of hydrogen atoms and compounds containing hydrogen atoms (such as water). By forming the oxide insulating layer 396 in the deposition chamber, the impurity concentration in the oxide insulating layer 396 can be reduced. do.

[0278] Note that as the oxide insulating layer 396, a silicon oxynitride layer or an oxide An aluminum layer, an aluminum oxynitride layer, or the like can also be used.

[0279] Further, the oxide insulating layer 396 and the oxide semiconductor layer 399 are heated at 100° C. to 40° C. in a state where the oxide insulating layer 396 and the oxide semiconductor layer 399 are in contact with each other. Heat treatment may be performed at 0° C. The oxide insulating layer 396 in this embodiment has many defects. Therefore, the heat treatment reduces hydrogen, moisture, and hydroxyl groups contained in the oxide semiconductor layer 399. Alternatively, impurities such as hydride are diffused into the oxide insulating layer 396 to form a layer in the oxide semiconductor layer 399. The impurities contained therein can be further reduced.

[0280] Through the above steps, the oxide semiconductor layer 39 in which the concentration of hydrogen, moisture, hydroxyl groups, or hydrides is reduced is formed. 11E, a transistor 390 having a first conductivity type 2 can be formed.

[0281] When forming the oxide semiconductor film as described above, residual moisture in the atmosphere during film formation is removed. This allows the concentrations of hydrogen and hydride in the oxide semiconductor film to be reduced. The oxide semiconductor film can be further stabilized.

[0282] Note that a protective insulating layer may be provided over the oxide insulating layer. 8 is formed on the oxide insulating layer 396. As the protective insulating layer 398, a silicon nitride film, a nitride film, A silicon oxide film, an aluminum nitride film, an aluminum nitride oxide film, or the like is used.

[0283] In this embodiment, as an example, the substrate 394 on which the oxide insulating layer 396 has been formed is It is heated to a temperature of ℃ to 400℃, and high-purity sputtering containing nitrogen from which hydrogen and moisture have been removed is performed. By introducing a silicon nitride gas and using a silicon semiconductor target, In this case, similarly to the oxide insulating layer 396, The protective insulating layer 398 is preferably formed while removing residual moisture in the treatment chamber.

[0284] When forming the protective insulating layer 398, the temperature is set to 100° C. to 400° C. during the formation of the protective insulating layer 398. The plate 394 is heated to oxidize hydrogen or moisture contained in the oxide semiconductor layer 399. In this case, after the oxide insulating layer 396 is formed, It is not necessary to perform a heat treatment.

[0285] In addition, a silicon oxide layer is formed as the oxide insulating layer 396, and a nitride layer is formed as the protective insulating layer 398. When stacking a silicon layer, the silicon oxide layer and the silicon nitride layer are simultaneously formed in the same processing chamber. It can be formed by using a silicon target containing oxygen. Gas is introduced to form a silicon oxide layer using a silicon target installed in the processing chamber. Then, the sputtering gas was switched to a nitrogen-containing sputtering gas and the same silicon A silicon nitride layer is formed using a silicon oxide target. Since it can be formed continuously without exposure to the atmosphere, hydrogen and moisture can be prevented from forming on the surface of the silicon oxide layer. In this case, the oxide insulating layer 396 can be formed by using an oxide film. After forming a silicon layer and laminating a silicon nitride layer as a protective insulating layer 398, an oxide semiconductor A heat treatment ( It is recommended to carry out the heating at a temperature of 100°C to 400°C.

[0286] In addition, when an oxide semiconductor layer having a channel formation region is formed over a gate insulating layer, Removal of residual moisture in the air reduces the concentrations of hydrogen and hydride in the oxide semiconductor layer. It is possible.

[0287] The above process is carried out at temperatures below 400°C, so the thickness is less than 1mm and the length is 1m. It can also be applied to manufacturing processes that use glass substrates at temperatures above 400°C. All steps can be carried out at the cooking temperature.

[0288] Furthermore, the conduction mechanism of a transistor using an oxide semiconductor will be explained using FIGS. In the following explanation, an ideal situation is assumed for ease of understanding. Not all of them necessarily reflect the actual situation. Please note that this is merely speculation.

[0289] FIG. 12 shows a longitudinal cross-sectional view of an inverted staggered transistor using an oxide semiconductor. An oxide semiconductor layer 1003 is provided on a gate insulating film 1002. A source electrode 1004a and a drain electrode 1004b are provided on the An oxide insulating layer 1005 is provided on the drain electrode 1004b, and the oxide insulating layer 1005 is provided on the drain electrode 1004b. A conductive layer 1006 is provided over the oxide semiconductor layer 1003 with the insulating film 1005 sandwiched therebetween.

[0290] FIG. 13 shows an energy band diagram (schematic diagram) in the cross section A-A' shown in FIG. 13(A) shows the case where the voltage between the source and drain is equipotential (Vd = 0 V), and Fig. 13(B) applies a positive potential (Vd>0) to the drain relative to the source, and a positive potential to the gate This shows the case where (Vg>0) is added.

[0291] FIG. 14 is an energy band diagram (schematic diagram) in the cross section taken along line B-B' in FIG. Figure 14(A) shows the state where a positive potential (+Vg) is applied to the gate (G1), and the source The figure shows the on-state where carriers (electrons) flow between the gate and drain. is the state in which a negative potential (-Vg) is applied to the gate (G1), and the transistor is in the off state (minority capacitance This shows the case where the rear does not flow.

[0292] Figure 15 shows the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). Shows.

[0293] Since metals are degenerate, the Fermi level is located in the conduction band. The body is generally N-type, in which case the Fermi level (Ef) is located in the center of the band gap. The intrinsic Fermi level (Ei) is located closer to the conduction band. In the case of a conductor, although it depends on the film formation method, the oxide semiconductor layer contains some hydrogen or water. It is known that some of these atoms act as donors that supply electrons, which is one of the reasons for the formation of N-type structures. It is being done.

[0294] In contrast, the oxide semiconductor used in the transistor of the DC converter circuit of one embodiment of the present invention is , hydrogen, which is an N-type impurity, is removed from the oxide semiconductor, and impurities other than the main components of the oxide semiconductor are removed. By purifying the material to the extent possible, it is possible to obtain an intrinsic (type I) or substantially intrinsic semiconductor. In other words, instead of adding impurities to make it I-type, hydrogen, water, etc. By removing impurities as much as possible, it is a highly purified I-type (intrinsic semiconductor) or something close to it. This allows the Fermi level to be at the same level as the intrinsic Fermi level. It can be up to.

[0295] When the band gap (Eg) of an oxide semiconductor is 3.15 eV, the electron affinity (χ) is The titanium (Ti) that makes up the source and drain electrodes is said to be 4.3 eV. The electron affinity function is approximately equal to the electron affinity of the oxide semiconductor. In this case, the metal-oxide semiconductor interface In this case, no Schottky barrier is formed for electrons.

[0296] In other words, when the work function of a metal and the electron affinity of an oxide semiconductor are equal, when the two come into contact, An energy band diagram (schematic diagram) such as that shown in FIG. 13(A) is shown.

[0297] In FIG. 13(B), the black circles (●) represent electrons, and when a positive potential is applied to the drain, Electrons are injected into the oxide semiconductor beyond the barrier (h) and flow toward the drain. In this case, the barrier height (h) changes depending on the gate voltage and drain voltage. When a rain voltage is applied, the barrier height of FIG. 13(A) without voltage application, i.e., In other words, the barrier height (h) is smaller than half the band gap (Eg).

[0298] At this time, the electrons penetrate into the gate insulating film and the highly purified oxide semiconductor as shown in FIG. The electrons move through the lowest energetically stable part on the oxide semiconductor side at the interface with the body.

[0299] In FIG. 14B, a negative potential (reverse bias) is applied to the gate electrode 1001. Since the number of holes, which are minority carriers, is essentially zero, the current is close to zero. value.

[0300] For example, if the channel width W of a transistor is 1×10 4 The device has a channel length of 3 μm and a width of 1 μm. Even if the off-state current is 10 -13 A or less, and the subthreshold swing value (S value) is 0.1V / dec. (gate insulating film thickness 100nm).

[0301] Thus, simply applying oxide semiconductors with wide band gaps to transistors is not enough. The carrier density is preferably 1. x10 12 / cm 3 less than 1.45 x 10 10 / cm 3 To be less than By doing so, thermally excited carriers are eliminated at practical operating temperatures, and the The transistor can be operated only by the injected carriers. Off-state current is 1×10 -13 A or less, and the off-state current is almost constant due to temperature changes. It is possible to obtain a transistor that operates extremely stably with almost no change.

[0302] As described above, a transistor including an oxide semiconductor layer has stable electrical characteristics. A highly reliable transistor can be provided.

[0303] This embodiment mode can be appropriately combined with or replaced with other embodiment modes. do.

[0304] (Embodiment 7) This embodiment can be applied to a transistor included in a DC converter circuit according to one embodiment of the present invention. An example of such a transistor will be described.

[0305] An example of a transistor and a manufacturing method of the transistor in this embodiment will be described with reference to FIGS. explain.

[0306] An example of a method for manufacturing a transistor is shown in FIGS. The transistor shown in Figure 1 has a bottom gate structure and is also called an inverted staggered transistor. cormorant.

[0307] The transistor 310 has a single gate structure. The transistor is a multi-gate transistor having a plurality of channel formation regions. That's fine.

[0308] 16(A) to 16(E), a process for fabricating a transistor 310 on a substrate 300 will be described. Explain the process.

[0309] First, a conductive film is formed on a substrate 300 having an insulating surface, and then a first photolithography is performed. A gate electrode layer 311 is formed by a process. If the resist mask is formed by an ink-jet method, the manufacturing cost can be reduced. do.

[0310] There is no significant limitation on the substrate that can be used for the substrate 300 having an insulating surface, but at least In both cases, the substrate 3 must have heat resistance to a degree that it can withstand heat treatment. 00 is a glass substrate such as barium borosilicate glass or aluminoborosilicate glass. can be used.

[0311] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. Alternatively, a substrate made of an insulating material may be used. Alternatively, a substrate made of a crystallized glass may be used. The substrate may be a semiconductor substrate such as silicon.

[0312] An insulating film serving as a base film may be provided between the substrate 300 and the gate electrode layer 311. , which has the function of preventing the diffusion of impurity elements from the substrate 300, and is a silicon nitride film, a silicon oxide film, A laminated structure of one or more films selected from a silicon nitride oxide film or a silicon oxynitride film It can be formed.

[0313] The gate electrode layer 311 may be made of molybdenum, titanium, chromium, tantalum, tungsten, Metallic materials such as aluminum, copper, neodymium, scandium, etc., or alloys containing these as their main components The gold material can be used to form a single layer or a multilayer structure.

[0314] For example, the gate electrode layer 311 may have a two-layer laminate structure, such as a molybdenum layer on an aluminum layer. Two-layer laminated structure with a molybdenum layer on a copper layer, two-layer laminated structure with a molybdenum layer on a copper layer, copper layer A two-layer laminate structure with a titanium nitride layer or tantalum nitride layer laminated on top, a titanium nitride layer and a metal layer Two-layer laminated structure with a tungsten nitride layer and a tungsten layer, or a tungsten nitride layer and a tungsten layer A two-layer laminate structure is preferable. A three-layer laminate structure is preferably a tungsten layer or a nitride layer. a tungsten nitride layer, and an aluminum-silicon alloy or aluminum-titanium alloy layer; It is preferable to use a laminated layer in which a titanium nitride layer or a titanium layer is laminated.

[0315] Next, the gate insulating layer 302 is formed on the gate electrode layer 311 .

[0316] Here, the oxide semiconductor (high-temperature) that has been made i-type or substantially i-type by removing impurities is Since the gate electrode (a purified oxide semiconductor) is extremely sensitive to the interface state and the interface charge, The interface between the gate insulating layer and the highly purified oxide semiconductor layer is important. The insulating layer (GI) is required to be of high quality.

[0317] For example, high density plasma CVD using microwaves (2.45 GHz) produces dense, high dielectric strength films. It is preferable to form a highly purified oxide semiconductor layer and a high-quality gate insulating film. By closely contacting the gate insulating layer, the interface state can be reduced and the interface characteristics can be improved. The high density plasma device used here is 1×10 11 / cm 3 Any device capable of achieving the above plasma density can be used.

[0318] For example, a microwave power of 3 kW to 6 kW is applied to generate plasma, and the insulating film is formed. The chamber is filled with monosilane gas (SiH4) and nitrous oxide (N2 O) and rare gas are introduced to generate high-density plasma under a pressure of 10 Pa to 30 Pa. An insulating film is formed on a substrate having an insulating surface such as a silicon dioxide gas. Nitrous oxide (N2O) and rare gases are introduced without exposing the insulating film to the atmosphere. Plasma treatment may be performed. At least nitrous oxide (N2O) and rare gases are introduced to provide insulation. The plasma treatment on the film surface is carried out after the insulating film is formed. The flow ratio of silane gas (SiH4) to nitrous oxide (N2O) is 1:10 to 1:20. The rare gas introduced into the chamber is helium, argon, Lipton, xenon, etc. can be used, but argon is the most inexpensive. It is preferable that:

[0319] Of course, if a good insulating film can be formed as the gate insulating layer 302, sputtering is also possible. Other film formation methods such as the ring method and plasma CVD method can be applied. The insulating film is one whose film quality and interface characteristics with the oxide semiconductor are improved by heat treatment. In any case, it goes without saying that the quality of the film as a gate insulating film is good. Any material may be used as long as it can reduce the interface state density with the oxide semiconductor and form a good interface.

[0320] Furthermore, at 85°C, 2 × 10 6 V / cm, 12-hour gate bias and thermal stress test (B In the T test, when impurities are added to an oxide semiconductor, the impurities and the oxide semiconductor The bonds between the main component of the compound are broken by a strong electric field (B: bias) and high temperature (T: temperature), The resulting dangling bonds induce a drift in the threshold voltage (Vth). The transistor used in the DC converter circuit of one embodiment of the present invention is an oxide semiconductor transistor. Impurities, especially hydrogen and water, are removed as much as possible to improve the interface characteristics with the gate insulating layer as described above. By doing so, it is possible to obtain a stable transistor even in BT tests. .

[0321] The gate insulating layer 302 may be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. a silicon nitride layer, a silicon oxide nitride layer, or an aluminum oxide layer, formed as a single layer or a stacked layer; can be done.

[0322] The gate insulating layer 302 may be, for example, HfO x Gate HfO as the insulating layer 302 x By using the above, the gate electrode can be formed from the oxide semiconductor layer side. This can reduce the leakage current flowing toward the

[0323] The gate insulating layer 302 has a structure in which a silicon oxide layer and a silicon nitride layer are stacked. In this embodiment, as an example, a high density microwave is generated at a pressure of 30 Pa and a microwave power of 6 kW. A silicon oxynitride layer with a thickness of 100 nm is formed by plasma CVD. The flow rate ratio of monosilane gas (SiH4) and nitrous oxide (N2O) introduced into the chamber is: The range is 1:10 to 1:200.

[0324] Next, an oxide semiconductor film 330 having a thickness of 2 nm to 200 nm is formed on the gate insulating layer 302. Form.

[0325] Before the oxide semiconductor film 330 was formed by a sputtering method, argon gas was introduced. The reverse sputtering is performed by introducing the silicon dioxide into the gate insulating layer 302 to generate plasma. It is preferable to remove particles that may be present in the atmosphere. Alternatively, hydrogen, oxygen, etc. may be used.

[0326] The oxide semiconductor film 330 is an In—Sn—Ga—Zn—O film, which is a quaternary metal oxide. and ternary metal oxide films such as In-Ga-Zn-O, In-Sn-Zn-O, and In- Al-Zn-O film, Sn-Ga-Zn-O film, Al-Ga-Zn-O film, Sn-Al-Z InO films, binary metal oxide films such as In-Zn-O films, Sn-Zn-O films, and Al-Zn -O film, Zn-Mg-O film, Sn-Mg-O film, In-Mg-O film, In-Sn-O film, For example, an oxide semiconductor film such as an In—O film, an Sn—O film, or a Zn—O film can be used. In addition, the oxide semiconductor film may contain SiO2.

[0327] The oxide semiconductor film 330 is made of InMO3(ZnO). m (m>0) Here, M is one or more selected from Ga, Al, Mn, and Co. indicates multiple metal elements. For example, M can be Ga, Ga and Al, Ga and Mn, or G Examples include a and Co.

[0328] In addition, an oxide semiconductor film 330 is formed by sputtering using an oxide semiconductor film. A target of a metal oxide containing zinc oxide as a main component can be used. Other examples of such targets include metal oxide targets (compositions) containing In, Ga, and Zn. The composition ratio is In2O3:Ga2O3:ZnO=1:1:1 [mol%], In:Ga Zn=1:1:0.5 [atom %]) can be used. In, Ga, and As a metal oxide target containing In and Zn, In:Ga:Zn=1:1:1 [atom% ], or a target having a composition ratio of In:Ga:Zn=1:1:2 [atom %] is used. The filling rate of the metal oxide target is 90% or more, preferably 95% or more. By using a metal oxide target with a high filling rate, the oxide semiconductor film formed The film becomes a dense film.

[0329] The sputtering gas used in forming the oxide semiconductor film 330 is hydrogen, water, or High purity impurities such as acid groups or hydrides have been removed to concentrations of ppm or ppb. It is preferable to use a high-temperature gas.

[0330] The substrate is held in a processing chamber maintained in a reduced pressure state, and the substrate temperature is preferably maintained at 100°C or higher and 600°C or lower. The temperature is preferably 200°C or higher and 400°C or lower. The concentration of impurities contained in the sputtered oxide semiconductor film can be reduced. Damage caused by heating is reduced. The removed sputtering gas is introduced, and metal oxide is used as a target to deposit on the substrate 300. The oxide semiconductor film 330 is formed. In order to remove residual moisture in the processing chamber, an adsorption type evaporator is used. It is preferable to use an air pump. As an adsorption type vacuum pump, for example, a cryopump is used. It is preferable to use an ion pump or a titanium sublimation pump. The stage can be, for example, a turbo pump equipped with a cold trap. The deposition chamber evacuated using a cryopump contains hydrogen atoms, water (H2O), and other hydrogen gases. Because compounds containing atoms (and more preferably compounds containing carbon atoms) are exhausted By forming the oxide semiconductor film in the deposition chamber, the concentration of impurities contained in the oxide semiconductor film can be reduced. .

[0331] An example of the film formation conditions is a distance between the substrate and the target of 100 mm, a pressure of 0.6 Pa, and a direct current The conditions are: (DC) power supply 0.5 kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, if a pulsed direct current (DC) power supply is used, particles can be reduced and the film thickness distribution can be made uniform. The thickness of the oxide semiconductor film is preferably 5 nm to 30 nm. Note that the appropriate thickness of the oxide semiconductor film varies depending on the oxide semiconductor material used. The thickness may be selected appropriately depending on the material.

[0332] Next, the oxide semiconductor film 330 is subjected to a second photolithography process to form an island-shaped oxide semiconductor film. In addition, a resist mask for forming an island-shaped oxide semiconductor layer is formed by inkjet printing. If the resist mask is formed by the ink-jet method, the manufacturing cost is can be reduced.

[0333] Next, the oxide semiconductor layer is subjected to first heat treatment. The temperature of the first heat treatment is 400° C. or higher. The temperature is set to 750° C. or less, preferably 400° C. or more and less than the strain point of the substrate. The substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is heated under a nitrogen atmosphere. After heat treatment at 450°C for 1 hour, the oxide semiconductor was The oxide semiconductor layer 331 is obtained while preventing water and hydrogen from being mixed into the oxide layer (see FIG. 16(B)).

[0334] When the temperature of the heat treatment device is lowered from the heat treatment temperature, the atmosphere may be changed to oxygen. When the temperature is lowered and the atmosphere is switched to oxygen, oxygen is replenished to the oxygen vacancies in the oxide semiconductor layer. Oxygen vacancies generate carriers, but when they disappear, the carriers are significantly reduced. Therefore, an oxide semiconductor layer with an extremely low carrier concentration can be obtained.

[0335] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat radiation from a heat source such as a resistance heating element. The apparatus may be equipped with a device for heating the object to be treated by irradiation. For example, a GRTA apparatus, an LR apparatus, etc. The RTA device can be used with a halogen lamp, a meter, or other RTA devices. Thallium halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps The material to be treated is heated by the radiation of light (electromagnetic waves) emitted from lamps such as high-pressure mercury lamps. The GRTA device is a device that uses high-temperature gas for heating. The body contains rare gases such as argon or nitrogen, which react with the material being treated by heat treatment. An inert gas that does not contain oxygen is used.

[0336] For example, as the first heat treatment, a base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The plate was moved and heated for several minutes, after which the substrate was moved and taken out of the inert gas heated to a high temperature. GRTA can be used to perform high-temperature heat treatment in a short time.

[0337] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. The purity of rare gases such as helium, neon, and argon is 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., 1 ppm or less, preferably It is preferable to keep the concentration below 0.1 ppm.

[0338] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. The semiconductor film 330 can also be subjected to the first heat treatment. In that case, after the first heat treatment, The substrate is removed and subjected to a photolithography process.

[0339] The heat treatment that has the effect of dehydrating and dehydrogenating the oxide semiconductor layer is performed by the oxide semiconductor layer formation. After that, a source electrode layer and a drain electrode layer are stacked on the oxide semiconductor layer, and then a source electrode The deposition may be performed either after forming a protective insulating layer over the drain electrode layer or after forming a protective insulating layer over the drain electrode layer.

[0340] In addition, when a contact hole is formed in the gate insulating layer 302, the process is performed using an oxide semiconductor. This may be done before or after the membrane 330 has been subjected to a dehydration or dehydrogenation treatment.

[0341] Note that the etching of the oxide semiconductor film here is not limited to wet etching, but may be dry etching. Etching may also be used.

[0342] The etching conditions (etching) are adjusted to suit the material so that the desired processing shape can be etched. Adjust the etching conditions (liquid, etching time, temperature, etc.) as appropriate.

[0343] Next, a conductive film is formed over the gate insulating layer 302 and the oxide semiconductor layer 331. For example, The conductive film may be formed by sputtering or vacuum deposition. An element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten Alternatively, alloys containing the above elements or alloy films of a combination of the above elements may be used. The conductive film material can be manganese, magnesium, zirconium, beryllium, Alternatively, a material selected from one or more of the following may be used: sulphur dioxide, yttrium, and ammonium hydroxide. The conductive film may have a single layer structure or a laminated structure of two or more layers. A single layer structure of aluminum film containing silicon is also available. A two-layer structure in which a titanium film is laminated on an aluminum film, and a Ti film and an aluminum film are laminated on the Ti film. Examples include a three-layer structure in which an aluminum film is laminated and a Ti film is further formed on top of that. Aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium A film made of a single or multiple combinations of elements selected from the group consisting of aluminum, an alloy film, or a nitride film is used. It's fine.

[0344] When a heat treatment is performed after the conductive film is formed, the conductive film must have heat resistance to withstand this heat treatment. It is preferable that

[0345] A resist mask is formed on the conductive film by a third photolithography process, and selective etching is performed. After forming the source electrode layer 315a and the drain electrode layer 315b by etching, a resist The mask is removed (see FIG. 16(C)).

[0346] The third photolithography process involves exposure to ultraviolet light or KrF laser light when forming a resist mask. The source electrode layer adjacent to each other on the oxide semiconductor layer 331 is formed by laser light or ArF laser light. The width of the gap between the end of the drain electrode layer and the bottom end of the drain electrode layer determines the channel width of the transistor to be formed later. When exposure is performed for a channel length L of less than 25 nm, the channel length L is determined by the Extreme ultraviolet rays have extremely short wavelengths of up to several tens of nanometers. The third photolithography step is performed using ultraviolet light to form a resist mask. Line exposure has high resolution and a large depth of focus. It is also possible to set the channel length L to 10 nm or more and 1000 nm or less, and the operating speed of the circuit can be improved. This allows for faster switching speeds and extremely small off-state current values, which also contributes to lower power consumption. can be done.

[0347] Note that the conductive film is etched so that the oxide semiconductor layer 331 is not removed. The materials and etching conditions for the oxide semiconductor film and the oxide semiconductor film are adjusted as appropriate.

[0348] In this embodiment, for example, a titanium film is used as the conductive film, and the oxide semiconductor layer 331 is An In-Ga-Zn-O oxide semiconductor layer was used as the etchant, and ammonium hydrogen peroxide was used as the etchant. Use water (a mixture of ammonia, water, and hydrogen peroxide).

[0349] Note that in the third photolithography step, part of the oxide semiconductor layer 331 is etched. In some cases, the oxide semiconductor layer has a groove (a recess). a) A resist mask for forming the drain electrode layer 315b is formed by an inkjet method. If the resist mask is formed by an ink-jet method, the manufacturing cost can be reduced.

[0350] Further, an oxide conductive layer is formed between the oxide semiconductor layer and the source electrode layer and the drain electrode layer. The oxide conductive layer and the metal layer for forming the source and drain electrode layers may be The oxide conductive layer can function as a source region and a drain region.

[0351] The oxide conductive layer is formed as a source region and a drain region by forming an oxide semiconductor layer and a source electrode layer. By providing the source and drain electrode layers between the source and drain regions, the resistance of the source and drain regions can be reduced. This allows the transistor to operate at high speed.

[0352] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, The resist mask is formed by a multi-tone mask, which is an exposure mask that allows the incident light to have multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0353] Next, a plasma treatment is performed using a gas such as N2O, N2, or Ar. The adsorbed water and the like adhering to the surface of the oxide semiconductor layer exposed by the treatment is removed. The plasma treatment may be performed using a mixed gas of oxygen and argon.

[0354] After the plasma treatment, the protective insulating film in contact with a part of the oxide semiconductor layer was removed without being exposed to the air. An oxide insulating layer 316 is formed as an insulating film.

[0355] The oxide insulating layer 316 has a thickness of at least 1 nm and is formed by an oxide method such as a sputtering method. The insulating layer 316 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed in. When hydrogen is contained in the oxide insulating layer 316, the hydrogen penetrates into the oxide semiconductor layer, Alternatively, oxygen in the oxide semiconductor layer is extracted by hydrogen, and the back-channel of the oxide semiconductor layer is formed. The resistance of the panel will become low (N-type), which may result in the formation of a parasitic channel. The oxide insulating layer 316 is formed using a method that does not use hydrogen so that the oxide insulating layer 316 contains as little hydrogen as possible. It is important that there is no

[0356] In this embodiment, as an example, a silicon oxide film with a thickness of 200 nm is used as the oxide insulating layer 316. The substrate temperature during film formation is set to between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. Formation of a silicon oxide film by sputtering The method is carried out under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) atmosphere. The target can be silicon dioxide. For example, a silicon target can be used. A silicon oxide film can be formed by sputtering in an atmosphere of oxygen and nitrogen. The oxide layer formed in contact with the oxide semiconductor layer becomes oxygen deficient and has low resistance, i.e., becomes N-type. The insulating layer 316 is resistant to moisture, hydrogen ions, OH - It does not contain impurities such as An inorganic insulating film is used to block the intrusion of silicon dioxide, silicon oxynitride, etc. A film made of aluminum, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0357] In this case, the oxide insulating layer 316 is formed while removing residual moisture in the treatment chamber. It is preferable that the oxide semiconductor layer 331 and the oxide insulating layer 316 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed.

[0358] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. Examples of adsorption type vacuum pumps include cryopumps, ion pumps, and titanium sublimation pumps. It is preferable to use a displacement pump. As the exhaust means, for example, a turbo pump is used. The film deposition chamber may be equipped with a cold trap. The chamber is evacuated, for example, of hydrogen atoms and compounds containing hydrogen atoms (such as water). By forming the oxide insulating layer 316 in the deposition chamber, the impurity concentration in the oxide insulating layer 316 can be reduced. do.

[0359] The oxide insulating layer 316 is formed using a sputtering gas such as hydrogen, water, or hydroxide. High purity, with impurities such as bases or hydrides removed to concentrations of ppm or ppb. It is preferable to use a gas.

[0360] Next, a second heat treatment (preferably 200 ℃ or higher and 400℃ or lower, for example, 250℃ or higher and 350℃ or lower). After the second heat treatment, the oxide semiconductor layer is heated in contact with the oxide insulating layer 316.

[0361] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After the resistance of the oxide semiconductor film is reduced by heat treatment for the purpose of forming the oxide semiconductor film, a part of the oxide semiconductor film is selectively formed into an oxygen-excess state. As a result, the channel forming region 313 overlapping with the gate electrode layer 311 becomes an I-type. , a low-resistance source region 314a overlapping the source electrode layer 315a, and a drain electrode layer 315b The low-resistance drain region 314b overlapping the transistor 314 is formed in a self-aligned manner. A resistor 310 is formed (see FIG. 16(D)).

[0362] Note that the oxide semiconductor layer overlapping with the drain electrode layer 315b (and the source electrode layer 315a) forming a low-resistance drain region 314b (or a low-resistance source region 314a) in This can improve the reliability of the transistor. By forming the region 314b, the low-resistance drain region 314 b) A structure in which the conductivity can be changed stepwise toward the channel forming region 313 Therefore, the wiring for supplying the high power supply potential VDD to the drain electrode layer 315b is When the gate electrode layer 311 and the drain electrode layer 315b are connected and operated, a high electric field is generated between the gate electrode layer 311 and the drain electrode layer 315b. Even if a high electric field is applied, the low-resistance drain region acts as a buffer, preventing the application of a local high electric field. This allows the transistor to have an improved dielectric strength.

[0363] A protective insulating layer may be further formed over the oxide insulating layer 316. For example, The silicon nitride film is formed using the RF sputtering method. The RF sputtering method is suitable for mass production. The protective insulating layer is formed by the method described above using a method for forming a protective insulating layer. , O.H. - It is an inorganic insulator that does not contain impurities such as those mentioned above and blocks their penetration from the outside. Using films, silicon nitride films, aluminum nitride films, silicon nitride oxide films, aluminum nitride oxide films In this embodiment, the protective insulating layer 303 is formed of a nitride film or the like. It is formed using a silicon film (see FIG. 16(E)).

[0364] In this embodiment, the substrate 300 on which the oxide insulating layer 316 has been formed is heated at 100° C. to 400° C. The temperature is then increased to 100°C, and hydrogen and moisture are removed, and a high-purity sputtering gas containing nitrogen is introduced. A silicon nitride film is formed as a protective insulating layer 303 using a silicon semiconductor target. In this case, as in the case of the oxide insulating layer 316, residual moisture in the treatment chamber is removed. It is preferable to deposit the protective insulating layer 303 while performing the above-described process.

[0365] In addition, a planarization insulating layer for planarization may be provided over the protective insulating layer 303.

[0366] In addition, an oxide film is formed on the protective insulating layer 303 (on the planarizing insulating layer if a planarizing insulating layer is provided). A conductive layer may be provided that overlaps the semiconductor layer. This may be the same as or different from the first gate electrode layer 311 and functions as the second gate electrode layer. The potential of the conductive layer may be a fixed potential such as GND or 0V. .

[0367] The conductive layer can control the electrical characteristics of the transistor 310 .

[0368] As described above, a transistor including an oxide semiconductor layer has stable electrical characteristics. A highly reliable transistor can be provided.

[0369] This embodiment mode can be combined with or replaced with any of the other embodiment modes as appropriate.

[0370] (Embodiment 8) This embodiment can be applied to a transistor included in a DC converter circuit according to one embodiment of the present invention. An example of such a transistor will be described.

[0371] An example of a transistor and a manufacturing method of the transistor of this embodiment will be described with reference to FIGS. explain.

[0372] An example of a method for manufacturing a transistor is shown in FIGS. The transistor shown in Figure 1 is a type called a channel protection type (also called a channel stop type). It is one of the Tom gate structures and is also called an inverted staggered transistor.

[0373] In addition, the transistor 360 has a single gate structure. The transistor is a multi-gate transistor having a plurality of channel formation regions. That's fine.

[0374] 17A to 17D, a process for fabricating a transistor 360 on a substrate 320 will be described. Explain the process.

[0375] First, a conductive film is formed on a substrate 320 having an insulating surface, and then a first photolithography is performed. A gate electrode layer 361 is formed by a process. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, manufacturing costs can be reduced.

[0376] The gate electrode layer 361 may be made of molybdenum, titanium, chromium, tantalum, tungsten, Metallic materials such as aluminum, copper, neodymium, scandium, etc., or alloys containing these as their main components The gold material can be used to form a single layer or a multilayer structure.

[0377] Next, the gate insulating layer 322 is formed on the gate electrode layer 361 .

[0378] Here, the oxide semiconductor (high-temperature) that has been made i-type or substantially i-type by removing impurities is Since the gate electrode (a purified oxide semiconductor) is extremely sensitive to the interface state and the interface charge, The interface between the gate insulating layer and the highly purified oxide semiconductor layer is important. The insulating layer (GI) is required to be of high quality.

[0379] For example, high density plasma CVD using microwaves (2.45 GHz) produces dense, high dielectric strength films. It is preferable to form a highly purified oxide semiconductor layer and a high-quality gate insulating film. By closely contacting the gate insulating layer, the interface state can be reduced and the interface characteristics can be improved. The high density plasma device used here is 1×10 11 / cm 3 Any device capable of achieving the above plasma density can be used.

[0380] For example, a microwave power of 3 kW to 6 kW is applied to generate plasma, and the insulating film is formed. The chamber is filled with monosilane gas (SiH4) and nitrous oxide (N2 O) and rare gas are introduced to generate high-density plasma under a pressure of 10 Pa to 30 Pa. An insulating film is formed on a substrate having an insulating surface such as a silicon dioxide gas. Nitrous oxide (N2O) and rare gases are introduced without exposing the insulating film to the atmosphere. Plasma treatment may be performed. At least nitrous oxide (N2O) and rare gases are introduced to provide insulation. The plasma treatment on the film surface is carried out after the insulating film is formed. The flow ratio of silane gas (SiH4) to nitrous oxide (N2O) is 1:10 to 1:20. The rare gas introduced into the chamber is helium, argon, Lipton, xenon, etc. can be used, but argon is the most inexpensive. It is preferable that:

[0381] Of course, if a good insulating film can be formed as the gate insulating layer 322, sputtering is also possible. Other film formation methods such as the ring method and plasma CVD method can be applied. The insulating film is one whose film quality and interface characteristics with the oxide semiconductor are improved by heat treatment. In any case, it goes without saying that the quality of the film as a gate insulating film is good. Any material may be used as long as it can reduce the interface state density with the oxide semiconductor and form a good interface.

[0382] Furthermore, at 85°C, 2 × 10 6 V / cm, 12-hour gate bias thermal stress test (B In the T test, when impurities are added to an oxide semiconductor, the impurities and the oxide semiconductor The bonds between the main component of the compound are broken by a strong electric field (B: bias) and high temperature (T: temperature), The resulting dangling bonds induce a drift in the threshold voltage (Vth). The transistor used in the DC converter circuit of one embodiment of the present invention is an oxide semiconductor transistor. Impurities, especially hydrogen and water, are removed as much as possible to improve the interface characteristics with the gate insulating layer as described above. By doing so, it is possible to obtain a stable transistor even in BT tests. .

[0383] The gate insulating layer 322 may be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. a silicon nitride layer, a silicon oxide nitride layer, or an aluminum oxide layer, formed as a single layer or a stacked layer; can be done.

[0384] The gate insulating layer 322 may be, for example, HfO x Gate HfO as the insulating layer 322 x By using the above, the gate electrode can be formed from the oxide semiconductor layer side. This can reduce the leakage current flowing toward the

[0385] The gate insulating layer 322 may have a structure in which a silicon oxide layer and a silicon nitride layer are stacked. In this embodiment, as an example, a high density microwave is generated at a pressure of 30 Pa and a microwave power of 6 kW. A silicon oxynitride layer with a thickness of 100 nm is formed by plasma CVD. The flow rate ratio of monosilane gas (SiH4) and nitrous oxide (N2O) introduced into the chamber is: The range is 1:10 to 1:200.

[0386] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is formed over the gate insulating layer 322. The oxide semiconductor layer is then processed into an island-shaped oxide semiconductor layer by a second photolithography process. In this case, for example, sputtering was performed using an In-Ga-Zn-O metal oxide target. An oxide semiconductor film is formed by a deposition method.

[0387] In this case, it is preferable to form the oxide semiconductor film while removing residual moisture in the treatment chamber. This is preferable in order to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film.

[0388] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. Examples of adsorption type vacuum pumps include cryopumps, ion pumps, and titanium sublimation pumps. It is preferable to use a pump for the exhaust. A film forming chamber evacuated using a cryopump may be provided with a cold trap. For example, hydrogen atoms and compounds containing hydrogen atoms (such as water) are exhausted. By forming the oxide semiconductor film in the deposition chamber, the concentration of impurities contained in the oxide semiconductor film can be reduced.

[0389] The sputtering gas used in forming the oxide semiconductor film may be hydrogen, water, a hydroxyl group, or a fluorine-containing gas. is a high-purity gas in which impurities such as hydrides have been removed to concentrations of ppm or ppb. It is preferable to use

[0390] Next, the oxide semiconductor layer is subjected to first heat treatment. The temperature of the first heat treatment is 400° C. or higher. The temperature is set to 750°C or less, preferably 400°C or more and less than the distortion point of the substrate. The substrate was placed in an electric furnace, which is one of the facilities, and the oxide semiconductor layer was heated to 450°C in a nitrogen atmosphere. After the heat treatment for 1 hour at 2000 K, the oxide semiconductor layer was heated without being exposed to the air. The oxide semiconductor layer 332 is obtained by preventing the inclusion of oxygen and hydrogen (see FIG. 17A).

[0391] Next, a plasma treatment is performed using a gas such as N2O, N2, or Ar. The adsorbed water and the like adhering to the surface of the oxide semiconductor layer exposed by the treatment is removed. The plasma treatment may be performed using a mixed gas of oxygen and argon.

[0392] Next, an oxide insulating layer is formed over the gate insulating layer 322 and the oxide semiconductor layer 332. A resist mask is formed by a third photolithography process, and selective etching is performed. After the oxide insulating layer 366 is formed, the resist mask is removed.

[0393] In this embodiment, a silicon oxide film having a thickness of 200 nm is used as an example of the oxide insulating layer 366. The substrate temperature during film formation should be between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. The silicon oxide film is formed by sputtering. In a gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon ) and oxygen atmosphere. For example, a silicon target can be used to oxidize oxygen. A silicon oxide film can be formed by sputtering in a nitrogen atmosphere. The oxide insulating layer 366 formed in contact with the oxide semiconductor layer with reduced resistance is resistant to moisture, hydrogen ions, and the like. N, OH - It is an inorganic insulator that does not contain impurities such as chlorine and other substances and blocks their penetration from the outside. An insulating film is used, typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or For example, an aluminum oxide nitride film is used.

[0394] In this case, the oxide insulating layer 366 is formed while removing residual moisture in the processing chamber. It is preferable that the oxide semiconductor layer 332 and the oxide insulating layer 366 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed.

[0395] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. Examples of adsorption type vacuum pumps include cryopumps, ion pumps, and titanium sublimation pumps. It is preferable to use a displacement pump. As the exhaust means, for example, a turbo pump is used. The film deposition chamber may be equipped with a cold trap. The chamber is evacuated, for example, of hydrogen atoms and compounds containing hydrogen atoms (such as water). By forming the oxide insulating layer 366 in the deposition chamber, the impurity concentration in the oxide insulating layer 366 can be reduced. do.

[0396] The oxide insulating layer 366 can be formed using a sputtering gas such as hydrogen, water, or hydroxide. High purity, with impurities such as bases or hydrides removed to concentrations of ppm or ppb. It is preferable to use a gas.

[0397] Next, a second heat treatment (preferably 200 ℃ or higher and 400 ℃ or lower, for example, 250 ℃ or higher and 350 ℃ or lower). The second heat treatment is carried out at 250°C for 1 hour in an atmosphere. A part of the semiconductor layer (channel formation region) is heated in a state where the part is in contact with the oxide insulating layer 366.

[0398] In this embodiment, an oxide insulating layer 366 is further provided and a part of the oxide semiconductor is exposed. The layer 332 is subjected to a heat treatment in a nitrogen or inert gas atmosphere or under reduced pressure. The exposed areas of the oxide semiconductor layer 332 that are not covered by the edge layer 366 are filled with nitrogen, impurities, and the like. Heat treatment under an active gas atmosphere or under reduced pressure can lower the resistance. Then, heat treatment is carried out at 250° C. for 1 hour in a nitrogen atmosphere.

[0399] Heat treatment in a nitrogen atmosphere on the oxide semiconductor layer 332 provided with the oxide insulating layer 366 As a result, the exposed region of the oxide semiconductor layer 332 has a low resistance, and the region with a different resistance (FIG. 17( In Fig. 1B, the oxide semiconductor layer 362 has a region indicated by hatched areas and white areas.

[0400] Next, a conductive film was formed over the gate insulating layer 322, the oxide semiconductor layer 362, and the oxide insulating layer 366. After forming the film, a resist mask is formed by a fourth photolithography process. After etching the source electrode layer 365a and the drain electrode layer 365b, Remove the dysmask (see Figure 17(C)).

[0401] The source electrode layer 365a and the drain electrode layer 365b are made of aluminum, chromium, or the like. , copper, tantalum, titanium, molybdenum, tungsten, or any of the elements mentioned above. Examples include alloys containing the above elements or alloy films made up of a combination of the above elements. The conductive film may have a single layer structure or a laminated structure of two or more layers.

[0402] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After the resistance of the oxide semiconductor film is reduced by heat treatment for the purpose of forming the oxide semiconductor film, a part of the oxide semiconductor film is selectively formed into an oxygen-excess state. As a result, the channel formation region 363 overlapping with the gate electrode layer 361 becomes I-shaped. The low-resistance source region 364a overlaps the source electrode layer 365a, and the drain electrode layer 365 The low-resistance drain region 364b overlapping the transistor 364b is formed in a self-aligned manner. A transistor 360 is formed.

[0403] Note that the oxide semiconductor layer overlapping with the drain electrode layer 365b (and the source electrode layer 365a) forming a low-resistance drain region 364b (or a low-resistance source region 364a) in This can improve the reliability of the transistor. By forming the region 364b, the low resistance drain region 364b and the channel region 364b are formed from the drain electrode layer. The conductivity can be changed stepwise from the first region to the second region 363. Therefore, the drain electrode layer 365b is connected to a wiring that supplies a high power supply potential VDD. When the device is operated, a high electric field is applied between the gate electrode layer 361 and the drain electrode layer 365b. Even if the transistor is turned on, the low-resistance drain region acts as a buffer to prevent a local high electric field from being applied. It is possible to provide a configuration in which the dielectric strength of the semiconductor device is improved.

[0404] A protective insulating layer 3 is formed on the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366. In this embodiment, the protective insulating layer 323 is formed using a silicon nitride film. (See Figure 17(D)).

[0405] Note that an insulating film is further formed over the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366. An oxide insulating layer may be formed and a protective insulating layer 323 may be stacked over the oxide insulating layer.

[0406] As described above, a transistor including an oxide semiconductor layer has stable electrical characteristics. A highly reliable transistor can be provided.

[0407] Note that this embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0408] (Embodiment 9) In this embodiment, a transistor that can be used in a DC converter circuit according to one embodiment of the present invention will be described. An example of a transistor that can be used will be described below.

[0409] An example of a transistor and a manufacturing method of the transistor of this embodiment will be described with reference to FIGS. 18A to 18C are cross-sectional views illustrating a method for manufacturing a transistor of this embodiment mode.

[0410] In addition, the transistor 350 has a single gate structure. The transistor is a multi-gate transistor having a plurality of channel formation regions. That's fine.

[0411] 18(A) to 18(D), a process for fabricating a transistor 350 on a substrate 340 will be described. Explain the process.

[0412] First, a conductive film is formed on a substrate 340 having an insulating surface, and then a first photolithography is performed. In this embodiment, the gate electrode layer 351 is formed by a process. A tungsten film with a thickness of 150 nm was deposited by sputtering as a conductive film for forming the tungsten film. and form it.

[0413] Next, the gate insulating layer 342 is formed on the gate electrode layer 351 .

[0414] Here, the oxide semiconductor (high-temperature) that has been made i-type or substantially i-type by removing impurities is Since the gate electrode (a purified oxide semiconductor) is extremely sensitive to the interface state and the interface charge, The interface between the gate insulating layer and the highly purified oxide semiconductor layer is important. The insulating layer (GI) is required to be of high quality.

[0415] For example, high density plasma CVD using microwaves (2.45 GHz) produces dense, high dielectric strength films. It is preferable to form a highly purified oxide semiconductor layer and a high-quality gate insulating film. By closely contacting the gate insulating layer, the interface state can be reduced and the interface characteristics can be improved. The high density plasma device used here is 1×10 11 / cm 3 Any device capable of achieving the above plasma density can be used.

[0416] For example, a microwave power of 3 kW to 6 kW is applied to generate plasma, and the insulating film is formed. The chamber is filled with monosilane gas (SiH4) and nitrous oxide (N2 O) and rare gas are introduced to generate high-density plasma under a pressure of 10 Pa to 30 Pa. An insulating film is formed on a substrate having an insulating surface such as a silicon dioxide gas. Nitrous oxide (N2O) and rare gases are introduced without exposing the insulating film to the atmosphere. Plasma treatment may be performed. At least nitrous oxide (N2O) and rare gases are introduced to provide insulation. The plasma treatment on the film surface is carried out after the insulating film is formed. The flow ratio of silane gas (SiH4) to nitrous oxide (N2O) is 1:10 to 1:20. The rare gas introduced into the chamber is helium, argon, Lipton, xenon, etc. can be used, but argon is the most inexpensive. It is preferable that:

[0417] Of course, if a good insulating film can be formed as the gate insulating layer 342, sputtering is also possible. Other film formation methods such as the ring method and plasma CVD method can be applied. The insulating film is one whose film quality and interface characteristics with the oxide semiconductor are improved by heat treatment. In any case, it goes without saying that the quality of the film as a gate insulating film is good. Any material may be used as long as it can reduce the interface state density with the oxide semiconductor and form a good interface.

[0418] Furthermore, at 85°C, 2 × 10 6 V / cm, 12-hour gate bias and thermal stress test (B In the T test, when impurities are added to an oxide semiconductor, the impurities and the oxide semiconductor The bonds between the main component of the compound are broken by a strong electric field (B: bias) and high temperature (T: temperature), The resulting dangling bonds induce a drift in the threshold voltage (Vth). The transistor used in the DC converter circuit of one embodiment of the present invention is an oxide semiconductor transistor. Impurities, especially hydrogen and water, are removed as much as possible to improve the interface characteristics with the gate insulating layer as described above. By doing so, it is possible to obtain a stable transistor even in BT tests. .

[0419] The gate insulating layer 342 may be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. Silicon layer (SiO x N y where x>y>0), silicon oxynitride layer (SiN x O y Also called, where x>y>0), or aluminum oxide layer formed as a single layer or laminated layer. It is possible.

[0420] The gate insulating layer 342 may be, for example, HfO x Gate HfO as the insulating layer 342 x By using the above, the gate electrode can be formed from the oxide semiconductor layer side. This can reduce the leakage current flowing toward the

[0421] The gate insulating layer 342 may have a structure in which a silicon oxide layer and a silicon nitride layer are stacked. In this embodiment, as an example, a high density microwave is generated at a pressure of 30 Pa and a microwave power of 6 kW. A silicon oxynitride layer with a thickness of 100 nm is formed by plasma CVD. The flow rate ratio of monosilane gas (SiH4) and nitrous oxide (N2O) introduced into the chamber is: The range is 1:10 to 1:200.

[0422] Next, a conductive film is formed on the gate insulating layer 342, and a conductive film is formed by a second photolithography process. A resist mask is formed on the conductive film, and selective etching is performed to form a source electrode layer 355a, After the drain electrode layer 355b is formed, the resist mask is removed (see FIG. 18A). .

[0423] Next, an oxide semiconductor film 345 is formed (see FIG. 18B). The semiconductor film 345 is formed by sputtering using an In-Ga-Zn-O metal oxide target. The oxide semiconductor film 345 is formed into an island by a third photolithography process. The oxide semiconductor layer is then processed into a shaped oxide semiconductor layer.

[0424] In this case, the oxide semiconductor film 345 is formed while removing residual moisture in the treatment chamber. In order to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film 345, This is the case.

[0425] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. Examples of adsorption type vacuum pumps include cryopumps, ion pumps, and titanium sublimation pumps. It is preferable to use a displacement pump. As the exhaust means, for example, a turbo pump is used. The film deposition chamber may be equipped with a cold trap. The chamber is evacuated, for example, of hydrogen atoms and compounds containing hydrogen atoms (such as water). By forming the oxide semiconductor film 345 in the deposition chamber, the impurity concentration in the oxide semiconductor film 345 can be reduced. Cut.

[0426] The oxide semiconductor film 345 is formed using a sputtering gas containing hydrogen, water, or High purity impurities such as acid groups or hydrides have been removed to concentrations of ppm or ppb. It is preferable to use a high-temperature gas.

[0427] Next, the oxide semiconductor layer is subjected to first heat treatment. The temperature of the first heat treatment is 400° C. or higher. The temperature is set to 750°C or less, preferably 400°C or more and less than the distortion point of the substrate. The substrate was placed in an electric furnace, which is one of the facilities, and the oxide semiconductor layer was heated to 450°C in a nitrogen atmosphere. After the heat treatment for 1 hour, the oxide semiconductor layer was cooled to room temperature and then cooled to room temperature without being exposed to the air. The oxide semiconductor layer 346 is obtained by the first heat treatment (see FIG. 18C). This results in dehydration or dehydrogenation.

[0428] In the first heat treatment, the substrate is immersed in an inert gas heated to a high temperature of 650°C to 700°C. After heating for several minutes, the substrate is removed from the inert gas heated to a high temperature. GRTA may also be used, which allows high-temperature heat treatment in a short period of time.

[0429] Furthermore, an oxide insulating layer 356 serving as a protective insulating film in contact with the oxide semiconductor layer 346 is formed. .

[0430] The oxide insulating layer 356 has a thickness of at least 1 nm and is formed by an oxide method such as a sputtering method. The insulating layer 356 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed in. When hydrogen is contained in the oxide insulating layer 356, the hydrogen penetrates into the oxide semiconductor layer, Alternatively, oxygen in the oxide semiconductor layer is extracted by hydrogen, and the back-channel of the oxide semiconductor layer is formed. The resistance of the panel will become low (N-type), which may result in the formation of a parasitic channel. In order to form the oxide insulating layer 356 as a film containing as little hydrogen as possible, hydrogen is not used in the deposition method. It is important that there is no

[0431] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering as the oxide insulating layer 356. The substrate temperature during film formation should be between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. The silicon oxide film is formed by sputtering using a rare gas ( Typically, under an atmosphere of argon, under an oxygen atmosphere, or under a rare gas atmosphere (typically, argon) and The process can be carried out in an oxygen atmosphere. For example, a silicon target can be used to oxidize oxygen and A silicon oxide film can be formed by sputtering in a nitrogen atmosphere. The oxide insulating layer 356 is formed in contact with the oxide semiconductor layer, which is in a low resistance state, i.e., is made N-type. is water, hydrogen ions, OH -It does not contain impurities such as A blocking inorganic insulating film is used, typically a silicon oxide film, a silicon oxynitride film, or an oxide An aluminum film, an aluminum oxynitride film, or the like is used.

[0432] In this case, the oxide insulating layer 356 is formed while removing residual moisture in the treatment chamber. It is preferable that the oxide semiconductor layer 346 and the oxide insulating layer 356 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed.

[0433] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. Examples of adsorption type vacuum pumps include cryopumps, ion pumps, and titanium sublimation pumps. It is preferable to use a displacement pump. As the exhaust means, for example, a turbo pump is used. The film deposition chamber may be equipped with a cold trap. The chamber is evacuated, for example, to hydrogen atoms and compounds containing hydrogen atoms such as water (H2O). Therefore, the impurity concentration in the oxide insulating layer 356 formed in the deposition chamber can be reduced.

[0434] The oxide insulating layer 356 is formed using a sputtering gas such as hydrogen, water, or hydroxide. High purity, with impurities such as bases or hydrides removed to concentrations of ppm or ppb. It is preferable to use a gas.

[0435] Next, a second heat treatment (preferably 200 ℃ or higher and 400℃ or lower, for example, 250℃ or higher and 350℃ or lower). After the second heat treatment, the oxide semiconductor layer The insulating film 356 is heated while a part of the insulating film 356 (channel formation region) is in contact with the insulating film 356.

[0436] As described above, by performing heat treatment for dehydration or dehydrogenation, the oxide semiconductor layer After making the material oxygen-deficient to reduce resistance, that is, to make it N-type, it is oxidized so that it comes into contact with the oxide semiconductor layer. By forming the insulating layer, the oxide semiconductor layer is made oxygen-excessive. A resistive I-type oxide semiconductor layer 352 is formed. Through the above steps, the transistor 350 is formed. will be done.

[0437] A protective insulating layer may be further formed on the oxide insulating layer 356. For example, In this embodiment mode, a silicon nitride film is formed as a protective insulating layer. The edge layer 343 is formed using a silicon nitride film (see FIG. 18(D)).

[0438] Further, a planarization insulating layer for planarization may be provided over the protective insulating layer 343.

[0439] As described above, a transistor including an oxide semiconductor layer has stable electrical characteristics and is reliable. This makes it possible to provide a highly reliable transistor.

[0440] This embodiment mode can be combined with or replaced with any of the other embodiment modes as appropriate.

[0441] (Embodiment 10) This embodiment can be applied to a transistor included in a DC converter circuit according to one embodiment of the present invention. An example of such a transistor will be described.

[0442] In this embodiment, an example in which a part of a manufacturing process of a transistor is different from that in Embodiment 7 is shown in FIG. Figure 19 is the same as Figure 16 except for some differences in the process, so the same parts are marked with the same characters. Reference numerals are used and detailed explanations of the same parts are omitted.

[0443] First, a gate electrode layer 381 is formed on a substrate 370, and a first gate insulating layer 372a and a second gate insulating layer 372b are formed on the gate electrode layer 381. In this embodiment, the gate insulating layer has a two-layer structure. The first gate insulating layer 372a is a nitride insulating layer, and the second gate insulating layer 372b is an oxide insulating layer. A border layer is used.

[0444] The oxide insulating layer may be, for example, a silicon oxide layer, a silicon oxynitride layer, or an aluminum oxide layer. An aluminum layer, an aluminum oxynitride layer, or the like can be used. Examples of the layer include a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, and an aluminum nitride oxide layer. A minium layer or the like can be used.

[0445] The first gate insulating layer 372a or the second gate insulating layer 372b may be made of, for example, H fO x The first gate insulating layer 372a or the second gate insulating layer HfO as 372b x By using the above, it is possible to form a gate electrode from the oxide semiconductor layer side. The leakage current that may flow can be reduced.

[0446] In this embodiment, a silicon nitride layer and a silicon oxide layer are stacked from the gate electrode layer 381 side. The first gate insulating layer 372a is formed by sputtering to a thickness of 50 nm. A silicon nitride layer (SiN y (y> 0)) is formed on the first gate insulating layer 372a, and a film is formed as a second gate insulating layer 372b on the first gate insulating layer 372a. A silicon oxide layer (SiO ) having a thickness of 5 nm to 300 nm (100 nm in this embodiment) x (x>0)) is laminated to form a gate insulating layer with a thickness of 150 nm.

[0447] Next, an oxide semiconductor film is formed, and the oxide semiconductor film is divided into islands by a photolithography process. In this embodiment, an In—Ga—Zn—O system oxide semiconductor layer is used as an example. An oxide semiconductor film is formed by a sputtering method using a metal oxide target.

[0448] In this case, it is preferable to form the oxide semiconductor film while removing residual moisture in the treatment chamber. This is preferable in order to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film.

[0449] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. Examples of adsorption type vacuum pumps include cryopumps, ion pumps, and titanium sublimation pumps. It is preferable to use a displacement pump. As the exhaust means, for example, a turbo pump is used. The film deposition chamber may be equipped with a cold trap. The chamber is evacuated, for example, to hydrogen atoms and compounds containing hydrogen atoms such as water (H2O). Therefore, the impurity concentration in the oxide semiconductor film formed in the deposition chamber can be reduced.

[0450] The sputtering gas used in forming the oxide semiconductor film may be hydrogen, water, a hydroxyl group, or a fluorine-containing gas. is a high-purity gas in which impurities such as hydrides have been removed to concentrations of ppm or ppb. It is preferable to use

[0451] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment is 400°C or higher and 750°C or lower, preferably 425°C or higher and 750°C or lower. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. In this case, the heat treatment time is set to be longer than one hour. The substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to heat treatment in a nitrogen atmosphere. After this, the oxide semiconductor layer is prevented from being exposed to the air and from being contaminated with water or hydrogen. In the same furnace, high-purity oxygen gas, high-purity N2O gas, or ultra-dry air (dew point below -40°C) Cooling is performed by introducing oxygen gas or N2O gas into the reactor. It is preferable that hydrogen and the like are not contained. Alternatively, oxygen gas or N2 introduced into the heat treatment device The purity of the O gas is 6N (99.9999%) or more, preferably 7N (99.99999%). ) or more (i.e., the impurity concentration in the oxygen gas or N2O gas is 1 ppm or less, preferably 0. It is preferable to keep the concentration at 1 ppm or less.

[0452] The heat treatment device is not limited to an electric furnace, but may be any other suitable device such as a GRTA device or a LRTA device. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps It is a device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a In addition, heat conduction or heat from heating elements such as LRTA devices, lamps, and resistance heating elements is also used. A device that heats the object to be treated by radiation may be used. GRTA is a device that uses high-temperature gas. The gas used is a rare gas such as argon or a gas containing a nitriding agent such as nitrogen. An inert gas that does not react with the material to be treated is used. Heat treatment may be carried out at 0°C to 750°C for several minutes.

[0453] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. Heat treatment is usually performed at a temperature between 200°C and 300°C in an oxygen gas or N2O gas atmosphere. You may go.

[0454] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. The substrate is taken out and subjected to a photolithography process.

[0455] By going through the above steps, the entire oxide semiconductor layer is made into an oxygen-excess state, and thus a high resistance Thus, the oxide semiconductor layer 382 is entirely i-type.

[0456] Next, a conductive film is formed over the oxide semiconductor layer 382, ​​and a resist film is formed by a photolithography process. A mask is formed, and selective etching is performed to form the source electrode layer 385a and the drain electrode layer 385b. 385b is formed, and an oxide insulating layer 386 is formed by sputtering.

[0457] In this case, the oxide insulating layer 386 is formed while removing residual moisture in the processing chamber. It is preferable that the oxide semiconductor layer 382 and the oxide insulating layer 386 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed.

[0458] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. Examples of adsorption type vacuum pumps include cryopumps, ion pumps, and titanium sublimation pumps. It is preferable to use a displacement pump. As the exhaust means, for example, a turbo pump is used. The film deposition chamber may be equipped with a cold trap. The chamber is evacuated, for example, to hydrogen atoms and compounds containing hydrogen atoms such as water (H2O). Therefore, the impurity concentration in the oxide insulating layer 386 formed in the deposition chamber can be reduced.

[0459] The sputtering gas used in forming the oxide insulating layer 386 is hydrogen, water, a hydroxyl group, or a water High-purity gas is used, in which impurities such as chlorine compounds have been removed to concentrations of ppm or ppb. It is preferable that

[0460] Through the above steps, the transistor 380 can be formed.

[0461] Note that in order to reduce variations in the electrical characteristics of the transistors, Heat treatment (preferably at 150° C. or higher and lower than 350° C.) may be performed in a nitrogen gas atmosphere. For example, heat treatment is carried out in a nitrogen atmosphere at 250° C. for 1 hour.

[0462] In addition, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heat treatment may be carried out by maintaining the temperature at the heating temperature, or by heating from room temperature to 100°C or higher and 200°C or lower. Heat treatment may be performed by repeatedly raising the temperature to a heating temperature and lowering the temperature from the heating temperature to room temperature. Heat treatment under reduced pressure can shorten the heating time. Hydrogen is taken into the oxide insulating layer from the oxide semiconductor layer, and a normally-off transistor is formed. Therefore, the reliability of the transistor can be improved.

[0463] The protective insulating layer 373 is formed over the oxide insulating layer 386. In this embodiment, the protective insulating layer 3 As the film 73, a silicon nitride film having a thickness of 100 nm is formed by sputtering.

[0464] The protective insulating layer 373 and the first gate insulating layer 372a made of a nitride insulating layer are resistant to moisture and water. It does not contain impurities such as hydrogen, hydrides, or hydroxides, and blocks these from entering from the outside. It has the effect of checking.

[0465] Therefore, in the manufacturing process after the protective insulating layer 373 is formed, impurities such as moisture from the outside This can prevent the intrusion of foreign matter and improve the long-term reliability of the device.

[0466] Also, a protective insulating layer 373 made of a nitride insulating layer and a first gate insulating layer 372a are provided between the protective insulating layer 373 and the first gate insulating layer 372a. A part of the insulating layer to be formed is removed to bond the protective insulating layer 373 to the first gate insulating layer 372a. The structure may be such that:

[0467] Therefore, impurities such as moisture, hydrogen, hydrides, and hydroxides in the oxide semiconductor layer can be removed as much as possible. and preventing the inclusion of the impurities, thereby maintaining the impurity concentration in the oxide semiconductor layer low. It is possible.

[0468] Further, a planarization insulating layer for planarization may be provided over the protective insulating layer 373.

[0469] A conductive layer overlapping with the oxide semiconductor layer may be provided over the protective insulating layer 373. The potential may be the same as or different from that of the gate electrode layer 381 of the transistor 380. The conductive layer may also function as a second gate electrode layer. It may be a fixed potential of V.

[0470] The conductive layer can control the electrical characteristics of the transistor 380 .

[0471] As described above, a transistor including an oxide semiconductor layer has stable electrical characteristics. A highly reliable transistor can be provided.

[0472] This embodiment mode can be combined with or replaced with any of the other embodiment modes as appropriate.

[0473] (Embodiment 11) The DC converter circuit of one embodiment of the present invention can be combined with various other power storage devices to form a power supply circuit. In this embodiment, a power supply using a DC converter circuit according to one embodiment of the present invention can be realized. The power supply circuit will now be described.

[0474] An example of the configuration of the power supply circuit of this embodiment will be described with reference to FIG. 1 is a block diagram showing an example of the configuration of a power supply circuit according to an embodiment;

[0475] The power supply circuit shown in FIG. 20 includes a power storage device 601 and a DC conversion circuit 602.

[0476] The power storage device 601 has a function of supplying power. Conversion device, lithium ion secondary battery, lithium ion capacitor, electric double layer capacitor and a redox capacitor, or any one or more thereof. By using a lithium-ion secondary battery and a lithium-ion capacitor together, high-speed charging and discharging is possible. This makes it possible to provide a power storage device that can be charged and can supply power for a long period of time. The power storage device 601 is not limited to a lithium ion secondary battery, and may be any other alkaline metal A secondary battery using ions or alkaline earth metal ions as mobile ions may also be used. In addition, the power storage device 601 is not limited to a lithium ion capacitor, and may be any other alkaline A capacitor using lithium metal ions or alkaline earth metal ions as mobile ions is used. It's fine.

[0477] The DC conversion circuit 602 is electrically connected to the power storage device 601. For example, the DC converter circuit described in the first or second embodiment can be used. Cut.

[0478] As shown in FIG. 20, an example of the power supply circuit of this embodiment includes a power storage device and a DC conversion circuit. The power supplied by the power storage device is boosted or reduced by the DC conversion circuit, It generates a power supply voltage that is suitable for the specifications of the device that supplies power. In a power supply circuit of the present invention, a DC converter circuit according to one embodiment of the present invention is used as a DC converter circuit. This makes it possible to improve the reliability of the power supply circuit.

[0479] This embodiment mode can be appropriately combined with or replaced with other embodiment modes. do.

[0480] (Embodiment 12) This embodiment mode will describe an electronic device to which the power supply circuit shown in Embodiment 11 can be applied. An example will be described with reference to FIG.

[0481] FIG. 21(A) shows a notebook personal computer, which includes a main body 3001, a housing 300 2, a display unit 3003, a keyboard 3004, etc. A) is used to generate the power supply voltage for the notebook personal computer shown above. The power supply circuit of the eleventh embodiment can be applied.

[0482] FIG. 21(B) shows a mobile phone, which is composed of two housings, a housing 2800 and a housing 2801. The housing 2801 contains a display panel 2802, a speaker 2803, a microphone, and 2804, pointing device 2806, camera lens 2807, external connection terminal 2808. The housing 2800 also includes a solar cell for charging the mobile phone. The antenna is mounted on the housing 28 It is built into the 01.

[0483] The display panel 2802 is equipped with a touch panel, and in FIG. 21(B) an image is displayed. The multiple operation keys 2805 are shown by dotted lines. The solar cell 2810 and the voltage output from the solar cell 2810 are required for each circuit. The power supply circuit is implemented using a DC conversion circuit that converts the voltage into a suitable voltage.

[0484] As described above, the power supply circuit according to the eleventh embodiment can be applied to various electronic devices. Furthermore, by applying the power supply circuit according to the eleventh embodiment to electronic equipment, reliability can be improved. It is possible to provide high-quality electronic equipment.

[0485] This embodiment mode can be appropriately combined with or replaced with other embodiment modes. do. [Explanation of symbols]

[0486] 101 Inductive element 102 transistor 103 Rectifying element 104 Control circuit 201 Coil 202 Transistor 203 Diode 204 Capacitor element 205 Hysteresis Comparator 221 Comparator 222 Comparator 223 Inverter 224 Inverter 225 NOR Gate 226 NOR Gate 300 boards 302 Gate insulating layer 303 Protective insulation layer 310 Transistor 311 Gate electrode layer 313 Channel formation region 314a Low-resistance source region 314b Low-resistivity drain region 315a Source electrode layer 315b drain electrode layer 316 Oxide insulating layer 320 board 322 Gate insulating layer 323 Protective Insulation Layer 330 Oxide semiconductor film 331 Oxide semiconductor layer 332 Oxide semiconductor layer 340 PCB 342 Gate insulating layer 343 Protective Insulation Layer 345 Oxide semiconductor film 346 Oxide semiconductor layer 350 transistors 351 Gate electrode layer 352 Oxide semiconductor layer 355a Source electrode layer 355b drain electrode layer 356 Oxide insulating layer 360 Transistor 361 Gate electrode layer 362 Oxide semiconductor layer 363 Channel formation region 364a Low-resistance source region 364b Low-resistance drain region 365a Source electrode layer 365b drain electrode layer 366 Oxide insulating layer 370 PCB 372a Gate insulating layer 372b Gate insulating layer 373 Protective Insulation Layer 380 transistors 381 Gate electrode layer 382 Oxide semiconductor layer 385a Source electrode layer 385b Drain electrode layer 386 Oxide insulating layer 390 transistors 391 gate electrode layer 392 Oxide semiconductor layer 393 Oxide Semiconductor Film 394 PCB 395a Source electrode layer 395b Drain electrode layer 396 Oxide insulating layer 397 Gate insulating layer 398 Protective Insulation Layer 399 Oxide semiconductor layer 400 boards 402 Gate insulating layer 407 Insulating Layer 410 Transistor 411 Gate electrode layer 412 Oxide semiconductor layer 414a wiring layer 414b wiring layer 415a Source electrode layer 415b Drain electrode layer 420 silicon substrate 421a aperture 421b aperture 422 Insulating layer 423 Aperture 424 Conductive Layer 425 transistor 426 Transistor 427 Conductive Layer 450 board 452 Gate insulating layer 457 Insulating Layer 460 transistors 461 Gate electrode layer 461a Gate electrode layer 461b Gate electrode layer 462 Oxide semiconductor layer 464 Wiring layer 465a Electrode layer 465b Electrode layer 465a1 Electrode layer 465a2 Electrode layer 468 Wiring layer 601 Electricity storage device 602 DC conversion circuit 1001 gate electrode 1002 Gate insulating film 1003 Oxide semiconductor layer 1004a Source electrode 1004b Drain electrode 1005 oxide insulating layer 1006 Conductive layer 2800 chassis 2801 Case 2802 Display panel 2803 Speaker 2804 Microphone 2805 Operation Key 2806 Pointing Device 2807 Camera lenses 2808 External connection terminal 2810 solar cell 2811 External Memory Slot 3001 main unit 3002 Case 3003 Display section 3004 Keyboard

Claims

1. a first conductive film; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of a transistor; a second conductive film having a region in contact with the oxide semiconductor film and a region disposed above the oxide semiconductor film; a third conductive film having a region in contact with the oxide semiconductor film, a region disposed above the oxide semiconductor film, and electrically connected to the first conductive film; a fourth conductive film that functions as a gate electrode of the transistor and has a region located above the oxide semiconductor film, the third conductive film has a region overlapping with the first conductive film with the oxide semiconductor film interposed therebetween; the fourth conductive film has a region overlapping with the first conductive film with the oxide semiconductor film interposed therebetween; the fourth conductive film has an opening, the first conductive film has an area larger than that of the second conductive film; Semiconductor device.

2. a first conductive film; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of a transistor; a second conductive film having a region in contact with the oxide semiconductor film and a region disposed above the oxide semiconductor film; a third conductive film having a region in contact with the oxide semiconductor film, a region disposed above the oxide semiconductor film, and electrically connected to the first conductive film; a fourth conductive film that functions as a gate electrode of the transistor and has a region located above the oxide semiconductor film, the third conductive film has a region overlapping with the first conductive film with the oxide semiconductor film interposed therebetween; the fourth conductive film has a region overlapping with the first conductive film with the oxide semiconductor film interposed therebetween; the fourth conductive film has an opening, the first conductive film has an area larger than that of the second conductive film, an area of ​​a region where the first conductive film and the oxide semiconductor film overlap each other is larger than an area of ​​a region where the second conductive film and the oxide semiconductor film overlap each other; Semiconductor device.

3. a first conductive film; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of a transistor; a second conductive film having a region in contact with the oxide semiconductor film and a region disposed above the oxide semiconductor film; a third conductive film having a region in contact with the oxide semiconductor film, a region disposed above the oxide semiconductor film, and electrically connected to the first conductive film; a fourth conductive film that functions as a gate electrode of the transistor and has a region located above the oxide semiconductor film, the third conductive film has a region overlapping with the first conductive film with the oxide semiconductor film interposed therebetween; the fourth conductive film has a region overlapping with the first conductive film with the oxide semiconductor film interposed therebetween; the fourth conductive film has an opening, the oxide semiconductor film overlaps with the opening, the first conductive film has a larger area than the second conductive film; Semiconductor device.

4. a first conductive film; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of a transistor; a second conductive film having a region in contact with the oxide semiconductor film and a region disposed above the oxide semiconductor film; a third conductive film having a region in contact with the oxide semiconductor film, a region disposed above the oxide semiconductor film, and electrically connected to the first conductive film; a fourth conductive film that functions as a gate electrode of the transistor and has a region located above the oxide semiconductor film, the third conductive film has a region overlapping with the first conductive film with the oxide semiconductor film interposed therebetween; the fourth conductive film has a region overlapping with the first conductive film with the oxide semiconductor film interposed therebetween; the fourth conductive film has an opening, the oxide semiconductor film overlaps with the opening, the first conductive film has an area larger than that of the second conductive film, an area of ​​a region where the first conductive film and the oxide semiconductor film overlap each other is larger than an area of ​​a region where the second conductive film and the oxide semiconductor film overlap each other; Semiconductor device.

5. In any one of claims 1 to 4, the second conductive film does not have an area overlapping with the first conductive film; Semiconductor device.

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