Semiconductor element and semiconductor device having semiconductor element

Abstract

To provide a semiconductor element capable of suppressing chipping and capable of curbing a reduction in the number of products, in a manufacturing process.SOLUTION: A semiconductor element A10 comprises: a semiconductor substrate 31; a semiconductor layer 32 which is overlaid on the semiconductor substrate 31 and within which a circuit is formed; a conductive layer 34 which is arranged on the opposite side of the semiconductor substrate 31 with respect to the semiconductor layer 32 and which includes a part brought into conduction with the circuit; and a plurality of veers 38 which are arranged between the semiconductor layer 32 and the conductive layer 34 and which are brought into conduction with the conductive layer 34. The conductive layer 34 includes a confirmation pattern 342a that is not brought into conduction with the circuit. The plurality of veers 38 include an overlapping part 38a that overlaps the confirmation pattern 342a, in a view in a z-direction.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor element and a semiconductor device including the semiconductor element. [Background technology]

[0002] Semiconductor elements are manufactured by forming a semiconductor layer, electrodes, a protective layer, etc. on a semiconductor substrate and then dicing it into individual pieces. Patent Document 1 discloses a method for manufacturing semiconductor elements, and describes that semiconductor elements are manufactured by forming a semiconductor film, a dielectric film, a protective film, bonding pads, etc. on a silicon-based substrate and then cutting it in a dicing region.

[0003] During the semiconductor device manufacturing process, a check pattern is formed to inspect the appropriateness of the resist placement. Because the check pattern is not required for the finished product, it is formed in the dicing area, which is removed by dicing during the cutting process. If the check pattern contains hard metal, chipping may occur during dicing. For this reason, a region (hereinafter referred to as a "drop-in region") that is not the main pattern for the semiconductor device is provided within one shot of the photomask, and a check pattern is placed in this drop-in region. In this case, semiconductor devices that do not become products in the drop-in region are produced with each shot, resulting in a reduced number of semiconductor devices. If, for example, 30 main patterns can be placed within one shot without the drop-in region, adding the drop-in region reduces the number of semiconductor devices that can be produced to 29, a reduction of more than 3%. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] WO2015 / 068597 Summary of the Invention [Problem to be solved by the invention]

[0005] The present disclosure has been made in light of the above circumstances, and an object of the present disclosure is to provide a semiconductor element that can suppress chipping during the manufacturing process and also suppress a decrease in the yield. [Means for solving the problem]

[0006] The semiconductor element provided by the present disclosure comprises a semiconductor substrate, a semiconductor layer stacked on the semiconductor substrate and having a circuit formed therein, a conductive layer arranged on the opposite side of the semiconductor layer from the semiconductor substrate and including a portion that is conductive to the circuit, and a conductive portion arranged between the semiconductor layer and the conductive layer and that is conductive to the conductive layer, wherein the conductive layer includes a confirmation pattern that is not conductive to the circuit, and the conductive portion includes an overlapping portion that overlaps the confirmation pattern when viewed in the thickness direction of the semiconductor substrate.

[0007] The method for manufacturing a semiconductor element provided by the present disclosure includes a lamination process for laminating a semiconductor layer having a circuit formed therein and a passivation film on a semiconductor substrate, a via formation process for forming a plurality of vias penetrating the passivation film, and a conductive layer formation process for forming a conductive layer including a portion that is conductive to the circuit through the plurality of vias, wherein the conductive layer includes a confirmation pattern that is not conductive to the circuit, and the plurality of vias include vias that form an overlapping portion that overlaps the confirmation pattern when viewed in the thickness direction of the semiconductor substrate, and the conductive layer formation process includes a seed layer formation process for forming a seed layer in contact with the passivation film, a resist formation process for forming a resist on the seed layer having a plurality of openings for forming the conductive layer, and an inspection process for visually inspecting from the thickness direction to confirm the positional relationship between a confirmation opening for forming the confirmation pattern among the plurality of openings and the overlapping portion located in the confirmation opening. [Effects of the Invention]

[0008] According to the semiconductor element according to the present disclosure, chipping can be suppressed in the manufacturing process, and a decrease in the yield can be suppressed.

[0009] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view showing a semiconductor element according to a first embodiment of the present disclosure, seen through a protective layer. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 2 is a partially enlarged view of FIG. [Figure 5] FIG. 2 is a partially enlarged view of FIG. [Figure 6] FIG. 3 is a partially enlarged view of FIG. 2. [Figure 7] FIG. 4 is a partially enlarged view of FIG. [Figure 8] 2 is a plan view showing a step in an example of a method for manufacturing the semiconductor device of FIG. 1. FIG. [Figure 9] 2 is a cross-sectional view showing one step of an example of a method for manufacturing the semiconductor element of FIG. 1. [Figure 10] 2 is a cross-sectional view showing one step of an example of a method for manufacturing the semiconductor element of FIG. 1. [Figure 11] 2 is an enlarged cross-sectional view showing one step of an example of a method for manufacturing the semiconductor element of FIG. 1. FIG. [Figure 12] 2 is an enlarged cross-sectional view showing one step of an example of a method for manufacturing the semiconductor element of FIG. 1. FIG. [Figure 13] 2 is a cross-sectional view showing one step of an example of a method for manufacturing the semiconductor element of FIG. 1. [Figure 14] 2 is an enlarged cross-sectional view showing one step of an example of a method for manufacturing the semiconductor element of FIG. 1. FIG. [Figure 15] 2 is a plan view showing a step in an example of a method for manufacturing the semiconductor device of FIG. 1. FIG. [Figure 16] 2 is an enlarged plan view showing a step in an example of a method for manufacturing the semiconductor device of FIG. 1. FIG. [Figure 17]2 is an enlarged cross-sectional view showing one step of an example of a method for manufacturing the semiconductor element of FIG. 1. FIG. [Figure 18] 2 is a cross-sectional view showing one step of an example of a method for manufacturing the semiconductor element of FIG. 1. [Figure 19] 2 is a cross-sectional view showing one step of an example of a method for manufacturing the semiconductor element of FIG. 1. [Figure 20] 2 is a plan view showing a semiconductor device including the semiconductor element of FIG. 1, seen through a sealing resin. FIG. [Figure 21] FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 20. [Figure 22] FIG. 10 is a plan view showing a semiconductor element according to a second embodiment of the present disclosure, seen through a protective layer. [Figure 23] FIG. 10 is a plan view showing a semiconductor element according to a third embodiment of the present disclosure, seen through a protective layer. [Figure 24] FIG. 10 is a plan view showing a semiconductor element according to a fourth embodiment of the present disclosure, seen through a protective layer. [Figure 25] FIG. 10 is an enlarged plan view showing a semiconductor element according to a fifth embodiment of the present disclosure, seen through a protective layer. [Figure 26] FIG. 10 is an enlarged plan view showing a semiconductor element according to a sixth embodiment of the present disclosure, seen through a protective layer. [Figure 27] FIG. 10 is an enlarged cross-sectional view showing a semiconductor element according to a seventh embodiment of the present disclosure. [Figure 28] FIG. 13 is an enlarged plan view showing a semiconductor element according to a seventh embodiment of the present disclosure, seen through a protective layer. DETAILED DESCRIPTION OF THE INVENTION

[0011] Preferred embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0012] In this disclosure, unless otherwise specified, the terms "a certain object A is formed on an object B" and "a certain object A is formed on an object B" include "a certain object A is formed directly on an object B" and "a certain object A is formed on an object B with another object interposed between the objects A and B." Similarly, the terms "a certain object A is disposed on an object B" and "a certain object A is disposed on an object B" include "a certain object A is disposed directly on an object B" and "a certain object A is disposed on an object B with another object interposed between the objects A and B," unless otherwise specified. Similarly, the term "a certain object A is located on an object B" includes "a certain object A is located on an object B in contact with the object B" and "a certain object A is located on an object B with another object interposed between the objects A and B," unless otherwise specified. Additionally, unless otherwise specified, "something A overlaps something B when viewed from a certain direction" includes "something A overlaps the entirety of something B" and "something A overlaps part of something B."

[0013] First Embodiment 1 to 7 show an example of a semiconductor device according to the present disclosure. The semiconductor device A10 of this embodiment includes a semiconductor substrate 31, a semiconductor layer 32, a passivation film 33, a conductive layer 34, an insulating layer 35, a plurality of electrode terminals 36, a plurality of internal electrodes 37, and a plurality of vias 38. The semiconductor device A10 is a flip-chip type LSI having a circuit configured therein.

[0014] FIG. 1 is a plan view showing a semiconductor element A10. For ease of understanding, FIG. 1 shows an insulating layer 35 in a see-through manner. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1. FIG. 4 is a partial enlarged view of FIG. 1 (near a confirmation pattern 342a, which will be described later). FIG. 5 is a partial enlarged view of FIG. 1 (near a confirmation pattern 342b, which will be described later). FIG. 6 is a partial enlarged view of FIG. 2 (near an electrode terminal 36). FIG. 7 is a partial enlarged view of FIG. 3 (near a confirmation pattern 342a).

[0015] The semiconductor element A10 is plate-shaped and has a rectangular shape when viewed in the thickness direction (plan view). For ease of explanation, the thickness direction (plan view) of the semiconductor element A10 is defined as the z direction, the direction along one side of the semiconductor element A10 perpendicular to the z direction (the up-down direction in FIG. 1) is defined as the x direction, and the direction perpendicular to the z direction and the x direction (the left-right direction in FIG. 1) is defined as the y direction. The z direction corresponds to the "thickness direction" in this disclosure, the x direction corresponds to the "first direction" in this disclosure, and the y direction corresponds to the "second direction" in this disclosure. The shape and dimensions of the semiconductor element A10 are not limited.

[0016] The semiconductor element A10 has an element principal surface 30a and an element back surface 30b. The element principal surface 30a and the element back surface 30b face in opposite directions in the z direction. The element principal surface 30a faces one side in the z direction (upper side in FIGS. 2 and 3). The element principal surface 30a has a plurality of electrodes 341 and a plurality of electrode terminals 36 (described later) arranged thereon, and is the surface that is flip-chip mounted onto a circuit board or the like. The element back surface 30b faces the other side in the z direction (lower side in FIGS. 2 and 3).

[0017] As shown in FIGS. 2 and 3 , the semiconductor substrate 31 is provided with a semiconductor layer 32, a passivation film 33, a conductive layer 34, an insulating layer 35, and a plurality of electrode terminals 36 on one side in the z direction (hereinafter referred to as the “upper side”). The semiconductor substrate 31 is made of, for example, silicon (Si) or silicon carbide (SiC). In this embodiment, the surface of the semiconductor substrate 31 opposite to the side on which the semiconductor layer 32 is stacked constitutes the device back surface 30b. As shown in FIG. 1 , the semiconductor substrate 31 has a first substrate side 311, a second substrate side 312, a third substrate side 313, and a fourth substrate side 314. The first substrate side 311, the second substrate side 312, the third substrate side 313, and the fourth substrate side 314 are the sides of the surface of the semiconductor substrate 31 on which the semiconductor layer 32 is stacked. The first substrate side 311 and the third substrate side 313 extend in the x direction, and the second substrate side 312 and the fourth substrate side 314 extend in the y direction. The first substrate side 311 and the second substrate side 312 are perpendicular to each other.

[0018] As shown in FIGS. 2 and 3, the semiconductor layer 32 is stacked on the upper side of the semiconductor substrate 31 in the z direction. The semiconductor layer 32 includes a plurality of types of p-type semiconductors and n-type semiconductors based on differences in the amount of elements to be doped. The semiconductor layer 32 includes a switching circuit 321 and a control circuit 322 that is electrically connected to the switching circuit 321. The switching circuit 321 may be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). In this embodiment, the switching circuit 321 is divided into two regions: a high-voltage region (upper arm circuit) and a low-voltage region (lower arm circuit). Each region is configured with one n-channel MOSFET. The control circuit 322 is configured with a gate driver for driving the switching circuit 321, a bootstrap circuit corresponding to the high-voltage region of the switching circuit 321, and the like, and performs control for driving the switching circuit 321 normally. Note that a wiring layer (not shown) is further configured in the semiconductor layer 32. The wiring layer provides mutual conduction between the switching circuit 321 and the control circuit 322.

[0019] 2 and 3, the passivation film 33 covers the upper surface of the semiconductor layer 32 in the z direction. The passivation film 33 has electrical insulation properties. The passivation film 33 may be, for example, a silicon oxide (SiO2) film in contact with the semiconductor layer 32 and a silicon oxide film (SiO2) formed on the silicon oxide film. In this embodiment, the surface of the passivation film 33 opposite to the semiconductor layer 32 constitutes the element main surface 30a.

[0020] As shown in FIGS. 6 and 7, the multiple internal electrodes 37 are disposed at appropriate positions between the semiconductor layer 32 and the passivation film 33. Most of the internal electrodes 37 are connected to the wiring layer of the semiconductor layer 32 and are electrically connected to the switching circuit 321 and the control circuit 322. In this embodiment, the multiple internal electrodes 37 contain Al and are formed by, for example, electroless plating. The material and method for forming the multiple internal electrodes 37 are not limited. Furthermore, the shape and arrangement position of each internal electrode 37 are not limited.

[0021] The multiple internal electrodes 37 include multiple internal electrodes 371 (see FIG. 7). The multiple internal electrodes 371 are not connected to the wiring layer of the semiconductor layer 32. In this embodiment, the semiconductor element A10 has two internal electrodes 371. Each internal electrode 371 is disposed at a position where a confirmation pattern 342 (described later) is disposed, at the upper left corner of the semiconductor element A10 in FIG. 1 and at the diagonally opposite lower right corner. The number, arrangement position, and shape of the internal electrodes 371 are not limited.

[0022] As shown in FIGS. 6 and 7, the vias 38 are formed to penetrate the passivation film 33 and contact the internal electrodes 37. The vias 38 are conductors that electrically connect the internal electrodes 37, which are arranged in contact with the semiconductor layer 32, to the conductive layer 34 arranged on the element main surface 30a. The vias 38 are formed by forming through holes that penetrate the passivation film 33 and communicate with the internal electrodes 37, and forming a conductor containing, for example, W (tungsten) or Cu on the inner walls of the through holes. The shape of each via 38 when viewed in the x direction and the y direction is rectangular. The vias 38 correspond to the "conductive portion" of the present disclosure.

[0023] 7, the plurality of vias 38 includes a plurality of vias 381. The plurality of vias 381 are those of the plurality of vias 38 that contact the internal electrodes 371. Some of the plurality of vias 381 contact the internal electrodes 371 arranged in the upper left corner of the semiconductor element A10 in FIG. 1, and an overlapping portion 38a that is an aggregate of these vias has an overall shape, as shown in FIG. 4, in the z direction as viewed in the z direction, of a right-angled triangle having an overlapping portion first side 38a1 (shown by a two-dot chain line in FIG. 4) that is parallel to the substrate first side 311 and an overlapping portion second side 38a2 (shown by a two-dot chain line in FIG. 4) that is parallel to the substrate second side 312. In addition, the remaining multiple vias 381 are in contact with an internal electrode 371 located in the lower right corner of the semiconductor element A10 in Figure 1, and the overlapping portion 38b, which is a collection of these, has an overall shape when viewed in the z direction, as shown in Figure 5, in the shape of a right triangle having an overlapping portion first side 38b1 (shown by a dotted line in Figure 5) that is parallel to the substrate third side 313, and an overlapping portion second side 38b2 (shown by a dotted line in Figure 5) that is parallel to the substrate fourth side 314.

[0024] As shown in FIGS. 1 to 3, the conductive layer 34 is formed on the element principal surface 30a. In this embodiment, as shown in FIGS. 6 and 7, the conductive layer 34 is composed of multiple metal layers stacked on the passivation film 33, and includes a first layer 34a, a second layer 34b, and a third layer 34c. The first layer 34a contacts the passivation film 33 and is made of Cu. The second layer 34b contacts the first layer 34a and is made of Ni. The third layer 34c contacts the second layer 34b and is made of Pd. The configuration of the conductive layer 34 is not limited. The conductive layer 34 contacts multiple vias 38 provided in the passivation film 33 and is electrically connected to multiple internal electrodes 37 through the multiple vias 38. As shown in FIG. 1, the conductive layer 34 includes multiple electrodes 341 and multiple identification patterns 342.

[0025] The multiple electrodes 341 are electrically connected to either the switching circuit 321 or the control circuit 322 of the semiconductor layer 32. As shown in FIG. 1 , the multiple electrodes 341 formed in a region overlapping the switching circuit 321 as viewed in the z direction have a relatively large area and are arranged densely together. In this embodiment, the shapes of the electrodes 341 as viewed in the z direction include a shape in which two approximately rhombus shapes elongated in the y direction are connected in the y direction, a shape in which an approximately rhombus shape elongated in the y direction is connected to an approximately triangular shape elongated in the y direction, and a approximately triangular shape elongated in the y direction. The multiple electrodes 341 formed in a region overlapping the control circuit 322 as viewed in the z direction have a relatively small area and are arranged isolated from each other. The shapes of the electrodes 341 as viewed in the z direction include a rectangular shape and a shape having a portion extending from a rectangular shape. The shape and arrangement of each electrode 341 are not limited. As shown in Figure 6, the multiple electrodes 341 are connected to internal electrodes 37 connected to the wiring layer of the semiconductor layer 32 through multiple vias 38, and are thereby electrically connected to either the switching circuit 321 or the control circuit 322 of the semiconductor layer 32.

[0026] The multiple confirmation patterns 342 are intended to check whether the conductive layer 34 can be formed in the correct position during the process of forming the conductive layer 34 in the manufacturing process described below, and in this embodiment, two confirmation patterns 342 are arranged as shown in Fig. 1. The multiple confirmation patterns 342 include confirmation pattern 342a and confirmation pattern 342b.

[0027] As shown in FIG. 1, the confirmation pattern 342a is disposed in the upper left corner of the semiconductor element A10 (semiconductor substrate 31) when viewed in the z direction. As shown in FIG. 4, the confirmation pattern 342a overlaps with and includes the overlapping portion 38a when viewed in the z direction. The confirmation pattern 342a has a right-angled triangular shape when viewed in the z direction, with a first confirmation side 342a1 parallel to the substrate first side 311 and the overlapping portion first side 38a1, and a second confirmation side 342a2 parallel to the substrate second side 312 and the overlapping portion second side 38a2. The lengths of the first confirmation side 342a1 and the second confirmation side 342a2 are not limited, but are, for example, approximately 100 μm in this embodiment. In this embodiment, the distance w1 between the first confirmation side 342a1 and the overlapping portion 38a is within a predetermined range (for example, 20 μm to 30 μm). Furthermore, the distance w2 between the second confirmation side 342a2 and the overlapping portion 38a is also within a predetermined range (for example, 20 μm to 30 μm). Note that the ranges of w1 and w2 are not limited.

[0028] As shown in FIG. 1, the confirmation pattern 342b is disposed at the lower right corner of the semiconductor element A10 (semiconductor substrate 31) when viewed in the z direction. That is, the confirmation pattern 342a and the confirmation pattern 342b are disposed at diagonally opposite corners of the semiconductor element A10 (semiconductor substrate 31). The confirmation pattern 342b overlaps the overlapping portion 38b when viewed in the z direction and includes the overlapping portion 38b. The confirmation pattern 342b has a right-angled triangular shape when viewed in the z direction, having a first confirmation side 342b1 parallel to the substrate third side 313 and the overlapping portion first side 38b1, and a second confirmation side 342b2 parallel to the substrate fourth side 314 and the overlapping portion second side 38b2. In this embodiment, the distance w1′ between the first confirmation side 342b1 and the overlapping portion 38b is within a predetermined range (e.g., 20 μm or more and 30 μm or less). Furthermore, the distance w2' between the second check side 342b2 and the overlapping portion 38b is also within a predetermined range (for example, 20 μm to 30 μm). Note that the ranges of w1' and w2' are not limited.

[0029] 7, each confirmation pattern 342 is connected through a plurality of vias 381 to an internal electrode 371 that is not connected to a wiring layer of the semiconductor layer 32, and is not electrically connected to the switching circuit 321 and the control circuit 322 of the semiconductor layer 32. The number, arrangement position, and shape of each confirmation pattern 342 as viewed in the z direction are not limited. For example, the shape of each confirmation pattern 342 as viewed in the z direction may be rectangular, circular, fan-shaped, or another shape. However, a triangular shape such as a right-angled triangle is preferable because it allows for more effective use of the area of ​​the corners.

[0030] As shown in FIGS. 2 and 3 , the insulating layer 35 is formed on the element principal surface 30 a, contacts the passivation film 33 and the conductive layer 34, and covers most of them. The insulating layer 35 has electrical insulation properties. In this embodiment, the constituent material of the insulating layer 35 is phenolic resin. However, the constituent material of the insulating layer 35 is not limited, and other insulating materials such as polyimide resin may be used. As shown in FIG. 6 , the insulating layer 35 has a plurality of openings 35 a penetrating in the z direction. One of the electrodes 341 is exposed from each of the plurality of openings 35 a. The insulating layer 35 is formed, for example, by applying photolithography to a photosensitive resin material applied by a spin coater.

[0031] As shown in FIG. 6 , the multiple electrode terminals 36 are provided on the upper side (the element main surface 30a side) of the semiconductor element A10 in the z direction and protrude upward. The shape (planar shape) of the electrode terminals 36 as viewed in the z direction is not limited, and may be a circle, an oval, a rectangle, a polygon, or the like, as appropriate. In this embodiment, each electrode terminal 36 has the same circular shape as viewed in the z direction. The dimensions of the electrode terminals 36 are not limited, and an example is a diameter of 100 μm. Each of the multiple electrode terminals 36 contacts one of the electrodes 341 through an opening 35 a in the insulating layer 35. In this embodiment, each electrode terminal 36 contacts the electrode 341 at its center as viewed in the z direction and overlaps the insulating layer 35 at its peripheral edge. The multiple electrode terminals 36 are conductive. Each electrode terminal 36 is electrically connected to either the switching circuit 321 or the control circuit 322 of the semiconductor layer 32 via an electrode 341, a plurality of vias 38, an internal electrode 37, and a power distribution layer.

[0032] As shown in FIG. 6 , each electrode terminal 36 includes a pillar portion 361 and a solder portion 362. The pillar portion 361 includes a seed layer 361a, a first plating layer 361b, and a second plating layer 361c. The seed layer 361a is in contact with the electrode 341 and the insulating layer 35 and contains Cu. The seed layer 361a is formed, for example, by electroless plating. Note that the constituent material and formation method of the seed layer 361a are not limited. For example, the seed layer 361a may be formed by sputtering. The first plating layer 361b is laminated on the seed layer 361a and is made of, for example, Cu or a Cu alloy. The first plating layer 361b is formed by electrolytic plating. Note that the constituent material of the first plating layer 361b is not limited. The second plating layer 361c is laminated on the first plating layer 361b. The second plating layer 361c is interposed between the first plating layer 361b and the solder portion 362 and functions to suppress a chemical reaction between the first plating layer 361b and the solder portion 362. The constituent material of the second plating layer 361c is not particularly limited, and a metal capable of suppressing the chemical reaction is appropriately selected, such as Ni or Fe. In this embodiment, the first plating layer 361b contains Cu and the solder portion 362 contains Sn, so the second plating layer 361c is made of, for example, Ni. In this embodiment, the second plating layer 361c is formed by electrolytic plating. The constituent material and the method for forming the second plating layer 361c are not limited. Furthermore, the second plating layer 361c is not necessarily required. A recess 361d, the center of which is recessed from the periphery, is formed on the tip surface of the pillar portion 361 (the surface facing away from the electrode 341).

[0033] The solder portion 362 is conductive and is formed on the tip surface of the pillar portion 361. In this embodiment, the solder portion 362 is made of, for example, a solder containing Sn (such as SnAg). The solder portion 362 is formed by electrolytic plating. Note that the constituent material and formation method of the solder portion 362 are not limited.

[0034] Next, an example of a method for manufacturing the semiconductor element A10 will be described below with reference to FIGS. 8 to 19. FIGS. 8 to 19 each show a step in an example of a method for manufacturing the semiconductor element A10. FIGS. 8 and 15 are plan views. FIGS. 9 to 10, 13, 18, and 19 are cross-sectional views. FIGS. 11, 12, 14, and 17 are enlarged cross-sectional views. FIG. 16 is an enlarged plan view.

[0035] First, as shown in FIG. 8, a semiconductor substrate 81 is prepared. The semiconductor substrate 81 is, for example, a silicon wafer, in which a plurality of semiconductor substrates 31 are connected in a direction perpendicular to the z direction. In FIG. 8, the boundaries of each shot area on the semiconductor substrate 81, to which a photomask image is transferred by exposure, are indicated by imaginary lines (two-dot chain lines). In the example of FIG. 8, the semiconductor substrate 81 includes 54 shot areas. Each shot area includes multiple areas in which semiconductor elements A10 are formed. In the enlarged view below one shot area in FIG. 8, the boundaries of each area in which the semiconductor elements A10 are formed are indicated by imaginary lines (two-dot chain lines). In the example of FIG. 8, one shot area includes areas in which 30 semiconductor elements A10 are formed. Therefore, in the example of FIG. 8, one semiconductor substrate 81 includes areas in which 1620 semiconductor elements A10 are formed. Note that the number of shot areas included in the semiconductor substrate 81 and the number of areas in which the semiconductor elements A10 are formed in each shot area are not limited. Furthermore, the arrangement of each shot region on the semiconductor substrate 81 and the arrangement of the region in which the semiconductor element A10 is formed in the shot region are not limited.

[0036] 9, a semiconductor layer 82 is laminated on the semiconductor substrate 81. The semiconductor layer 82 corresponds to the semiconductor layer 32 of the semiconductor element A10. The semiconductor layer 82 is formed by, for example, epitaxial growth. A switching circuit 321 and a control circuit 322 are formed inside the semiconductor layer 82.

[0037] Next, as shown in FIG. 10, a passivation film 83 is laminated on the semiconductor layer 82. The passivation film 83 corresponds to the passivation film 33 of the semiconductor element A10. As shown in FIG. 11, a plurality of internal electrodes 37 are formed at appropriate positions between the semiconductor layer 82 and the passivation film 83. The internal electrodes 37 are formed, for example, by electroless plating, and the passivation film 83 is formed, for example, by plasma CVD. At this time, internal electrodes 371 are formed at positions corresponding to two diagonal corners of each semiconductor element A10, as shown in FIG. 11. Each internal electrode 371 is not electrically connected to the switching circuit 321 and the control circuit 322 of the semiconductor layer 32.

[0038] Next, as shown in Fig. 12, a plurality of vias 38 are formed. First, through holes are formed through the passivation film 83 to reach the internal electrodes 37, and then a conductor containing, for example, W (tungsten) or Cu is formed on the inner walls of the through holes, thereby forming the vias 38. At this time, a plurality of vias 381 are formed in contact with the internal electrodes 371, as shown in Fig. 12. A collection of these vias 381 constitutes an overlapping portion 38a whose overall shape when viewed in the z direction is a right-angled triangle.

[0039] Next, the conductive layer 34 is formed. First, a seed layer 34d is formed in contact with the passivation film 83. The seed layer 34d is made of Cu and is formed, for example, by sputtering. The constituent material and formation method of the seed layer 34d are not limited. The seed layer 34d may be a laminate of multiple layers. Next, as shown in FIGS. 13 to 16, a resist 84 is formed on the seed layer 34d. The resist 84 has an opening 85 in the area where the conductive layer 34 will be formed. FIG. 13 is a cross-sectional view corresponding to FIG. 2. FIG. 14 is an enlarged cross-sectional view corresponding to FIG. 7. FIG. 15 is a plan view in which the resist 84 is dotted. FIG. 16 is an enlarged plan view in which the area X surrounded by the thick line in FIG. 15 is enlarged. In FIG. 16, the boundary lines of the areas where the semiconductor elements A10 are formed are indicated by imaginary lines (two-dot chain lines). The resist 84 is formed by applying a resist material so as to cover the entire surface of the seed layer 34d, and then applying photolithography to transfer an image of a photomask and patterning it to form openings 85.

[0040] Next, the appropriateness of the position of each opening 85 in the resist 84 is inspected so that the conductive layer 34 can be formed in the correct position. This inspection is performed in an area X centered on the intersection of the area where the four semiconductor elements A10 are to be formed, as shown in Figures 15 and 16. Note that it is not necessary to inspect the areas X at all intersections, and inspection is performed in a plurality of areas X (for example, nine areas) that are set in advance on the semiconductor substrate 81.

[0041] 16 , region X includes a confirmation opening 85a, which is an opening 85 for forming a confirmation pattern 342a of one semiconductor element A10, and a confirmation opening 85b, which is an opening 85 for forming a confirmation pattern 342b of another semiconductor element A10. When viewed in the z direction, the overlapping portion 38a contained in the confirmation opening 85a and the overlapping portion 38b contained in the confirmation opening 85b are visible due to the steps of the multiple vias 381, even after the thin seed layer 34d is formed. In inspection of region X, the positional relationship between the confirmation opening 85a and the overlapping portion 38a and the positional relationship between the confirmation opening 85b and the overlapping portion 38b when viewed in the z direction are confirmed based on, for example, an image captured of region X. Specifically, it is determined whether the distance w1 between the first opening side 851 of the confirmation opening 85a, which is parallel to the x direction, and the overlapping portion 38a is within a predetermined range (e.g., 20 μm to 30 μm), and whether the distance w2 between the second opening side 852 of the confirmation opening 85a, which is parallel to the y direction, and the overlapping portion 38a is within a predetermined range (e.g., 20 μm to 30 μm). It is also determined whether the distance w1' between the first opening side 851 of the confirmation opening 85b, which is parallel to the x direction, and the overlapping portion 38b is within a predetermined range (e.g., 20 μm to 30 μm), and whether the distance w2' between the second opening side 852 of the confirmation opening 85b, which is parallel to the y direction, and the overlapping portion 38b is within a predetermined range (e.g., 20 μm to 30 μm). If the distances w1, w2, w1', and w2' are all within the predetermined ranges, it is determined that the inspection has passed. The predetermined ranges of the intervals w1, w2, w1', and w2' are not limited and may be different from one another.

[0042] If the inspection passes, a plating layer 34e is formed in contact with the seed layer 34d exposed from the opening 85. The plating layer 34e is made of Cu and is formed by electrolytic plating using the seed layer 34d as a conductive path. The plating layer 34e is integrated with the seed layer 34d to form the first layer 34a. Next, a second layer 34b is formed in contact with the first layer 34a. The second layer 34b is made of Ni and is formed by electrolytic plating. Next, a third layer 34c is formed in contact with the second layer 34b. The third layer 34c is made of Pd and is formed by electrolytic plating. Next, as shown in Figures 17 and 18, the resist 84 and unnecessary seed layer 34d are removed, thereby forming the conductive layer 34.

[0043] Next, as shown in FIG. 19, an insulating layer 86 is formed to cover the passivation film 83 and the conductive layer 34. A plurality of openings 86a penetrating the insulating layer 86 in the z direction are formed at appropriate locations. The insulating layer 86 is formed, for example, by applying photolithography to a photosensitive resin material applied by a spin coater. The insulating layer 86 corresponds to the insulating layer 35 of the semiconductor element A10, and the openings 86a correspond to the openings 35a of the semiconductor element A10.

[0044] Next, a plurality of electrode terminals 36 are formed so as to contact any of the electrodes 341 through the openings 86a in the insulating layer 86. Next, the semiconductor substrate 81, the semiconductor layer 82, the passivation film 83, and the insulating layer 86 are cut with a dicing blade along cutting lines parallel to the x direction and cutting lines parallel to the y direction to separate them into individual pieces. Through the above steps, the semiconductor element A10 shown in FIGS. 1 to 7 is manufactured.

[0045] Next, a semiconductor device B10 incorporating the semiconductor element A10 will be described.

[0046] The semiconductor element A10 is provided as a semiconductor device that is flip-chip bonded to multiple leads and covered with a sealing resin. FIGS. 20 and 21 show a semiconductor device B10 that includes the semiconductor element A10. The semiconductor device B10 includes the semiconductor element A10, multiple leads 10, and a sealing resin 40. FIG. 20 is a plan view showing the semiconductor device B10. For ease of understanding, in FIG. 20, the outline of the sealing resin 40 is shown by an imaginary line (a two-dot chain line) through the sealing resin 40. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 20. The package format of the semiconductor device B10 is not particularly limited, and in this embodiment, it is a QFN (Quad Flat Non-leaded package) type, as shown in FIG. 20. Furthermore, the application and function of the semiconductor device B10 are not limited in any way. Examples of applications of the semiconductor device B10 include electronic devices, general industrial equipment, and automotive applications. Furthermore, the functions of the semiconductor device B10 include, for example, a DC / DC converter, an AC / DC converter, and the like, as appropriate.

[0047] 20, the semiconductor element A10 is disposed in the center of the semiconductor device B10 when viewed in the z direction. The semiconductor element A10 is supported by a plurality of leads 10. The semiconductor element A10 is flip-chip bonded with the element main surface 30a facing the plurality of leads 10, and each electrode 341 is connected to one of the plurality of leads 10 via an electrode terminal 36. The semiconductor element A10 is covered with a sealing resin 40.

[0048] As shown in FIG. 20, the multiple leads 10 support the semiconductor element A10. Also, as shown in FIG. 21, a portion of each of the multiple leads 10 is covered with a sealing resin 40. A portion of each lead 10 is exposed from the sealing resin 40 and serves as a terminal for mounting the semiconductor device B10 on a wiring board. The multiple leads 10 are formed by, for example, etching a metal plate made of, for example, Cu or a Cu alloy. The multiple leads 10 are spaced apart from one another and include leads 11 to 15 and multiple leads 16. Leads 11 to 15 are electrically connected to a switching circuit 321 of the semiconductor element A10. The multiple leads 16 are each electrically connected to a control circuit 322 of the semiconductor element A10. The number of the multiple leads 10, and the shape and arrangement of each lead 10 are not limited.

[0049] The sealing resin 40 covers the entire semiconductor element A10 and a portion of each of the leads 10. The sealing resin 40 is made of a material containing, for example, black epoxy resin. However, the material of the sealing resin 40 is not limited.

[0050] The package type and structure of the semiconductor device on which the semiconductor element A10 is mounted are not limited. The mounting method of the semiconductor element A10 is not limited to flip-chip bonding, and the semiconductor element A10 may be connected to each lead by wire or the like.

[0051] Next, the effects of the semiconductor device A10 will be described.

[0052] According to this embodiment, the conductive layer 34 includes a confirmation pattern 342a and a confirmation pattern 342b. The vias 38 include a plurality of vias 381. Some of the vias 381 form overlapping portions 38a that are included in the confirmation pattern 342a when viewed in the z direction. The remaining vias 381 form overlapping portions 38b that are included in the confirmation pattern 342b when viewed in the z direction. During the formation process of the conductive layer 34, the appropriateness of the position of each opening 85 in the resist 84 can be inspected by checking the positional relationship between the confirmation opening 85a and the overlapping portions 38a and the positional relationship between the confirmation opening 85b and the overlapping portions 38b when viewed in the z direction. The confirmation patterns 342a and 342b are located at corners of the semiconductor element A10 (semiconductor substrate 31) when viewed in the z direction, and are not formed in the area to be diced. Therefore, chipping due to the confirmation patterns 342a and 342b does not occur during dicing in the manufacturing process. Furthermore, since there is no need to provide a drop-in area within one shot of the photomask, the reduction in the number of products that can be obtained can be suppressed.

[0053] Furthermore, according to this embodiment, the shape of the confirmation pattern 342a, as viewed in the z direction, is a right-angled triangle having a first confirmation side 342a1 parallel to the first substrate side 311 and a second confirmation side 342a2 parallel to the second substrate side 312. The shape of the confirmation pattern 342b, as viewed in the z direction, is a right-angled triangle having a first confirmation side 342b1 parallel to the third substrate side 313 and a second confirmation side 342b2 parallel to the fourth substrate side 314. The confirmation patterns 342a and 342b are disposed at diagonal corners of the semiconductor element A10 (semiconductor substrate 31) as viewed in the z direction. Therefore, in the process of inspecting the resist 84, by visually checking the region X, it is possible to simultaneously check the misalignment of each opening 85 of the resist 84 in four directions (one side and the other side in the x direction, and one side and the other side in the y direction).

[0054] Furthermore, according to this embodiment, when viewed in the z direction, overlapping portion 38a is included in confirmation pattern 342a, and overlapping portion 38b is included in confirmation pattern 342b. Therefore, in the process of inspecting resist 84, it is easy to check for misalignment between confirmation opening 85a in resist 84 and confirmation opening 85a.

[0055] Furthermore, according to this embodiment, the check patterns 342a and 342b are arranged at the corners of the semiconductor element A10 (semiconductor substrate 31) when viewed in the z direction, and therefore do not interfere with the arrangement of the electrodes 341.

[0056] 22 to 28 show other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are denoted by the same reference numerals as those in the above embodiment.

[0057] Second Embodiment Fig. 22 is a diagram illustrating a semiconductor element A20 according to a second embodiment of the present disclosure. Fig. 22 is a plan view showing the semiconductor element A20, and corresponds to Fig. 1. For ease of understanding, Fig. 22 shows the insulating layer 35 through-holes. The semiconductor element A20 of this embodiment differs from the first embodiment in the number of confirmation patterns 342.

[0058] In this embodiment, the semiconductor element A20 has four confirmation patterns 342, including confirmation patterns 342c and 342d in addition to confirmation patterns 342a and 342b according to the first embodiment. Confirmation pattern 342c is located at the lower left corner of the semiconductor element A20 (semiconductor substrate 31) in FIG. 22. Confirmation pattern 342d is located at the upper right corner of the semiconductor element A20 (semiconductor substrate 31) in FIG. 22. That is, confirmation patterns 342 are located at all four corners of the semiconductor element A20 as viewed in the z direction. Furthermore, multiple vias 381 forming overlapping portions are located at positions included in confirmation patterns 342c and 342d as viewed in the z direction.

[0059] In this embodiment as well, the appropriateness of the position of each opening 85 in the resist 84 can be inspected in the process of forming the conductive layer 34. Furthermore, chipping caused by the confirmation patterns 342a, 342b, 342c, and 342d does not occur during dicing in the manufacturing process, and a decrease in the number of pieces obtained can be suppressed.

[0060] Furthermore, according to this embodiment, the confirmation patterns 342a, 342b, 342c, and 342d are each a right-angled triangle and are arranged at the four corners of the semiconductor element A10 (semiconductor substrate 31) when viewed in the z direction. Therefore, in the inspection process of the resist 84, by visually checking the area X, it is possible to check misalignment in four directions of each opening 85 of the resist 84 at once.

[0061] Furthermore, according to this embodiment, when viewed in the z direction, the confirmation patterns 342a, 342b, 342c, and 342d each include an overlapping portion, which makes it easy to check for misalignment of each confirmation opening in the resist 84 in the process of inspecting the resist 84. Furthermore, when viewed in the z direction, the confirmation patterns 342a, 342b, 342c, and 342d are arranged at corners of the semiconductor element A20 (semiconductor substrate 31), which does not interfere with the arrangement of the electrode 341.

[0062] Third Embodiment 23 is a diagram illustrating a semiconductor element A30 according to a third embodiment of the present disclosure. FIG. 23 is a plan view showing the semiconductor element A30, and corresponds to FIG. 1. For ease of understanding, FIG. 23 shows the insulating layer 35 in a transparent manner. The semiconductor element A30 of this embodiment differs from the first embodiment in the number and shape of the confirmation patterns 342.

[0063] In this embodiment, the semiconductor element A30 has only one confirmation pattern 342a. In FIG. 23, the confirmation pattern 342a is located in the upper left corner of the semiconductor element A30 (semiconductor substrate 31). When viewed in the z direction, the confirmation pattern 342a has a rectangular shape with each side parallel to the x direction or the y direction. When viewed in the z direction, the overlapping portion 38a that overlaps the confirmation pattern 342a has a rectangular shape that matches the confirmation pattern 342a and is included in the confirmation pattern 342a.

[0064] In this embodiment as well, the appropriateness of the position of each opening 85 in the resist 84 can be inspected in the process of forming the conductive layer 34. Furthermore, chipping caused by the confirmation pattern 342a does not occur during dicing in the manufacturing process, and a decrease in the number of pieces obtained can be suppressed.

[0065] Furthermore, in this embodiment, the shape of the confirmation pattern 342a is a rectangle with each side parallel to the x-direction or the y-direction. Therefore, in the process of inspecting the resist 84, by visually checking the confirmation opening 85a for forming the confirmation pattern 342a, it is possible to simultaneously check for misalignment in four directions (one side and the other side in the x-direction, and one side and the other side in the y-direction) of the opening 85 in the resist 84.

[0066] Furthermore, according to this embodiment, the confirmation pattern 342a includes the overlapping portion 38a when viewed in the z direction, making it easy to check for misalignment of the confirmation opening 85a of the resist 84 in the inspection process of the resist 84. Furthermore, the confirmation pattern 342a is disposed at a corner of the semiconductor element A30 (semiconductor substrate 31) when viewed in the z direction, so it does not interfere with the placement of the electrode 341.

[0067] <Fourth embodiment> Fig. 24 is a diagram illustrating a semiconductor element A40 according to a fourth embodiment of the present disclosure. Fig. 24 is a plan view showing the semiconductor element A40 and corresponds to Fig. 1. For ease of understanding, Fig. 24 shows the insulating layer 35 through the view. The semiconductor element A40 of this embodiment differs from the third embodiment in the position of the confirmation pattern 342.

[0068] In this embodiment, the semiconductor element A40 has only one confirmation pattern 342a. In FIG. 24, the confirmation pattern 342a is disposed in a position where no electrodes 341 are formed, in the center in the x direction and toward the right side in the y direction of the semiconductor element A30 (semiconductor substrate 31). When viewed in the z direction, the shape of the confirmation pattern 342a is a rectangle with each side parallel to the x direction or the y direction. When viewed in the z direction, the shape of the overlapping portion 38a that overlaps the confirmation pattern 342a when viewed in the z direction is a rectangle that matches the confirmation pattern 342a and is included in the confirmation pattern 342a.

[0069] In this embodiment as well, the appropriateness of the position of each opening 85 in the resist 84 can be inspected in the process of forming the conductive layer 34. Furthermore, chipping caused by the confirmation pattern 342a does not occur during dicing in the manufacturing process, and a decrease in the number of pieces obtained can be suppressed.

[0070] Furthermore, in this embodiment, the shape of the confirmation pattern 342a is a rectangle with each side parallel to the x-direction or the y-direction. Therefore, in the process of inspecting the resist 84, by visually checking the confirmation opening 85a for forming the confirmation pattern 342a, it is possible to check for misalignment in four directions of the opening 85 of the resist 84 at once.

[0071] Furthermore, according to this embodiment, the confirmation pattern 342a includes the overlapping portion 38a when viewed in the z direction, so that misalignment of the confirmation opening 85a of the resist 84 can be easily confirmed in the process of inspecting the resist 84.

[0072] The arrangement position of the confirmation patterns 342a is not limited, and may be an end in the x direction or an end in the y direction. As in the first to third embodiments, each confirmation pattern 342 is preferably arranged at a corner of the semiconductor substrate 31 when viewed in the z direction, but may be arranged anywhere as long as it does not interfere with the arrangement of the electrodes 341.

[0073] Fifth Embodiment 25 is a diagram illustrating a semiconductor element A50 according to a fifth embodiment of the present disclosure. FIG. 25 is an enlarged plan view showing the semiconductor element A50, and corresponds to FIG. 4. For ease of understanding, FIG. 25 shows the insulating layer 35 in a transparent manner. The semiconductor element A50 of this embodiment differs from the third embodiment in the shape of the confirmation pattern 342.

[0074] In this embodiment, the semiconductor element A50 has only one confirmation pattern 342a. The confirmation pattern 342a is located in the upper left corner of the semiconductor element A50 (semiconductor substrate 31) in FIG. 25. When viewed in the z direction, the shape of the confirmation pattern 342a is a regular octagon with two sides parallel to the x direction and the other two sides parallel to the y direction. When viewed in the z direction, the shape of the overlapping portion 38a that overlaps with the confirmation pattern 342a is a regular octagon that matches the confirmation pattern 342a and is included in the confirmation pattern 342a.

[0075] In this embodiment as well, the appropriateness of the position of each opening 85 in the resist 84 can be inspected in the process of forming the conductive layer 34. Furthermore, chipping caused by the confirmation pattern 342a does not occur during dicing in the manufacturing process, and a decrease in the number of pieces obtained can be suppressed.

[0076] Furthermore, in this embodiment, the shape of the confirmation pattern 342a is a regular octagon. Therefore, in the process of inspecting the resist 84, by visually checking the confirmation opening 85a for forming the confirmation pattern 342a, it is possible to check misalignment in eight directions of the opening 85 of the resist 84 at once.

[0077] Furthermore, according to this embodiment, the confirmation pattern 342a includes the overlapping portion 38a when viewed in the z direction, making it easy to check for misalignment of the confirmation opening 85a of the resist 84 in the inspection process of the resist 84. Furthermore, the confirmation pattern 342a is disposed at a corner of the semiconductor element A50 (semiconductor substrate 31) when viewed in the z direction, so it does not interfere with the placement of the electrode 341.

[0078] The shape of the confirmation pattern 342a as viewed in the z direction is not limited to this and may be another polygonal shape.

[0079] Sixth Embodiment 26 is a diagram illustrating a semiconductor element A60 according to a sixth embodiment of the present disclosure. FIG. 26 is an enlarged plan view showing the semiconductor element A60, and corresponds to FIG. 4. For ease of understanding, FIG. 26 shows the insulating layer 35 in perspective. The semiconductor element A60 of this embodiment differs from the first embodiment in that the confirmation pattern 342a is included in the overlapping portion 38a when viewed in the z direction.

[0080] In this embodiment, when viewed in the z direction, the overlapping portion 38a is not included in the confirmation pattern 342a, but rather includes the confirmation pattern 342a. The overlapping portion 38a is formed to extend beyond the first confirmation side 342a1 and the second confirmation side 342a2 by a predetermined amount. Although not shown in FIG. 26, the overlapping portion 38b is also formed to include the confirmation pattern 342b and extend beyond the first confirmation side 342b1 and the second confirmation side 342b2 by a predetermined amount when viewed in the z direction.

[0081] According to this embodiment, in the inspection step of the conductive layer 34 formation step, if the confirmation opening 85a is visually observed from the z direction and a portion other than the overlapping portion 38a is exposed through the confirmation opening 85a, it can be determined that the position of each opening 85 in the resist 84 is misaligned by a predetermined amount or more. Therefore, by checking the positional relationship between the confirmation opening 85a and the overlapping portion 38a and the positional relationship between the confirmation opening 85b and the overlapping portion 38b when viewed from the z direction, the appropriateness of the position of each opening 85 in the resist 84 can be inspected. Furthermore, during dicing in the manufacturing process, chipping due to the confirmation patterns 342a and 342b does not occur, and a decrease in the number of pieces that can be obtained can be suppressed.

[0082] Furthermore, according to this embodiment, the confirmation patterns 342a and 342b are each shaped like a right triangle and are arranged at diagonal corners of the semiconductor element A60 (semiconductor substrate 31) when viewed in the z direction. Therefore, in the process of inspecting the resist 84, by visually checking the area X, it is possible to check misalignment in four directions of each opening 85 of the resist 84 at once. Furthermore, because the confirmation patterns 342a and 342b are arranged at the corners of the semiconductor element A60 (semiconductor substrate 31) when viewed in the z direction, they do not interfere with the arrangement of the electrodes 341.

[0083] Seventh Embodiment 27 and 28 are diagrams illustrating a semiconductor element A70 according to a seventh embodiment of the present disclosure. Fig. 27 is an enlarged cross-sectional view showing the semiconductor element A70, and corresponds to Fig. 7. Fig. 28 is an enlarged plan view showing the semiconductor element A70, and corresponds to Fig. 4. The semiconductor element A70 of this embodiment differs from the first embodiment in that it does not include multiple vias 38.

[0084] In this embodiment, the semiconductor element A70 does not have multiple vias 38 formed therein, and multiple internal electrodes 37 are in contact with the conductive layer 34. Therefore, as shown in FIG. 27, the confirmation pattern 342a is in contact with the internal electrode 371. The confirmation pattern 342b is also in contact with the internal electrode 371. As shown in FIG. 28, the shape of the internal electrode 371a, which is the internal electrode 371 in contact with the confirmation pattern 342a, when viewed in the z direction is the same as the shape of the overlapping portion 38a according to the first embodiment, and is included in the confirmation pattern 342a. Although not shown, the shape of the internal electrode 371b, which is the internal electrode 371 in contact with the confirmation pattern 342b, when viewed in the z direction is the same as the shape of the overlapping portion 38b according to the first embodiment, and is included in the confirmation pattern 342b. In this embodiment, the multiple internal electrodes 37 correspond to the "second conductive layer" of the present disclosure, and the internal electrodes 371a and 371b correspond to the "overlapping portion" of the present disclosure.

[0085] According to this embodiment, in the step of forming the conductive layer 34, by checking the positional relationship between the confirmation opening 85a and the internal electrode 371a and the positional relationship between the confirmation opening 85b and the internal electrode 371b as viewed in the z direction, it is possible to inspect the appropriateness of the position of each opening 85 in the resist 84. Furthermore, during dicing in the manufacturing process, chipping due to the confirmation patterns 342a and 342b does not occur, and a decrease in the number of pieces that can be obtained can be suppressed.

[0086] Furthermore, according to this embodiment, the confirmation patterns 342a and 342b are each shaped like a right triangle and are arranged at diagonal corners of the semiconductor element A70 (semiconductor substrate 31) as viewed in the z direction. Therefore, in the process of inspecting the resist 84, by visually checking the area X, misalignment of each opening 85 in the resist 84 in four directions can be checked at once. Furthermore, according to this embodiment, as viewed in the z direction, the internal electrode 371a is included in the confirmation pattern 342a, and the internal electrode 371b is included in the confirmation pattern 342b. Therefore, in the process of inspecting the resist 84, misalignment of the confirmation opening 85a and the confirmation opening 85a in the resist 84 can be easily checked. Furthermore, since the confirmation patterns 342a and 342b are arranged at corners of the semiconductor element A60 (semiconductor substrate 31) as viewed in the z direction, they do not interfere with the arrangement of the electrodes 341.

[0087] The semiconductor element, semiconductor device, and semiconductor element manufacturing method according to the present disclosure are not limited to the above-described embodiments. The specific configurations of each part of the semiconductor element and semiconductor device according to the present disclosure, and the specific processing of each step of the semiconductor element manufacturing method according to the present disclosure can be freely designed in various ways.

[0088] [Appendix 1] a semiconductor substrate; a semiconductor layer laminated on the semiconductor substrate and having a circuit formed therein; a conductive layer disposed on the opposite side of the semiconductor layer from the semiconductor substrate and including a portion electrically connected to the circuit; a conductive portion disposed between the semiconductor layer and the conductive layer and electrically connected to the conductive layer; the conductive layer includes a confirmation pattern that is not conductive to the circuit; the conductive portion includes an overlapping portion that overlaps the confirmation pattern when viewed in a thickness direction of the semiconductor substrate. Semiconductor element. [Appendix 2] When viewed in the thickness direction, the overlapping portion is included in the confirmation pattern. 2. The semiconductor device of claim 1. [Appendix 3] The conductive layer contains Cu. 3. The semiconductor device according to claim 1 or 2. [Appendix 4] the semiconductor substrate includes a substrate first side extending in a first direction perpendicular to the thickness direction, and a substrate second side extending in a second direction perpendicular to the thickness direction and the first direction; The confirmation pattern has a first confirmation side parallel to the first side of the substrate and a second confirmation side parallel to the second side of the substrate. A semiconductor device according to any one of appendices 1 to 3. [Appendix 5] the overlapping portion is composed of a plurality of conductors each having a rectangular shape when viewed in the first direction, When viewed in the thickness direction, the overall shape of the overlapping portion made up of the plurality of conductors includes an overlapping portion first side that is parallel to the confirmation first side. 5. The semiconductor device of claim 4. [Appendix 6] When viewed in the thickness direction, the overall shape includes an overlapping portion second side that is parallel to the confirmation second side. 6. The semiconductor device of claim 5. [Appendix 7] When viewed in the thickness direction, the shape of the confirmation pattern is triangular. A semiconductor device according to any one of appendices 1 to 6. [Appendix 8] When viewed in the thickness direction, the shape of the confirmation pattern is quadrangular. A semiconductor device according to any one of appendices 1 to 6. [Appendix 9] the confirmation pattern is located at a corner of the semiconductor substrate when viewed in the thickness direction. A semiconductor device according to any one of appendices 1 to 8. [Appendix 10] the conductive layer includes a second confirmation pattern that is not conductive to the circuit; the conductive portion includes a second overlapping portion that overlaps the second confirmation pattern when viewed in the thickness direction, and the second confirmation pattern is located at a second corner portion diagonally opposite the corner portion of the semiconductor substrate when viewed in the thickness direction. 10. The semiconductor device of claim 9. [Appendix 11] a passivation film interposed between the semiconductor layer and the conductive layer; the conductive portion is a plurality of vias that penetrate the passivation film and contact the conductive layer; A semiconductor device according to any one of appendixes 1 to 10. [Appendix 12] 11. The semiconductor element according to claim 1, wherein the conductive portion is a second conductive layer formed on the semiconductor layer and in contact with the conductive layer. [Appendix 13] The second conductive layer contains Al. 13. The semiconductor device of claim 12. [Appendix 14] an insulating layer in contact with the conductive layer and having an opening exposing a portion of the conductive layer; 14. A semiconductor device according to any one of claims 1 to 13. [Appendix 15] A semiconductor element according to any one of Supplementary Notes 1 to 14; a sealing resin that covers the semiconductor element; Equipped with Semiconductor device. [Appendix 16] a lamination step of laminating a semiconductor layer having a circuit formed therein and a passivation film on a semiconductor substrate; a via forming step of forming a plurality of vias penetrating the passivation film; a conductive layer forming step of forming a conductive layer including a portion that is electrically connected to the circuit through the plurality of vias; Equipped with the conductive layer includes a confirmation pattern that is not conductive to the circuit; the plurality of vias include a via that forms an overlapping portion that overlaps the confirmation pattern when viewed in a thickness direction of the semiconductor substrate, The conductive layer forming step includes: a seed layer forming step of forming a seed layer in contact with the passivation film; a resist forming step of forming a resist having a plurality of openings for forming the conductive layer on the seed layer; an inspection step of visually inspecting the thickness direction to confirm a positional relationship between a confirmation opening for forming the confirmation pattern among the plurality of openings and the overlapping portion located in the confirmation opening; Equipped with A method for manufacturing semiconductor devices. [Appendix 17] the confirmation opening has an opening first side parallel to a first direction perpendicular to the thickness direction, and an opening second side parallel to a second direction perpendicular to the thickness direction and the first direction, The inspection step includes measuring a distance between the first side of the opening and the overlapping portion, and measuring a distance between the second side of the opening and the overlapping portion. 17. A method for manufacturing a semiconductor device according to claim 16. [Explanation of symbols]

[0089] A10, A20, A30, A40, A50, A60, A70: Semiconductor elements 30a: element main surface 30b: Back side of element 31: Semiconductor substrate 311: First edge of the board 312: Second edge of the board 313: Third edge of the board 314: 4th edge of the board 32: Semiconductor layer 321: Switching circuit 322: Control circuit 33: Passivation film 34: Conductive layer 34a: 1st layer 34b: 2nd layer 34c: 3rd layer 34d: seed layer 34e: plating layer 341: Electrode 342, 342a, 342b: Confirmation pattern 342a1, 342b1: Confirmation 1st side 342a2, 342b2: Confirmation side 2 35: Insulating layer 35a: opening 35b: overlapping part 36: Electrode terminal 361: Pillar section 361a: seed layer 361b: First plating layer 361c: Second plating layer 361d: Recess 362: Soldering part 37,371: Internal electrode 38,381: Via 38a, 38b: overlapping portion 38a1, 38b1: First side of overlapping portion 38a2, 38b2: Second side of overlapping portion B10: Semiconductor device 10, 11-16: Lead 40: Sealing resin 81: Semiconductor substrate 82: Semiconductor layer 83: Passivation film 84: Resist 85:Aperture 85a, 85b: Confirmation opening 851: First side of opening 852: Second side of opening 86: Insulating layer 86a:Aperture

Claims

1. a semiconductor substrate; a semiconductor layer laminated on the semiconductor substrate and having a circuit formed therein; a conductive layer that is disposed on the opposite side of the semiconductor substrate with respect to the semiconductor layer, includes a portion that is electrically connected to the circuit, and is composed of at least one first layer that is stacked in a thickness direction of the semiconductor substrate; a conductive portion disposed between the semiconductor layer and the conductive layer, electrically connected to the conductive layer, and including a plurality of first conductors each having a rectangular shape when viewed in a first direction perpendicular to the thickness direction; Equipped with the conductive layer includes a confirmation pattern that is not electrically connected to the circuit, is formed of at least one second layer stacked in the thickness direction, and has a shape that includes at least one corner when viewed in the thickness direction; the conductive portion includes an overlapping portion that at least partially overlaps the confirmation pattern when viewed in the thickness direction and is made up of a plurality of second conductors, each of which has a rectangular shape when viewed in the first direction. Semiconductor element.

2. When viewed in the thickness direction, the shape of the confirmation pattern is polygonal. The semiconductor device according to claim 1 .

3. When viewed in the thickness direction, the shape of the confirmation pattern is triangular. The semiconductor device according to claim 1 or 2.

4. When viewed in the thickness direction, the shape of the confirmation pattern is rectangular. The semiconductor device according to claim 1 or 2.

5. the overlapping portion overlaps the confirmation pattern so as to be included within the confirmation pattern when viewed in the thickness direction.

5. The semiconductor device according to claim 1.

6. the semiconductor substrate includes a substrate first side extending in the first direction and a substrate second side extending in a second direction perpendicular to the thickness direction and the first direction; The confirmation pattern includes a first confirmation side parallel to the first substrate side and a second confirmation side parallel to the second substrate side.

6. The semiconductor device according to claim 1.

7. When viewed in the thickness direction, the overall shape of the overlapping portion formed of the plurality of second conductors is a first side of the overlapping portion that is parallel to the first side of the confirmation; The semiconductor device according to claim 6 .

8. When viewed in the thickness direction, the overall shape includes an overlapping portion second side that is parallel to the confirmation second side. The semiconductor device according to claim 7 .

9. the confirmation pattern is located at a corner of the semiconductor substrate when viewed in the thickness direction.

9. The semiconductor device according to claim 1.

10. the conductive layer includes a second confirmation pattern that is not conductive to the circuit; the conductive portion includes a second overlapping portion that overlaps the second confirmation pattern when viewed in the thickness direction, the second confirmation pattern is located at a second corner portion diagonally opposite the corner portion of the semiconductor substrate when viewed in the thickness direction. The semiconductor device according to claim 9 .

11. a passivation film interposed between the semiconductor layer and the conductive layer; the conductive portion is a plurality of vias that penetrate the passivation film and contact the conductive layer; 11. The semiconductor device according to claim 1.

12. The semiconductor device further includes a second conductive layer interposed between the semiconductor layer and the conductive portion.

12. The semiconductor device according to claim 1.

13. an insulating layer in contact with the conductive layer and having an opening exposing a portion of the conductive layer; 13. The semiconductor device according to claim 1.

14. a semiconductor substrate; a semiconductor layer laminated on the semiconductor substrate and having a circuit formed therein; a conductive layer that is disposed on the opposite side of the semiconductor substrate with respect to the semiconductor layer, includes a portion that is electrically connected to the circuit, and is composed of at least one first layer that is stacked in a thickness direction of the semiconductor substrate; a conductive portion disposed between the semiconductor layer and the conductive layer, electrically connected to the conductive layer, and including a plurality of first conductors each having a rectangular shape when viewed in a first direction perpendicular to the thickness direction; Equipped with the conductive layer includes a confirmation pattern that is not electrically connected to the circuit, that is formed of at least one second layer stacked in the thickness direction, and that has a shape including an arc when viewed in the thickness direction; the conductive portion includes an overlapping portion that at least partially overlaps the confirmation pattern when viewed in the thickness direction and is made up of a plurality of second conductors, each of which has a rectangular shape when viewed in the first direction. Semiconductor element.

15. A semiconductor element according to any one of claims 1 to 14; a sealing resin that covers the semiconductor element; Equipped with Semiconductor device.

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