Power supply control device, and dc / dc converter

Abstract

To provide a power supply control device capable of reducing circuit area.SOLUTION: A power supply control device (11) includes: a high-side transistor (HM); a plurality of low-side transistors (LM1, LM2) connected in parallel; a switch terminal (SW) connected to a first node (Nsw) at which the high-side transistor and the low-side transistor are connected, and configured to be connectable with an external output capacitor (Cout); and a drive control part (111) configured to discharge the output capacitor through the switch terminal and the low-side transistor by driving at least a part (LM2) of the plurality of low-side transistors on-state.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a power supply control device. [Background technology]

[0002] Various power supply control devices for controlling DC / DC converters have been proposed in the past (for example, Patent Document 1). The DC / DC converter is provided with an output capacitor on the output side. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-82752

[0004] [overview] In power supply control devices, there is a demand for a reduction in the circuit area.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a power supply control device that can reduce the circuit area.

[0006] A power supply control device according to one aspect of the present disclosure includes: A high-side transistor; a plurality of low-side transistors connected in parallel; a switch terminal connected to a first node to which the high-side transistor and the low-side transistor are connected, and configured to allow connection of an external output capacitor; a drive control unit configured to drive at least some of the plurality of low-side transistors to an on state, thereby discharging the output capacitor via the switch terminal and the low-side transistor; The configuration is provided with the following. [Brief explanation of the drawings]

[0007] [Figure 1]FIG. 1 is a diagram showing the configuration of a DC / DC converter according to a comparative example. [Figure 2] FIG. 2 is a diagram showing the configuration of the DC / DC converter according to the first embodiment. [Figure 3] FIG. 3 is a diagram showing the configuration of a DC / DC converter according to the second embodiment. [Figure 4] FIG. 4 is a diagram showing the configuration of a DC / DC converter according to the third embodiment. [Figure 5] FIG. 5 is a diagram showing the configuration of a DC / DC converter according to the fourth embodiment.

[0008] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0009] <Comparative Example> Before describing the embodiments of the present disclosure, a comparative example will be described for comparison. This will make the problems more clear. Fig. 1 is a diagram showing the configuration of a DC / DC converter 20 according to the comparative example.

[0010] 1 is a step-down converter that converts an input voltage Vin, which is a DC voltage, into an output voltage Vout, which is also a DC voltage. The DC / DC converter 20 includes a power supply control device 10, and an inductor L1 and an output capacitor Cout, which are discrete elements provided outside the power supply control device 10.

[0011] The power supply control device 10 is a semiconductor device that has an integrated DC / DC control unit 10A. The DC / DC control unit 10A has a high-side transistor HM, a low-side transistor LM, a high-side driver DrH, a low-side driver DrL, feedback resistors Rf1 and Rf2, a switch S, and a discharge resistor Rds. The power supply control device 10 also has a switch terminal SW and a feedback terminal FB, which are external terminals for establishing electrical connection with the outside.

[0012] The high-side transistor HM is configured as a P-channel MOSFET (metal-oxide-semiconductor field-effect transistor). The low-side transistor LM is configured as an N-channel MOSFET. The source of the high-side transistor HM is connected to the terminal to which the input voltage Vin is applied. The drain of the high-side transistor HM is connected to the drain of the low-side transistor LM at a node Nsw. The node Nsw is connected to the switch terminal SW. The source of the low-side transistor LM is connected to the terminal to which the ground potential is applied.

[0013] The high-side driver DrH outputs a gate signal Gh to the gate (control terminal) of the high-side transistor HM to drive the high-side transistor HM. When the gate signal Gh is at a low level, the high-side transistor HM is turned on, and when the gate signal Gh is at a high level, the high-side transistor HM is turned off.

[0014] The low-side driver DrL outputs a gate signal Gl to the gate of the low-side transistor LM to drive the low-side transistor LM. When the gate signal Gl is at a high level, the low-side transistor LM is turned on, and when the gate signal Gl is at a low level, the low-side transistor LM is turned off.

[0015] The switch terminal SW is connected to one end of the inductor L1. The other end of the inductor L1 is connected to the output terminal Tout. One end of the output capacitor Cout is connected to the other end of the inductor L1. The other end of the output capacitor Cout is connected to a terminal to which the ground potential is applied.

[0016] The high-side transistor HM and the low-side transistor LM are switched and driven in a complementary manner by the gate signals Gh and Gl, thereby generating an output voltage Vout at the output terminal Tout. In addition, in the complementary switching, a simultaneous off period (dead time) in which both the high-side transistor HM and the low-side transistor LM are turned off may be provided.

[0017] The output terminal Tout is connected to a feedback terminal FB. Feedback resistors Rf1 and Rf2 are connected in series between the feedback terminal FB and the terminal to which the ground potential is applied. As a result, a feedback voltage Vfb obtained by dividing the output voltage Vout is generated at the node to which the feedback resistors Rf1 and Rf2 are connected. The DC / DC control unit 10A has a control circuit (not shown). The control circuit performs, for example, PWM (pulse width modulation) control by driving drivers DrH and DrL based on the feedback voltage Vfb. As a result, the feedback voltage Vfb is controlled to match the reference voltage, i.e., the output voltage Vout is controlled to a target voltage. The feedback resistors may be provided external to the power supply control device 10.

[0018] One end of a resistor Rds is connected to the feedback terminal FB via a switch S. The other end of the resistor Rds is connected to the terminal to which the ground potential is applied. During power conversion operation, which converts the input voltage Vin to the output voltage Vout, the switch S is in the off state. Furthermore, when the power conversion operation is stopped, the switch S is turned on, and the charge in the output capacitor Cout is extracted via the feedback terminal FB and the resistor Rds, thereby discharging the output capacitor Cout.

[0019] However, in such a comparative example, when the capacitance of the output capacitor Cout increases due to the recent trend toward larger currents, the resistance value of the discharge resistor Rds must be reduced to achieve the desired discharge time for discharging the output capacitor Cout. A smaller resistance value increases the size of the resistor Rds. This results in an increase in the circuit area. To solve this problem, the following embodiments of the present disclosure are implemented. Below, differences from the comparative example are mainly described.

[0020] First Embodiment 2 is a diagram showing a configuration of a DC / DC converter 21 according to a first embodiment of the present disclosure. The DC / DC converter 21 includes a power supply control device 11. The power supply control device 11 has a DC / DC control unit 11A. In the DC / DC control unit 11A, low-side transistors LM1 and LM2 are connected in parallel. The drains of the low-side transistors LM1 and LM2 are connected to a node Nsw. The DC / DC control unit 11A also includes a drive control unit 111. The drive control unit 111 has a low-side driver DrL and an OR circuit OR.

[0021] A gate signal Gl output from the low-side driver DrL is applied to the gate of the low-side transistor LM1. The gate signal Gl is applied to one input terminal of the OR circuit OR, and a control signal Sc is applied to the other input terminal. The logical sum of the gate signal Gl and the control signal Sc is taken, and a gate signal G2 is output from the OR circuit OR. The gate signal G2 is applied to the gate of the low-side transistor LM2.

[0022] During power conversion operation, the control signal Sc is set to a low level. As a result, the level of the gate signal G2 is set to a level corresponding to the gate signal Gl. That is, when the gate signal Gl is at a low level, the gate signal G2 is at a low level, and when the gate signal Gl is at a high level, the gate signal G2 is at a high level. Therefore, the low-side transistors LM1 and LM2 are synchronously turned on and off by the low-side driver DrL.

[0023] On the other hand, when power conversion operation is stopped, the control signal Sc is set to high level. As a result, when the gate signal Gl is set to low level and the low-side transistor LM1 is off, the gate signal G2 is set to high level and the low-side transistor LM2 is on. Therefore, the charge in the output capacitor Cout is extracted and discharged via the switch terminal SW and the low-side transistor LM2. In other words, the on-resistance of the low-side transistor LM2 functions as a discharge resistor.

[0024] In this manner, in this embodiment, the output capacitor Cout is discharged using LM2, which is one of the low-side transistors LM1 and LM2 connected in parallel. This eliminates the need for the discharge resistor Rds provided in the comparative example, as shown in Figure 2. Therefore, it is possible to achieve the desired discharge time for the output capacitor Cout while reducing the circuit area.

[0025] Second Embodiment FIG. 3 is a diagram showing a configuration of a DC / DC converter 22 according to a second embodiment of the present disclosure. The DC / DC converter 22 includes a power supply control device 12. The power supply control device 12 has a DC / DC control unit 12A. In the DC / DC control unit 12A, low-side transistors LM2A, LM2B, LM2C, etc. are connected in parallel to the low-side transistor LM1. In this embodiment, the number of low-side transistors connected in parallel to the low-side transistor LM1 is not important as long as there are more than one. The DC / DC control unit 12A also includes a drive control unit 121. The drive control unit 121 has OR circuits OA, OB, OC, etc. that are provided corresponding to the low-side transistors LM2A, LM2B, LM2C, etc., respectively.

[0026] A gate signal Gl output from the low-side driver DrL is applied to the gate of the low-side transistor LM1. The gate signal Gl is applied to one input terminal of each of the OR circuits OA, OB, OC, etc., and a control signal ScA, ScB, ScC, etc. is applied to the other input terminal of each of the OR circuits. A logical OR is taken between the gate signal Gl and each of the control signals ScA, ScB, ScC, etc., and gate signals GA, GB, GC, etc. are output from the OR circuits OA, OB, OC, etc. The gate signals GA, GB, GC, etc. are applied to the gates of the corresponding low-side transistors LM2A, LM2B, LB2C, etc.

[0027] During power conversion operation, the levels of the control signals ScA, ScB, ScC, etc. are all set to low level, which causes the levels of the gate signals GA, GB, GC, etc. to be the same as the level of the gate signal Gl, so that the low-side transistors LM1 and LM2A, LM2B, LM2C, etc. are turned on and off synchronously.

[0028] On the other hand, when the power conversion operation is stopped, at least one of the control signals ScA, ScB, ScC, etc. is set to a high level, and the others are set to a low level. The levels of the control signals ScA, ScB, ScC, etc. are set, for example, by an OTP (One Time Programmable) memory 12B. When the gate signal Gl is at a low level, the gate signals GA, GB, GC corresponding to the control signals ScA, ScB, ScC, etc. that are set to a low level are set to a low level, and the corresponding low-side transistors LM2A, LM2B, LM2C are turned off, similar to the low-side transistor LM1.

[0029] On the other hand, when the gate signal Gl is at a low level, the gate signals GA, GB, GC corresponding to the high-level control signals ScA, ScB, ScC, etc., are at a high level, and the corresponding low-side transistors LM2A, LM2B, LM2C are turned on, thereby discharging the output capacitor Cout via the transistors.

[0030] According to this embodiment, by setting the levels of the control signals ScA, ScB, ScC, etc., it is possible to select the transistor to be used for discharging the output capacitor Cout from among the low-side transistors LM2A, LM2B, LM2C, etc., and adjust the resistance value for discharge. Therefore, it is possible to adjust the resistance value for discharge according to the capacitance value of the output capacitor Cout, and achieve a desired discharge time.

[0031] <Third embodiment> 4 is a diagram showing a configuration of a DC / DC converter 23 according to a third embodiment of the present disclosure. The DC / DC converter 23 includes a power supply control device 13. The power supply control device 13 has a DC / DC control unit 13A. In the DC / DC control unit 13A, a low-side transistor LM1 and a low-side transistor LM2 are connected in parallel. The DC / DC control unit 13A is provided with a drive control unit 131. The drive control unit 131 has low-side drivers DrL1 and DrL2 provided corresponding to the low-side transistors LM1 and LM2, respectively, a voltage application unit 1311, and a switch SW3.

[0032] A drive signal Sdr is commonly input to the low-side drivers DrL1 and DrL2. In response to the drive signal Sdr, the low-side drivers DrL1 and DrL2 output gate signals Gl1 and Gl2, respectively, of the same level. The gate signal Gl1 is applied to the gate of the low-side transistor LM1.

[0033] The voltage application unit 1311 has variable resistors R1 and R2 and switches SW1 and SW2. The variable resistor R1 and switch SW1 are connected in series between an application terminal of the internal voltage Vreg and a node Nd. The variable resistor R2 and switch SW2 are connected in series between the application terminal of the node Nd and a ground potential application terminal. The switch SW3 is connected between the output terminal of the low-side driver DrL2 and the node Nd. The node Nd is connected to the gate of the low-side transistor LM2.

[0034] During power conversion operation, switch SW3 is turned on and switches SW1 and SW2 are turned off. This disables the voltage application unit 1311, and gate signals Gl1 and Gl2 are applied to the gates of low-side transistors LM1 and LM2 at the same level based on the drive signal Sdr. Therefore, the low-side transistors LM1 and LM2 are driven on and off synchronously.

[0035] On the other hand, when the power conversion operation is stopped, the switch SW3 is turned off and the switches SW1 and SW2 are turned on. This enables the voltage application unit 1311, and a gate signal G2 obtained by dividing the internal voltage Vreg by the variable resistors R1 and R2 is applied to the gate of the low-side transistor LM2. As a result, when the gate signal Gl1 is at a low level and the low-side transistor LM1 is turned off, the output capacitor Cout is discharged via the low-side transistor LM2.

[0036] According to this embodiment, the voltage value of the gate signal G2 can be varied by the variable resistors R1 and R2, thereby varying the on-resistance of the low-side transistor LM2, i.e., the discharge resistance value. Therefore, the discharge resistance value can be adjusted according to the capacitance value of the output capacitor Cout, thereby achieving a desired discharge time. Note that, in this embodiment, either one of the variable resistors R1 and R2 may have a fixed resistance value.

[0037] <Fourth embodiment> Fig. 5 is a diagram showing the configuration of DC / DC converters 24A, 24B according to a fourth embodiment of the present disclosure. That is, in this embodiment, multiple DC / DC converters are provided. The power supply control device 14 shown in Fig. 5 has DC / DC control units 14A, 14B.

[0038] The DC / DC converter 24A has a DC / DC control unit 14A, an inductor LA, and an output capacitor CoA, and has the same configuration as the DC / DC converter 21 (FIG. 2) of the first embodiment. In the DC / DC converter 24A, an output voltage VoA is generated at an output terminal ToA.

[0039] The DC / DC converter 24B includes a DC / DC control unit 14B, an inductor LB, and an output capacitor CoB. In the DC / DC converter 24B, an output voltage VoB is generated at an output terminal ToB. The DC / DC converter 24B is provided with a low-side transistor LMM. Note that in FIG. 5, components other than the low-side transistor LMM of the DC / DC converter 24B are omitted for convenience.

[0040] In the configuration of the comparative example (Fig. 1), when multiple DC / DC control units 10A are provided, the ground GND1 connected to the discharge resistor Rds needs to have a certain width because a large current flows through it, and it is therefore necessary to share the ground GND1 among multiple channels (DC / DC control units).This poses a problem in that when discharge is performed in one channel, other channels are subject to interference due to the common impedance of the ground GND1.

[0041] In contrast, in the configuration according to this embodiment (FIG. 5), the ground of the path for discharge in the DC / DC control unit 14A is the ground PGND of the low-side transistor LM2. Since the ground PGND of the low-side transistor of each channel in the power supply control device 14 can be independent, the influence of interference on other channels can be reduced. Note that the DC / DC control unit 14B may have the same configuration as the DC / DC control unit 14A or a different configuration. Furthermore, the DC / DC control unit according to the second or third embodiment may be applied to this embodiment.

[0042] <Other> In addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present disclosure should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0043] For example, in the above embodiment, some of the low-side transistors that are turned on and off during power conversion operation are used for discharge, but depending on the required on-resistance value for discharge, all of them may be used for discharge.

[0044] <Additional Notes> As described above, the power supply control device (11) according to one aspect of the present disclosure includes: A high-side transistor (HM), A plurality of low-side transistors (LM1, LM2) connected in parallel; a switch terminal (SW) connected to a first node (Nsw) to which the high-side transistor and the low-side transistor are connected, and configured to be able to connect an external output capacitor (Cout); and a drive control unit (111) configured to discharge the output capacitor via the switch terminal and the low-side transistor by driving at least a part (LM2) of the plurality of low-side transistors to an on state (first configuration, FIG. 2).

[0045] According to this configuration, the output capacitor is discharged using the on-resistance of the low-side transistor, so a separate resistor for discharge is not required, and the circuit area can be reduced.

[0046] In the first configuration, the plurality of low-side transistors include a part of first low-side transistors (LM1) and a part of remaining second low-side transistors (LM2), The drive control unit (111) may be configured to turn the first low-side transistor off and the second transistor on when discharging the output capacitor (second configuration, FIG. 2).

[0047] In addition, in the second configuration, the drive control unit (111) may be configured to have a logic circuit (OR) that receives a first drive signal (Gl) and a control signal (Sc) for driving the control terminal of the first low-side transistor (LM1) and that is configured to output a second drive signal (G2) to the control terminal of the second low-side transistor (LM2) (third configuration, FIG. 2).

[0048] In the third configuration, the logic circuit may be an OR circuit (fourth configuration, FIG. 2).

[0049] In the third or fourth configuration, the logic circuits (OA, OB, OC, etc.) are provided in plural numbers corresponding to the second low-side transistors (LM2A, LM2B, LM2C, etc.), respectively; A configuration may be adopted in which each of the plurality of control signals (ScA, ScB, ScC, etc.) is input to each of the plurality of logic circuits (fifth configuration, FIG. 3).

[0050] Furthermore, the fifth configuration may be configured to include a memory (12B) configured to be able to set the levels of the plurality of control signals (sixth configuration, FIG. 3).

[0051] In addition, in the second configuration, the drive control unit (131) may have a voltage application unit (1311) configured to apply a predetermined voltage to the control terminal of the second low-side transistor when the first low-side transistor is turned off, thereby turning on the second low-side transistor (seventh configuration, FIG. 4).

[0052] In addition, in the seventh configuration, the voltage application unit may generate the predetermined voltage by dividing a power supply voltage (Verg) at a predetermined voltage division ratio, and the voltage division ratio may be variable (eighth configuration, FIG. 4).

[0053] Furthermore, in the eighth configuration, the voltage application unit includes a second node (Nd) at which the predetermined voltage is generated, a first resistor (R1) and a first switch (SW1) connected in series between an application terminal of the power supply voltage and the second node, and a second resistor (R2) and a second switch (SW2) connected in series between an application terminal of the second node and an application terminal of a ground potential, At least one of the first resistor and the second resistor is a variable resistor; The drive control unit may be configured to have a third switch (SW3) connected between an application terminal of a drive signal (Gl2) for driving the control terminal of the second low-side transistor and the second node (ninth configuration, FIG. 4).

[0054] In addition, in any one of the first to ninth configurations, a first DC / DC control unit (14A) having the high-side transistor, the low-side transistor, and the drive control unit; At least one second DC / DC control unit (14B) separate from the DC / DC control unit; Equipped with The ground (PGND) connected to the low-side transistor and the ground (PGND) connected to the low-side transistor (LMM) included in the second DC / DC control unit may be configured to be independent (tenth configuration, FIG. 5).

[0055] Furthermore, a DC / DC converter (21) according to an embodiment of the present disclosure includes a power supply control device (11) having any one of the first to tenth configurations, the output capacitor, and an inductor (L1) connected between the switch terminal and the output capacitor (eleventh configuration, FIG. 2). [Industrial Applicability]

[0056] The present disclosure can be used, for example, in DC / DC converters for various applications. [Explanation of symbols]

[0057] 10 Power supply control device 10A DC / DC control unit 11 Power supply control device 11A DC / DC control unit 111 Drive control unit 12 Power supply control device 12A DC / DC control unit 12B OTP memory 121 Drive control unit 13 Power supply control device 13A DC / DC control unit 131 Drive control unit 1311 Voltage application section 14 Power supply control device 14A, 14B DC / DC control unit 20~23 DC / DC converter 24A, 24B DC / DC converter CoA Output Capacitor CoB Output Capacitor Cout Output capacitor DrH High-side driver DrL Low-side driver DrL1, DrL2 Low-side drivers FB Feedback terminal HM High-side transistor L1 inductor LA inductor LB inductor LM low-side transistor LM1, LM2 low-side transistors LM2A, LM2B, LB2C low-side transistors LMM low-side transistor OA, OB, OC OR circuit OR OR circuit R1, R2 variable resistors Rds resistance Rf1, Rf2 feedback resistors S Switch SW Switch terminal SW1, SW2, SW3 switches ToA, ToB output terminals Tout output terminal

Claims

1. A high-side transistor; a plurality of low-side transistors connected in parallel; a switch terminal connected to a first node to which the high-side transistor and the low-side transistor are connected, the switch terminal being configured to be able to connect an output capacitor to an external circuit; a drive control unit configured to drive at least some of the plurality of low-side transistors to an on state, thereby discharging the output capacitor via the switch terminal and the low-side transistor; A power supply control device comprising:

2. the plurality of low-side transistors include some first low-side transistors and the remaining some second low-side transistors; 2 . The power supply control device according to claim 1 , wherein the drive control unit turns the first low-side transistor off and the second transistor on when discharging the output capacitor.

3. 3. The power supply control device according to claim 2, wherein the drive control unit includes a logic circuit configured to receive a first drive signal and a control signal for driving the control terminal of the first low-side transistor and to output a second drive signal to the control terminal of the second low-side transistor.

4. 4. The power supply control device according to claim 3, wherein the logic circuit is an OR circuit.

5. a plurality of the logic circuits are provided corresponding to the plurality of second low-side transistors, 4. The power supply control device according to claim 3, wherein each of the plurality of control signals is input to each of the plurality of logic circuits.

6. The power supply control device according to claim 5 , further comprising a memory configured to be able to set levels of the plurality of control signals.

7. 3. The power supply control device according to claim 2, wherein the drive control unit includes a voltage application unit configured to apply a predetermined voltage to a control terminal of the second low-side transistor to turn on the second low-side transistor when the first low-side transistor is turned off.

8. the voltage application unit generates the predetermined voltage by dividing a power supply voltage at a predetermined voltage division ratio; The power supply control device according to claim 7 , wherein the voltage division ratio is variable.

9. the voltage application unit has: a second node at which the predetermined voltage is generated; a first resistor and a first switch connected in series between an application terminal of the power supply voltage and the second node; and a second resistor and a second switch connected in series between an application terminal of the second node and an application terminal of a ground potential; At least one of the first resistor and the second resistor is a variable resistor; 9. The power supply control device according to claim 8, wherein the drive control section has a third switch connected between an application terminal of a drive signal for driving a control terminal of the second low-side transistor and the second node.

10. a first DC / DC control unit having the high-side transistor, the low-side transistor, and the drive control unit; At least one second DC / DC control unit separate from the DC / DC control unit; Equipped with 2. The power supply control device according to claim 1, wherein a ground connected to said low-side transistor and a ground connected to a low-side transistor included in said second DC / DC control unit are independent of each other.

11. The power supply control device according to any one of claims 1 to 10; the output capacitor; an inductor connected between the switch terminal and the output capacitor; A DC / DC converter comprising:

Images