Bootstrap circuit and switching regulator

Abstract

To provide a bootstrap circuit and switching regulator with a small chip area.SOLUTION: The circuit includes: a first NMOS transistor and a second NMOS transistor connected in series between a power supply terminal and a ground terminal; an inverting buffer having an input connected to a second input terminal, an output connected to the gate of the first NMOS transistor, and a second power supply terminal connected to an output terminal; a bootstrap capacitor connected between a first power supply terminal and an output terminal of the inverting buffer; a step-up circuit including an inverter, a depletion-type NMOS transistor, and a boosting capacitor; and a third NMOS transistor having a gate connected to one end of the boosting capacitor, a source connected to a first input terminal, and a drain connected to one end of the bootstrap capacitor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a bootstrap circuit and a switching regulator. [Background technology]

[0002] Generally, bootstrap circuits are used in switching regulators and the like, and a PMOS transistor is used as a synchronous switch for charging a bootstrap capacitor. Patent Document 1 can be cited as an example of the prior art. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-62427 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in conventional bootstrap circuits, the PMOS transistors used in the synchronous switches have high on-resistance, which increases the chip area, leaving room for improvement.

[0005] SUMMARY OF THE INVENTION In consideration of the above circumstances, an object of the present invention is to provide a bootstrap circuit and a switching regulator that occupy a small chip area. [Means for solving the problem]

[0006] a bootstrap circuit having an input terminal, a second input terminal, an output terminal, a first NMOS transistor connected between a power supply terminal and the output terminal, a second NMOS transistor connected between the output terminal and a ground terminal, an inverting buffer having an input connected to the second input terminal, an output connected to the gate of the first NMOS transistor, and a second power supply terminal connected to the output terminal, a bootstrap capacitor having one end connected to the first power supply terminal of the inverting buffer and the other end connected to the output terminal, an inverter having an input connected to the second input terminal, a depletion-mode NMOS transistor having a gate connected to the output of the inverter and a source connected to the first input terminal, a boost capacitor having one end connected to the drain of the depletion-mode NMOS transistor and the other end connected to the second input terminal, and a third NMOS transistor having a gate connected to one end of the boost capacitor, a source connected to the first input terminal, and a drain connected to one end of the bootstrap capacitor. [Effects of the Invention]

[0007] According to the present invention, by using an NMOS transistor with a small on-resistance for the synchronous switch, it is possible to provide a bootstrap circuit and a switching regulator with a small chip area. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a circuit diagram illustrating a configuration example of a bootstrap circuit according to an embodiment of the present invention. [Figure 2] 1 is a circuit diagram showing a switching regulator including a bootstrap circuit according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A bootstrap circuit and a switching regulator according to embodiments of the present invention will now be described with reference to the accompanying drawings.

[0010] FIG. 1 is a circuit diagram of a bootstrap circuit 100 according to this embodiment.

[0011] The bootstrap circuit 100 includes a power supply terminal 101, a ground terminal 102, an input terminal 110 (first input terminal), an input terminal 111 (second input terminal), a bootstrap switch circuit 103, NMOS transistors 127 and 128, a capacitor 129 that is a bootstrap capacitor, an inverting buffer 125, and an output terminal 112. The bootstrap switch circuit 103 includes a depletion-type NMOS transistor 120, an inverter 123, an NMOS transistor 121, and a capacitor 122 that is a boost capacitor.

[0012] The NMOS transistor 120 has a gate connected to the output of the inverter 123, a source connected to the input terminal 110, and a drain connected to one end of the capacitor 122. The NMOS transistor 121 has a gate connected to one end of the capacitor 122, a source connected to the input terminal 110, and a drain connected to one end of the capacitor 129. The inverter 123 has an input connected to the input terminal 111. The capacitor 122 has the other end connected to the input terminal 111. The inverting buffer 125 has a first power supply terminal connected to one end of the capacitor 129, a second power supply terminal connected to the output terminal 112, an input connected to the input terminal 111, and an output connected to the gate of the NMOS transistor 127. The NMOS transistor 127 has a source connected to the output terminal 112 and a drain connected to the power supply terminal 101. The NMOS transistor 128 has a gate connected to the input terminal 111, a source connected to the ground terminal 102, and a drain connected to the output terminal 112. The other end of the capacitor 129 is connected to the output terminal 112 .

[0013] Next, the operation of the bootstrap circuit 100 will be described. A predetermined power supply voltage is supplied to the power supply terminal 101. Unlike the power supply terminal 101, the ground terminal 102 is supplied with a power supply voltage that serves as a reference for circuit operation, for example, 0 V (hereinafter referred to as the ground voltage).

[0014] A DC voltage signal V1 is input to an input terminal 110. A pulse voltage signal VPWM is applied to an input terminal 111. A bootstrap switch circuit 103 turns an NMOS transistor 121 on and off in synchronization with the signal VPWM. An inverting buffer 125 outputs a signal VGH based on the input signal VPWM, turning an NMOS transistor 127 on and off. Here, since a first power supply terminal of the inverting buffer 125 is supplied with a signal VBST and a second power supply terminal thereof is supplied with a signal VSW, a high level of the output signal VGH is equivalent to the signal VBST, and a low level of the output signal VGH is equivalent to the signal VSW.

[0015] The gate voltages of NMOS transistor 127 and NMOS transistor 128 are in opposite phases due to inversion buffer 125, and are alternately turned on and off to output a pulse voltage signal VSW from output terminal 112. Capacitor 129 supplies the voltage between signal VBST and signal VSW, which is charged by a bootstrap operation described later, as the power supply voltage for inversion buffer 125.

[0016] For ease of explanation, the voltage of each signal is defined below. The low level of the signals VPWM and VDG is 0 V, and the high level is 5 V. The signal V1 is a DC voltage of 5 V. The NMOS transistor 120 has a threshold voltage of about −1V.

[0017] When the signal VPWM is low (0V), the output signal VDG of the inverter 123 is high (5V). The NMOS transistor 120 is on because the voltage difference between its gate and source is 0V. Therefore, the voltage of the signal VGN is equal to the voltage of the signal V1 (5V), so the capacitor 122 is charged with 5V. The NMOS transistor 121 is off because the voltage difference between its gate and source is 0V. The capacitor 129 is charged with the signal VBST based on the signal VSW. The inverting buffer 125 is supplied with the voltage (5V) between the signal VBST charged in the capacitor 129 and the signal VSW as the power supply voltage. The NMOS transistor 128 is off because the gate voltage is low (0V). The NMOS transistor 127 is on because the high-level (VBST) signal VGH is supplied to its gate from the inverting buffer 125. Therefore, the power supply voltage is output from the output terminal 112.

[0018] When the signal VPWM is at a high level (5V), the output signal VDG of the inverter 123 is at a low level (0V). The NMOS transistor 120 is off because its source voltage is 5V and its gate voltage is 0V. The signal VGN at one end of the capacitor 122 is 10V because the signal VPWM input to the other end is at a high level (5V). That is, the NMOS transistor 120, the inverter 123, and the capacitor 122 operate as a boost circuit. The NMOS transistor 121 is on because its source voltage is 5V and its gate voltage is 10V. The NMOS transistor 128 is on because its gate voltage is at a high level (5V). The capacitor 129 is charged with the voltage (5V) of the signal V1 at the input terminal 110 via the NMOS transistors 121 and 128. The NMOS transistor 127 is off because a low-level (VSW) signal VGH is supplied to its gate from the inverting buffer 125. Therefore, the output terminal 112 outputs the ground voltage of 0V.

[0019] As described above, the bootstrap switch circuit 103 generates the signal VGN by boosting the signal V1 using the NMOS transistor 120, the capacitor 122, and the inverter 123 in order to turn on the NMOS transistor 121. That is, the NMOS transistor 121 is controlled by the boosted signal VGN, and is thereby able to operate as a synchronous switch for charging the capacitor 129.

[0020] Therefore, the bootstrap circuit 100 can turn the NMOS transistor 127 on and off by supplying the signals VBST and VSW, which are floating voltages generated in synchronization with the signal VPWM, as the power supply for the inverting buffer 125.

[0021] Generally, when the size of a PMOS transistor is adjusted so that the on-resistance is equal to that of an NMOS transistor, the area of ​​the PMOS transistor is two to three times that of an NMOS transistor. The bootstrap circuit 100 of this embodiment can reduce the circuit area by configuring the synchronous switch of the bootstrap switch circuit 103 with the NMOS transistor 121.

[0022] Next, the use of the bootstrap circuit 100 of this embodiment will be described. The bootstrap circuit 100 can be used, for example, in a switching regulator as shown in FIG.

[0023] FIG. 2 is a circuit diagram showing a switching regulator 200 including a bootstrap circuit according to this embodiment. The switching regulator 200 includes a constant voltage circuit 137 that outputs a DC voltage signal V1, a bootstrap circuit 100, an output terminal 131, a coil 130 and a capacitor 132 that constitute an LC filter, resistors 133 and 134 that are voltage dividing resistors that output a feedback voltage VFB based on the output voltage of the output terminal 131, a reference voltage circuit 136 that outputs a reference voltage VREF, an error amplifier 135 that outputs a voltage VERR that is a result of comparing the reference voltage VREF and the feedback voltage VFB, and a PWM conversion circuit 138 that outputs a signal VPWM based on the voltage VERR.

[0024] The bootstrap circuit 100 according to this embodiment is suitable for a switching regulator that uses an NMOS transistor as a switching element as shown in FIG.

[0025] The circuits disclosed in the present embodiment are merely examples, and can be embodied in various forms. Various omissions, additions, substitutions, or modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents set forth in the claims.

[0026] For example, the voltages of the signals are defined for the convenience of explanation and are not limited to these. [Explanation of symbols]

[0027] 100 Bootstrap Circuit 103 Bootstrap Switch Circuit 120 Depletion-type NMOS transistor 122, 129, 132 capacitors 123 Inverter 121, 127, 128 NMOS transistors 125 Inverting Buffer 130 coils 133, 134 Resistor 135 Error amplifier 136 Reference voltage circuit 137 Constant voltage circuit 138 PWM conversion circuit 200 Switching Regulator

Claims

1. a first input terminal; a second input terminal; An output terminal; a first NMOS transistor connected between a power supply terminal and the output terminal; a second NMOS transistor connected between the output terminal and a ground terminal; an inverting buffer having an input connected to the second input terminal, an output connected to the gate of the first NMOS transistor, and a second power supply terminal connected to the output terminal; a bootstrap capacitor having one end connected to the first power supply terminal of the inverting buffer and the other end connected to the output terminal; an inverter having an input connected to the second input terminal; a depletion-mode NMOS transistor having a gate connected to the output of the inverter and a source connected to the first input terminal; a boost capacitor having one end connected to the drain of the depletion-mode NMOS transistor and the other end connected to the second input terminal; a third NMOS transistor having a gate connected to one end of the boost capacitor, a source connected to the first input terminal, and a drain connected to one end of the bootstrap capacitor.

2. the depletion-mode NMOS transistor, the boost capacitor, and the inverter constitute a boost circuit; generating a boosted voltage based on a first input signal input from the first input terminal and a second input signal input from the second input terminal; 2. The bootstrap circuit according to claim 1, wherein the third NMOS transistor is made conductive by the boosted voltage.

3. A switching regulator comprising the bootstrap circuit according to claim 1 or 2.

Images