Multiphase power supply circuit

Abstract

To provide a multiphase power supply circuit capable of continuing a desired output even when one of the multiple DC / DC converters fails.SOLUTION: The multiphase power supply circuit includes multiple DC-DC converters and a control unit. The control unit is configured to control each of the multiple DC-DC converters to operate for a predetermined operating time in a predetermined switching period so that the operation periods of multiple DC / DC converters are shifted from each other. The control unit is also configured so as to, when a fault is detected in any of the multiple DC / DC converters, change the predetermined switching period or predetermined operating time of the DC-DC converters to compensate for the output of the failed DC-DC converter.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a multiphase power supply circuit. [Background technology]

[0002] The multiphase DC / DC converter described in Patent Document 1 operates by shifting the output phases of multiple DC / DC converters connected in parallel and adds up the outputs to generate a desired output voltage from an input voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5210806 Summary of the Invention [Problem to be solved by the invention]

[0004] If any of the multiple DC / DC converters fails, the multiphase DC / DC converter will not be able to continue to output the desired output voltage, which may result in a sudden shutdown of the system that operates using the output of the multiphase DC / DC converter.

[0005] One aspect of the present disclosure provides a multiphase power supply circuit that can continue to provide a desired output even if any of a plurality of DC / DC converters fails. [Means for solving the problem]

[0006] A multiphase power supply circuit according to one aspect of the present disclosure includes a plurality of DC-DC converters (10, 20, 30, 40, 210, 220, 230) and a control unit (11, 290). The control unit is configured to operate each of the plurality of DC-DC converters for a predetermined operating time at a predetermined switching period so that the operation periods of the plurality of DC-DC converters are shifted from one another. The control unit is also configured to, when a failure is detected in any of the plurality of DC-DC converters, change the predetermined switching period or the predetermined operating time of the remaining DC-DC converters to compensate for the output of the failed DC-DC converter.

[0007] According to a multiphase power supply circuit of one aspect of the present disclosure, when a failure of any of the DC-DC converters is detected, the switching cycles or operating times of the remaining DC-DC converters are changed to compensate for the output of the failed DC-DC converter. Therefore, the multiphase power supply circuit can continue to provide a desired output even if any of the DC-DC converters fails. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a diagram showing a schematic configuration of a multiphase power supply circuit according to a first embodiment. [Figure 2] 2 is a diagram showing the switching timing of each DC-DC converter of the multiphase power supply circuit according to the first embodiment; FIG. [Figure 3] 4A to 4C are diagrams illustrating the outputs, response signals, and SW instruction signals of the DC-DC converters when a slave in the multiphase power supply circuit according to the first embodiment fails. [Figure 4] 4A to 4C are diagrams illustrating the outputs of the DC-DC converters, response signals, and SW instruction signals when the daisy chain of the multiphase power supply circuit according to the first embodiment is interrupted. [Figure 5] 10A and 10B are diagrams illustrating SW instruction signals and response signals to each of the DC-DC converters of the multiphase power supply circuit according to the second embodiment. [Figure 6]10 is a time chart of the operation of each DC-DC converter of the multiphase power supply circuit according to the second embodiment. [Figure 7] FIG. 10 is a diagram showing a schematic configuration of a multiphase power supply circuit according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] (1. First embodiment) <1-1.Configuration> The configuration of a multiphase power supply circuit 100 according to a first embodiment will be described with reference to Figure 1. In this embodiment, the multiphase power supply circuit 100 is assumed to be installed in a vehicle and to supply power to on-board equipment. In another embodiment, the multiphase power supply circuit 100 may be installed outside the vehicle and to supply power to various electrical equipment.

[0010] The multiphase power supply circuit 100 includes a master 10, a first slave 20, a second slave 30, a third slave 40, a bus line 50, daisy chain lines 61, 62, 63, and 64, a first resistor 17, a second resistor 27, a third resistor 37, a fourth resistor 47, a first power supply 18, a second power supply 28, a third power supply 38, a fourth power supply 48, a smoothing capacitor 70, an output line 80, and an output terminal 90.

[0011] The bus line 50 is a wiring that connects the master 10, the first slave 20, the second slave 30, and the third slave 40 in a bus system. In this embodiment, the bus line 50 corresponds to the first wiring of the present disclosure.

[0012] The daisy chain lines 61, 62, 63, and 64 are wirings that daisy chain connect the master 10, the first slave 20, the second slave 30, and the third slave 40. In this embodiment, the daisy chain lines 61, 62, 63, and 64 correspond to the second wirings of the present disclosure.

[0013] The master 10 is connected to the output line 80 via a first resistor 17. The first slave 20 is connected to the output line 80 via a second resistor 27. The second slave 30 is connected to the output line 80 via a third resistor 37. The third slave 40 is connected to the output line 80 via a fourth resistor 47. The master 10, the first slave 20, the second slave 30, and the third slave 40 are connected in parallel to the output line 80 via the first, second, and third resistors 17, 27, 37, and 47, respectively.

[0014] The output line 80 is connected to an output terminal 90. The output terminal 90 is connected to an in-vehicle device (for example, an electronic control device) or various electric devices. The smoothing capacitor 70 has a first pole and a second pole, the first pole being connected to the output line 80 and the second pole being grounded. Therefore, the first resistor 17, the second resistor 27, the third resistor 37, and the fourth resistor 47, and the smoothing capacitor 70, form a smoothing circuit. That is, the master 10, the first slave 20, the second slave 30, and the third slave 40 are each connected to the output terminal 90 via the smoothing circuit.

[0015] The multiphase power supply circuit 100 is a four-phase power supply circuit including four converters. The master 10, the first slave 20, the second slave 30, and the third slave 40 operate with a predetermined operating time staggered. In the multiphase power supply circuit 100, if the period from when the master 10 starts operating until the next time the master 10 starts operating is defined as a switching period, the operating time of each of the master 10, the first slave 20, the second slave 30, and the third slave 40 is one-fourth of the switching period. The operating period is the time during which each DC-DC converter operates and corresponds to the value obtained by dividing the switching period by the number of phases. In another embodiment, the multiphase power supply circuit 100 may be a two-phase or three-phase power supply circuit including two or three converters, or a five- or more-phase power supply circuit including five or more converters.

[0016] Each of the master 10, the first slave 20, the second slave 30, and the third slave 40 stores in advance a correspondence table between the number of operating phases and operating time in a predetermined switching cycle, and after detecting the number of phases, sets the operating time by referring to the correspondence table. When the operating time of the master 10 ends, the operating time of the first slave 20 begins, and when the operating time of the first slave 20 ends, the operating time of the second slave 30 begins. When the operating time of the second slave 30 ends, the operating time of the third slave 40 begins, and when the operating time of the third slave 40 ends, the operating time of the master 10 begins.

[0017] The master 10 is a DC-DC converter that functions as a master, and includes a pulse signal generating unit 11, a pulse signal transmitting / receiving circuit 12, a bus line communication circuit 13, a driving unit 14, a first switching element 15, and a second switching element 16.

[0018] The pulse signal generating unit 11 is connected to a pulse signal transmitting / receiving circuit 12 and a bus line communication circuit 13. Feedback is input to the pulse signal generating unit 11 from an output line 80. The pulse signal transmitting / receiving circuit 12 is connected to the bus line communication circuit 13 and a drive unit 14. Furthermore, the pulse signal transmitting / receiving circuit 12 is connected to a pulse signal transmitting / receiving circuit 22 of a first slave 20 (described later) by a daisy chain line 61, and is also connected to a pulse signal transmitting / receiving circuit of a third slave 40 (described later) by a daisy chain line 64. Furthermore, the bus line communication circuit 13 is connected to a bus line 50.

[0019] The pulse signal generating unit 11 generates a SW instruction signal for switching the first switching elements 15, 25, 35, and 45 and the second switching elements 16, 26, 36, and 46 of the master 10 and the first, second, and third slaves 20, 30, and 40 in each switching period. The SW instruction signal is a pulse signal having a duty ratio calculated by the pulse signal generating unit 11. The pulse signal generating unit 11 calculates the duty ratio based on a feedback input of the output voltage Vout so that the output voltage Vout becomes a desired voltage. The duty ratio is the pulse width of the SW instruction signal relative to the operating time, and the pulse width of the SW instruction signal corresponds to the on-time of the first switching elements 15, 25, 35, and 45. The pulse signal generating unit 11 transmits the generated SW instruction signal to the pulse signal transmitting / receiving circuit 12 and the bus line communication circuit 13.

[0020] 2, the pulse signal transmitting / receiving circuit 12 adjusts the SW instruction signal (hereinafter referred to as the first instruction signal) received from the pulse signal generating unit 11 so that the phase is delayed based on the SW instruction signal (hereinafter referred to as the second instruction signal) received from the third slave 40 via the daisy chain line 64. The second instruction signal corresponds to the SW instruction signal generated by the pulse signal generating unit 11 in the previous switching cycle.

[0021] The pulse signal transmitting / receiving circuit 12 does not transmit the first instruction signal immediately after receiving the first instruction signal from the pulse signal generating unit 11. The pulse signal transmitting / receiving circuit 12 delays the phase of the first instruction signal so that it waits until a predetermined time point before transmitting the first instruction signal. The predetermined time point corresponds to the time point when the operating time has elapsed since the pulse signal transmitting / receiving circuit 12 received the second instruction signal. In other words, the pulse signal generating unit 11 waits to transmit the first instruction signal until the operating time of the third slave 40 ends. The pulse signal transmitting / receiving circuit 12 transmits the delay-adjusted SW instruction signal to the driving unit 14 and the bus line communication circuit 13, and also to the daisy chain line 61.

[0022] When the bus line communication circuit 13 receives the SW instruction signal from the pulse signal transmitting / receiving circuit 12, it transmits a response signal to the bus line 50. The response signal is a pulse signal having a certain width. The bus line communication circuit 13 also receives response signals output from the first, second, and third slaves 20, 30, and 40. If an abnormality is found in the response signal transmitted from the first, second, and third slaves 20, 30, and 40, the bus line communication circuit 13 determines that the slave corresponding to the abnormal response signal has failed. An example of an abnormality in the response signal is the loss of the response signal. The bus line communication circuit 13 can identify the failed slave based on the number of response signals in which the abnormality occurred since the bus line communication circuit 13 transmitted the response signal.

[0023] Upon receiving the SW instruction signal from the pulse signal transmitting / receiving circuit 12, the driver 14 generates a first drive signal and a second drive signal based on the SW instruction signal. The driver 14 controls the on / off of the first switching element 15 by the first drive signal, and controls the on / off of the second switching element 16 by the second drive signal.

[0024] The first switching element 15 and the second switching element 16 are transistors, for example, N-channel MOS field effect transistors. The gates of the first switching element 15 and the second switching element 16 are individually connected to the drive unit 14. The drain of the first switching element 15 is connected to a first power supply 18, and the source of the first switching element 15 is connected to the drain of the second switching element 16. The source of the first switching element 15 and the drain of the second switching element 16 are connected to an output line 80 via a first resistor 17. The source of the second switching element 16 is grounded.

[0025] The driver 14 outputs a first drive signal to the gate of the first switching element 15 to control the on / off of the first switching element 15. When the first drive signal is at a high level, the first switching element 15 is turned on, and when the first drive signal is at a low level, the first switching element 15 is turned off. The driver 14 also outputs a second drive signal to the gate of the second switching element 16 to control the on / off of the second switching element 16. When the second drive signal is at a high level, the second switching element 16 is turned on, and when the second drive signal is at a low level, the second switching element 16 is turned off.

[0026] In accordance with the ON period of the SW instruction signal, the drive unit 14 turns on the first switching element 15 and turns off the second switching element 16. The drive unit 14 controls the first switching element 15 and the second switching element 16 in a complementary manner.

[0027] When the first drive signal is high and the second drive signal is low, an output voltage Vout having a potential based on the first power supply 18 is output on output line 80. When the first drive signal is low and the second drive signal is high, the output signal Vout is pulled down to ground potential.

[0028] The above-described correspondence between the logic levels of the first and second drive signals and the on / off of the first and second switching elements 15 and 16 is merely an example, and the correspondence may be reversed. Furthermore, the first and second switching elements 15 and 16 may be P-channel MOS transistors or may be transistors other than MOS.

[0029] The first slave 20 is a DC-DC converter that functions as a slave, and includes a pulse signal transmitting / receiving circuit 22, a bus line communication circuit 23, a drive unit 24, a first switching element 25, and a second switching element 26. The pulse signal transmitting / receiving circuit 22 is connected to a pulse signal transmitting / receiving circuit 32 of the second slave 30 (described later) via a daisy chain line 62. The bus line communication circuit 23 is connected to a bus line 50. The configuration of the first slave 20 is similar to that of the master 10, except that the first slave 20 does not include a pulse signal generating unit 11.

[0030] When the pulse signal transmitting / receiving circuit 22 receives the SW instruction signal via the daisy chain line 61, it adjusts the delay of the SW instruction signal in the same manner as the pulse signal transmitting / receiving circuit 12. Then, the pulse signal transmitting / receiving circuit 22 transmits the delay-adjusted SW instruction signal to the bus line communication circuit 23 and the drive unit 24, and also transmits it to the daisy chain line 62.

[0031] When the bus line communication circuit 23 receives the SW instruction signal from the pulse signal transmitting / receiving circuit 22, it transmits a response signal to the bus line 50. The bus line communication circuit 23 also receives response signals output from the master 10, the second slave 30, and the third slave 40. If an abnormality is found in the response signal transmitted from the second or third slave 30, 40, the bus line communication circuit 23 determines that the slave corresponding to the abnormal response signal has failed. The bus line communication circuit 23 can identify the failed slave based on the number of response signals in which the abnormality occurred since the bus line communication circuit 23 transmitted the response signal.

[0032] When the driver 24 receives the SW instruction signal from the pulse signal transmitting / receiving circuit 22, it generates a first drive signal and a second drive signal based on the SW instruction signal. The driver 24 controls the on / off of the first switching element 25 and the second switching element 26 using the first drive signal and the second drive signal. The configurations and operations of the driver 24, the first switching element 25, and the second switching element 26 are similar to those of the driver 14, the first switching element 15, and the second switching element 16, and therefore will not be described in detail.

[0033] The second slave 30 is a DC-DC converter that functions as a slave and has the same configuration as the first slave 20. That is, the second slave 30 includes a pulse signal transmitting / receiving circuit 32, a bus line communication circuit 33, a drive unit 34, a first switching element 35, and a second switching element 36. The pulse signal transmitting / receiving circuit 32 is connected to the pulse signal transmitting / receiving circuit 22 by a daisy chain line 63. The bus line communication circuit 33 is connected to the bus line 50. The configuration of the second slave 30 is the same as the configuration of the first slave 20.

[0034] When the pulse signal transmitting / receiving circuit 32 receives the SW instruction signal via the daisy chain line 62, it adjusts the delay of the SW instruction signal in the same manner as the pulse signal transmitting / receiving circuit 12. Then, the pulse signal transmitting / receiving circuit 32 transmits the delay-adjusted SW instruction signal to the bus line communication circuit 33 and the drive unit 34, and also transmits it to the daisy chain line 63.

[0035] When the bus line communication circuit 33 receives the SW instruction signal from the pulse signal transmitting / receiving circuit 32, it transmits a response signal to the bus line 50. The bus line communication circuit 33 also receives the response signals output from the master 10, the first slave 20, and the third slave 40. If there is an abnormality in the response signal transmitted from the first or third slave 20, 40, the bus line communication circuit 33 determines that the slave corresponding to the abnormal response signal has failed.

[0036] When the driver 34 receives the SW instruction signal from the pulse signal transmitting / receiving circuit 32, it generates a first drive signal and a second drive signal based on the SW instruction signal. The driver 34 controls the on / off of the first switching element 35 and the second switching element 36 using the first drive signal and the second drive signal. The configurations and operations of the driver 34, the first switching element 35, and the second switching element 36 are similar to those of the driver 14, the first switching element 15, and the second switching element 16, and therefore will not be described in detail.

[0037] The third slave 40 is a DC-DC converter that functions as a slave and has a configuration similar to that of the first slave 20. Details of the third slave 40 are omitted. When the third slave 40 receives an SW instruction signal via the daisy chain line 63, it adjusts the delay of the SW instruction signal. The third slave 40 transmits the delay-adjusted SW instruction signal to the daisy chain line 64 and also transmits a response signal to the bus line 50.

[0038] In this embodiment, the pulse signal generating unit 11 of the master 10 corresponds to the control unit of the present disclosure.

[0039] <1-2. Operation> <1-2-1. If the slave fails> With reference to FIG. 3, the operation of the multiphase power supply circuit 100 when any of the slaves in the multiphase power supply circuit 100 fails will be described.

[0040] In steady-state operation, the master 10 and the first, second, and third slaves 20, 30, and 40 operate in sequence for an operating time Ta at a duty ratio Da in one switching cycle. The master 10 and the first, second, and third slaves 20, 30, and 40 confirm each other's operation (specifically, whether they are operating normally or whether an abnormality has occurred) by sending and receiving response signals via the bus line 50. Each of the master 10 and the first, second, and third slaves 20, 30, and 40 detects the number of phases from the number of response signals received between receiving a SW instruction signal and receiving the next SW instruction signal.

[0041] When the master 10 and the first, second, and third slaves 20, 30, and 40 determine that any of the slaves has failed, they do not change the switching period, but change the operating time Ta to the operating time Tb to compensate for the output of the failed slave. By maintaining a constant switching period, it is possible to suppress noise generated from the multiphase power supply circuit 100. The remaining three DC-DC converters other than the failed slave operate in turn at the duty ratio Da for the operating time Tb each.

[0042] As shown in FIG. 3, if the second slave 30 fails, the master 10 and the first and third slaves 20 and 40 determine the failure of the second slave 30 based on an abnormality (e.g., loss) in the response signal that should be transmitted from the second slave 30. The master 10 and the first and third slaves 20 and 40 then change the operating time Ta to the operating time Tb (specifically, lengthen the operating time) so that the multiphase power supply circuit 100 can output the same output voltage Vout in three-phase operation as in four-phase operation. When the four-phase operation changes to three-phase operation, the operating time Tb is 4 / 3 times the operating time Ta. That is, when the phase changes from N (N is a natural number) to M (M is a natural number smaller than N), the operating time is increased by N / M times. When the phase master 10 and the first, second, and third slaves 20, 30, and 40 detect a failure in any of the slaves, they adjust the operating time by referring to the correspondence table described above and adjust the delay of the SW instruction signal based on the changed operating time.

[0043] After determining that the second slave 30 has failed, the master 10 and the first and third slaves 20 and 40 stop transmitting response signals to the bus line 50. Because the master 10 cannot transmit SW instruction signals using the daisy chain lines 61 to 64 due to the failure of the second slave 30, the master 10 transmits SW instruction signals to the bus line 50 to notify the switching timing and duty ratio. The master 10 repeatedly transmits the SW instruction signals in a switching cycle.

[0044] When the first and third slaves 20 and 40 receive the SW instruction signal via the bus line 50, they adjust the delay of the SW instruction signal and operate based on the delayed SW instruction signal. Specifically, the first slave 20 recognizes that its turn to operate is after the master 10 based on the transmission and reception of the response signal. Therefore, the first slave 20 delays the phase of the SW instruction signal until the operation time Tb has elapsed since the first slave 20 received the SW instruction signal via the bus line 50. Furthermore, the third slave 40 recognizes that its turn to operate is after the first slave 20 due to a failure of the second slave 30. Therefore, the third slave 40 delays the phase of the SW instruction signal until the operation time Tb×2 has elapsed since the second slave 30 received the SW instruction signal via the bus line 50.

[0045] If the master 10 determines that an abnormality has occurred in the response signals from multiple slaves and that multiple slaves have failed, it stops controlling the first, second, and third slaves 20, 30, and 40 and shuts down the output of the multiphase power supply circuit 100.

[0046] <1-2-2. If the daisy chain is interrupted> With reference to FIG. 4, the operation of the multiphase power supply circuit 100 when the daisy chain is interrupted will be described.

[0047] If any of the daisy chain lines 61 to 64 is broken, the daisy chain is interrupted, and the master 10 and multiple DC-DC converters among the first, second, and third slaves 20, 30, and 40 cannot receive the SW instruction signal. If only any of the daisy chain lines 61 to 64 is broken and none of the first, second, and third slaves 20, 30, and 40 has failed, the multiphase power supply circuit 100 can continue to operate in four phases.

[0048] In order for the multiphase power supply circuit 100 to operate in four phases even if the daisy chain is interrupted, the master 10 must determine that the daisy chain is interrupted. Furthermore, the master 10 must supply SW instruction signals to the first, second, and third slaves 20, 30, and 40 without using the daisy chain lines 61 to 64.

[0049] Therefore, when the first, second, and third slaves 20, 30, and 40 cannot receive the SW instruction signal, they output a modified response signal that is different from that used in steady-state operation to the bus line 50. In steady-state operation, the first, second, and third slaves 20, 30, and 40 receive the SW instruction signal via the daisy chain lines 61, 62, and 63 for each switching period. When the first, second, and third slaves 20, 30, and 40 have not received an SW instruction signal even though a switching period has passed since they last received an SW instruction signal, they output the modified response signal to the bus line 50. The modified response signal is a signal obtained by changing the voltage amplitude or pulse width of the response signal used in steady-state operation, and is, for example, a signal with a voltage amplitude level higher or lower than that of the response signal used in steady-state operation.

[0050] After receiving the modified response signal, the master 10 and the first, second, and third slaves 20, 30, and 40 stop outputting the response signal to the bus line 50. Then, the master 10 transmits a SW instruction signal to the bus line 50 for each switching period to notify the switching timing and duty ratio. The first, second, and third slaves 20, 30, and 40 receive the SW instruction signal via the bus line 50. The first, second, and third slaves 20, 30, and 40 recognize their own operation order by transmitting and receiving the response signal. The first, second, and third slaves 20, 30, and 40 adjust the delay of the SW instruction signal received via the bus line 50 based on their own operation order. Then, the first, second, and third slaves 20, 30, and 40 operate based on the delay-adjusted SW instruction signal.

[0051] <1-3.Effects> According to the first embodiment described above in detail, the following effects are achieved. (1) In the multiphase power supply circuit 100, when a failure is detected in any of the first, second, and third slaves 20, 30, and 40, the operating times of the master 10 and the remaining slaves are changed to compensate for the output of the failed slave. Therefore, the multiphase power supply circuit 100 can continue to provide the desired output even if any of the slaves fails.

[0052] (2) The master 10 and the first, second, and third slaves 20, 30, and 40 are connected by daisy chain lines 61 to 64, and SW instruction signals are sequentially transmitted via the daisy chain lines 61 to 64, allowing the first, second, and third slaves 20, 30, and 40 to recognize their own switching timings. Furthermore, because the master 10 and the first, second, and third slaves 20, 30, and 40 are connected by the bus line 50, they can output response signals to the bus line 50 at their own switching timings and confirm each other's operation. Consequently, if any of the first, second, and third slaves 20, 30, and 40 fails, the master 10 can detect the failure of any slave, identify the failed slave, and allow the remaining slaves to continue operating to compensate for the output of the failed slave.

[0053] (3) When the daisy chain is interrupted, the master 10 can determine that the daisy chain has been interrupted by a slave that has not received the SW instruction signal outputting a modified response signal to the bus line 50. Furthermore, by the master 10 outputting a response signal to the bus line 50, the multiphase power supply circuit 100 can continue to operate with the original number of phases.

[0054] (2. Second Embodiment) <2-1. Differences from the first embodiment> The second embodiment has the same basic configuration as the first embodiment, so differences will be described below. Note that the same reference numerals as those in the first embodiment indicate the same configuration, and reference will be made to the preceding description.

[0055] The multiphase power supply circuit 110 according to the second embodiment differs from the multiphase power supply circuit 100 according to the first embodiment in that it does not include the daisy chain lines 61 to 64. 5, in the multiphase power supply circuit 110, the master 10, the first slave 20, the second slave 30, and the third slave 40 are connected by a bus line 50, but are not connected by daisy chain lines 61 to 64. The configuration of the multiphase power supply circuit 110 is similar to that of the multiphase power supply circuit 100, except that the multiphase power supply circuit 110 does not include the daisy chain lines 61 to 64.

[0056] <2-2. Operation> 5, the operation of the multiphase power supply circuit 110 will be described. In steady-state operation, the master 10 transmits a SW instruction signal to the bus line 50 for each switching period to notify the first, second, and third slaves 20, 30, and 40 of the switching timing and duty ratio.

[0057] When the first, second, and third slaves 20, 30, and 40 receive the SW instruction signal via the bus line 50, they adjust the delay of the SW instruction signal based on their own operation order. Then, the first, second, and third slaves 20, 30, and 40 operate based on the delay-adjusted SW instruction signal and output a response signal to the bus line 50 at the operation timing. The response signal is a pulse signal with a higher voltage level than the SW instruction signal so that it can be distinguished from the SW instruction signal. Note that the response signal may also be a pulse signal with a lower voltage level than the SW instruction signal.

[0058] Here, the first, second, and third slaves 20, 30, and 40 have the same hardware configuration and cannot be distinguished from one another by their hardware configurations. Therefore, in the multiphase power supply circuit 100, the master 10 and the first, second, and third slaves 20, 30, and 40 recognize the number of phases and the order of their own operations by sequentially transmitting SW instruction signals via the daisy chain lines 61 to 64.

[0059] Since the multiphase power supply circuit 110 does not have daisy chain lines 61-64, the first, second, and third slaves 20, 30, and 40 each have a slave number recognition port. During startup, a different multi-bit signal is input to each of the recognition ports of the first, second, and third slaves 20, 30, and 40 by pull-up and pull-down of the peripheral circuits. The first, second, and third slaves 20, 30, and 40 determine the high level / low level of the multi-bit signal input to their recognition ports to recognize their own slave numbers (i.e., the order of operation).

[0060] 6, in start-up operation, the first, second, and third slaves 20, 30, and 40 transmit number signals corresponding to their recognized slave numbers to the bus line 50. The master 10 receives the number signals via the bus line 50 and recognizes the number of slaves (i.e., the number of phases) based on the number of number signals received.

[0061] The master 10 determines an operation time based on the recognized number of phases and transmits a delay adjustment signal corresponding to the operation time to the bus line 50. The first, second, and third slaves 20, 30, and 40 receive the delay adjustment signal via the bus line 50. Thereafter, the master 10 and the first, second, and third slaves 20, 30, and 40 transition from startup operation to steady-state operation. The first, second, and third slaves 20, 30, and 40 adjust the delay of the SW instruction signal received via the bus line 50 based on the received delay adjustment signal and their own slave numbers.

[0062] Specifically, the first slave 20 recognizes that it is the first slave, and therefore delays the phase of the SW instruction signal until the operation time has elapsed since it received the SW instruction signal. The second slave 30 recognizes that it is the second slave, and therefore delays the phase of the SW instruction signal until 2 times the operation time has elapsed since it received the SW instruction signal. The third slave 40 recognizes that it is the third slave, and therefore delays the phase of the SW instruction signal until 3 times the operation time has elapsed since it received the SW instruction signal.

[0063] Furthermore, when the master 10 and the first, second, and third slaves 20, 30, and 40 determine that any of the slaves has failed based on an abnormality in the response signal, the remaining DC-DC converters change their operating times to compensate for the output of the failed slave. Specifically, as in the first embodiment described above, the master 10 changes its operating time at a fixed switching period based on a correspondence table between the number of operating phases and operating times, and continues to operate.

[0064] <2-3. Effects> According to the second embodiment described above in detail, the effect (1) of the first embodiment described above is achieved, and further, the following effect is achieved.

[0065] (4) In the multiphase power supply circuit 110, by changing the voltage level of the response signal from that of the SW instruction signal, both the response signal and the SW instruction signal are transmitted separately using the same bus line 50. Therefore, even if the multiphase power supply circuit 110 does not have a daisy chain line, the master 10 can determine a failure in any of the slaves via the bus line 50 and can keep the remaining slaves operating to compensate for the output of the failed slave.

[0066] (3. Third Embodiment) <3-1. Differences from the first embodiment> The third embodiment has the same basic configuration as the first embodiment, so differences will be described below. Note that the same reference numerals as those in the first embodiment indicate the same configuration, and reference will be made to the preceding description.

[0067] The multiphase power supply circuit 200 according to the third embodiment differs from the first embodiment in that the multiple DC-DC converters are not divided into master and slave roles, and their operations are controlled by a control circuit provided separately from the multiple DC-DC converters.

[0068] <3-2. Structure> 7 , a multiphase power supply circuit 200 according to the third embodiment includes a control circuit 290, a switching operation detection circuit 280, a first converter 210, a second converter 220, a third converter 230, a first resistor 17, a second resistor 27, a third resistor 37, a first power supply 18, a second power supply 28, a third power supply 38, a smoothing capacitor 70, an output line 80, and an output terminal 90. The first, second, and third converters 210, 220, and 230 are connected in parallel to the output line 80 via the first, second, and third resistors 17, 27, and 37, respectively.

[0069] The first, second, and third converters 210, 220, and 230 are DC-DC converters having the same configuration. The first converter 210 includes a driver 14, a first switching element 15, and a second switching element 16. The second converter 220 includes a driver 24, a first switching element 25, and a second switching element 26. The third converter 230 includes a driver 34, a first switching element 35, and a second switching element 36. The drivers 14, 24, and 34 control the on / off of the first switching elements 15, 25, and 26 and the second switching elements 16, 26, and 36, respectively, based on a SW instruction signal from a control circuit 290.

[0070] The control circuit 290 stores a correspondence table between the number of operating phases and operating times. During steady operation, when the control circuit 290 detects the number of phases, it references the correspondence table and sets an operating time according to the number of phases. The control circuit 290 sequentially transmits SW instruction signals to the drivers 14, 24, and 34, shifting the operating times by each signal.

[0071] The switching operation detection circuit 280 is connected to the first connection point, the second connection point, the third connection point, and the control circuit 290. The first connection point is the connection point between the first switching element 15 and the second switching element 16. The second connection point is the connection point between the first switching element 25 and the second switching element 26. The third connection point is the connection point between the first switching element 35 and the second switching element 36.

[0072] The switching operation detection circuit 280 detects whether or not the first, second, and third converters 210, 220, and 230 are operating based on the potentials of the first connection point, the second connection point, and the third connection point.The switching operation detection circuit 280 then transmits the detected presence or absence of switching operations of the first, second, and third converters 210, 220, and 230 to the control circuit 290.

[0073] When the control circuit 290 does not detect a switching operation of the converter to which the SW instruction signal is sent despite transmitting the SW instruction signal, the control circuit 290 determines that the converter to which the SW instruction signal is sent is faulty. For example, when the control circuit 290 does not detect an operation of the second converter 220 despite transmitting the SW instruction signal to the second converter 220, the control circuit 290 determines that the second converter 220 is faulty.

[0074] If the control circuit 290 determines that any of the first, second, and third converters 210, 220, and 230 has failed, it refers to the correspondence table and changes the operating time so as to compensate for the output of the failed converter at a fixed switching period. Then, the control circuit 290 transmits SW instruction signals corresponding to the changed operating times to the remaining converters in order.

[0075] <3-3.Effects> According to the third embodiment described above in detail, the effect (1) of the first embodiment described above is achieved, and further, the following effect is achieved.

[0076] (5) When a failure occurs in any of the first, second, and third converters 210, 220, and 230, the control circuit 290 can determine whether the converter has failed based on whether an SW instruction signal is output and whether the first, second, and third converters 210, 220, and 230 are operating. Consequently, the control circuit 290 can continue the operation of the remaining converters to compensate for the output of the failed converter.

[0077] (4. Other Embodiments) Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments and can be implemented in various modified forms.

[0078] (a) In the above embodiments, the multiphase power supply circuits 100, 110, and 200 change the operating time of each DC-DC converter without changing the switching period when a failure is detected in one of the DC-DC converters. However, the multiphase power supply circuits 100, 110, and 200 may change the switching period without changing the operating time. Specifically, when a failure is detected in one of the DC-DC converters, the multiphase power supply circuits 100, 110, and 200 may shorten the switching period while keeping the operating time constant to compensate for the output of the failed DC-DC converter. For example, when the phase changes from N (N is a natural number) to M (M is a natural number smaller than N), the switching period may be multiplied by M / N.

[0079] (b) In the first embodiment, after it is determined that one of the multiple slaves has failed, the master 10 and the remaining slaves stop transmitting response signals to the bus line 50. However, as in the second embodiment, a response signal with a voltage level different from that of the SW instruction signal may be transmitted to the bus line 50. Then, when it is determined that one more slave has failed, the master 10 may further change the operating time to allow the remaining slaves to continue operating.

[0080] (c) Multiple functions possessed by one component in the above embodiments may be realized by multiple components, or one function possessed by one component may be realized by multiple components. Also, multiple functions possessed by multiple components may be realized by one component, or one function realized by multiple components may be realized by one component. Also, part of the configuration of the above embodiments may be omitted. Also, at least part of the configuration of the above embodiments may be added to or substituted for the configuration of another of the above embodiments.

[0081] (d) In addition to the multiphase power supply circuit described above, the present disclosure can also be realized in various forms, such as a system including the multiphase power supply circuit as a component, or a method of operating a multiphase power supply circuit. [Explanation of symbols]

[0082] 10...master, 11...pulse signal generating unit, 12, 22, 32...pulse signal transmitting / receiving circuit, 13, 23, 33...bus line communication circuit, 20...first slave, 30...second slave, 40...third slave, 50...bus line, 61-64...daisy chain lines, 100, 110, 200...multiphase power supply circuit, 210...first converter, 220...second converter, 230...third converter, 280...switching operation detection circuit, 290...control circuit.

Claims

1. A plurality of DC-DC converters (10, 20, 30, 40, 210, 220, 230); a control unit (11, 290) configured to operate each of the plurality of DC-DC converters for a predetermined operation time at a predetermined switching cycle so that the operation periods of the plurality of DC-DC converters are shifted from one another; The control unit and when a failure is detected in any of the plurality of DC-DC converters, changing the predetermined switching period or the predetermined operation time of the remaining DC-DC converters so as to compensate for the output of the failed DC-DC converter. Multiphase Power Supply Circuit

2. a first wiring (50) that connects the plurality of DC-DC converters (10, 20, 30, 40) in a bus system; Further provided is a second wiring (61 to 64) that connects the plurality of DC-DC converters in a daisy chain manner, Each of the plurality of DC-DC converters transmitting and receiving a first signal to and from each other via the one wiring; confirming each other's operations based on the first signal received via the first wiring; It is structured as follows: The control unit (11) connected to the first wiring and the second wiring, transmitting a second signal to each of the plurality of DC-DC converters in sequence via the second wiring to control a switching timing of each of the plurality of DC-DC converters; when any of the first signals transmitted from each of the plurality of DC-DC converters becomes abnormal, a failure of any of the plurality of DC-DC converters is detected, the failed DC-DC converter is identified, and the predetermined operation time of the remaining DC-DC converters is changed; It is configured as follows:

2. The multiphase power supply circuit of claim 1.

3. The control unit (11) is configured to transmit the second signal to each of the plurality of DC-DC converters (10, 20, 30, 40) via the first wiring (50) when the second signal is interrupted.

3. The multiphase power supply circuit of claim 2.

4. further comprising a bus wiring (50) that connects the plurality of DC-DC converters (10, 20, 30, 40) in a bus system; Each of the plurality of DC-DC converters transmitting and receiving a first signal to and from each other via the bus line; confirming each other's operations based on the first signal received via the bus line; It is structured as follows: The control unit (11) connected to the bus wiring, transmitting a second signal different from the first signal to the bus line to control operation timing of each of the plurality of DC-DC converters; when any of the first signals transmitted from each of the plurality of DC-DC converters becomes abnormal, a failure of any of the plurality of DC-DC converters is detected, the failed DC-DC converter is identified, and the predetermined operation time is changed.

2. The multiphase power supply circuit of claim 1.

5. An operation detection circuit (280) connected to each of the plurality of DC-DC converters (210, 220, 230) and configured to detect operation of each of the plurality of DC-DC converters, The control unit (290) is configured to detect a failure of any of the plurality of DC-DC converters based on the output of the operation detection circuit, identify the failed DC-DC converter, and change the predetermined operation time.

2. The multiphase power supply circuit of claim 1.

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