Semiconductor device and semiconductor substrate including semiconductor device

Abstract

To improve contactless wireless communication that uses magnetic coupling of an inductor of a semiconductor device.SOLUTION: A semiconductor device according to one embodiment includes a first inductor which includes a first coil wiring, a second coil wiring in which at least a portion of wiring is on the same plane as the first coil wiring, and a drive unit that supplies the same signal to the first coil wiring and the second coil wiring, and in which a first region surrounded by the first coil wiring and a second region surrounded by the second coil wiring overlap when viewed from a direction perpendicular to the same plane.SELECTED DRAWING: Figure 2B

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to semiconductor devices and semiconductor substrates that include semiconductor devices. [Background technology]

[0002] There are semiconductor devices that include inductors for the purpose of contactless wireless communication using magnetic coupling. Such semiconductor devices enable contactless communication, eliminating the need for signal wiring between transmitters and receivers that is essential in wired communication devices. They also reduce transmission loss due to this signal wiring. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 7,312,685 [Patent Document 2] US Patent Application Publication No. 2008 / 0169895 [Patent Document 3] US Patent Application Publication No. 2016 / 0155558 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device including an inductor that improves non-contact wireless communication using magnetic coupling is provided. [Means for solving the problem]

[0005] A semiconductor device according to one embodiment includes a first coil wiring, a second coil wiring in which at least a portion of the wiring is on the same plane as the first coil wiring, and a drive unit that supplies the same signal to the first coil wiring and the second coil wiring, and includes a first inductor in which a first region surrounded by the first coil wiring and a second region surrounded by the second coil wiring overlap when viewed from a direction perpendicular to the same plane. [Brief explanation of the drawings]

[0006] [Figure 1A] FIG. 1 is a perspective view illustrating non-contact wireless communication using magnetic coupling. [Figure 1B] FIG. 1 illustrates an input signal across a transmitting inductor. [Figure 1C] FIG. 10 is a diagram showing a change over time in current flowing through a transmitting inductor. [Figure 2A] FIG. 2 is a top view illustrating an inductor of a semiconductor device according to an embodiment of the present disclosure. [Figure 2B] FIG. 2 is a circuit diagram illustrating a drive unit of a semiconductor device according to an embodiment of the present disclosure. [Figure 2C] FIG. 2 is a perspective view illustrating an inductor of a semiconductor device according to an embodiment of the present disclosure. [Figure 2D] FIG. 2 is a perspective view illustrating an inductor of a semiconductor device according to an embodiment of the present disclosure. [Figure 3] FIG. 2 is a circuit diagram illustrating a drive unit of a semiconductor device according to an embodiment of the present disclosure. [Figure 4] FIG. 2 is a circuit diagram illustrating a drive unit of a semiconductor device according to an embodiment of the present disclosure. [Figure 5] 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure. [Figure 6] 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure. [Figure 7] FIG. 1 is a top view illustrating a configuration of a semiconductor substrate according to an embodiment of the present disclosure. [Figure 8] FIG. 2 is an enlarged top view illustrating a semiconductor substrate according to an embodiment of the present disclosure. [Figure 9] FIG. 2 is an enlarged top view illustrating a semiconductor substrate according to an embodiment of the present disclosure. [Figure 10] FIG. 2 is an enlarged top view illustrating a semiconductor substrate according to an embodiment of the present disclosure. [Figure 11] FIG. 2 is an enlarged top view illustrating a semiconductor substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0007] The semiconductor device and semiconductor substrate according to the present embodiment will be specifically described below with reference to the drawings. In the following description, elements having substantially the same functions and configurations are designated by the same reference numerals or reference numerals with an alphabetical suffix, and will be described only when necessary. The following embodiments exemplify devices and methods for embodying the technical ideas of the embodiments. Various modifications can be made to the embodiments without departing from the spirit of the invention. These embodiments and their variations are included within the scope of the invention described in the claims and their equivalents.

[0008] In order to clarify the description, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements having the same functions as those explained with reference to the previous drawings may be assigned the same reference numerals, and duplicate explanations may be omitted.

[0009] In this specification, unless otherwise specified, an expression such as "α includes A, B, or C" does not exclude the case where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude the case where α includes other elements.

[0010] The following embodiments can be combined with each other unless a technical contradiction occurs.

[0011] <Contactless wireless communication using magnetic coupling> Contactless wireless communication using magnetic coupling will be described with reference to Figs. 1A to 1C. Fig. 1A is a perspective view illustrating contactless wireless communication using magnetic coupling. Fig. 1B is a diagram showing an input signal across both ends of a transmitting inductor. Fig. 1C is a diagram showing the time variation of the current flowing through the transmitting inductor.

[0012] As shown in Figure 1A, when a current flows through transmitting inductor 1, a signal is transmitted to its paired receiving inductor 2 by mutual induction via the generated magnetic flux. Mutual induction is a phenomenon in which a change in the current in one inductor of two magnetically connected inductors generates an electromotive force in the other inductor. The induced electromotive force e2 generated in receiving inductor 2 is expressed by the following equation:

number

[0013] As shown in FIG. 1B, for example, an inverter circuit is connected to one end of the transmission inductor 1 and the second inverter circuit 1b to the other end of the transmission inductor 1, and the respective input signals are VINP and VINN. Here, VINP is a NRZ (Non Return to Zero) signal that becomes 0 (GND) when (1) t < t1, 1 (VDD) when (2) t1 < t < t2, and 0 (GND) when (3) t2 < t. VINN is the inverted signal of VINP. In case (1), one end of the transmission inductor 1 connected to the first inverter circuit 1a is VDD, the other end of the transmission inductor 1 connected to the second inverter circuit 1b is GND, and a constant current I1 that does not change with time flows in the direction of the arrow. At time t1, the logic of VINP (VINN) switches, and the direction of the current in the transmission inductor 1 tries to reverse, generating a rapid current change. After passing time t1 and settling into the state of (2), one end of the transmission inductor 1 connected to the first inverter circuit 1a is GND, the other end of the transmission inductor 1 connected to the second inverter circuit 1b is VDD, and a constant current -I1 that does not change with time in the opposite direction to the state of (1) flows through the transmission inductor 1. At time t2, the current in the transmission inductor 1 changes rapidly. At this time, since the current in the transmission inductor 1 tries to change from the state of (2) to (1), the time change of the current is opposite to that at t1. As shown in FIG. 1C, the rapid current change of the transmission inductor 1 occurs in a pulse shape only at times t1 and t2 when the NRZ signal transitions, and becomes 0 at other times. Also, the directions of the changes at t1 and t2 are opposite to each other.

[0014] On the other hand, the magnitude of the mutual inductance M is expressed by the following formula.

Equation

[0014] , ,

[0015] , , , , , L R and L are the inductances of the transmission inductor 1 and the reception inductor 2, respectively. Also, k is the coupling coefficient. k is a function of the distance between the two inductors, and k decreases as the distance increases.

[0015] For example, if the shapes (sizes) of the two inductors are constant, the inductance L T , L R is constant. At this time, if the distance between the inductors increases, k becomes smaller, the induced electromotive force e2 decreases, and normal reception becomes impossible. Therefore, in order to extend the communication distance, it is necessary to increase the instantaneous value of the current that can flow through the transmitting inductor 1.

[0016] The current flowing through the inductor at times t1 and t2 is determined by the magnitude of the power supply voltage VDD and the path resistance. The path resistance is the sum of (1) the on-resistance of the transistor that is enabled in the inverter circuit and (2) the wiring parasitic resistance of transmitting inductor 1. Reducing the path resistance allows the current flowing through the inductor to be increased. Increasing the gate width of the transistor that makes up the inverter circuit reduces the resistance of (1), thereby reducing the path resistance. On the other hand, if the inductor size, wiring width, wiring layer, and number of turns are constant, the resistance value of (2) remains constant. Therefore, when the resistance of (1) becomes sufficiently small, the value of the current flowing through the inductor is determined solely by the wiring parasitic resistance of (2). In other words, the maximum distance between inductors that can communicate without contact depends on the wiring parasitic resistance of transmitting inductor 1.

[0017] First Embodiment [Inductor configuration] The configuration of the inductor of the semiconductor device according to this embodiment will be described with reference to Fig. 2A to Fig. 2C. Fig. 2A is a top view illustrating the inductor of the semiconductor device according to this embodiment. Fig. 2B is a circuit diagram illustrating a drive unit of the semiconductor device according to this embodiment. Fig. 2C is a perspective view illustrating the inductor of the semiconductor device according to this embodiment.

[0018] 2A and 2B, inductor 10 includes first coil wiring 11, second coil wiring 12, third coil wiring 13, fourth coil wiring 14, and drive unit 15 (here, first coil wiring 11, second coil wiring 12, third coil wiring 13, and fourth coil wiring 14 are referred to as coil wiring when not being distinguished from one another). First coil wiring 11, second coil wiring 12, third coil wiring 13, and fourth coil wiring 14 are each an independent piece of wiring and are electrically separated from one another.

[0019] The first coil wiring 11, the second coil wiring 12, the third coil wiring 13, and the fourth coil wiring 14 each extend on an XY plane including the X direction and the Y direction perpendicular to the X direction. The first coil wiring 11, the second coil wiring 12, the third coil wiring 13, and the fourth coil wiring 14 are each arranged with their ends, which are not connected to each other, facing each other. The first coil wiring 11, the second coil wiring 12, the third coil wiring 13, and the fourth coil wiring 14 are each arranged in the shape of a square loop with one turn having a gap (a gap between the facing ends). The first coil wiring 11, the second coil wiring 12, the third coil wiring 13, and the fourth coil wiring 14 each have different lengths. The second coil wiring 12 may be longer than the first coil wiring 11, the third coil wiring 13 may be longer than the second coil wiring 12, and the fourth coil wiring 14 may be longer than the third coil wiring 13. As shown in FIG. 2C, the first coil wiring 11, the second coil wiring 12, the third coil wiring 13, and the fourth coil wiring 14 are arranged in the same layer (same plane) in the Z direction perpendicular to the XY plane including the X and Y directions.

[0020] However, there is no particular limitation to the number, shape, or length of the coil wiring included in inductor 10. The shape of the coil wiring included in inductor 10 may be, for example, a rectangle, a regular polygon, or a circle.

[0021] Furthermore, the layer in the Z direction on which the coil wiring included in inductor 10 is arranged is not particularly limited. Fig. 2D is a perspective view illustrating an inductor of a semiconductor device according to a modified example of this embodiment. As shown in Fig. 2D, the coil wiring included in inductor 10 may be arranged on different layers in the Z direction parallel to the XY plane.

[0022] The region surrounded by the first coil wiring 11 is the first region, the region surrounded by the second coil wiring 12 is the second region, the region surrounded by the third coil wiring 13 is the third region, and the region surrounded by the fourth coil wiring 14 is the fourth region. When viewed from the Z direction, the first region, the second region, the third region, and the fourth region overlap. The second region may be larger than the first region, the third region may be larger than the second region, and the fourth region may be larger than the third region. The second region may include the first region, the third region may include the second region, and the fourth region may include the third region. That is, the first coil wiring 11 may be surrounded by the second coil wiring 12, the second coil wiring 12 may be surrounded by the third coil wiring 13, and the third coil wiring 13 may be surrounded by the fourth coil wiring 14. However, this is not limited to this. For example, when the coil wirings are arranged on different layers in the Z direction as shown in Figure 2D, the position, shape, and length of each coil wiring in the XY direction may be the same, and the areas surrounded by each coil wiring may overlap when viewed from the Z direction.

[0023] When viewed from the Z direction, the centers of the first, second, third, and fourth regions preferably overlap each other. Here, the centers of the regions may be, for example, the points where the diagonals of the regions intersect.

[0024] When viewed from the Z direction, one end of the first coil wiring 11, one end of the second coil wiring 12, one end of the third coil wiring 13, and one end of the fourth coil wiring 14 are preferably arranged on the same line, and the other end of the first coil wiring 11, the other end of the second coil wiring 12, the other end of the third coil wiring 13, and the other end of the fourth coil wiring 14 are preferably arranged on the same line. The gaps in the first coil wiring 11, the second coil wiring 12, the third coil wiring 13, and the fourth coil wiring 14 are preferably the same length. It is more preferable that the gaps in the first coil wiring 11, the second coil wiring 12, the third coil wiring 13, and the fourth coil wiring 14 are arranged on the same line that includes the center of the first region. Here, the one end of each coil wiring may be an end located on the same side of the gaps in the respective coil wiring (located at the same position in the Y direction in FIG. 2). The other end of each coil wiring may be an end located opposite to one end of the coil wiring. The gap between each coil wiring may be a gap between one end and the other end of the coil wiring. However, this is not limited thereto. For example, when the coil wirings are arranged on different layers in the Z direction, the one end and the other end of each coil wiring and the gap may overlap when viewed from the Z direction.

[0025] The first coil wiring 11, the second coil wiring 12, the third coil wiring 13, and the fourth coil wiring 14 are connected to a drive unit 15 that supplies the same signal to each of the coil wirings. The drive unit 15 includes a first driver 11c that supplies a signal to the first coil wiring 11, a second driver 12c that supplies a signal to the second coil wiring 12, a third driver 13c that supplies a signal to the third coil wiring 13, and a fourth driver 14c that supplies a signal to the fourth coil wiring 14 (here, the first driver 11c, the second driver 12c, the third driver 13c, and the fourth driver 14c are collectively referred to as drivers when not being distinguished from one another). The first driver 11c includes a first inverter circuit 11a connected to one end of the first coil wiring 11, and a second inverter circuit 11b connected to the other end of the first coil wiring 11. The second driver 12c includes a first inverter circuit 12a connected to one end of the second coil wiring 12 and a second inverter circuit 12b connected to the other end of the second coil wiring 12. The third driver 13c includes a first inverter circuit 13a connected to one end of the third coil wiring 13 and a second inverter circuit 13b connected to the other end of the third coil wiring 13. The fourth driver 14c includes a first inverter circuit 14a connected to one end of the fourth coil wiring 14 and a second inverter circuit 14b connected to the other end of the fourth coil wiring 14.

[0026] The first inverter circuit 11a of the first driver 11c, the first inverter circuit 12a of the second driver 12c, the first inverter circuit 13a of the third driver 13c, and the first inverter circuit 14a of the fourth driver 14c each receive the same input signal VINP. The second inverter circuit 11b of the first driver 11c, the second inverter circuit 12b of the second driver 12c, the second inverter circuit 13b of the third driver 13c, and the second inverter circuit 14b of the fourth driver 14c each receive the same input signal VINN. That is, the first driver 11c, the second driver 12c, the third driver 13c, and the fourth driver 14c each receive the same signal at the same time and in the same direction.

[0027] In the inductor 10 according to this embodiment, the length of the coil wiring driven by each driver is shorter than the overall length of the inductor 10, thereby reducing the parasitic resistance of the wiring driven by each driver. The overall parasitic resistance of the wiring of the inductor 10 can be divided among the multiple coil wirings, thereby increasing the instantaneous value of the current that can flow through the inductor 10. Therefore, by inputting the same signal to all drivers for the same time and in the same direction, the instantaneous value of the current flowing through the inductor 10 can be increased, generating a large induced electromotive force e2 in the receiving inductor. As a result, the communication distance can be extended compared to a conventional inductor of the same size (e.g., the transmitting inductor 1), improving contactless wireless communication. Furthermore, by inputting the same signal to each of the multiple coil wirings for the same time and in the same direction, the potential difference across the parasitic capacitance between the multiple coils is reduced, thereby further increasing the instantaneous value of the current flowing through the inductor 10.

[0028] Second Embodiment [Inductor configuration] The configuration of the inductor of the semiconductor device according to this embodiment will be described with reference to Fig. 3. Fig. 3 is a circuit diagram illustrating a drive unit of the semiconductor device according to this embodiment. The configuration of the inductor according to this embodiment is the same as the configuration of the inductor 10 according to the first embodiment, except that each driver is connected to a timing adjustment circuit. Explanations of the same things as in the first embodiment will be omitted, and only the parts that differ from the first embodiment will be described here.

[0029] 3, the inductor includes first coil wiring 11, second coil wiring 12, third coil wiring 13, fourth coil wiring 14, and a drive unit 15. The first coil wiring 11, second coil wiring 12, third coil wiring 13, and fourth coil wiring 14 are connected to a drive unit 25 that supplies the same signal to each of the coil wirings. The structure of the coil wiring is the same as in the first embodiment, so a description thereof will be omitted.

[0030] The drive unit 25 includes a first driver 21c that supplies a signal to the first coil wiring 11, a second driver 22c that supplies a signal to the second coil wiring 12, a third driver 23c that supplies a signal to the third coil wiring 13, and a fourth driver 24c that supplies a signal to the fourth coil wiring 14 (here, when the first driver 21c, the second driver 22c, the third driver 23c, and the fourth driver 24c are not to be distinguished from one another, they are referred to as drivers, as in the first embodiment).

[0031] The first driver 21c includes the first timing adjustment circuit 21, the second driver 22c includes the second timing adjustment circuit 22, the third driver 23c includes the third timing adjustment circuit 23, and the fourth driver 24c includes the fourth timing adjustment circuit 24. The first inverter circuit 11a connected to one end of the first coil wiring 11 is connected to the first timing adjustment circuit 21. The first inverter circuit 12a connected to one end of the second coil wiring 12 is connected to the second timing adjustment circuit 22. The first inverter circuit 13a connected to one end of the third coil wiring 13 is connected to the third timing adjustment circuit 23. The first inverter circuit 14a connected to one end of the fourth coil wiring 14 is connected to the fourth timing adjustment circuit 24.

[0032] The first inverter circuit 11a of the first driver 21c, the first inverter circuit 12a of the second driver 22c, the first inverter circuit 13a of the third driver 23c, and the first inverter circuit 14a of the fourth driver 24c each receive the same input signal VINP. The second inverter circuit 11b of the first driver 21c, the second inverter circuit 12b of the second driver 22c, the second inverter circuit 13b of the third driver 23c, and the second inverter circuit 14b of the fourth driver 24c each receive the same input signal VINN. That is, the first driver 21c, the second driver 22c, the third driver 23c, and the fourth driver 24c each receive the same signal at the same time and in the same direction.

[0033] For example, if the timing of signal input to the first driver 21c is earlier than the timing of signal input to the second driver 22c due to layout or the like, the timing of the signal input to the first driver 21c may be delayed by the first timing adjustment circuit 21. The timing of signal input to the first driver 21c and the timing of signal input to the second driver 22c may be adjusted to coincide with each other.

[0034] On the other hand, for example, if the first coil wiring 11, the second coil wiring 12, the third coil wiring 13, and the fourth coil wiring 14 are all different lengths, even if each driver inputs the same signal for the same time in the same direction, the timing of times t1 and t2 at which pulses are generated in each coil wiring will be different. Therefore, the first timing adjustment circuit 21, the second timing adjustment circuit 22, the third timing adjustment circuit 23, and the fourth timing adjustment circuit 24 may adjust the timing of the signals input by their respective drivers (here, when there is no need to distinguish between the first timing adjustment circuit 21, the second timing adjustment circuit 22, the third timing adjustment circuit 23, and the fourth timing adjustment circuit 24, they will be referred to as timing adjustment circuits).

[0035] For example, if the second coil wiring 12 is longer than the first coil wiring 11, the second timing adjustment circuit 22 may input the signal earlier than the first timing adjustment circuit 21. If the third coil wiring 13 is longer than the second coil wiring 12, the third timing adjustment circuit 23 may input the signal earlier than the second timing adjustment circuit 22. If the fourth coil wiring 14 is longer than the third coil wiring 13, the fourth timing adjustment circuit 24 may input the signal earlier than the third timing adjustment circuit 23. The positions of times t1 and t2 at which pulses are generated in each coil wiring may be adjusted to coincide with the center between one end and the other end of each coil wiring (on the opposite side of the cut across the center of the area surrounded by each coil wiring).

[0036] In the inductor according to this embodiment, by adjusting the timing of the signals input by each driver using each timing adjustment circuit, the positions of times t1 and t2 at which pulses are generated in each of the multiple coil wires of different lengths can be adjusted, thereby increasing the instantaneous value of the current that can be passed through the inductor per unit time and generating a larger induced electromotive force e2 in the receiving inductor. As a result, the communication distance can be further extended compared to conventional inductors of the same size (e.g., transmitting inductor 1), and non-contact wireless communication can be further improved.

[0037] <Third embodiment> [Inductor configuration] The configuration of the inductor of the semiconductor device according to this embodiment will be described with reference to Fig. 4. Fig. 4 is a circuit diagram illustrating a drive unit of the semiconductor device according to this embodiment. The configuration of the inductor according to this embodiment is the same as the configuration of the inductor 10 according to the first embodiment, except that each coil wiring is connected to one driver. Explanations of the same things as in the first embodiment will be omitted, and only differences from the first embodiment will be described here.

[0038] 4, the inductor includes first coil wiring 11, second coil wiring 12, third coil wiring 13, fourth coil wiring 14, and a drive unit 35. The first coil wiring 11, second coil wiring 12, third coil wiring 13, and fourth coil wiring 14 are connected to the drive unit 35, which supplies the same signal to each of the coil wirings. The structure of the coil wiring is the same as in the first embodiment, so a description thereof will be omitted.

[0039] The drive unit 35 includes a driver 35c that supplies signals to the first coil wiring 11, the second coil wiring 12, the third coil wiring 13, and the fourth coil wiring 14. The driver 35c includes a first inverter circuit 35a connected in parallel to one ends of the first coil wiring 11, the second coil wiring 12, the third coil wiring 13, and the fourth coil wiring 14, and a second inverter circuit 35b connected in parallel to the other ends of the first coil wiring 11, the second coil wiring 12, the third coil wiring 13, and the fourth coil wiring 14.

[0040] The first inverter circuit 35a of the driver 35c inputs the same input signal VINP to one end of the first coil wiring 11, the second coil wiring 12, the third coil wiring 13, and the fourth coil wiring 14. The second inverter circuit 35b of the first driver inputs the same input signal VINN to the other end of the first coil wiring 11, the second coil wiring 12, the third coil wiring 13, and the fourth coil wiring 14. In other words, the driver 35c inputs the same signal to each coil wiring for the same time and in the same direction.

[0041] In the inductor 30 according to this embodiment, each of the multiple coil wires is connected in parallel to one driver, thereby dividing the wiring parasitic resistance of the inductor 30 and increasing the instantaneous value of the current that can flow through the inductor 30. By inputting the same signal for the same time and in the same direction to each of the multiple coil wires, the inductor 30 can increase the instantaneous value of the current that can flow through the inductor 30 per unit time, and can generate a large induced electromotive force e2 in the receiving inductor. As a result, the communication distance can be extended compared to a conventional inductor of the same size (e.g., the transmitting inductor 1), and contactless wireless communication can be improved.

[0042] <Fourth embodiment> [Configuration of semiconductor device] The configuration of a semiconductor device 400 according to this embodiment will be described with reference to Fig. 5. Fig. 5 is a cross-sectional view showing the basic configuration of the semiconductor device 400. As shown in Fig. 5, the semiconductor device 400 is a laminated substrate, and includes a memory cell array chip 100 and a control circuit (CMOS circuit) chip 200. The memory cell array chip 100 and the control circuit chip 200 are connected at a connection surface C1.

[0043] [Memory cell array chip structure] As shown in FIG. 5, the memory cell array chip 100 includes a semiconductor element layer having a source line side wiring layer 150, multiple electrode layers 160, and a memory side wiring layer 170. The multiple electrode layers 160 include a memory cell array region 110 and a contact region 120. The multiple electrode layers 160 are stacked alternately with multiple insulating layers (not shown). Semiconductor pillars CL are arranged in the stacking direction, penetrating the multiple electrode layers 160. Each semiconductor pillar CL is combined with the multiple electrode layers 160 via an insulating layer to function as multiple transistors including memory cells. That is, multiple transistors including memory cells are arranged three-dimensionally in the memory cell array region 110. One end of the semiconductor pillar CL (on the control circuit chip 200 side) is electrically connected to the memory side wiring layer 170 including the bit lines BL, and the other end (opposite the control circuit chip 200) is electrically connected to the source line side wiring layer 150 including the source lines. A connection terminal for connecting to the control circuit chip 200 is arranged on a connection surface C1 of the memory side wiring layer 170.

[0044] A contact region 120 is arranged alongside the memory cell array region 110. In the contact region 120, terminal portions of each of the multiple electrode layers 160 are drawn out in a stepped manner. Each terminal portion is connected to vertical wiring via a contact hole opened in the insulating film. These vertical wirings are electrically connected to the memory-side wiring layer 170, and are connected to the control circuit chip 200 via connection terminals.

[0045] [Control circuit chip structure] 5, the control circuit chip 200 includes a semiconductor element layer having a substrate 250, a plurality of transistors 260 that constitute the control circuit, and a circuit-side wiring layer 270. The plurality of transistors 260 are formed on the substrate 250 and are electrically connected to the circuit-side wiring layer 270 on the side opposite to the substrate 250. A connection terminal for connecting to the memory cell array chip 100 is arranged on a connection surface C1 of the circuit-side wiring layer 270. The substrate 250 may be a semiconductor wafer such as a silicon substrate.

[0046] The inductor 40 according to this embodiment corresponds to the first coil wiring 11, the second coil wiring 12, the third coil wiring 13, and the fourth coil wiring 14 described in the first to third embodiments. The inductor 40 according to this embodiment may be arranged in the source line side wiring layer 150. Here, the inductor 40 corresponds to the back surface wiring of the memory cell array chip 100. As shown in FIG. 2C , the inductors 40 may be arranged on the same layer in the Z direction. Some of the multiple transistors 260 according to this embodiment correspond to the drive units 15.

[0047] The inductor 40 according to this embodiment can divide the wiring parasitic resistance of the inductor 40, thereby increasing the instantaneous value of the current that can flow through the inductor 40. By inputting the same signal for the same time and in the same direction to each of the multiple coil wirings of the inductor 40, the instantaneous value of the current that can flow through the inductor 40 per unit time can be increased, and a large induced electromotive force e2 can be generated in the receiving inductor. This can extend the communication distance of the semiconductor device 400 according to this embodiment, thereby improving contactless wireless communication.

[0048] Fifth Embodiment [Configuration of semiconductor device] The configuration of a semiconductor device 500 according to this embodiment will be described with reference to Fig. 6. Fig. 6 is a cross-sectional view showing the basic configuration of the semiconductor device 500. The configuration of the semiconductor device 500 according to this embodiment is the same as the configuration of the semiconductor device 400 according to the fourth embodiment, except for the position of the inductor. Explanations of the same things as in the fourth embodiment will be omitted, and only differences from the fourth embodiment will be described here.

[0049] 6, the semiconductor device 500 is a laminated substrate, and includes a memory cell array chip 100 and a control circuit chip 200. The memory cell array chip 100 and the control circuit chip 200 are connected at a connection surface C1. The structures of the memory cell array chip 100 and the control circuit chip 200 are the same as those in the fourth embodiment, and therefore a description thereof will be omitted.

[0050] The inductor 50 according to this embodiment has the configuration described in the first to third embodiments, and may be arranged in the memory-side wiring layer 170 and the circuit-side wiring layer 270. Here, at least one layer of the inductor 50 may be arranged on the connection surface C1 of the memory-side wiring layer 170 or the circuit-side wiring layer 270. Other layers of the inductor 50 may be arranged on layers other than the connection surface C1 of the memory-side wiring layer 170 or the circuit-side wiring layer 270. As shown in FIG. 2D , the inductor 50 may be arranged on different layers in the Z direction.

[0051] The inductor 50 according to this embodiment can divide the wiring parasitic resistance of the inductor 50, thereby increasing the instantaneous value of the current that can flow through the inductor 50. By inputting the same signal for the same time and in the same direction to each of the multiple coil wirings of the inductor 50, the instantaneous value of the current that can flow through the inductor 50 per unit time can be increased, and a large induced electromotive force e2 can be generated in the receiving inductor. This can extend the communication distance of the semiconductor device 500 according to this embodiment, thereby improving contactless wireless communication.

[0052] Sixth Embodiment [Semiconductor substrate configuration] The configuration of a semiconductor substrate 6000 according to this embodiment will be described with reference to FIGS. 7 and 8. FIG. 7 is a top view showing the basic configuration of the semiconductor substrate. FIG. 8 is an enlarged top view explaining the semiconductor substrate. As shown in FIGS. 7 and 8, the semiconductor substrate 6000 includes a plurality of effective element regions R1 for manufacturing a plurality of semiconductor devices 600. The effective element regions R1 are arranged in a matrix on the semiconductor substrate 6000. The semiconductor substrate 6000 includes non-effective element regions R2 around each effective element region R1, which serve as cutting margins when the semiconductor devices 600 are diced into individual pieces.

[0053] An inductor 60 is disposed in each of the multiple active element regions R1 of the semiconductor substrate 6000. The inductor 60 according to this embodiment has the configuration described in the first to fifth embodiments. Receiving inductors 3 are disposed in the inactive element region R2 of the semiconductor substrate 6000, each corresponding to one of the multiple inductors 60. Here, the structure of the receiving inductor 3 is not particularly limited. Furthermore, a transmitting / receiving inverter circuit such as a drive unit and a power supply means are added to the receiving inductor 3. However, the configuration of the circuit associated with the receiving inductor 3 is not particularly limited.

[0054] The inductor 60 arranged in the effective element region R1 and the receiving inductor 3 arranged in the non-effective element region R2 are arranged close to each other so as to be magnetically coupled. The inductor 60 according to this embodiment can generate a large induced electromotive force e2 in the receiving inductor 3.

[0055] Each of the multiple receiving inductors 3 is connected to a common external terminal 5 located in the non-active element region R2. The external terminal 5 is located at an edge of the semiconductor substrate 6000. The external terminal 5 is used, for example, to send a test signal to the semiconductor device 600. The test signal is input to each receiving inductor 3 from a probe 4 of a communication device via the external terminal 5. The test signal is transmitted by non-contact wireless communication between the inductor 60 and the corresponding receiving inductor 3 and is transmitted to all semiconductor devices 600 connected to the external terminal 5. If a means for supplying power to the receiving inductor 3 is required, the power supply means can be simplified by, for example, sharing the power among the multiple receiving inductors 3. Alternatively, means such as laser or wireless power supply can be applied.

[0056] The semiconductor substrate 6000 of this embodiment transmits test signals using a non-contact communication means within the semiconductor substrate 6000, thereby reducing the total number of probes 4 required by the communication equipment, thereby reducing the total load of the communication equipment and making it possible to lower the price of the communication equipment.

[0057] The inductor 60 according to this embodiment can divide the wiring parasitic resistance of the inductor 60, thereby increasing the instantaneous value of the current that can be passed through the inductor 60. By inputting the same signal for the same time and in the same direction to each of the multiple coil wirings of the inductor 60, the instantaneous value of the current that can be passed through the inductor 60 per unit time can be increased, and a large induced electromotive force e2 can be generated in the receiving inductor 3. This improves contactless wireless communication within the semiconductor substrate 6000 of the semiconductor device 600 according to this embodiment. Furthermore, because the inductor 60 and the corresponding receiving inductor 3 are arranged in close proximity, signal transmission is possible even if the inductor area is small, and an increase in the area of ​​the semiconductor device 600 can be suppressed.

[0058] Seventh Embodiment [Semiconductor substrate configuration] The configuration of the semiconductor substrate 7000 according to this embodiment will be described with reference to FIG. 9. FIG. 9 is an enlarged top view illustrating the semiconductor substrate. The configuration of the semiconductor substrate 7000 according to this embodiment is the same as the configuration of the semiconductor substrate 6000 according to the sixth embodiment, except for the arrangement and number of inductors. A description of the same parts as in the sixth embodiment will be omitted, and only the parts that differ from the sixth embodiment will be described here.

[0059] An inductor 70 is disposed in each of the multiple active element regions R1 of the semiconductor substrate 7000. The inductor 70 according to this embodiment has the configuration described in the first to fifth embodiments. A multiple number of receiving inductors 3 are disposed in the inactive element region R2 of the semiconductor substrate 7000, with a two-to-one correspondence with the two inductors 70. Here, the structure of the receiving inductor 3 is not particularly limited. Furthermore, a transmitting / receiving inverter circuit such as a drive unit and a power supply means are added to the receiving inductor 3. However, the configuration of the circuit associated with the receiving inductor 3 is not particularly limited.

[0060] The inductors 70 arranged in the two effective element regions R1 and the receiving inductor 3 arranged in the non-effective element region R2 are arranged close to each other so as to be magnetically coupled. Therefore, it is preferable that the two inductors 70 arranged in each effective element region R1 are arranged so as to sandwich the receiving inductor 3. The inductor 70 according to this embodiment can generate a large induced electromotive force e2 in the receiving inductor 3.

[0061] Each of the multiple receiving inductors 3 is connected to a common external terminal 5 arranged in the non-effective element region R2. The external terminal 5 is arranged at an edge of the semiconductor substrate 7000. The external terminal 5 is used, for example, when sending a test signal to the semiconductor device 700. The test signal is input to each receiving inductor 3 from a probe 4 of a communication device via the external terminal 5. The test signal is transmitted in contactless wireless communication between the inductor 70 and the corresponding receiving inductor 3 and is transmitted to all of the semiconductor devices 700 connected to the external terminal 5.

[0062] The semiconductor substrate 7000 of this embodiment transmits test signals using a non-contact communication means within the semiconductor substrate 7000, thereby reducing the total number of probes 4 required by the communication equipment, thereby reducing the total load of the communication equipment and making it possible to lower the price of the communication equipment.

[0063] The inductor 70 according to this embodiment can divide the wiring parasitic resistance of the inductor 70, thereby increasing the instantaneous value of the current that can be passed through the inductor 70. By inputting the same signal for the same time and in the same direction to each of the multiple coil wirings of the inductor 70, the instantaneous value of the current that can be passed through the inductor 70 per unit time can be increased, and a large induced electromotive force e2 can be generated in the receiving inductor 3. This improves contactless wireless communication within the semiconductor substrate 7000 of the semiconductor device 700 according to this embodiment. Furthermore, the number of receiving inductors 3 corresponding to the inductor 70 can be reduced, thereby suppressing an increase in the area of ​​the semiconductor device 700.

[0064] Eighth Embodiment [Semiconductor substrate configuration] The configuration of a semiconductor substrate 8000 according to this embodiment will be described with reference to FIG. 10. FIG. 10 is an enlarged top view illustrating the semiconductor substrate. The configuration of the semiconductor substrate 8000 according to this embodiment is the same as the configuration of the semiconductor substrate 6000 according to the sixth embodiment, except for the arrangement and number of inductors. Explanations of the same parts as in the sixth embodiment will be omitted, and only parts that differ from the sixth embodiment will be described here.

[0065] A plurality of inductors 80 are arranged in each of a plurality of effective element regions R1 of the semiconductor substrate 8000. The inductors 80 according to this embodiment have the configurations described in the first to fifth embodiments. A plurality of receiving inductors 3-1 in one-to-one correspondence with the inductors 80, and a plurality of receiving inductors 3-2 in two-to-one correspondence with the two inductors 80, are arranged in the ineffective element region R2 of the semiconductor substrate 8000. Here, the configurations of the receiving inductors 3-1 and 3-2 are not particularly limited.

[0066] The inductors 80 arranged in one effective element region R1 are arranged close to each other so as to be magnetically coupled to each other. The inductors 80 arranged in one effective element region R1 according to this embodiment can generate a large induced electromotive force e2.

[0067] The inductor 80 arranged in the effective element region R1 and the receiving inductor 3-1 arranged in the ineffective element region R2 are arranged close to each other so as to be magnetically coupled. The inductor 80 according to this embodiment can generate a large induced electromotive force e2 in the receiving inductor 3.

[0068] The inductors 80 arranged in the two effective element regions R1 and the receiving inductor 3-2 arranged in the non-effective element region R2 are arranged close to each other so as to be magnetically coupled. Therefore, it is preferable that the two inductors 80 arranged in each effective element region R1 are arranged so as to sandwich the receiving inductor 3-2. The inductor 80 according to this embodiment can generate a large induced electromotive force e2 in the receiving inductor 3-2.

[0069] Each of the multiple receiving inductors 3-1 is connected to a common external terminal 5 arranged in the non-effective element region R2. The external terminal 5 is arranged at an edge of the semiconductor substrate 8000. The external terminal 5 is used, for example, to send a test signal to the semiconductor device 800. A probe 4 of a communication device inputs the test signal to each receiving inductor 3-1 via the external terminal 5. The test signal is contactlessly and wirelessly communicated between the inductors 80 and the corresponding receiving inductors 3-1 and transmitted to all semiconductor devices 800 connected to the external terminal 5. The test signal is contactlessly and wirelessly communicated between the inductors 80 arranged in the same effective element region R1, and is contactlessly and wirelessly communicated with inductors 80 in different effective element regions R1, including semiconductor devices 800 not connected to the external terminal 5, via receiving inductors 3-2 that correspond two-to-one to the two inductors 80, and is also transmitted to semiconductor devices 800 not connected to the external terminal 5.

[0070] The semiconductor substrate 8000 of this embodiment transmits test signals using a non-contact communication means within the semiconductor substrate 8000, thereby reducing the total number of probes 4 required by the communication equipment, thereby reducing the total load of the communication equipment and making it possible to lower the price of the communication equipment.

[0071] The inductor 80 according to this embodiment can divide the wiring parasitic resistance of the inductor 80, thereby increasing the instantaneous value of the current that can flow through the inductor 80. By inputting the same signal for the same time and in the same direction to each of the multiple coil wirings of the inductor 80, the instantaneous value of the current that can flow through the inductor 80 per unit time can be increased, and a large induced electromotive force e2 can be generated in the receiving inductor 3-1 and the receiving inductor 3-2. This improves contactless wireless communication within the semiconductor substrate 8000 of the semiconductor device 800 according to this embodiment. Furthermore, the wiring between the receiving inductor 3-1 and the external terminal 5 can be reduced, thereby improving the communication speed between the semiconductor devices 800.

[0072] Ninth Embodiment [Semiconductor substrate configuration] The configuration of the semiconductor substrate 9000 according to this embodiment will be described with reference to FIG. 11. FIG. 11 is an enlarged top view illustrating the semiconductor substrate. The configuration of the semiconductor substrate 9000 according to this embodiment is the same as the configuration of the semiconductor substrate 6000 according to the sixth embodiment, except for the arrangement and number of inductors. Explanations of the same aspects as in the sixth embodiment will be omitted, and only differences from the sixth embodiment will be described here.

[0073] A plurality of inductors 90 are arranged in each of a plurality of effective element regions R1 of the semiconductor substrate 9000. The inductors 90 according to this embodiment have the configurations described in the first to fifth embodiments. A plurality of receiving inductors 3-1 are arranged in the non-effective element region R2 of the semiconductor substrate 9000, each of which corresponds one-to-one to the inductors 90. Here, the configuration of the receiving inductors 3-1 is not particularly limited.

[0074] The inductors 90 arranged in one effective element region R1 are arranged close to each other so as to be magnetically coupled to each other. According to this embodiment, the inductors 90 arranged in one effective element region R1 can generate a large induced electromotive force e2.

[0075] The inductors 90 arranged in the different effective element regions R1 are arranged close to each other so as to be magnetically coupled to each other. The inductors 90 arranged in the different effective element regions R1 according to this embodiment can generate an induced electromotive force e2.

[0076] The inductor 90 arranged in the effective element region R1 and the receiving inductor 3-1 arranged in the ineffective element region R2 are arranged close to each other so as to be magnetically coupled. The inductor 90 according to this embodiment can generate a large induced electromotive force e2 in the receiving inductor 3-1.

[0077] Each of the multiple receiving inductors 3-1 is connected to a common external terminal 5 arranged in the non-effective element region R2. The external terminal 5 is arranged at an edge of the semiconductor substrate 9000. The external terminal 5 is used, for example, to send a test signal to the semiconductor device 900. A probe 4 of a communication device inputs the test signal to each receiving inductor 3-1 via the external terminal 5. The test signal is wirelessly and contactlessly communicated between the inductor 90 and the corresponding receiving inductor 3-1 and transmitted to all semiconductor devices 900 connected to the external terminal 5. The test signal is wirelessly and contactlessly communicated between inductors 90 arranged in the same effective element region R1, and between inductors 90 arranged in different effective element regions R1, including semiconductor devices 900 not connected to the external terminal 5, and transmitted to semiconductor devices 900 not connected to the external terminal 5.

[0078] The semiconductor substrate 9000 of this embodiment transmits test signals using a non-contact communication means within the semiconductor substrate 9000, thereby reducing the total number of probes 4 required by the communication equipment, thereby reducing the total load of the communication equipment and making it possible to lower the price of the communication equipment.

[0079] The inductor 90 according to this embodiment can divide the wiring parasitic resistance of the inductor 90, thereby increasing the instantaneous value of the current that can flow through the inductor 90. By inputting the same signal for the same time and in the same direction to each of the multiple coil wirings of the inductor 90, the instantaneous value of the current that can flow through the inductor 90 per unit time can be increased, and a large induced electromotive force e2 can be generated in the receiving inductor 3-1. This improves contactless wireless communication within the semiconductor substrate 9000 of the semiconductor device 900 according to this embodiment. Furthermore, the number of receiving inductors 3-2 corresponding to the inductor 90 can be reduced, thereby preventing an increase in the area of ​​the semiconductor device 900. The wiring between the receiving inductor 3-1 and the external terminal 5 can be reduced, thereby improving the communication speed between the semiconductor devices 900. [Explanation of symbols]

[0080] 1a first inverter circuit, 1b second inverter circuit, 4 probe, 5 external terminal, 10 inductor, 11 first coil wiring, 11a first inverter circuit, 11b second inverter circuit, 11c first driver, 12 second coil wiring, 12a first inverter circuit, 12b second inverter circuit, 12c second driver, 13 third coil wiring, 13a first inverter circuit, 13b second inverter circuit, 13c third driver, 14 fourth coil wiring, 14a first inverter circuit, 14b second inverter circuit, 14c fourth driver, 15 drive unit, 21 first timing adjustment circuit, 21c first driver, 22 second timing adjustment circuit, 22c second driver, 23 third timing adjustment circuit, 23c third driver, 24 fourth timing adjustment circuit, 24c fourth driver, 25 drive unit, 30 inductor, 35 drive unit, 35a first inverter circuit, 35b Second inverter circuit, 35c driver

Claims

1. A first coil wiring; a second coil wiring, at least a portion of which is on the same plane as the first coil wiring; a drive unit that supplies the same signal to the first coil wiring and the second coil wiring; A semiconductor device including a first inductor, in which a first region surrounded by the first coil wiring and a second region surrounded by the second coil wiring overlap when viewed from a direction perpendicular to the same plane.

2. The drive unit is a first driver that supplies the signal to the first coil wiring; The semiconductor device according to claim 1 , further comprising: a second driver that supplies the signal to the second coil wiring.

3. a first timing adjustment circuit connected to the first driver; 3. The semiconductor device according to claim 2, further comprising: a second timing adjustment circuit connected to said second driver.

4. a first chip including a first semiconductor device layer; a second chip bonded to the first chip and including a second semiconductor element layer; The semiconductor device according to claim 1 , wherein the first coil wiring and the second coil wiring are arranged on a surface of the first chip opposite to a surface to which the second chip is attached.

5. a first semiconductor device including a first inductor, the first inductor including a first coil wiring, a second coil wiring having at least a portion thereof on the same plane as the first coil wiring, and a drive unit that supplies the same signal to the first coil wiring and the second coil wiring, wherein a first region surrounded by the first coil wiring and a second region surrounded by the second coil wiring overlap when viewed from a direction perpendicular to the same plane; a second inductor disposed in an inactive element region surrounding the first semiconductor device and magnetically coupled to the first inductor;

6. 6. The semiconductor substrate of claim 5, further comprising a second semiconductor device including a third coil wiring, a fourth coil wiring at least a portion of which is on the same plane as the third coil wiring, and a second drive unit that supplies signals to the third coil wiring and the fourth coil wiring, wherein a third region surrounded by the third coil wiring and a fourth region surrounded by the fourth coil wiring overlap when viewed from the direction, and further comprising a third inductor that is magnetically coupled to the second inductor.

7. the first semiconductor device includes fifth coil wiring, sixth coil wiring at least a portion of which is on the same plane as the fifth coil wiring, and a third drive unit that supplies signals to the fifth coil wiring and the sixth coil wiring, a fifth region surrounded by the fifth coil wiring and a sixth region surrounded by the sixth coil wiring overlap when viewed from the direction, and the first semiconductor device further includes a fourth inductor that is magnetically coupled to the first inductor; 6. The semiconductor substrate of claim 5, further comprising a second semiconductor device including: seventh coil wiring; eighth coil wiring, at least a portion of which exists on the same plane as the seventh coil wiring; and a fourth drive unit that supplies signals to the seventh coil wiring and the eighth coil wiring, wherein a seventh region surrounded by the seventh coil wiring and an eighth region surrounded by the eighth coil wiring overlap when viewed from the direction, and further comprising a fifth inductor that is magnetically coupled to the fourth inductor.

8. the first semiconductor device includes fifth coil wiring, sixth coil wiring at least a portion of which is on the same plane as the fifth coil wiring, and a third drive unit that supplies signals to the fifth coil wiring and the sixth coil wiring, a fifth region surrounded by the fifth coil wiring and a sixth region surrounded by the sixth coil wiring overlap when viewed from the direction, and the first semiconductor device further includes a fourth inductor that is magnetically coupled to the first inductor; a sixth inductor disposed in the inactive element region and magnetically coupled to the fourth inductor; 6. The semiconductor substrate of claim 5, further comprising: a second semiconductor device including: seventh coil wiring; eighth coil wiring, at least a portion of which is on the same plane as the seventh coil wiring; and a fourth drive unit that supplies signals to the seventh coil wiring and the eighth coil wiring, wherein a seventh region surrounded by the seventh coil wiring and an eighth region surrounded by the eighth coil wiring overlap when viewed from the direction; and a fifth inductor that is magnetically coupled to the sixth inductor.

9. The semiconductor substrate according to claim 5 , further comprising an external terminal connected to said second inductor.

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