Diamond semiconductor device and semiconductor module

Abstract

To provide a diamond semiconductor device with improved breakdown voltage and a semiconductor module including the same.SOLUTION: There is provided a diamond semiconductor device 100 having a trench part 50 on a front surface 11. The diamond semiconductor device includes: a diamond layer 15; an epitaxial layer 30 of diamond, which is provided on the diamond layer; a front surface-side insulating film 120 which is provided above the epitaxial layer; and a front surface-side electrode 110 which is provided on the front surface-side insulating film. The inside of a trench of the trench part is filled with the front surface-side insulating film and the front surface-side electrode. The diamond layer includes: a p-type first doped layer 21 having a dope concentration of 3×1019 cm-3 or more and 5×1021 cm-3 or less; and a p-type second doped layer 22 provided on the first doped layer and having a dope concentration lower than that of the first doped layer. The bottom face of the trench part is in contact with the first doped layer.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present invention relates to a diamond semiconductor device and a semiconductor module. [Background technology]

[0002] Patent Document 1 discloses a diamond semiconductor device having a trench structure. [Prior art document] [Patent Documents] Patent Document 1: JP 2017-092398 A Summary of the Invention [Problem to be solved by the invention]

[0003] It is preferable to improve the breakdown voltage of the diamond semiconductor device. [Means for solving the problem]

[0004] In a first aspect of the present invention, there is provided a diamond semiconductor device having a trench portion on its front surface, comprising a diamond layer, a diamond epitaxial layer provided on the diamond layer, a front surface side insulating film provided above the epitaxial layer, and a front surface side electrode provided on the front surface side insulating film. The inside of the trench of the trench portion may be filled with the front surface side insulating film and the front surface side electrode. The diamond layer has a doping concentration of 3×10 19 cm -3 That's it, 5 x 10 21 cm -3 The diamond layer may have a P-type first doped layer having a doping concentration lower than that of the first doped layer. The bottom surface of the trench portion may be in contact with the first doped layer.

[0005] In a second aspect of the present invention, there is provided a semiconductor module comprising a diamond semiconductor device.

[0006] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0007] [Figure 1A] An example of the configuration of a diamond semiconductor device 100 is shown. [Figure 1B] An example of a top view of a diamond semiconductor device 100 is shown. [Figure 2A] A modified example of the diamond semiconductor device 100 is shown. [Figure 2B] A modified example of the diamond semiconductor device 100 is shown. [Figure 2C] A modified example of the diamond semiconductor device 100 is shown. [Figure 2D] A modified example of the diamond semiconductor device 100 is shown. [Figure 3A] 2 is an enlarged view of the vicinity of a trench portion 50 of the diamond semiconductor device 100. FIG. [Figure 3B] 2 is an enlarged view of the vicinity of a trench portion 50 of the diamond semiconductor device 100. FIG. [Figure 3C] 2 is an enlarged view of the vicinity of a trench portion 50 of the diamond semiconductor device 100. FIG. [Figure 4A] 1 shows a diamond semiconductor device 500 as a comparative example. [Figure 4B] 1 shows a diamond semiconductor device 500 as a comparative example. [Figure 4C] 1 shows a diamond semiconductor device 500 as a comparative example. [Figure 5] 2 shows an outline of the configuration of a semiconductor module 200. DETAILED DESCRIPTION OF THE INVENTION

[0008] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0009] FIG. 1A shows an example of the configuration of a diamond semiconductor device 100. The diamond semiconductor device 100 of this example is an example of a semiconductor device that functions as a MOSFET (metal oxide semiconductor field effect transistor). The diamond semiconductor device 100 includes a diamond layer 15. The diamond layer 15 has a support layer 10 and a doped region 20. The diamond layer 15 has the support layer 10 on the back surface 12 side, and the doped region 20 on the front surface 11 side. The diamond semiconductor device 100 of this example has a trench portion 50 on the front surface 11.

[0010] The support layer 10 may be a P-type substrate made of diamond. The doping concentration of the P-type dopant in the support layer 10 is 1×10 19 cm -3 The doping concentration of the support layer 10 may be 3×10 19 cm -3 That's it, 5 x 10 21 cm -3 The support layer 10 may be the following. The support layer 10 may contain a P-type dopant. The P-type dopant may be a Group III element such as boron (B), aluminum (Al) or gallium (Ga). The support layer 10 in this example is P+ type, but is not limited to this. The diamond semiconductor device 100 in this example has a gate structure on the front surface 11 side.

[0011] In this specification, one side in a direction parallel to the depth direction of the support layer 10 is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface, and the other surface is referred to as the lower surface. The directions of "upper," "lower," "front," and "back" are not limited to the direction of gravity or the direction in which the semiconductor device is attached to a substrate or the like when mounted.

[0012] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. In this specification, orthogonal axes parallel to the upper and lower surfaces of the support layer 10 are defined as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the support layer 10 is defined as the Z-axis. The Z-axis direction is the depth direction of the support layer 10. In this specification, a top view refers to a viewpoint viewed from the positive side to the negative side in the Z-axis direction.

[0013] In this specification, the doping concentration of a dopant may refer to the concentration of a dopant that is intentionally introduced. That is, the doping concentration of a dopant does not necessarily include the doping concentration of unintentionally remaining impurities. The dopant may be introduced during epitaxial growth or may be implanted after growth.

[0014] The doped region 20 is provided above the support layer 10. In this example, the doped region 20 includes both a region containing an N-type dopant and a region containing a P-type dopant. The N-type dopant may be a Group V element such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). The P-type dopant may be a Group III element such as boron (B), aluminum (Al), or gallium (Ga).

[0015] The doped region 20 may be a region epitaxially grown on the support layer 10. The doped region 20 may be formed by microwave plasma chemical vapor deposition (MPCVD). The N-type dopant and P-type dopant may be introduced during epitaxial growth, or may be introduced by other methods such as ion implantation after epitaxial growth of an undoped diamond layer. The doped region 20 in this example has a first doped layer 21, a second doped layer 22, and a third doped layer 23.

[0016] The first doped layer 21 is provided above the support layer 10. In this example, the first doped layer 21 is provided in contact with the upper surface of the support layer 10. In this example, the first doped layer 21 contains a P-type dopant. In this example, the first doped layer 21 is P+ type. The doping concentration of the first doped layer 21 may be the same as or different from the doping concentration of the support layer 10. The doping concentration of the first doped layer 21 is 3×10 19 cm -3 That's it, 5 x 10 21 cm -3 It may be the following:

[0017] The thickness of the first doped layer 21 may be thinner than the thickness of the support layer 10. The thickness of the first doped layer 21 may be thicker than the thickness of the second doped layer 22 and may be thicker than the thickness of the third doped layer 23. The first doped layer 21 may be a diamond substrate. That is, the first doped layer 21 may not be a layer epitaxially grown on the support layer 10, but may form a diamond substrate together with the support layer 10.

[0018] The first doped layer 21 in this example is a P+ type region in contact with the epitaxial layer 30. The first doped layer 21 may be in contact with the epitaxial layer 30 provided on the sidewall of the trench portion 50, or may be in contact with the epitaxial layer 30 provided on the bottom surface of the trench portion 50. The upper end of the first doped layer 21 may be provided above the bottom surface of the trench portion 50. The lower end of the first doped layer 21 may be provided below the bottom surface of the trench portion 50.

[0019] The second doped layer 22 is provided above the first doped layer 21. In this example, the second doped layer 22 is provided on the first doped layer 21. The second doped layer 22 includes a P-type dopant. In this example, the second doped layer 22 is P-type. The doping concentration of the P-type dopant in the second doped layer 22 may be different from the doping concentration of the P-type dopant in the first doped layer 21. The doping concentration of the P-type dopant in the second doped layer 22 may be lower than the doping concentration of the P-type dopant in the first doped layer 21. The doping concentration of the second doped layer 22 may be lower than the doping concentration of the first doped layer 21. The doping concentration of the second doped layer 22 may be 1×10 16 cm-3 That's it, 5 x 10 17 cm -3 It may be the following:

[0020] The thickness of the second doped layer 22 may be thinner than the thickness of the support layer 10 and may be thinner than the thickness of the first doped layer 21. The thickness of the second doped layer 22 may be 0.2 μm or more and 5.0 μm or less. The thickness of the second doped layer 22 may be 0.5 μm or more and 3.0 μm or less. By providing the second doped layer 22 between the front surface side electrode 110 of the trench portion 50 and the first doped layer 21, the breakdown voltage can be improved. The doping concentration and thickness of the N-type dopant of the second doped layer 22 may be determined in consideration of the breakdown voltage of the diamond semiconductor device 100, etc.

[0021] The third doped layer 23 is provided above the second doped layer 22. In this example, the third doped layer 23 is provided on the second doped layer 22. In this example, the third doped layer 23 contains an N-type dopant. The doping concentration of the third doped layer 23 is 1×10 17 cm -3 That's it, 1 x 10 21 cm -3 The doping concentration of the N-type dopant and the thickness of the third doped layer 23 may be determined in consideration of the withstand voltage of the diamond semiconductor device 100. Furthermore, by setting the doping concentration of the N-type dopant of the third doped layer 23 to a high concentration, it becomes easier to suppress leakage current in the off state.

[0022] The thickness of the third doped layer 23 may be the same as or different from the thicknesses of the first doped layer 21 and the second doped layer 22. The thickness of the third doped layer 23 may be thinner than the thickness of the first doped layer 21 and may be thinner than the thickness of the second doped layer 22. The thickness of the third doped layer 23 may be 0.2 μm or more and 3.0 μm or less.

[0023] The interface 101 is the boundary between the second doped layer 22 and the third doped layer 23. The diamond semiconductor device 100 can improve the breakdown voltage by mitigating the electric field concentration in the vicinity of the interface 101. The interface 101 will be described later.

[0024] The epitaxial layer 30 is provided on the diamond layer 15. In this example, the epitaxial layer 30 is provided on the doped region 20, but may also be provided on the support layer 10 if the support layer 10 is exposed in the trench T of the trench portion 50. The epitaxial layer 30 is made of diamond. The epitaxial layer 30 may be formed after the trench T of the trench portion 50 is formed in the doped region 20. The epitaxial layer 30 contacts the first doped layer 21 at the bottom surface of the trench portion 50, but may also contact the support layer 10.

[0025] The trench T may be a depression formed by etching the diamond layer 15. The sidewalls and bottom surface of the trench T may be made of the diamond layer 15. In this example, the sidewalls of the trench T are made of a first doped layer 21, a second doped layer 22, and a third doped layer 23. The bottom surface of the trench T is made of the first doped layer 21.

[0026] The thickness of the epitaxial layer 30 may be 10 nm or more and 500 nm or less. The thickness of the epitaxial layer 30 may be 10 nm or more and 100 nm or less. The thickness of the epitaxial layer 30 may be 30 nm or more and 100 nm or less. By reducing the thickness of the epitaxial layer 30, the distance that holes penetrate through the epitaxial layer 30 when the diamond semiconductor device 100 is on is shortened, and the on-resistance can be reduced.

[0027] The doping concentration of the epitaxial layer 30 is 1×10 13 cm -3 That's it, 1 x 10 16 cm -3 The epitaxial layer 30 may include an N-type dopant. The N-type dopant may be nitrogen. The epitaxial layer 30 may have a lower doping concentration of the N-type dopant than the doped region 20. The doping concentration of the N-type dopant in the epitaxial layer 30 may be 1×10 or less. 13 cm -3 That's it, 1 x 10 16 cm-3 By reducing the doping concentration of the N-type dopant in the epitaxial layer 30, when holes from the termination layer 40 flow into the epitaxial layer 30, pass through the epitaxial layer 30 to the first doped layer 21, and then flow to the support layer 10, the potential barrier in the epitaxial layer 30 becomes smaller, thereby reducing the on-resistance.

[0028] The epitaxial layer 30 may contain a P-type dopant. The doping concentration of the P-type dopant in the epitaxial layer 30 may be set to a range that allows the gate to be turned on and off. In one example, the doping concentration of the P-type dopant in the epitaxial layer 30 is 1×10 13 cm -3 That's it, 1 x 10 16 cm -3 The following is the result.

[0029] The termination layer 40 is provided on the epitaxial layer 30. In this example, the termination layer 40 is provided between the epitaxial layer 30 and the gate insulating film 125. The termination layer 40 may be a layer that induces two-dimensional hole gas (2DHG) in the epitaxial layer 30. The conductivity of the termination layer 40 may be low enough to achieve normally-off characteristics. The thickness of the termination layer 40 may be 20 nm or less, or 0.1 nm or more.

[0030] Termination layer 40 may be a hydrogen-terminated layer, a silicon oxide-terminated layer, or may include both a hydrogen-terminated region and a silicon oxide-terminated region. Termination layer 40 may be hydrogen-terminated by hydrogen radical irradiation, or silicon oxide-terminated by a reduction reaction of silicon dioxide and diamond in a high-temperature atmosphere.

[0031] The termination layer 40 may include at least one of a C-H bond, a C-O bond, a C-Si bond, a C-Si-O bond, a C-F bond, a C-OH bond, a C-N bond, or a C-NH bond. The termination layer 40 may have the same bond throughout the entire region of the termination layer 40, or may have different bonds in different regions. The termination layer 40 may have the same bond over the entire surface between the epitaxial layer 30 and the gate insulating film 125. The termination layer 40 may have a C-H bond over the entire surface between the epitaxial layer 30 and the gate insulating film 125.

[0032] The front-side insulating film 120 is provided above the epitaxial layer 30. In this example, the front-side insulating film 120 has a first buried insulating film 121 and a gate insulating film 125. The material of the front-side insulating film 120 may include at least one of Al2O3, SiO2, SiNx, HfO2, HfSiO4, and BN. The front-side insulating film 120 may be formed by a method such as atomic layer deposition (ALD) or CVD.

[0033] The gate insulating film 125 is provided on the front surface 11 side of the diamond layer 15. The gate insulating film 125 is provided above the epitaxial layer 30. The gate insulating film 125 may be provided on the termination layer 40. The gate insulating film 125 may be provided on the sidewalls and bottom surface of the trench T in the trench portion 50. The gate insulating film 125 has a thickness that allows gate control by the gate electrode 112. The thickness of the gate insulating film 125 may be 50 nm or more and 200 nm or less. The thickness of the gate insulating film 125 may be 50 nm or more and 100 nm or less. The thickness of the gate insulating film 125 is, for example, 100 nm.

[0034] The material of the gate insulating film 125 may include at least one of aluminum oxide (Al2O3), silicon oxide (SiO2), silicon nitride (SiNx), hafnium oxide (HfO2), hafnium silicate (HfSiO4), and boron nitride (BN). The composition of Al2O3 does not necessarily have to be Al:O=2:3. The gate insulating film 125 may be a single layer, or may have a layered structure in which different materials are layered. The gate insulating film 125 in this example is a single layer of Al2O3 formed by the ALD method.

[0035] The front surface side electrode 110 is provided above the diamond layer 15. In this example, the front surface side electrode 110 is provided on the front surface side insulating film 120. The front surface side electrode 110 in this example has a gate electrode 112 provided on the front surface side insulating film 120. The front surface side electrode 110 may be provided on the first buried insulating film 121 inside the trench T. The front surface side electrode 110 may also be provided on the gate insulating film 125. As will be described later, the front surface side electrode 110 may have a source electrode 114. The gate electrode 112 and the source electrode 114 are examples of the front surface side electrode 110. The front surface side electrode 110 may have any electrode material, such as aluminum (Al). The symbol G indicates the region of the front surface side electrode 110 that is the gate electrode 112.

[0036] The inside of the trench T of the trench portion 50 is filled with the front surface side insulating film 120 and the front surface side electrode 110. Filling the inside of the trench T of the trench portion 50 with the front surface side insulating film 120 and the front surface side electrode 110 may refer to forming the epitaxial layer 30 and the termination layer 40 inside the trench T and then filling the inside of the termination layer 40 with the front surface side insulating film 120 and the front surface side electrode 110. In this example, the inside of the trench T is filled with the gate insulating film 125, the first buried insulating film 121, and the gate electrode 112 after forming the epitaxial layer 30 and the termination layer 40 inside the trench T.

[0037] The first buried insulating film 121 may be provided inside the gate insulating film 125 inside the trench portion 50. The first buried insulating film 121 fills the inside of the gate insulating film 125. A bottom surface of the first buried insulating film 121 may be in contact with the gate insulating film 125. A sidewall of the first buried insulating film 121 may be in contact with the gate insulating film 125. An upper surface of the first buried insulating film 121 may be in contact with the gate electrode 112. The material of the first buried insulating film 121 may include at least one of Al2O3, SiO2, SiNx, HfO2, HfSiO4, and BN. The material of the first buried insulating film 121 may be SiO2 or SiNx.

[0038] The gate electrode 112 is provided inside the trench T above the first buried insulating film 121. The bottom surface of the gate electrode 112 may be in contact with the top surface of the first buried insulating film 121. The sidewall of the gate electrode 112 may be in contact with the gate insulating film 125. The gate electrode 112 may also be provided above the front surface 11. In this example, the gate electrode 112 is provided outside the trench T on the top surface of the gate insulating film 125.

[0039] The trench portion 50 is provided so as to extend in the depth direction of the diamond layer 15. The trench portion 50 includes an epitaxial layer 30, a termination layer 40, a front surface side electrode 110, and a front surface side insulating film 120 provided inside the trench T. The termination layer 40 may be omitted. The lower end of the trench portion 50 may be deeper than the upper end of the first doped layer 21. That is, the trench portion 50 may extend to the inside of the first doped layer 21. The lower end of the trench portion 50 may be deeper than the upper end of the support layer 10.

[0040] The trench width of the trench portion 50 may be 100 nm or more and 1.5 μm or less. The trench width of the trench portion 50 may be the width of the trench portion 50 at the upper end of the trench portion 50. In this example, the upper end of the trench portion 50 is the gate electrode 112 at the height of the front surface 11. The depth of the trench T may be 60 nm or more and 20 μm or less. The aspect ratio of the trench portion 50 may be 2 or more and 5 or less.

[0041] The bottom surface of the trench portion 50 may be in contact with the first doped layer 21. The entire bottom surface of the trench portion 50 may be in contact with the first doped layer 21, or only a portion of the bottom surface of the trench portion 50 may be in contact with the first doped layer 21. The sidewall of the trench portion 50 may be in contact with the first doped layer 21.

[0042] The contact region 60 is provided above the epitaxial layer 30. The contact region 60 may be provided in contact with the source electrode 114. The contact region 60 may contain a P-type dopant. In this example, the contact region 60 is P+ type, but is not limited to this. The doping concentration of the contact region 60 in this example may be the same as or different from the doping concentration of the support layer 10. The doping concentration of the contact region 60 may be higher or lower than the doping concentration of the support layer 10. The P-type dopant may be a Group III element such as boron (B), aluminum (Al), or gallium (Ga). The P-type dopant may be introduced during epitaxial growth or by other methods such as ion implantation after epitaxial growth of an undoped diamond layer. The thickness of the contact region 60 may be thicker than the thickness of the epitaxial layer 30. The thickness of the contact region 60 may be thinner than the thickness of the epitaxial layer 30.

[0043] The source electrode 114 is provided above the diamond layer 15. The source electrode 114 may be provided on the front surface 11 side of the diamond layer 15. The source electrode 114 may be provided on the contact region 60. The source electrode 114 may be provided in the same region as the contact region 60 when viewed from above, or may be provided inside the contact region 60. The source electrode 114 may be a laminated film formed by laminating titanium (Ti) and gold (Au). The source electrode 114 may also be a laminated film formed by laminating titanium (Ti), platinum (Pt), and gold (Au). A source voltage may be applied to the source electrode 114 provided on the front surface 11 side of the diamond layer 15. The symbol S indicates the region of the source electrode 114.

[0044] The drain electrode 130 is provided on the back surface 12 side of the diamond layer 15. The drain electrode 130 may be provided on the entire back surface 12 or on a part of the back surface 12. The drain electrode 130 may be a laminated film formed by laminating titanium (Ti) and gold (Au). The drain electrode 130 may also be a laminated film formed by laminating titanium (Ti), platinum (Pt), and gold (Au). The drain electrode 130 in this example is provided in contact with the back surface 12 of the support layer 10. A drain-source voltage may be applied to the drain electrode 130 provided on the back surface 12 side of the diamond layer 15. The symbol D indicates the region of the drain electrode 130.

[0045] The diamond semiconductor device 100 of this example has a gate electrode 112 and a source electrode 114 on the front surface 11 side of the diamond layer 15, and a drain electrode 130 on the back surface 12 side of the diamond layer 15. When the diamond semiconductor device 100 is turned on, a current flows from the source electrode 114 to the contact region 60 and then to the termination layer 40, and holes pass through the epitaxial layer 30 and move into the support layer 10, causing a current to flow to the drain electrode 130.

[0046] In this example, the case where the diamond semiconductor device 100 is a P-type channel field effect transistor has been described, but the diamond semiconductor device 100 may be an N-type channel field effect transistor. When the diamond semiconductor device 100 functions as an N-type channel field effect transistor, the P-type dopant may be replaced with an N-type dopant, and the N-type dopant may be replaced with a P-type dopant.

[0047] The diamond semiconductor device 100 of this example can alleviate electric field concentration by providing a front surface side electrode 110 near the interface 101 inside the trench T. Furthermore, the diamond semiconductor device 100 of this example can improve the breakdown voltage by separating the front surface side electrode 110 of the trench portion 50 from the P+ type first doped layer 21. Furthermore, the diamond semiconductor device 100 of this example can increase the doping concentration of the first doped layer 21 in contact with the bottom surface of the trench portion 50 by separating the front surface side electrode 110 of the trench portion 50 from the bottom surface of the trench T. This can reduce the on-resistance of the diamond semiconductor device 100.

[0048] FIG. 1B shows an example of a top view of the diamond semiconductor device 100. A gate electrode 112 and a source electrode 114 are provided on the top surface of the diamond semiconductor device 100, but a drain electrode 130 is not provided. The drain electrode 130 is provided on the bottom surface of the diamond semiconductor device 100. The gate electrode 112 and the source electrode 114 may have pads for connecting to the outside of the diamond semiconductor device 100. A trench portion 50 is provided between opposing portions of the source electrode 114. Note that the diamond semiconductor device 100 of this example has one trench portion 50, but may be an integrated device having multiple trench portions 50. Note that the top view of the diamond semiconductor device 100 of this example is an example and is not limited to this.

[0049] FIG. 2A shows a modified example of the diamond semiconductor device 100. In the diamond semiconductor device 100 of this example, the structure of the trench portion 50 differs from that of the diamond semiconductor device 100 of FIG. 1A. In this example, differences from the diamond semiconductor device 100 of FIG. 1A will be particularly described, and other aspects may be the same as those of the diamond semiconductor device 100 of FIG. 1A. The front surface side insulating film 120 of this example has a first buried insulating film 121, a second buried insulating film 122, and a gate insulating film 125. The front surface side electrode 110 of this example has a gate electrode 112 inside the trench T of the trench portion 50.

[0050] The first buried insulating film 121 is provided inside the trench T of the trench portion 50. The first buried insulating film 121 is provided inside the trench T below the front surface side electrode 110. The upper end of the first buried insulating film 121 may be in contact with the lower end of the front surface side electrode 110. The bottom surface and sidewalls of the first buried insulating film 121 may be in contact with the gate insulating film 125.

[0051] The second buried insulating film 122 is provided above the first buried insulating film 121 inside the trench T of the trench portion 50. The second buried insulating film 122 is provided above the front surface side electrode 110 inside the trench T. A bottom surface of the second buried insulating film 122 may be in contact with the front surface side electrode 110 of the trench portion 50. A side wall of the second buried insulating film 122 may be in contact with the gate insulating film 125. The second buried insulating film 122 may be provided outside the trench T. In this example, the second buried insulating film 122 is provided inside the recess formed by the gate insulating film 125, but it may also be provided outside the recess formed by the gate insulating film 125.

[0052] The material of the second buried insulating film 122 may be the same as or different from that of the first buried insulating film 121. The material of the second buried insulating film 122 may include at least one of Al2O3, SiO2, SiNx, HfO2, HfSiO4, and BN. The material of the second buried insulating film 122 may be SiO2 or SiNx.

[0053] The front surface side electrode 110 is provided inside the trench T of the trench portion 50, between the first buried insulating film 121 and the second buried insulating film 122. That is, the front surface side electrode 110 may be provided only inside the trench T in a cross section passing through the trench width direction of the trench portion 50. In this example, the gate electrode 112 is provided inside the trench T, between the first buried insulating film 121 and the second buried insulating film 122.

[0054] Inside the trench T, the thickness in the depth direction of the front surface side electrode 110 may be smaller than the thickness in the depth direction of the first buried insulating film 121. Inside the trench T, the thickness in the depth direction of the front surface side electrode 110 may be larger than the thickness in the depth direction of the second buried insulating film 122. Inside the trench T, the thickness in the depth direction of the first buried insulating film 121 may be larger than the thickness in the depth direction of the second buried insulating film 122.

[0055] The bottom surface of the front surface side electrode 110 inside the trench T of the trench portion 50 may be flat. However, the shape of the bottom surface of the front surface side electrode 110 is not limited to this. The bottom surface of the front surface side electrode 110 may include a tapered shape, a curved shape, or a combination thereof. The top surface of the front surface side electrode 110 inside the trench T may also be flat. The top surface of the first buried insulating film 121 may also be flat.

[0056] Figure 2B shows a modified example of the diamond semiconductor device 100. In the diamond semiconductor device 100 of this example, the structure of the source electrode 114 is different from that of the diamond semiconductor device 100 of Figure 2A. In this example, differences from the diamond semiconductor device 100 of Figure 2A will be particularly described, and other points may be the same as those of the diamond semiconductor device 100 of Figure 2A.

[0057] The source electrode 114 covers the upper part of the trench portion 50. In this example, the source electrode 114 extends from above one sidewall of the trench portion 50 to above the other sidewall. The source electrode 114 may cover the upper part of the mesa portion 152. In this example, the source electrode 114 is provided on the contact region 60. The source electrode 114 may also be provided on the gate insulating film 125. In the diamond semiconductor device 100 of this example, the on-resistance can be reduced by increasing the area of ​​the source electrode 114.

[0058] Figure 2C shows a modified example of the diamond semiconductor device 100. In the diamond semiconductor device 100 of this example, the structure of the front surface side electrode 110 is different from that of the diamond semiconductor device 100 of Figure 2A. In this example, differences from the diamond semiconductor device 100 of Figure 2A will be particularly described, and other points may be the same as those of the diamond semiconductor device 100 of Figure 2A.

[0059] The front surface side electrode 110 has a tapered bottom surface inside the trench T of the trench portion 50. The taper angle θt is the angle of the bottom surface of the front surface side electrode 110 with respect to a direction parallel to the front surface 11. The taper angle θt may be greater than 0°, may be less than 60°, or may be less than 45°. The depth position of the lower end of the front surface side electrode 110 may be the same as the depth position of the interface 101 between the second doped layer 22 and the third doped layer 23. The taper of the front surface side electrode 110 may be applied as appropriate to other embodiments of the diamond semiconductor device 100.

[0060] The first buried insulating film 121 may have a tapered upper surface. The tapered first buried insulating film 121 may be formed when depositing the first buried insulating film 121 inside the trench T. The bottom surface or the upper surface of the second buried insulating film 122 may also have a tapered surface.

[0061] Figure 2D shows a modified example of the diamond semiconductor device 100. In the diamond semiconductor device 100 of this example, the structure of the front surface side electrode 110 is different from that of the diamond semiconductor device 100 of Figure 2A. In this example, differences from the diamond semiconductor device 100 of Figure 2A will be particularly described, and other points may be the same as those of the diamond semiconductor device 100 of Figure 2A.

[0062] The front surface side electrode 110 provided inside the trench T of the trench portion 50 is a source electrode 114. However, the source electrode 114 may also be provided on the contact region 60. The front surface side electrode 110 provided inside the trench T of the trench portion 50 may be at a floating potential. By providing the front surface side electrode 110 inside the trench T in this way, electric field concentration near the interface 101 can be alleviated, as in the case where the gate electrode 112 is provided inside the trench T.

[0063] The front surface side electrode 110 of this example has a gate electrode 112 outside the trench T. The gate electrode 112 of this example is located above the front surface 11 and is not provided inside the trench T. The gate electrode 112 of this example is provided above the trench portion 50 and the mesa portion 152. The gate electrode 112 may be provided in a region inside the region where the gate insulating film 125 is provided in a top view. That is, the gate electrode 112 may be provided so as to overlap the gate insulating film 125 in a top view. At least a portion of the gate electrode 112 is provided on the gate insulating film 125. The gate electrode 112 of this example is also provided on the second buried insulating film 122.

[0064] The gate electrode 112 may extend from above one sidewall of the trench portion 50 to above the other sidewall, and may be provided so as to cover the top of the front surface-side insulating film 120 provided inside the trench T. The gate electrode 112 may be provided so as to cover the entire top surface of the trench portion 50, or may be provided so as to cover a portion of the top surface of the trench portion 50. The gate electrode 112 may terminate without extending from above one sidewall of the trench portion 50 to above the other sidewall, and may be provided so as not to completely cover the top of the second buried insulating film 122.

[0065] Fig. 3A is an enlarged view of the vicinity of the trench portion 50 of the diamond semiconductor device 100. This figure shows an enlarged view of the vicinity of the trench portion 50 of the diamond semiconductor device 100 of Fig. 2A.

[0066] The dashed lines near the interface 101 between the second doped layer 22 and the third doped layer 23 indicate the equipotential surface when the diamond semiconductor device 100 is off. The depth position of the interface 101 coincides with the depth position of the bottom surface of the front surface side electrode 110 inside the trench T. However, the depth position of the interface 101 may be different from the depth position of the bottom surface of the front surface side electrode 110 inside the trench T. The front surface side electrode 110 functions as a field plate, so that the equipotential surface becomes approximately linear. As a result, the diamond semiconductor device 100 of this example can suppress electric field concentration near the interface 101.

[0067] Position B110 is the position in the depth direction of the diamond layer 15 of the lower end of the front surface side electrode 110 provided inside the trench T. Position U21 is the position in the depth direction of the upper end of the first doped layer 21. Position B110 may be shallower than position U21. Position B110 may be shallower than half the position of the trench depth of the trench T. However, position B110 may also be deeper than half the position of the trench depth.

[0068] The shortest distance Ls1 is the shortest distance between the interface 101 and the front surface side electrode 110 provided inside the trench T of the trench portion 50. The shortest distance Ls1 may be 0.1 μm or more and 1.5 μm or less. By shortening the distance between the interface 101 and the front surface side electrode 110, electric field concentration can be more easily alleviated.

[0069] The shortest distance Ls2 is the shortest distance between the first doped layer 21 and the front surface side electrode 110. The shortest distance Ls2 may be 0.5 μm or more and 10 μm or less. By increasing the shortest distance Ls2, it becomes easier to increase the breakdown voltage of the diamond semiconductor device 100.

[0070] 3B is an enlarged view of the vicinity of the trench portion 50 of the diamond semiconductor device 100. This figure shows a modification of the diamond semiconductor device 100 of FIG. 2A. The depth position B110 of the lower end of the front surface side electrode 110 is shallower than the depth position of the interface 101.

[0071] Distance Ld indicates the difference between position B110 and the depth position of interface 101. The difference between the position of interface 101 in the depth direction of diamond layer 15 and position B110 in the depth direction of the lower end of front surface side electrode 110 provided inside trench T may be within 0.5 μm. In this example, distance Ld may be greater than 0 and equal to or less than 0.5 μm.

[0072] Figure 3C is an enlarged view of the vicinity of the trench portion 50 of the diamond semiconductor device 100. This figure shows a modified example of the diamond semiconductor device 100 of Figure 2A. The depth position B110 of the lower end of the front surface side electrode 110 is deeper than the depth position of the interface 101. The distance Ld in this example may be greater than 0 and 0.5 μm or less.

[0073] FIG. 4A shows a diamond semiconductor device 500 of a comparative example. The inside of the trench T is filled with an insulating layer 621 and an insulating layer 625. The gate electrode 612 and the source electrode 614 are both provided outside the trench T. An insulating layer 622, which functions as a gate insulating film, is provided above the trench T. Since the doping concentration of the epitaxial layer 30 is lower than that of the third doped layer 23, the depletion layer extends further than that of the third doped layer 23. As a result, the equipotential surface near the trench T has a curved shape, which increases the electric field strength and tends to reduce the breakdown voltage compared to equipotential surfaces that are closer to a straight line, such as those of the diamond semiconductor device 100.

[0074] Region R indicates a breakdown voltage maintaining region for maintaining the breakdown voltage when off. Region R includes the second doped layer 22 and the third doped layer 23. Region R includes the region of the epitaxial layer 30 below the gate electrode 612 and the regions adjacent to the side walls of the second doped layer 22 and the third doped layer 23. Thus, in the diamond semiconductor device 500, the second doped layer 22, the third doped layer 23 and the epitaxial layer 30 constitute a breakdown voltage maintaining region.

[0075] FIG. 4B shows a diamond semiconductor device 500 of a comparative example. The diamond semiconductor device 500 of this example has a structure in which a gate electrode 612 is filled inside an insulating layer 625 that functions as a gate insulating film. The depth position of the lower end of the gate electrode 612 of this example is deeper than the depth position of the upper end of the first doped layer 521. In this example, the region R for maintaining the breakdown voltage when off is the epitaxial layer 30 provided between the first doped layer 521 and the gate electrode 612. In this way, if the gate electrode 612 is formed deep, the region R for maintaining the breakdown voltage may become thin.

[0076] FIG. 4C shows a diamond semiconductor device 500 of a comparative example. The lower end of the trench of the diamond semiconductor device 500 of this example is in contact with a P-type first doped layer 521. The diamond semiconductor device 500 of this example has a structure in which the gate electrode 612 is formed up to the vicinity of the lower end of the trench, and therefore includes a P-type first doped layer 521 to improve the breakdown voltage. However, when a P-type first doped layer 521 is provided, the resistance from the epitaxial layer 30 to the support layer 10 increases, and the on-resistance is likely to increase. In particular, in low temperature regions, the activation rate of impurities in diamond is low, and resistance may increase.

[0077] 5 shows an outline of the configuration of the semiconductor module 200. The semiconductor module 200 includes a diamond semiconductor device 100 that functions as a MOSFET. The semiconductor module 200 includes a gate terminal 210, a source terminal 220, and a drain terminal 230. The gate terminal 210, the source terminal 220, and the drain terminal 230 may be external connection terminals for electrically connecting the semiconductor module 200 to the outside.

[0078] The gate terminal 210 is connected to the front surface side electrode 110 of the diamond semiconductor device 100. The source terminal 220 is connected to the source electrode 114 of the diamond semiconductor device 100. The drain terminal 230 is connected to the drain electrode 130 of the diamond semiconductor device 100. The diamond semiconductor device 100 may be provided on the insulating substrate of the semiconductor module 200 with the drain electrode 130 facing downward. The drain electrode 130 may be electrically connected to the drain terminal 230 via metal wiring on the insulating substrate.

[0079] The semiconductor module 200 may have a single diamond semiconductor device 100, or may have a plurality of diamond semiconductor devices 100. The semiconductor module 200 may have an inverter circuit. The semiconductor module 200 may have an inverter circuit that combines a P-type channel diamond semiconductor device 100 and an N-type channel semiconductor element. The N-type channel semiconductor element may be the N-type channel diamond semiconductor device 100, or may be another semiconductor element such as GaN or SiC.

[0080] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention. [Explanation of symbols]

[0081] 10 Support layer, 11 Front surface, 12 Back surface, 15 Diamond layer, 20 Doped region, 21 First doped layer, 22 Second doped layer, 23 Third doped layer, 30 Epitaxial layer, 40 Termination layer, 50 Trench portion, 60 Contact region, 110 Front electrode, 112 Gate electrode, 114 Source electrode, 120 Front insulating film, 121 First buried insulating film, 122 Second buried insulating film, 125... gate insulating film, 130... drain electrode, 152... mesa portion, 100... diamond semiconductor device, 101... interface, 200... semiconductor module, 210... gate terminal, 220... source terminal, 230... drain terminal, 500... diamond semiconductor device, 521... first doped layer, 612... gate electrode, 614... source electrode, 621... insulating layer, 622... insulating layer, 625... insulating layer

Claims

1. A diamond semiconductor device having a trench portion on a front surface thereof, A diamond layer; an epitaxial layer of diamond disposed on the diamond layer; a front surface insulating film provided above the epitaxial layer; a front surface electrode provided on the front surface insulating film; Equipped with the inside of the trench of the trench portion is filled with the front surface side insulating film and the front surface side electrode; The diamond layer comprises: Doping concentration is 3×10 １９ cm －３ That's it, 5 x 10 ２１ cm －３ a first doped layer of P type, which is: a second doped layer of P type provided on the first doped layer and having a doping concentration lower than that of the first doped layer; and The bottom surface of the trench portion is in contact with the first doped layer. Diamond semiconductor devices.

2. the diamond layer has an N-type third doped layer disposed on the second doped layer; The shortest distance between the interface between the second doped layer and the third doped layer and the front surface electrode provided inside the trench is 0.1 μm or more and 1.5 μm or less. The diamond semiconductor device according to claim 1.

3. a difference between a position in the depth direction of the diamond layer of the interface between the second doped layer and the third doped layer and a position in the depth direction of a lower end of the front surface side electrode provided inside the trench is within 0.5 μm; The diamond semiconductor device according to claim 2 .

4. The position of the lower end of the front surface side electrode provided inside the trench in the depth direction of the diamond layer is shallower than the position of the upper end of the first doped layer in the depth direction. The diamond semiconductor device according to claim 1 .

5. The shortest distance between the first doped layer and the front surface electrode is 0.5 μm or more and 10 μm or less. The diamond semiconductor device according to claim 1 .

6. The trench width of the trench portion is 100 nm or more and 1.5 μm or less. The diamond semiconductor device according to claim 1 .

7. The doping concentration of the second doped layer is 1×10 １６ cm －３ That's it, 5 x 10 １７ cm －３ is The diamond semiconductor device according to claim 2 .

8. The thickness of the second doped layer is 0.2 μm or more and 5.0 μm or less. The diamond semiconductor device according to claim 2 .

9. The doping concentration of the third doped layer is 1×10 １７ cm －３ That's it, 1 x 10 ２１ cm －３ is The diamond semiconductor device according to claim 2 .

10. The thickness of the third doped layer is 0.2 μm or more and 3.0 μm or less. The diamond semiconductor device according to claim 2 .

11. The doping concentration of the epitaxial layer is 1×10 １３ cm －３ That's it, 1 x 10 １６ cm －３ is The diamond semiconductor device according to claim 1 .

12. The front surface side insulating film is a gate insulating film provided inside the trench; a first buried insulating film provided inside the trench and on the inner side of the gate insulating film; have A diamond semiconductor device according to any one of claims 1 to 11.

13. The front surface side insulating film is a first buried insulating film provided inside the trench; a second buried insulating film provided above the first buried insulating film inside the trench; and The front surface side electrode is provided inside the trench between the first buried insulating film and the second buried insulating film. A diamond semiconductor device according to any one of claims 1 to 11.

14. The bottom surface of the front surface side electrode inside the trench is flat. A diamond semiconductor device according to any one of claims 1 to 11.

15. The front surface electrode has a tapered bottom surface inside the trench. A diamond semiconductor device according to any one of claims 1 to 11.

16. The front surface electrode provided inside the trench is a gate electrode. A diamond semiconductor device according to any one of claims 1 to 11.

17. The front surface electrode provided inside the trench is a source electrode. A diamond semiconductor device according to any one of claims 1 to 11.

18. The front surface electrode provided inside the trench is at a floating potential. A diamond semiconductor device according to any one of claims 1 to 11.

19. a source electrode provided above the diamond layer; The source electrode covers the upper part of the trench portion. A diamond semiconductor device according to any one of claims 1 to 11.

20. A semiconductor module comprising the diamond semiconductor device according to claim 1.

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