Semiconductor device

Abstract

To provide a highly reliable semiconductor device which can achieve high voltage resistance.SOLUTION: A semiconductor substrate 10 has: a first semiconductor region 11 of a first conductivity type; and a second semiconductor region 12 of a second conductivity type, opposite to the first conductivity type, which is located on the first semiconductor region 11. In the semiconductor substrate, a semiconductor device has, in plan view: an element region where a semiconductor element is formed; and a termination region which is closer to an end side of the semiconductor substrate than the element region. In the termination region, the semiconductor device has a plurality of groove structures T2 which penetrate the second semiconductor region 12 from an upper surface side and reach the first semiconductor region 11, internally have conductive layers in a floating state, and are formed in parallel to one another in the plan view. On bottom parts of the plurality of groove structures T2 on the semiconductor substrate 10, there is provided a third semiconductor region 41 of the first conductivity type whose impurity concentration is higher than that of the first semiconductor region 11.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a structure of a semiconductor device having a termination region that suppresses a local increase in electric field strength on the termination side of a chip of a power semiconductor element. [Background technology]

[0002] In order to increase the breakdown voltage of the switching element, a termination region having a structure for suppressing local increases in electric field strength is provided so as to surround the outside of the region (element region) in which the switching element is formed.

[0003] When a trench-type IGBT (insulated gate bipolar transistor) (whose on / off state is controlled by the potential of the gate electrode in the trench) is used as the switching element, it is preferable to use a similar trench structure in the termination region in order to simplify the manufacturing process. Patent Documents 1 and 2 describe semiconductor devices having such termination regions.

[0004] 9 is a cross-sectional view of a part of the element region of the semiconductor device 9, and FIG. 10 is a cross-sectional view of a part of the termination region. In the element region (FIG. 9), a thick n-type semiconductor layer that will become a drift layer in the IGBT is formed in a semiconductor substrate 70. - A p-layer (a p-type (second conductivity type) second semiconductor region) 12, which serves as a base region, is formed on a layer (a n-type (first conductivity type) first semiconductor region) 11. On the surface side of the semiconductor substrate 70, an n-type semiconductor layer 12 is formed by passing through the p-layer 12 from the surface along the vertical direction of the paper. - A trench structure T1 is formed extending in the direction perpendicular to the paper surface, and the trench structure T1 has n-type regions that become emitter regions adjacent to both side surfaces of the trench structure T1. +A layer 13 is locally formed. A thin oxide film (gate insulating film) 14 is formed inside the trench structure T1, and then a gate electrode 21, which is a conductive layer made of polycrystalline silicon, is formed so as to fill the trench structure T1. An interlayer insulating layer 16 is locally formed above the trench structure T1 so as to seal the trench structure T1 from above. An emitter electrode 22 is formed on the surface of the semiconductor substrate 70, and the emitter electrode 22 is n-type between the interlayer insulating layers 16. + The layer 13 and the p-layer 12 are electrically connected, and the emitter electrode 22 is spaced apart from the gate electrode 21 .

[0005] Also, n - The back side of the layer 11 (the lower side in FIG. 9) is provided with a p + Layer 17 is formed, and p + A collector electrode 23 is formed on the layer 17. The gate electrodes 21 in all of the trench structures T1 are connected outside the illustrated range, and a control voltage is applied to them. With this structure, the IGBT operates when potentials are applied to the gate electrodes 21, emitter electrodes 22, and collector electrodes 23. Although only four trench structures T1 are shown in FIG. 9, in reality, many more trench structures T1 are similarly formed in parallel.

[0006] The structure of the termination region shown in Fig. 10 is actually provided outside the element region shown in Fig. 9. In Fig. 10, a common semiconductor substrate 70 is also used, and similarly, - A layer (n-type first semiconductor region) 11, a p-layer 12, etc. are provided, and a plurality of trench structures T2 are formed in parallel. Here, a common p-layer 12 is provided in the element region and the termination region, but in reality, the impurity concentration, etc. of the p-layer 12 may be different between the element region and the termination region. An oxide film 14 is formed inside this trench structure T2, just like the element region, and a conductive layer made of polycrystalline silicon similar to the gate electrode 21 is also formed, but the conductive layer formed here is insulated from the surroundings, is not electrically connected to the gate electrode 21, and serves as an electrically independent pseudo gate electrode 31 (floating conductive layer) for each trench structure T2. In addition, an emitter region (n +No layer corresponding to layer 13) is formed in the termination region. Furthermore, unlike the device region, in the termination region, interlayer insulating layer 16 is formed to cover the upper portion of the semiconductor region between the plurality of trench structures T2. Although only five trench structures T2 are shown in FIG. 10, in reality, many more trench structures T2 are arranged outside the illustrated range on the left side.

[0007] Further, on the termination side (right side in FIG. 10) of the trench structure T2 in the termination region, n - n formed locally on the surface of layer 11 + A termination electrode 32 is connected through layer 18 .

[0008] Semiconductor device 9n - When a reverse bias is applied between the p-layer 11 and the p-layer 12, a capacitance is generated in the structure of Fig. 10 as shown in Fig. 11. Here, the p-layer 12 and the n-layer 13 directly below it - The capacitance generated by the expansion of the depletion layer between the layer 11 and the pseudo gate electrode 31 in the trench structure T2 and the n - The capacitance generated by the expansion of the depletion layer between the pseudo gate electrode 31 and the p-layer 12 on the left and right sides thereof is denoted by C2, and the capacitances generated by the expansion of the depletion layer between the pseudo gate electrode 31 and the p-layer 12 on the left and right sides thereof are denoted by C3 and C4. These capacitive junctions distribute the potential at each point from the element region X to the end (termination electrode 32) of the semiconductor substrate 70, thereby preventing the occurrence of regions where the electric field (potential gradient) is locally large. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 9-283754 [Patent Document 2] Patent No. 5315638 Summary of the Invention [Problem to be solved by the invention]

[0010] Mobile ions may be trapped on the surface of the semiconductor substrate 70 or on the protective film thereon. Since the potential of the pseudo gate electrode 31 is not fixed, the charges of these mobile ions affect the potential of the pseudo gate electrode 31, causing n - There was a problem in that the region of layer 11 in contact with the bottom of trench structure T2 was inverted to the opposite conductivity type (p-type). When the inverted region connected to the p-layer 12 on both sides in contact with trench structure T2, capacitances C2 and C3 between the pseudo gate electrode 31 and p-layer 12 were no longer generated, and good voltage distribution became impossible.

[0011] For this reason, there has been a demand for a semiconductor device that is highly reliable and capable of withstanding high voltages.

[0012] The present invention has been made in view of the above problems, and an object of the present invention is to provide an invention that solves the above problems. [Means for solving the problem]

[0013] In order to solve the above problems, the present invention has the following configurations. The present invention relates to a semiconductor device having, in a planar view, a semiconductor substrate having a first semiconductor region of a first conductivity type and a second semiconductor region on the first semiconductor region of a second conductivity type opposite to the first conductivity type, an element region in which a semiconductor element is formed, and a termination region located closer to the end of the semiconductor substrate than the element region, wherein the termination region is provided with a plurality of trench structures formed in parallel in a planar view, the trench structures penetrating the second semiconductor region from the top surface side and reaching the first semiconductor region, with a floating conductive layer formed therein, and a third semiconductor region of the first conductivity type having a higher impurity concentration than the first semiconductor region is provided at the bottom of the plurality of trench structures in the semiconductor substrate. In a plan view, the third semiconductor region may be formed in a ring shape so as to surround the element region. The third semiconductor region may not be provided at the bottom of the trench structure located on the end side of the plurality of trench structures. The third semiconductor region may not be provided at the bottom of the trench structure located on the device region side among the plurality of trench structures. The present invention relates to a semiconductor device in which, in a planar view, a device region in which a semiconductor element is formed and a termination region on an end side of the semiconductor substrate that is closer to the element region than the element region are formed in a semiconductor substrate having a first semiconductor region of a first conductivity type and a second semiconductor region on the first semiconductor region that is of a second conductivity type opposite to the first conductivity type, and in which a shallow junction region is formed in the termination region, the shallow junction region is formed so that the depth of the second semiconductor region between the adjacent trench structures between the element region and the end side is shallower than the depth of the second semiconductor region between the adjacent trench structures on the element region side and the depth of the second semiconductor region between the adjacent trench structures on the end side. The shallow junction region may be formed between at least three adjacent trench structures. In a plan view, the shallow junction region may be formed in a ring shape surrounding the element region. The semiconductor device may further include a termination electrode electrically connected to the first semiconductor region on the end side of the plurality of trench structures in plan view. The termination electrode may include a field plate portion facing the first semiconductor region via an insulating layer on the element region side, and the field plate portion may not extend to above the trench structure on the end side. The interval between two adjacent trench structures may be wider on the element region side than on the end side. [Effects of the Invention]

[0014] Since the present invention is configured as described above, it is possible to obtain a semiconductor device that is highly reliable and has a high breakdown voltage. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention. [Figure 2]1 is a diagram showing a simplified view of a part of a planar structure of a semiconductor device according to a first embodiment of the present invention. [Figure 3] 10 shows the results of calculating the potential distribution in the first semiconductor region in a conventional semiconductor device and a semiconductor device according to an embodiment. [Figure 4] FIG. 4 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention. [Figure 5] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention. [Figure 6] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a fourth embodiment of the present invention. [Figure 7] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a fifth embodiment of the present invention. [Figure 8] 10 shows the results of calculating the potential distribution and the shape of the depletion layer in the first semiconductor region in accordance with the position of the termination electrode and the presence or absence of trapped charges in the semiconductor device according to the fifth embodiment of the present invention. [Figure 9] FIG. 10 is a cross-sectional view showing a part of the structure of an element region in a conventional semiconductor device. [Figure 10] FIG. 10 is a cross-sectional view showing a part of the structure of a termination region in a conventional semiconductor device. [Figure 11] FIG. 1 is a schematic diagram showing a capacitive component of a depletion layer generated in a termination region in a conventional semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0016] Semiconductor devices according to embodiments of the present invention will now be described. In the following drawings, identical or similar parts are designated by identical or similar reference numerals. It should be noted, however, that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of lengths of various parts, and other characteristics may differ from those of the actual device. Therefore, specific dimensions should be determined with reference to the following description. Naturally, the drawings also include parts with different dimensional relationships and ratios. The following embodiments are merely illustrative examples of devices embodying the technical concept of the present invention. The technical concept of the present invention does not limit the shape, structure, or arrangement of components to those described below. Various modifications may be made to the embodiments of the present invention within the scope of the claims. In the present invention, terms such as "top" and "bottom" are used for convenience of description. Even if a component is provided on a side surface, it is within the scope of the present invention as long as it is substantially identical to the components of the present invention. Furthermore, "top" includes not only a component formed in contact with an object but also a component formed via another layer. Furthermore, in the present invention, "connection" is not limited to direct connection, and even if a connection is made via an intervening resistor or other element, it falls within the scope of the present invention as long as it is substantially the same as the constituent elements of the present invention.

[0017] This semiconductor device has a termination region including trench structures T2, similar to the semiconductor device 9. However, in this case, electrical connection between p-layers 12 that should be separated is prevented due to an inversion layer occurring directly below trench structures T2. This makes it possible to more reliably achieve a high breakdown voltage than with conventional techniques.

[0018] (First embodiment) FIG. 1 is a diagram showing a semiconductor device 1 according to a first embodiment. The left side of FIG. 1 corresponds to an element region X (FIG. 9), and the right side corresponds to a termination region Y (FIG. 10). Here, for simplicity, n in FIGS. 9 and 10 is used. + The layer 13, the internal structure of each trench structure T1, T2 (oxide film 14, gate electrode 21, pseudo gate electrode 31), and the n- The structure below the layer 11 is omitted. The structure in the element region X is the same as that of the prior art (FIG. 9).

[0019] 2 is a plan view showing a simplified planar structure of the groove structures T1, T2 and the termination electrode 32 in this semiconductor device 1. Here, only five groove structures T1 and T2 are provided. In a plan view, the semiconductor device 1 (chip) has a generally rectangular shape overall, but only the structure around one vertex (the vertex at the bottom right) is shown here, with the center of the chip located at the upper left in FIG. 2. As for the structures around the other three vertices, similar to the configuration in FIG. 2, groove structure T1 extends in the vertical direction of the page, while groove structure T2 and termination electrode 32 are rotated by 90 degrees.

[0020] Fig. 1 shows a cross section taken along the line AA in Fig. 2. As shown in Fig. 2, the trench structure T2 and the termination electrode 32 (termination region Y) are formed in a ring shape surrounding all of the trench structures T1 (element region X).

[0021] As shown in Figure 2, trench structure T2 is formed in a closed ring shape, so p-layer 12 in Figure 1 is divided by trench structure T2. For example, p-layer 12A between trench structure T2A on the leftmost side and trench structure T2B on the right side in termination region Y in Figure 1 is divided from p-layer 12B between trench structure T2B and trench structure T2C on the right side. Therefore, if an inversion layer is not formed directly below trench structure T2, the capacitances shown in Figure 11 will be formed.

[0022] The structure of the termination region Y in the semiconductor substrate 10 used here is different from that of the semiconductor device 70. - The n-layer (third semiconductor region) 41 having a higher impurity concentration than the layer 11 is formed in the n-type semiconductor region near the bottom of the four trench structures T2 on the central side in the termination region Y. - The p-layer 12 is formed between the n-layer 41 and the p-layer 12, and the p-layer 12 above the n-layer 41 is shallowly junctioned as a shallow p-layer 121. - The impurity concentration of the layer 11 is, for example, 2×10 15 cm-3 On the other hand, the impurity concentration of the n-layer 41 is, for example, 2×10 16 cm -3 As a result, the portion in contact with the bottom side of the trench structure T2 becomes an n-layer 41 with a high impurity concentration, making it difficult for an inversion layer to occur on the bottom side of the trench structure T2. This prevents the p-layers 121 on both sides of the trench structure T2 from being electrically connected to each other due to the inversion layer as described above, and ensures good potential distribution.

[0023] 3 shows the results of simulations of the potential distribution in the n-type layer (first semiconductor region or third semiconductor region) in the termination region at a depth near the bottom of the trench structure T2 for a conventional semiconductor device 9 without an n-layer 41 and a semiconductor device with an n-layer 41 (including the embodiments described below). Here, the horizontal axis represents position, with the left side representing the element region (emitter electrode 22) side and the right side representing the end (termination electrode 32) side. The vertical axis represents potential.

[0024] 3, (1) shows the simulation results for the conventional semiconductor device 9 when there is no trapped charge (ideal case), and (2) shows the simulation results when there is trapped charge. Here, the saturation value (maximum value) of the potential on the right corresponds to the breakdown voltage. In (1), the potential is distributed almost evenly in the termination region, resulting in a high breakdown voltage. In contrast, in (2), an inversion layer is formed at the bottom of adjacent trench structures T2, electrically connecting the p-layers 12 on both sides of the trench structures T2, resulting in a nearly constant potential across multiple trench structures T2. As a result, the potential rises sharply near the p-layer 12 on the end (termination electrode 32) side, resulting in a lower breakdown voltage.

[0025] In contrast, (3) is a simulation result when trapped charge exists in the semiconductor device 1 having the structure of FIG. 1. This result is close to the result of (1), and the breakdown voltage is also significantly improved compared to (2). In other words, even if trapped charge exists, the potential is distributed almost evenly in the termination region Y, resulting in a high breakdown voltage. In other words, it can be confirmed that the above configuration is effective.

[0026] 1, it is preferable that the n layer 41 is not provided on the element region X side of the termination region Y. - The potential difference between the layer 11 and the pseudo gate electrode 31 becomes relatively large. However, by not providing the n layer 41 on the element region X side of the termination region Y, the n - The depletion layer formed between the layer 11 and the pseudo gate electrode 31 can be expanded.

[0027] It is also preferable not to provide the n-layer 41 on the termination electrode 32 side of the termination region Y. Since the termination electrode 32 side of the termination region Y is prone to breakdown, providing the n-layer (third semiconductor region) 41 reduces the n - This is because the depletion layer generated between the layer 11 and the pseudo gate electrode 31 in the trench structure T2 in contact with the n-layer 41 becomes difficult to expand, making breakdown more likely.

[0028] Furthermore, in order to suppress bonding between p layers 121 due to the inversion layer described above, it is particularly preferable to form n layer (third semiconductor region) 41 in a ring shape when viewing semiconductor device 1 in a plan view, corresponding to trench structure T2 in Fig. 2. However, if the formation of the inversion layer described above is particularly likely to occur locally due to an upper surface structure other than the structure of semiconductor device 1 described above, n layer 41 may be formed locally only in this region. In other words, unlike trench structure T2, n layer 41 does not necessarily have to be formed in a closed ring shape, and may be formed scattered locally in the circumferential direction.

[0029] The position, size (height, width, thickness, etc.), impurity concentration, etc. of n-layer 41, together with other layers, are appropriately set according to the characteristics required of semiconductor device 1. Furthermore, n-layer 41 may be formed separately in termination region Y, relatively closer to element region X and relatively closer to termination electrode 32. While FIG. 1 shows four trench structures T2 each having an n-layer 41 at its bottom, the number may be more or less. Furthermore, n-layer 41 may be appropriately formed by, for example, performing ion implantation toward the bottom of the trench after dry etching to form trench structures T1 and T2. This also applies to other embodiments described below.

[0030] In the structure of FIG. 1, if all the trench structures T2 have the same structure and are spaced evenly, the potential gradient (electric field strength) will be approximately uniform, as in the case of no trapped charge in FIG. 3. In this case, for example, if the spacing is widened on the element region X side, the electric field on the element region X side can be weakened, thereby suppressing electric field concentration in this area. As described in Patent Document 2, suppressing electric field concentration on the element region X side is particularly effective in improving breakdown voltage, so it is preferable to widen the spacing of the trench structures T2 on the element region X side and narrow it on the edge side from the perspective of improving breakdown voltage. On the other hand, maintaining a uniform spacing rather than widening the spacing on the element region X side is effective in miniaturizing the semiconductor device 1. The above points also apply to other embodiments described below.

[0031] It is preferable that the intervals between the trench structures T2 gradually increase from the trench structure T2 having the n-layer 41 at its bottom toward the element region X, and that the intervals between the trench structures T2 having the n-layer 41 at its bottom remain constant. Furthermore, it is also preferable that the intervals between the trench structures T2 on the termination electrode 32 side of the trench structure T2 having the n-layer 41 at its bottom remain constant. This allows the semiconductor device 1 to be miniaturized and achieve high reliability and high breakdown voltage.

[0032] (Second embodiment) 4 is a cross-sectional view of a semiconductor device 2 according to the second embodiment, corresponding to FIG. 1. In this case, an n-layer (third semiconductor region) 42 having the same impurity concentration as the n-layer 41 is also formed in the semiconductor substrate 110. - 1, the formation of the n-layer 42 does not result in a locally shallow portion of the p-layer 12 (shallow junction p-layer 121). The bottom of the trench structure T2 is prone to breakdown, and the closer (deeper) the depth of the p-layer 12 on the trench structure T2 side is to the depth of the bottom of the trench structure T2, the less likely breakdown occurs. From this perspective, the breakdown voltage of the semiconductor device 2 can be increased.

[0033] In this case as well, it is clear that, similarly to the semiconductor device 1 described above, the formation of an inversion layer on the bottom side of the trench structure T2 is suppressed.

[0034] (Third embodiment) 5 is a cross-sectional view of a semiconductor device 3 according to a third embodiment, corresponding to FIG. 1. The semiconductor substrate 120 used in this case also has an n-layer (third semiconductor region) 43 formed therein that has the same impurity concentration as the n-layer 41. However, the n-layer 43 is formed more locally than the n-layer 42, only at the bottom of each trench structure T2. Therefore, in this case, no n-layer is formed connecting the bottoms of the trench structures T2. Note that portions of adjacent n-layers 43 may be connected to each other, and when viewed from above in the termination region Y, portions of the n-layer 41 in FIG. 1 or the n-layer 42 in FIG. 4 may coexist with portions of the n-layer 43 in FIG. 5.

[0035] In this case as well, it is clear that, similarly to the semiconductor device 1 described above, the formation of an inversion layer on the bottom side of the trench structure T2 is suppressed.

[0036] (Fourth embodiment) Conduction between the p layers 12 adjacent to the trench structure T2 can also be suppressed by lengthening the conduction path between the p layers 12 adjacent to the trench structure T2 due to the inversion of the n layer in contact with the bottom of the trench structure T2. FIG. 6 is a cross-sectional view of a semiconductor device 4 according to a fourth embodiment, corresponding to FIG. 1. In the termination region Y of this semiconductor substrate 130, the n layer 41 in the semiconductor device 1 is not formed, and instead, the p layer 12 and a shallow junction p layer 121 shallower than the p layer 12 are formed. In FIG. 4, the location where the shallow junction p layer 121 is provided is indicated as a shallow junction region L1. This lengthens the path from one shallow junction p layer 121 adjacent to the trench structure T2 to the other shallow junction p layer 121, thereby suppressing conduction between the shallow junction p layers 121 on both sides of the trench structure T2 due to the inversion layer. In addition, the space between adjacent trench structures T2 does not have to be a shallow junction p layer 121. If the space between adjacent trench structures T2 is a shallow junction p layer 121, the space between adjacent trench structures T2 may be a p layer 12, or shallow junction p layers 121 and p layers 12 may be arranged alternately.

[0037] As with the n layer (third semiconductor region), the shallow junction region L1 does not have to be formed annularly in a planar view, but may be formed locally in the circumferential direction, the shallow junction region L1 does not have to be provided on the inside or outside of the termination region Y, and the shallow junction region L1 may be formed separately on the element region X side and the termination electrode 32 side of the termination region Y.

[0038] The p-layer 12, a portion of which is made into the shallow junction p-layer 121, can be formed by, for example, changing the energy of the ion implantation that forms it. Any of the structures of the semiconductor devices according to the first to fourth embodiments may be combined.

[0039] (Fifth embodiment) 7 shows a semiconductor device 5 according to the fifth embodiment. Here, the structure of the termination region Y, particularly the end side (near the termination electrode 32), is shown. Compared to the structures according to the first to fourth embodiments, the semiconductor substrate 140 has a structure in which the termination electrode 32 and n - The contact point with layer 11 (or n + The distance M between the end of the p-layer 18 and the end of the p-layer 12 is large.

[0040] Then, by extending the termination electrode 32 on the interlayer insulating layer 16 toward the p-layer 12, a portion of the termination electrode 32 functions as a field plate. However, the portion of the termination electrode 32 that functions as a field plate (field plate portion) does not extend above the outermost trench structure T2 (on the right side in the figure). For example, the distance N from the portion that functions as a field plate to the top of the trench structure T2 is wider than the interval S between adjacent trench structures T2.

[0041] 8(a) and 8(b) show the n in the state where there is no trapped charge (a) and the state where there is trapped charge (b) when the field plate portion of the termination electrode 32 in the structure of FIG. 7 extends over the trench structure T2 on its left side (N<0). - The graph shows the results of simulations of the equipotential lines (black lines) and depletion layers (white lines) in layer 11. Similarly, Figures 8(c) and 8(d) show the results for the structure in Figure 7 (N>0) in the absence of trapped charges (c) and the presence of trapped charges (d).

[0042] In (c) and (d), where the field plate portion (termination electrode 32) is spaced apart from the trench structure T2 at the end, the equipotential lines on the semiconductor surface on the outermost p-layer 12 side are gentler than in (a) and (b).

[0043] 3 (4) shows the potential distribution when there is trapped charge in this semiconductor device 5. Here, the trench structure T2 and its surrounding structure are the same as those in the first embodiment. In this case, the potential is evenly distributed as in (3), and furthermore, due to the above-mentioned effect, the highest breakdown voltage is obtained among (1) to (4).

[0044] In the above example, an IGBT is formed in the element region X, but the element formed in the element region X may be any element, such as a diode or MOSFET. However, like the IGBT, it is particularly preferable to form this element using a trench structure, as this simplifies the manufacturing process. In addition, other layers can be added to the semiconductor substrate as appropriate. It is also clear that the same configuration can be applied even if the p-type and n-type in the semiconductor substrate are all reversed in the above example. [Explanation of symbols]

[0045] 1, 2, 3, 4, 5, 9 Semiconductor device 10, 70, 110, 120, 130, 140 Semiconductor substrate 11n - layer (first semiconductor region) 12 p-layer (second semiconductor region) 13, 18n + layer 14 Oxide film (insulating film) 16 Interlayer insulation layer 17 p + layer 21 gate electrode 22 Emitter electrode 23 Collector electrode 31 Pseudo gate electrode 32 Termination electrode 41-43 n layer (third semiconductor region) 121 Shallow junction p layer (p layer: second semiconductor region) L1 shallow junction area T1, T2 groove structure X element area Y termination area

Claims

1. A semiconductor device comprising: a semiconductor substrate having a first semiconductor region of a first conductivity type; and a second semiconductor region on the first semiconductor region, the second semiconductor region having a second conductivity type opposite to the first conductivity type; an element region in which a semiconductor element is formed; and a termination region located closer to an end of the semiconductor substrate than the element region in a plan view; In the termination region, a plurality of trench structures formed in parallel in a plan view, the trench structures being formed so as to penetrate the second semiconductor region from the upper surface side and reach the first semiconductor region, and a floating conductive layer being formed therein; a third semiconductor region of the first conductivity type having an impurity concentration higher than that of the first semiconductor region, provided at the bottom of the plurality of trench structures in the semiconductor substrate;

2. 2. The semiconductor device according to claim 1, wherein the third semiconductor region is formed in a ring shape so as to surround the element region in a plan view.

3. 2. The semiconductor device according to claim 1, wherein the third semiconductor region is not provided at the bottom of the groove structure located on the end side of the plurality of groove structures.

4. 2. The semiconductor device according to claim 1, wherein the third semiconductor region is not provided at the bottom of any of the plurality of groove structures that is located on the device region side.

5. A semiconductor device comprising: a semiconductor substrate having a first semiconductor region of a first conductivity type; and a second semiconductor region on the first semiconductor region, the second semiconductor region having a second conductivity type opposite to the first conductivity type; an element region in which a semiconductor element is formed; and a termination region located closer to an end of the semiconductor substrate than the element region in a plan view; In the termination region, a plurality of trench structures formed in parallel in a plan view, the trench structures being formed so as to penetrate the second semiconductor region from the upper surface side and reach the first semiconductor region, and a floating conductive layer being formed therein; a shallow junction region formed such that the depth of the second semiconductor region between the trench structures provided adjacently between the element region side and the end side is shallower than the depth of the second semiconductor region between the trench structures provided adjacently on the element region side, and the depth of the second semiconductor region between the trench structures provided adjacently on the end side.

6. 6. The semiconductor device according to claim 5, wherein the shallow junction region is formed between at least three adjacent trench structures.

7. 6. The semiconductor device according to claim 5, wherein the shallow junction region is formed in a ring shape surrounding the element region in a plan view.

8. 6. The semiconductor device according to claim 1, further comprising a terminal electrode electrically connected to the first semiconductor region on the end side of the plurality of trench structures in plan view.

9. the termination electrode includes a field plate portion facing the first semiconductor region via an insulating layer on the element region side, 9. The semiconductor device according to claim 8, wherein the field plate portion does not extend above the trench structure on the end side.

10. 10. The semiconductor device according to claim 1, wherein the distance between two adjacent trench structures is wider on the device region side than on the end side.

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