Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of suppressing the occurrence of insulation defects.SOLUTION: A semiconductor device includes a semiconductor element, an encapsulant 30, and an external connection terminal 90 including a P terminal 91. The P terminal 91 includes a portion electrically connected to the semiconductor element, and has a covered portion 911 covered by the encapsulant 30, and a protruding portion 912 protruding outside the encapsulant 30. The external connection terminal 90 has a plated region 903 on whose surface a plating film 902 is provided, and a non-plated region 904 on which the plating film 902 is not provided. The protruding portion 912 includes a bent portion 913, and the non-plated region 904 includes at least a portion of the surface of the bent portion 913.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The disclosure herein relates to semiconductor devices and methods for manufacturing the same. [Background technology]

[0002] Patent Document 1 discloses a power semiconductor device including a semiconductor element, a terminal electrically connected to the semiconductor element, and a sealing resin, and a method for manufacturing the same. The contents of the prior art document are incorporated by reference as an explanation of the technical elements in this specification. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-33569 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, after the tie bars of the lead frame including the terminals are cut, the terminals are plated and then bent. Therefore, there is a risk that the plating may peel off when the terminals are bent, which may result in poor insulation. In the above-mentioned respects and in other respects not mentioned, further improvements are required in semiconductor devices and manufacturing methods thereof.

[0005] An object of the present disclosure is to provide a semiconductor device capable of suppressing the occurrence of insulation defects and a method for manufacturing the same. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of the disclosure includes: A semiconductor element (40); an encapsulant (30) that encapsulates the semiconductor element; an external connection terminal (90) including a portion electrically connected to a semiconductor element and having a covering portion (911, 921, 931) covered by the sealing body and a protruding portion (912, 922, 932) protruding outside the sealing body; Equipped with The external connection terminal has a plated region (903) on the surface of which a plated film (902) is provided, and a non-plated region (904) on which no plated film is provided; The protrusion includes a bent portion (913, 923, 933); The non-plated area includes at least a portion of the surface of the bend.

[0007] According to the disclosed semiconductor device, at least a portion of the surface of the bent portion is a non-plated region. In other words, at least a portion of the surface of the bent portion is not provided with a plating film. This makes it possible to suppress, for example, peeling of the plating film when forming the bent portion, and therefore to suppress the occurrence of insulation defects.

[0008] Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising: Plating is performed to form a plating film (902) on the surface of the external connection terminal (90), electrically connecting the external connection terminals on which the plating film is formed to the semiconductor element (40); forming a sealing body (30) that seals the external connection terminals and the semiconductor element; The external connection terminal is bent at a portion thereof protruding from the sealing body to form a bent portion (913, 923, 933); Before forming the bent portion, at least a part of the plating film is removed from the portion of the external connection terminal that corresponds to the bent portion.

[0009] According to the disclosed method for manufacturing a semiconductor device, the plating film is removed from at least a portion of the external connection terminal at a portion corresponding to the bent portion, and then the external connection terminal is bent to form the bent portion. This makes it possible to prevent, for example, peeling of the plating film when forming the bent portion, and therefore to prevent poor insulation.

[0010] Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising: Plating is performed to form a plating film (902) on the surface of the external connection terminal (90), electrically connecting the external connection terminals on which the plating film is formed to the semiconductor element (40); forming a sealing body (30) that seals the external connection terminals and the semiconductor element; The external connection terminal is bent at a portion thereof protruding from the sealing body to form a bent portion (913, 923, 933); When forming the plating film, partial plating is performed so that the plating film is not formed on at least a part of the portion of the external connection terminal that corresponds to the bent portion.

[0011] According to the disclosed method for manufacturing a semiconductor device, the external connection terminals are partially plated so that a plating film is not formed on at least a portion of the portion corresponding to the bent portion of the external connection terminal. This makes it possible to prevent, for example, peeling of the plating film when forming the bent portion, and therefore to prevent poor insulation.

[0012] The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The reference numerals in parentheses in the claims and in this section are intended to exemplify correspondences with the following embodiments and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become more apparent by reference to the following detailed description and the accompanying drawings. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a diagram showing a power conversion circuit and a drive system to which the semiconductor device according to the first embodiment is applied; [Figure 2] FIG. 1 is a plan view showing a semiconductor device. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. [Figure 4]FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 2. [Figure 5] FIG. 10 is a plan view showing a portion covered with a sealing body. [Figure 6] FIG. 2 is a plan view showing the substrate on the drain electrode side. [Figure 7] FIG. 2 is a plan view showing the substrate on the source electrode side. [Figure 8] FIG. 2 is a cross-sectional view showing a power conversion module. [Figure 9] FIG. 10 is an enlarged cross-sectional view of the P terminal periphery. [Figure 10] 1 is a flowchart showing a manufacturing method. [Figure 11] FIG. 10 is a cross-sectional view showing a state before partial removal is performed. [Figure 12] FIG. 10 is a cross-sectional view showing partial removal by laser irradiation. [Figure 13] FIG. 2 is a plan view showing a state before bending is performed. [Figure 14] FIG. 10 is a diagram showing laser marks. [Figure 15] 10 is a flowchart showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 16] FIG. 10 is a plan view showing a state before partial removal is performed. [Figure 17] FIG. 10 is a plan view showing the state after partial removal by cutting the tie bars. [Figure 18] 18 is a side view showing the periphery of the P terminal after bending, as seen from the X1 direction shown in FIG. 17. FIG. [Figure 19] FIG. [Figure 20] FIG. 10 is a diagram showing the effect of through holes. [Figure 21] FIG. [Figure 22] 10 is a flowchart showing a method for manufacturing a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, several embodiments will be described with reference to the drawings. Note that in each embodiment, corresponding components are designated by the same reference numerals, and redundant description may be omitted. When only a portion of the configuration is described in each embodiment, the configuration of another embodiment previously described may be applied to the remaining portion of the configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations of several embodiments may be partially combined together even if not explicitly stated, provided that there is no particular problem with the combination.

[0015] (First embodiment) The semiconductor device of this embodiment is applied to, for example, a mobile object using a rotating electric machine as a drive source. The mobile object may be, for example, an electric vehicle such as a battery electric vehicle (BEV), a hybrid electric vehicle (HEV), or a plug-in hybrid electric vehicle (PHEV), an electric flying object such as a drone or an electric vertical take-off and landing aircraft (eVTOL), a ship, a construction machine, or an agricultural machine. An example of application to a vehicle will be described below.

[0016] <Vehicle drive system> As shown in FIG. 1, a vehicle drive system 1 includes a DC power supply 2, a motor generator 3, and a power conversion circuit 4.

[0017] The DC power supply 2 is a DC voltage source made up of a rechargeable secondary battery. The secondary battery may be, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a drive source for the vehicle, that is, an electric motor. The motor generator 3 functions as a generator during regeneration. The power conversion circuit 4 converts power between the DC power supply 2 and the motor generator 3.

[0018] <Power conversion circuit> 1 shows an example of a power conversion circuit 4. The power conversion circuit 4 shown in FIG.

[0019] The smoothing capacitor 6 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 6 is connected to a P line 7, which is a power supply line on the high potential side, and an N line 8, which is a power supply line on the low potential side. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 6 is connected to the P line 7 between the DC power supply 2 and the inverter 5. The negative electrode of the smoothing capacitor 6 is connected to the N line 8 between the DC power supply 2 and the inverter 5. The smoothing capacitor 6 is connected in parallel to the DC power supply 2.

[0020] Inverter 5 is a DC-AC conversion circuit. In accordance with switching control by the control circuit, inverter 5 converts DC voltage into three-phase AC voltage and outputs it to motor generator 3. This drives motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, inverter 5 converts the three-phase AC voltage generated by motor generator 3 in response to rotational force from the wheels into DC voltage in accordance with switching control by the control circuit and outputs it to P line 7. In this way, inverter 5 performs bidirectional power conversion between DC power supply 2 and motor generator 3.

[0021] The inverter 5 is configured with upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. The upper and lower arm circuits 9 have an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side.

[0022] The connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the motor generator 3 via an output line 10. The inverter 5 has six arms. Each arm is configured with a switching element. The number of switching elements constituting each arm is not particularly limited. There may be one or more. When there are more than one switching elements, the multiple switching elements connected in parallel to each other are turned on and off at the same timing by a common gate drive signal (drive voltage).

[0023] The illustrated switching element is an n-channel MOSFET 11. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. In the upper arm 9H, a drain terminal of the MOSFET 11 is connected to a P line 7. In the lower arm 9L, a source terminal of the MOSFET 11 is connected to an N line 8. The source terminal of the MOSFET 11 in the upper arm 9H and the drain terminal of the MOSFET 11 in the lower arm 9L are connected to each other.

[0024] A freewheeling diode 12 is connected in antiparallel to each MOSFET 11. The diode 12 may be a parasitic diode (body diode) of the MOSFET 11, or may be provided separately from the parasitic diode. The anode terminal of the diode 12 is connected to the source terminal of the corresponding MOSFET 11, and the cathode terminal is connected to the drain terminal.

[0025] The switching element is not limited to the MOSFET 11. For example, an IGBT may be used. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. In the case of an IGBT, a freewheeling diode is also connected in anti-parallel.

[0026] The power conversion circuit 4 may include a converter. The converter is a DC-DC conversion circuit configured to be able to convert a DC voltage into, for example, a DC voltage of a different value. The converter is provided between the DC power supply 2 and the smoothing capacitor 6. The converter is configured to include, for example, a reactor and the above-mentioned upper and lower arm circuits 9. This configuration allows for voltage step-up and step-down. The power conversion circuit 4 may also include a filter capacitor that removes power supply noise from the DC power supply 2. The filter capacitor is provided between the DC power supply 2 and the converter.

[0027] The power conversion circuit 4 may include a snubber circuit. The snubber circuit is connected in parallel to the upper and lower arm circuits 9. The snubber circuit reduces the inductance of the upper and lower arm circuits 9. In other words, the snubber circuit absorbs a transient high voltage, a so-called switching surge, that occurs when the switching elements (MOSFETs 11) that make up the upper and lower arm circuits 9 are switched. This enables the inverter 5 to perform high-speed switching.

[0028] The power conversion circuit 4 may include a drive circuit for a switching element constituting the inverter 5 or the like. The drive circuit supplies a drive voltage to the gate of the MOSFET 11 of the corresponding arm based on a drive command from the control circuit. The drive circuit drives the corresponding MOSFET 11, i.e., turns it on and off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0029] The power conversion circuit 4 may include a control circuit for the switching element. The control circuit generates a drive command for operating the MOSFET 11 and outputs it to the drive circuit. The control circuit generates the drive command based on, for example, a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. ECU is an abbreviation for Electronic Control Unit.

[0030] The various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 6. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit is configured with, for example, a processor and a memory. PWM is an abbreviation for Pulse Width Modulation.

[0031] <Semiconductor device> FIG. 2 is a plan view showing an example of a semiconductor device according to this embodiment. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 2. FIG. 5 is a plan view showing a portion covered by a sealing body. In FIG. 5, the sealing body is shown by a dashed line, and the substrate and conductor pattern on the source electrode side are shown by dashed lines. For convenience, bonding wires are omitted from FIG. 5. FIG. 6 is a plan view showing the substrate on the drain electrode side. FIG. 7 is a plan view showing the substrate on the source electrode side. Surface metal bodies are shown in FIGS. 6 and 7.

[0032] In the following, the thickness direction of a semiconductor element (semiconductor substrate) is referred to as the Z direction. The direction perpendicular to the Z direction is referred to as the Y direction. The direction perpendicular to both the Z direction and the Y direction is referred to as the X direction. The X direction, Y direction, and Z direction are mutually perpendicular. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is referred to as the planar shape. The planar view from the Z direction is sometimes simply referred to as the planar view.

[0033] The semiconductor device 20 constitutes the upper and lower arm circuits 9 described above, i.e., the inverter 5. The illustrated semiconductor device 20 constitutes one of the upper and lower arm circuits 9, i.e., one phase of the upper and lower arm circuit 9. The semiconductor device 20 may be referred to as a semiconductor module, a power module, or the like. As shown in FIGS. 2 to 7 , the semiconductor device 20 includes a sealing body 30, a semiconductor element 40, substrates 50 and 60, a conductive spacer 70, a joint portion 80, and an external connection terminal 90.

[0034] The encapsulant 30 encapsulates some of the other elements constituting the semiconductor device 20. The remaining parts of the other elements are exposed to the outside of the encapsulant 30. The encapsulant 30 is formed using, for example, a resin material. The encapsulant 30 shown in the example is molded using an epoxy resin by a transfer molding method. Such an encapsulant 30 may be referred to as a molded resin, a resin molded body, or the like.

[0035] The sealing body 30 has a generally rectangular shape in plan view. The sealing body 30 has one surface 30a, a back surface 30b, and side surfaces 30c, 30d, 30e, and 30f as surfaces that form the outer shell. The back surface 30b is the surface opposite to the one surface 30a in the Z direction. The one surface 30a and the back surface 30b are, for example, flat surfaces. The side surface 30d is the surface opposite to the side surface 30c in the Y direction. The side surface 30f is the surface opposite to the side surface 30e in the X direction.

[0036] The sealing body 30 has recesses 31 provided between adjacent external connection terminals 90. The recesses 31 are provided on the side surfaces. The recesses 31 are provided to ensure a creepage distance between adjacent external connection terminals 90. The recesses 31 penetrate the sealing body 30, for example, in the Z direction. The illustrated recesses 31 are provided on the side surfaces 30c and 30d. The recesses 31 are open not only on the side surfaces but also on the one surface 30a and the back surface 30b. On the side surface 30c, one recess 31 is provided between the P terminal 91 and the N terminal 92, and the other is provided between the N terminal 92 and the O terminal 93. On the side surface 30d, one recess 31 is provided between the signal terminal 94 on the upper arm side and the suspension lead 95, and the other is provided between the signal terminal 94 on the lower arm side and the suspension lead 95.

[0037] The encapsulant 30 has a gate mark 32. The gate mark 32 is a mark left by a gate when the encapsulant 30 is molded. The gate mark 32 is recessed relative to the surrounding area of ​​the encapsulant 30. The illustrated gate mark 32 is provided on the side surface 30f. The gate mark 32 is provided at a position closer to the side surface 30d than to the side surface 30c in the Y direction.

[0038] The semiconductor element 40 is formed by forming a switching element on a semiconductor substrate made of silicon (Si) or a wide bandgap semiconductor with a wider bandgap than silicon. Examples of wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. The semiconductor element 40 is sometimes called a power element or a semiconductor chip.

[0039] The illustrated semiconductor element 40 has the above-described n-channel MOSFET 11 formed on a semiconductor substrate made of SiC. The MOSFET 11 has a vertical structure so that a main current flows in the thickness direction of the semiconductor element 40 (semiconductor substrate), i.e., in the Z direction. The semiconductor element 40 has main electrodes of a switching element on both sides in its thickness direction, i.e., in the Z direction. Specifically, the main electrodes include a drain electrode 41 on one side and a source electrode 42 on the back side.

[0040] When diode 12 is a parasitic diode, source electrode 42 also serves as an anode electrode, and drain electrode 41 also serves as a cathode electrode. Diode 12 may be formed on a chip separate from MOSFET 11. Drain electrode 41 is a main electrode on the high potential side, and source electrode 42 is a main electrode on the low potential side.

[0041] The semiconductor element 40 has a generally rectangular shape in plan view. The semiconductor element 40 has a pad 43 formed on the back surface at a position different from the source electrode 42. The source electrode 42 and the pad 43 are exposed from a protective film (not shown) formed on the back surface of the semiconductor substrate. The drain electrode 41 is formed on almost the entire surface. The source electrode 42 is formed on a portion of the back surface of the semiconductor element 40. The pad 43 is an electrode for signals. The pad 43 is formed at the end opposite the region where the source electrode 42 is formed in the Y direction. The pad 43 includes a pad for a gate electrode.

[0042] The semiconductor device 20 includes a plurality of semiconductor elements 40. The plurality of semiconductor elements 40 may include a plurality of types of semiconductor elements with different specifications. As in the illustrated semiconductor device 20, all of the semiconductor elements 40 may have a common configuration. The plurality of semiconductor elements 40 include a semiconductor element 40H that constitutes an upper arm 9H and a semiconductor element 40L that constitutes a lower arm 9L. The semiconductor element 40H is sometimes referred to as an upper arm element, and the semiconductor element 40L is sometimes referred to as a lower arm element. The semiconductor elements 40H and 40L are aligned in the X direction. The semiconductor elements 40H and 40L are disposed at approximately the same position as each other in the Z direction. The drain electrodes 41 of the semiconductor elements 40H and 40L face the substrate 50. The source electrodes 42 of the semiconductor elements 40H and 40L face the substrate 60.

[0043] The substrates 50, 60 are arranged in the Z direction to sandwich the plurality of semiconductor elements 40. The substrates 50, 60 are arranged so that at least portions thereof face each other in the Z direction. The substrates 50, 60 contain all of the plurality of semiconductor elements 40 in a plan view.

[0044] The substrate 50 is disposed on the drain electrode 41 side. The substrate 60 is disposed on the source electrode 42 side. The substrate 50 is electrically connected to the drain electrode 41 and provides a wiring function. The substrate 60 is electrically connected to the source electrode 42 and provides a wiring function. The substrates 50 and 60 provide a heat dissipation function for dissipating heat generated by the semiconductor element 40.

[0045] The substrate 50 includes an insulating base material 51, a front surface metal body 52, and a back surface metal body 53. The substrate 60 includes an insulating base material 61, a front surface metal body 62, and a back surface metal body 63. The insulating base materials 51, 61 may be made of resin or ceramic. The insulating base material 51 electrically separates the front surface metal body 52 and the back surface metal body 53. The insulating base material 61 electrically separates the front surface metal body 62 and the back surface metal body 63.

[0046] The front surface metal bodies 52, 62 and the back surface metal bodies 53, 63 are provided as metal plates or metal foils. The front surface metal bodies 52, 62 and the back surface metal bodies 53, 63 are made of a metal with good electrical and thermal conductivity, such as Cu or Al. The front surface metal bodies 52, 62 are patterned. The front surface metal bodies 52, 62 may have a plating film of Ni, Au, or the like on the metal surface. The front surface metal body 52 has a P wiring 521 and a relay wiring 522. The P wiring 521 and the relay wiring 522 are electrically separated by a predetermined gap. The gap is filled with the sealing body 30.

[0047] The P wiring 521 is connected to the P terminal 91 and the drain electrode 41 of the semiconductor element 40H. The P wiring 521 electrically connects the P terminal 91 and the drain electrode 41 of the semiconductor element 40H. The P wiring 521 has a rectangular shape with its longitudinal direction extending in the Y direction in a plan view. The relay wiring 522 is connected to the drain electrode 41 of the semiconductor element 40L, the joint portion 80, and the O terminal 93. The relay wiring 522 electrically connects the O terminal 93 and the drain electrode 41 of the semiconductor element 40L. The relay wiring 522 has a substantially L-shape in plan view. The relay wiring 522 has a substantially rectangular base portion in plan view and an extension portion connected to the base portion.

[0048] The P wiring 521 and the relay wiring 522 are arranged side by side in the X direction. The relay wiring 522 is arranged so that its extended portion is adjacent to the P wiring 521. The relay wiring 522 is arranged so that its base is closer to the side surface 30d than to the side surface 30d. The drain electrode 41 of the semiconductor element 40L is connected to the relay wiring 522. The joint portion 80 is connected to the extended portion of the relay wiring 522. The P terminal 91 is connected to the P wiring 521 near one end in the Y direction. The O terminal 93 is connected to the relay wiring 522 near one end in the Y direction. The P terminal 91 and the O terminal 93 are arranged on the same side in the Y direction with respect to the semiconductor element 40.

[0049] The surface metal body 62 has an N wiring 621 and a relay wiring 622. The N wiring 621 and the relay wiring 622 are electrically separated by a predetermined gap. This gap is filled with a sealing body 30. The N wiring 621 is connected to the N terminal 92 and the source electrode 42 of the semiconductor element 40L. The N wiring 621 electrically connects the N terminal 92 and the source electrode 42 of the semiconductor element 40L. The relay wiring 622 is connected to the source electrode 42 of the semiconductor element 40H and the joint 80. The relay wiring 622 electrically connects the source electrode 42 of the semiconductor element 40H and the drain electrode 41 of the semiconductor element 40L via the joint 80.

[0050] The N wiring 621 has a substantially L-shape in plan view. The relay wiring 622 also has a substantially L-shape in plan view. The N wiring 621 and the relay wiring 622 each have a substantially rectangular base in plan view and an extended portion connected to the base. The N wiring 621 and the relay wiring 622 are arranged to interdigitate with each other. The N wiring 621 and the relay wiring 622 are arranged so that the extended portion of the N wiring 621 is located on the side face 30c side and the extended portion of the relay wiring 622 is located on the side face 30d side. The base of the N wiring 621 and the base of the relay wiring 622 are aligned in the X direction. The extended portion of the N wiring 621 and the extended portion of the relay wiring 622 are aligned in the Y direction.

[0051] The source electrode 42 of the semiconductor element 40L is connected to the base of the N wiring 621. The N terminal 92 is connected to the extended portion of the N wiring 621. The source electrode 42 of the semiconductor element 40H is connected to the base of the relay wiring 622. The joint portion 80 is connected to the extended portion of the relay wiring 622.

[0052] The back surface metal bodies 53, 63 are electrically isolated from the front surface metal bodies 52, 62 by the insulating base materials 51, 61. The illustrated back surface metal bodies 53, 63 are so-called solid conductors arranged over almost the entire back surface of the insulating base materials 51, 61. The back surface metal body 53 is exposed from one surface 30a of the encapsulant 30, and the back surface metal body 63 is exposed from the back surface 30b. The exposed surface 53a of the back surface metal body 53 is approximately flush with the one surface 30a. The exposed surface 63a of the back surface metal body 63 is approximately flush with the back surface 30b.

[0053] The wiring members are not limited to the substrates 50 and 60. For example, a heat sink (metal plate material) may be used instead of the substrates 50 and 60. The heat sink may be provided as a part of the lead frame.

[0054] The conductive spacer 70 functions as a spacer to ensure a predetermined distance between the semiconductor element 40 and the substrate 60. The conductive spacer 70 ensures a height required for electrically connecting the corresponding signal terminal 94 to the pad 43 of the semiconductor element 40, for example. The conductive spacer 70 is located midway along the electrical and thermal conduction path between the source electrode 42 of the semiconductor element 40 and the substrate 60, providing wiring and heat dissipation functions. The conductive spacer 70 includes a metal material with good electrical and thermal conductivity, such as Cu. The conductive spacer 70 may have a plating film on its surface. The conductive spacer 70 is a generally rectangular columnar body having approximately the same size as the source electrode 42 in a planar view.

[0055] The conductive spacers 70 may also be referred to as terminals, terminal blocks, metal blocks, etc. The semiconductor device 20 includes the same number of conductive spacers 70 as the semiconductor elements 40. Specifically, the semiconductor device 20 includes two conductive spacers 70. One of the conductive spacers 70 electrically connects the source electrode 42 of the semiconductor element 40H to the relay wiring 622. The other conductive spacer 70 electrically connects the source electrode 42 of the semiconductor element 40L to the N wiring 621.

[0056] The joint 80 electrically connects the relay wirings 522, 622. That is, the joint 80 electrically connects the upper arm 9H and the lower arm 9L. The joint 80 is provided between the semiconductor element 40H and the semiconductor element 40L in the X direction. The joint 80 is disposed in the overlapping region of the extended portions of the relay wirings 522, 622 in a plan view. The illustrated joint 80 is a metal columnar body provided separately from the surface metal bodies 52, 62. The joint 80 extends in the Z direction. One end of the joint 80 is connected to the relay wiring 522, and the other end is connected to the relay wiring 622.

[0057] The joint portion 80 may be integrally connected to the surface metal bodies 52, 62. In other words, the joint portion 80 may be provided integrally with the surface metal bodies 52, 62 as part of the substrates 50, 60. A part of the joint portion 80 may be provided as part of the substrate 50, and another part of the joint portion 80 may be provided as part of the substrate 60.

[0058] The external connection terminals 90 are terminals for electrically connecting the semiconductor device 20 to an external device. The external connection terminals 90 are formed using a metal material with good conductivity, such as Cu. The external connection terminals 90 are, for example, a plate material. The external connection terminals 90 are sometimes referred to as leads. The external connection terminals 90 include a P terminal 91, an N terminal 92, an O terminal 93, and a signal terminal 94. The P terminal 91, the N terminal 92, and the O terminal 93 are sometimes referred to as main terminals because they are electrically connected to main electrodes of the semiconductor element 40. The P terminal 91 and the N terminal 92 are sometimes referred to as power supply terminals.

[0059] The P terminal 91 is connected to the P wiring 521 near one end in the Y direction. The P terminal 91 has a covering portion 911 and a protruding portion 912. The covering portion 911 is a portion covered by the sealing body 30. The covering portion 911 includes a connection portion of the P terminal 91 with the P wiring 521. The protruding portion 912 is continuous with one end of the covering portion 911 and is disposed outside the sealing body 30. The protruding portion 912 is a portion of the P terminal 91 that protrudes from the side surface 30c to the outside of the sealing body 30. The protruding portion 912 includes a bent portion 913. The illustrated P terminal 91 is substantially L-shaped in a plan view from the X direction. The portion from the connection portion of the covering portion 911 with the P wiring 521 to the bent portion 913 extends generally in the Y direction. The portion from the bent portion 913 to the protruding tip extends generally in the Z direction.

[0060] The N terminal 92 is connected to an extended portion of the N wiring 621. The N terminal 92 has a covering portion 921 and a protruding portion 922. The covering portion 921 is a portion covered by the sealing body 30. The covering portion 921 includes a connection portion of the N terminal 92 with the N wiring 621. The protruding portion 922 is continuous with one of the ends of the covering portion 921 and is disposed outside the sealing body 30. The protruding portion 922 is a portion of the N terminal 92 that protrudes from the side surface 30c to the outside of the sealing body 30. The protruding portion 922 includes a bent portion 923. The illustrated N terminal 92 is substantially L-shaped in a plan view from the X direction. The portion from the connection portion of the covering portion 921 with the N wiring 621 to the bent portion 923 extends generally in the Y direction. The portion from the bent portion 923 to the protruding tip extends generally in the Z direction, the same direction as the P terminal 91.

[0061] The O terminal 93 is connected to a base of the relay wiring 522 near one end in the Y direction. The O terminal 93 has a covering 931 and a protruding portion 932. The covering 931 is a portion covered by the sealing body 30. The covering 931 includes a connection portion of the O terminal 93 with the relay wiring 522. The protruding portion 932 is continuous with one end of the covering 931 and is disposed outside the sealing body 30. The protruding portion 932 is a portion of the O terminal 93 that protrudes from the side surface 30c to the outside of the sealing body 30. The protruding portion 932 includes a bent portion 933. The illustrated O terminal 93 is substantially L-shaped in a plan view from the X direction. The portion from the connection portion of the covering 931 with the relay wiring 522 to the bent portion 933 extends generally in the Y direction. The portion from the bent portion 933 to the protruding tip extends generally in the Z direction, the same direction as the P terminal 91 and the N terminal 92.

[0062] The P terminal 91, the N terminal 92, and the O terminal 93 are aligned in the X direction. They are arranged in this order in the X direction: P terminal 91, N terminal 92, O terminal 93. The length from the side surface 30c to the bent portion 913 and the length from the side surface 30c to the bent portion 923 are approximately equal. The length from the side surface 30c to the bent portion 933 is longer than the lengths from the side surface 30c to the bent portions 913 and 923. The length from the bent portion 913 to the protruding tip of the P terminal 91, the length from the bent portion 923 to the protruding tip of the N terminal 92, and the length from the bent portion 933 to the protruding tip of the O terminal 93 are approximately equal to one another. The lengths of the protruding portions 912 and 922 are approximately equal to one another. The side surface of the protruding portion 912 and the side surface of the protruding portion 922 face each other over almost their entire lengths. A portion of the side surface of the protruding portion 932 faces the side surface of the protruding portion 922.

[0063] The bent portions 913, 923, and 933 have a predetermined bending angle. The predetermined bending angle is, for example, about 90 degrees. An example bending angle is set within a range of, for example, 90 degrees to 100 degrees.

[0064] The signal terminals 94 are electrically connected to the pads 43 of the corresponding semiconductor elements 40. The signal terminals 94 include a signal terminal connected to the pads 43 of the semiconductor element 40H and a signal terminal connected to the pads 43 of the semiconductor element 40L. The illustrated signal terminals 94 are connected to the corresponding pads 43 via bonding wires 100. The signal terminals 94 extend generally in the Y direction in a plan view. A portion of the signal terminals 94, including the connection portion with the pads 43, is covered by the encapsulant 30, and the remaining portion protrudes from the encapsulant 30. The signal terminals 94 protrude from the center of the side surface 30d in the Z direction to the outside of the encapsulant 30.

[0065] The external connection terminals 90 are provided as, for example, part of a lead frame. During the manufacturing process of the semiconductor device 20, unnecessary parts of the lead frame, such as tie bars, are removed. The semiconductor device 20 includes suspension leads 95. Before the unnecessary parts are removed, the suspension leads 95 hold the signal terminals 94 in place via the tie bars. One of the suspension leads 95 is connected to the P wiring 521, and the other is connected to the relay wiring 522. The suspension leads 95 extend generally in the Y direction in a plan view. The two suspension leads 95 are arranged in the X direction to sandwich the signal terminal 94 corresponding to the semiconductor element 40H and the signal terminal 94 corresponding to the semiconductor element 40L. A portion of the suspension lead 95, including the connection portion with the front surface metal body 52, is covered by the sealing body 30, and the remaining portion protrudes from the side surface 30d of the sealing body 30.

[0066] The semiconductor device 20 includes a bonding material 101. The bonding material 101 may be a solder or a sintered material. The drain electrode 41 of the semiconductor element 40 is connected to the surface metal body 52 via the bonding material 101. The source electrode 42 of the semiconductor element 40 is connected to the conductive spacer 70 via the bonding material 101. The conductive spacer 70 is connected to the surface metal body 62 via the bonding material 101. The joint portion 80 is connected to the surface metal bodies 52, 62 via the bonding material 101. The multiple bonding materials 101 may be made of a common material, or the material of some of the bonding materials 101 may be different from the material of the other bonding materials 101.

[0067] The P terminal 91, the N terminal 92, the O terminal 93, and the suspension lead 95 may be connected to the corresponding surface metal bodies 52, 62 by the above-mentioned bonding material 101. The P terminal 91, the N terminal 92, the O terminal 93, and the suspension lead 95 may be solid-state bonded to the corresponding surface metal bodies 52, 62. Examples of solid-state bonding include ultrasonic bonding, room-temperature bonding, friction stir bonding, diffusion bonding, and friction welding.

[0068] As described above, in the semiconductor device 20, the sealing body 30 seals the multiple semiconductor elements 40 that constitute one phase of the upper and lower arm circuits 9. The sealing body 30 integrally seals the multiple semiconductor elements 40, a portion of the substrate 50, a portion of the substrate 60, the multiple conductive spacers 70, the joint portion 80, and a portion of the external connection terminals 90. The sealing body 30 seals the insulating base materials 51, 61 and the surface metal bodies 52, 62 of the substrates 50, 60.

[0069] The semiconductor element 40 is disposed between the substrates 50 and 60 in the Z direction. The semiconductor element 40 is sandwiched between the substrates 50 and 60, which are disposed opposite each other. This allows heat from the semiconductor element 40 to be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The exposed surface 53a of the back surface metal body 53 is substantially flush with one surface 30a of the sealing body 30. The exposed surface 63a of the back surface metal body 63 is substantially flush with the back surface 30b of the sealing body 30. The exposed surfaces 53a and 63a can improve heat dissipation.

[0070] <Power conversion module> Fig. 8 is a cross-sectional view showing an example of a power conversion module. Fig. 8 shows a part of the power conversion module. Fig. 8 corresponds to Fig. 4.

[0071] The power conversion module 110 includes the semiconductor device 20 and a cooler 111. The cooler 111 is formed using a metal material such as Al or Cu. The cooler 111 may have a channel through which a refrigerant flows. The cooler 111 may be a heat dissipation member such as a heat sink. A heat sink may also be called a heat sink or a cooling plate. The heat dissipation member may include heat dissipation fins. A bonding material such as solder or sintered Ag may be interposed between the exposed surfaces 53a, 63a of the back metal bodies 53, 63 and the cooler 111. A thermally conductive member such as a TIM may be interposed between the exposed surfaces 53a, 63a and the cooler 111. TIM is an abbreviation for Thermal Interface Material. The cooler 111 may be part of a housing that houses the semiconductor device 20, or may be provided separately from the housing. The exposed surfaces 53a, 63a are thermally connected to the cooler 111.

[0072] Although not shown, the power conversion module 110 includes three semiconductor devices 20 that constitute the inverter 5. The power conversion module 110 may have a structure in which the semiconductor devices 20 and the coolers 111 are alternately stacked in the Y direction. The power conversion module 110 may also have a structure in which three semiconductor devices 20 are arranged side by side between a pair of coolers 111.

[0073] <Plating film and bent parts> Fig. 9 is an enlarged cross-sectional view of the periphery of a main terminal having a bent portion, showing a P terminal as an example.

[0074] The P terminal 91 includes a base material 901 and a plating film 902. The base material 901 is made of a metal with good conductivity, such as Cu or a Cu alloy. The plating film 902 covers the surface of the base material 901. The plating film 902 may be formed by electrolytic plating or by electroless plating. An example of the plating film 902 includes a NiP film formed by electroless plating. The plating film 902 may also include an Au film formed on the NiP film.

[0075] The P terminal 91 has a plated region 903 where a plating film 902 is provided on the surface of a base material 901, and a non-plated region 904 where the plating film 902 is not provided on the surface of the base material 901. The non-plated region 904 includes at least a portion of the surface of a bent portion 913. The P terminal 91 has plate surfaces 905 and 906 and side surfaces. The plate surface 906 is the surface opposite the plate surface 905 in the plate thickness direction.

[0076] The illustrated non-plated region 904 includes the entire surface of the plate 905, 906 at the bent portion 913. The non-plated region 904 also includes the portion (peripheral portion) of the plate surfaces 905, 906 adjacent to the bent portion 913. The non-plated region 904 is a removal region formed by intentionally removing a formed plating film. As will be described later, the non-plated region 904 is formed by partially removing the plating film by laser irradiation. The P terminal 91 has a laser mark 961 which is a removal mark 96 of the plating film. The laser mark 961 is a unique mark caused by laser irradiation. The P terminal 91 has the laser mark 961 on the plate surfaces 905, 906 including the bent portion 913.

[0077] Although not shown, the N terminal 92 and O terminal 93 also have a structure similar to that of the P terminal 91. The N terminal 92 and O terminal 93 also have a plated region 903 and a non-plated region 904. The non-plated region 904 includes at least a portion of the surface of each of the bent portions 923 and 933. The illustrated non-plated region 904 includes the entire plate surfaces 905 and 906 of the bent portions 923 and 933. The non-plated region 904 also includes portions of the plate surfaces 905 and 906 adjacent to the bent portions 923 and 933. The N terminal 92 and O terminal 93 each have a laser mark 961.

[0078] <Manufacturing method> 10 is a flowchart showing an example of a method for manufacturing a semiconductor device. FIG. 10 shows part of the manufacturing process of a semiconductor device.

[0079] The semiconductor device 20 described above is manufactured by including the steps shown in FIG. 10. In the plating step (step S10), the external connection terminals 90 are plated to form plating films 902 on the surfaces of the external connection terminals 90 (base material 901). The plating may be electrolytic plating or electroless plating. The plating may be performed before connecting (bonding) the external connection terminals 90 to the substrate 50, or after connecting the external connection terminals 90 to the substrate 50. As an example, a NiP film is formed by electroless plating, and then an Au film is formed. Alternatively, plating is performed before connecting the external connection terminals 90 to the substrate 50.

[0080] In the connection process (step S20), the plated external connection terminals 90 are electrically connected to the semiconductor element 40. By mounting the semiconductor element 40 on the substrate 50, a plating film 902 is formed, electrically connecting the external connection terminals 90 connected to the substrates 50, 60 to the semiconductor element 40. When the P terminal 91 and the O terminal 93 are connected using the bonding material 101, they may be connected to the substrate 50 in the same process as the semiconductor element 40. The P terminal 91 and the O terminal 93 may also be connected to the substrate 50 at different times.

[0081] In the sealing process (step S30), sealing body 30 is formed to seal external connection terminals 90 and semiconductor element 40. As an example, sealing body 30 is formed by transfer molding.

[0082] In the partial removal process (step S40), the plating film 902 is partially removed before the bending process. The partial removal process may be performed after the plating process and before the bending process. For example, it may be performed after the sealing process, or after the connecting process and before the sealing process. As an example, it is performed after the sealing process. Figure 11 shows the state before the partial removal, i.e., after the sealing process. For convenience, the elements covered by the sealer 30 are omitted.

[0083] In the partial removal process, as shown in FIG. 12, a laser is irradiated onto plate surfaces 905 and 906 to partially remove plating film 902. FIG. 12 illustrates partial removal by laser irradiation. For convenience, elements covered by sealing body 30 are omitted. The hollow arrow indicates the laser. Specifically, a pulsed laser is scanned in a predetermined direction (e.g., the X direction) to remove plating film 902 from plate surfaces 905 and 906 in the portions corresponding to bent portions 913, 923, and 933, i.e., portions to be bent 913a, 923a, and 933a. As a result, plating film 902 is removed from portions to be bent 913a, 923a, and 933a, as shown in FIG. 13. FIG. 13 is a plan view illustrating the state after partial removal and before bending.

[0084] When the plating film 902 is partially removed by irradiating it with a laser, laser marks 961 remain as removal marks 96 in the portions of the plate surfaces 905 and 906 where the plating film 902 has been removed. The laser also affects the surface of the base material 901 in the portions where the plating film 902 has been removed, leaving the laser marks 961. The laser marks 961 are, for example, depressions on the plate surfaces 905 and 906 in the portions where the plating film 902 remains. As shown in FIG. 14, these depressions have a shape in which depressions for each pulse are connected in the scanning direction. FIG. 14 shows the laser marks 961. The laser marks 961 may be traces of melting or changes in color instead of or in addition to depressions.

[0085] In the bending step (step S50), bent portions 913, 923, and 933 are formed in the external connection terminals 90 by bending. At this time, the portions to be bent 913a, 923a, and 933a from which the plating film 902 has been removed are bent. In the case of a lead frame, bending is performed after unnecessary portions such as tie bars are removed. Through the bending step, a semiconductor device 20 having bent portions 913, 923, and 933 can be obtained. In the semiconductor device 20, laser marks 961 remain to a considerable extent on the plate surfaces 905 and 906 of the bent portions 913, 923, and 933.

[0086] <Summary of the First Embodiment> The semiconductor device 20 of this embodiment includes a semiconductor element 40, a sealing body 30, and an external connection terminal 90, which is a main terminal. The external connection terminal 90 has a plated region 903 and a non-plated region 904. The protruding portions 912, 922, and 932 of the external connection terminal 90 include bent portions 913, 923, and 933. The non-plated region 904 includes at least a portion of the surfaces of the bent portions 913, 923, and 933.

[0087] In this way, the plating film 902 is not provided on at least a portion of the surfaces of the bent portions 913, 923, and 933. This makes it possible to suppress, for example, peeling of the plating film 902 when forming the bent portions 913, 923, and 933 by bending. This therefore makes it possible to suppress the occurrence of insulation defects. For example, it is possible to suppress the adhesion of metal foreign matter caused by peeling of the plating film to the side surface of the sealing body 30. This makes it possible to ensure a creepage insulation distance between adjacent external connection terminals 90.

[0088] As illustrated, the non-plated region 904 may include plate surfaces 905 and 906 of the external connection terminals 90 at the bent portions 913, 923, and 933. Since the plated film 902 is not provided on the plate surfaces 905 and 906 of the bent portions 913, 923, and 933, peeling of the plated film 902 during the formation of the bent portions 913, 923, and 933 can be suppressed.

[0089] The non-plated region 904 may be a region where the plating film 902 is not formed by partial plating. As illustrated, the non-plated region 904 may be a removed region where the plating film 902 has been removed. In the case of a removed region, the external connection terminal 90 may have laser marks 961 which are marks left by removing the plating film 902. The laser marks 961 are marks left by laser irradiation. By using laser irradiation, the non-plated region 904 (removed region) can be provided at a predetermined position with high precision in a short time.

[0090] As illustrated, before forming the bent portions 913, 923, and 933, at least a portion of the plating film 902 at the portions to be bent 913a, 923a, and 933a in the external connection terminal 90 may be removed. The portions to be bent 913a, 923a, and 933a correspond to the bent portions. According to this manufacturing method, the plating film 902 at the portions to be bent 913a, 923a, and 933a is removed, and then bending is performed to form the bent portions 913, 923, and 933. This makes it possible to prevent peeling of the plating film 902 from occurring during bending.

[0091] As illustrated, the plating film 902 may be removed by irradiating the portions to be bent 913a, 923a, and 933a of the plate surfaces 905 and 906 with a laser. The plating film 902 can be removed with good positional accuracy in a short time.

[0092] (Second embodiment) This embodiment is a modification based on the previous embodiment, and the description of the previous embodiment can be used. In the previous embodiment, the non-plated area is formed by laser irradiation. Alternatively, or in addition, the non-plated area may be formed by tie bar cutting.

[0093] <Manufacturing method> 15 is a flowchart showing an example of a manufacturing method, which illustrates part of the manufacturing process of a semiconductor device.

[0094] The plating step (step S110) is the same as step S10 shown in FIG. 10. The connection step (step S120) is the same as step S20. The sealing step (step S130) is the same as step S30. In this embodiment, a lead frame 97 is used as shown in FIG. 16. In step S110, plating is applied to the lead frame 97. FIG. 16 shows the state after the sealing step, i.e., before partial removal. In FIG. 16, the protruding portions of the P terminal 91, the N terminal 92, and the O terminal 93 are indicated by dashed lines. Furthermore, portions to be bent 913a, 923a, and 933a are indicated by dashed lines.

[0095] The lead frame 97 has an outer periphery frame 971 and tie bars 972, 973, and 974 in addition to the external connection terminals 90 and the suspension leads 95. The outer periphery frame 971 has a substantially rectangular frame shape. The external connection terminals 90 and the suspension leads 95 are supported by the outer periphery frame 971 via the tie bars 972, 973, and 974. The tie bars 972, 973, and 974 extend substantially in the X direction. Both ends of each of the tie bars 972, 973, and 974 are connected to the outer periphery frame 971.

[0096] The tie bar 972 is connected to the portion to be bent 913a of the P terminal 91, the portion to be bent 923a of the N terminal 92, and the O terminal 93. The tie bar 972 is connected to a portion of the O terminal 93 that is at approximately the same distance from the sealing body 30 as the portions to be bent 913a and 923a. The tie bar 972 is connected to the O terminal 93 at a position closer to the sealing body 30 than the portion to be bent 933a.

[0097] The tie bar 973 is provided at a position farther from the sealing body 30 in the Y direction than the tie bar 972. The tie bar 973 is connected to the portion to be bent 933a of the O terminal 93, an extension portion 975 extending from the P terminal 91, and an extension portion 976 extending from the N terminal 92. The extension portion 975 is connected to the P terminal 91. The extension portion 975 extends in the Y direction from the tip of the P terminal 91. The extension portion 976 is connected to the N terminal 92. The extension portion 976 extends in the Y direction from the tip of the N terminal 92.

[0098] The tie bar 974 is connected to the signal terminals 94 and the suspension leads 95. The tie bar 974 is arranged on the opposite side of the sealing body 30 to the tie bars 972 and 973. The suspension leads 95 are located between the signal terminals 94 and the outer peripheral frame 971.

[0099] In the partial removal process (step S140), plating film 902 is partially removed by tie bar cutting before the bending process. The partial removal process is performed after the sealing process. By cutting the tie bars, base material 901 is exposed at the cut surface. In the partial removal process, unnecessary portions of lead frame 97, including tie bars 972, 973, and 974, are removed. Figure 17 shows the state after partial removal by tie bar cutting.

[0100] When the plating film 902 on the side surface is partially removed by cutting the tie bar, a tie bar mark 962 remains as a removal mark 96 in the portion where the plating film 902 was removed. The tie bar mark 962 is at least one of a convex portion, a concave portion, and a fractured surface. A convex portion is a protrusion on the side surface of the base material that is formed by cutting while leaving a portion of the tie bar. A concave portion is a depression on the side surface of the base material that is formed by cutting so that the tie bar bites into the external connection terminal side. A fractured surface is a cut surface. The tie bar mark 962 illustrated in FIG. 17 is a convex portion of the remaining tie bar.

[0101] The bending step (step S150) is the same as step S50. Through the bending step, a semiconductor device 20 having bent portions 913, 923, and 933 can be obtained. The other configurations are the same as those described in the preceding embodiment.

[0102] <Bent section and removal marks> Fig. 18 is a side view of the semiconductor device as seen from the X1 direction shown in Fig. 17. Fig. 18 shows the periphery of the P terminal after bending.

[0103] The semiconductor device 20 obtained by the above-described manufacturing method has tie bar marks 962 in the bent portions 913, 923, and 933. As described above, the tie bar marks 962 are at least one of a convex portion, a concave portion, and a fracture surface. The tie bar marks 962 illustrated in FIG. 18 are convex portions. The side surfaces 907 of the bent portion 913 protrude relative to the side surfaces 907 around the bent portion. The base material 901 is exposed at the side surfaces 907 of the bent portion 913. The non-plated region 904 includes the side surfaces 907 of the bent portion 913. The plate surfaces 905 and 906 of the bent portion 913 are covered with a plating film 902. The same applies to the bent portions 923 and 933. The other configurations are the same as those described in the preceding embodiment.

[0104] <Summary of the second embodiment> As illustrated, the non-plated region 904 may include side surfaces 907 of the bent portions 913, 923, and 933. Since the plating film 902 is not provided on the side surfaces 907 of the bent portions 913, 923, and 933, peeling of the plating film 902 during the formation of the bent portions 913, 923, and 933 can be suppressed.

[0105] As illustrated, the non-plated region 904 is the removal region, and the external connection terminal 90 may have tie bar marks 962, which are marks left by removing the plating film 902. The tie bar marks 962 are marks left by cutting the tie bars. By cutting the tie bars, the base material 901 is exposed. In other words, the plating film 902 on the side surface 907 is removed. In a configuration using a lead frame 97, it is possible to prevent poor insulation without increasing the number of processes.

[0106] As shown in the example, a lead frame 97 having tie bars 972, 973 connected to the portions to be bent 913a, 923a, and 933a may be prepared, a plating film 902 may be formed, and the tie bars 972, 973 may be cut before bending. By intentionally providing the tie bars 972, 973 at positions connected to the portions to be bent 913a, 923a, and 933a, the plating film 902 on the side surface 907 can be removed by cutting the tie bars. This makes it possible to prevent the plating film 902 from peeling off during bending.

[0107] As shown in the example, the lengths from the side surface of the sealing body 30 to the bent portion may be different between adjacent external connection terminals 90. In the example semiconductor device 20, the N terminal 92 corresponds to the first terminal, and the O terminal 93 corresponds to the second terminal. The length from the side surface 30c to the bent portion 923 in the N terminal 92 is different from the length from the side surface 30c to the bent portion 933 in the O terminal 93.

[0108] The N terminal 92, which is a power terminal, and the O terminal 93, which is an output terminal, are connected to different objects. Therefore, the positions of the bending portions 923 and 933 are different in the Y direction. As described above, by intentionally locating the tie bars 972 and 973 in positions that are continuous with the intended bending portions 913a, 923a, and 933a, the plating film 902 on the side surface 907 can be removed by cutting the tie bars. This makes it possible to prevent poor insulation.

[0109] <Modification> The configuration shown in this embodiment may be combined with the configuration shown in the preceding embodiment. That is, the removal marks 96 may include both the laser marks 961 and the tie bar marks 962.

[0110] Note that the configuration using the lead frame 97 in the preceding embodiment is not limited to the configuration having the tie bar marks 962 at the bending portions 913, 923, and 933. For example, the tie bars may be provided so as to be connected to positions different from the portions to be bent 913a, 923a, and 933a, and the non-plated regions 904 may be provided only on the plate surfaces 905 and 906 by laser irradiation.

[0111] 19, a through hole 981 may be provided in a lead frame 97. The through hole 981 is provided at the boundary between the portions to be bent 913a, 923a, 933a and the corresponding tie bars 972, 973. The tie bars 972, 973 are cut so that the end of a cutting punch is positioned at the boundary.

[0112] FIG. 20 shows a power conversion module 110 formed by stacking semiconductor devices 20, each having a through-hole 981 formed in a lead frame 97. For convenience, the portion covered by the sealing body 30 is omitted. The power conversion module 110 includes three semiconductor devices 20 to form a three-phase upper and lower arm circuit 9. The semiconductor devices 20 and the coolers 111 are alternately arranged so that the coolers 111 are located on both sides of the semiconductor device 20 in the Z direction. The semiconductor device 20 has a recess 982 resulting from the through-hole 981 on the side surface 907 of the bent portion 913. The burr 983 generated by cutting the tie bar is short because it is bisected by the through-hole 981. This ensures a sufficient spatial insulation distance between adjacent P terminals 91 in the stacking direction. The same applies to the N terminal 92 and the O terminal 93, although not shown.

[0113] 21 , the P terminal 91, the N terminal 92, and the O terminal 93 may be provided with recesses 984 adjacent to the connecting portions (boundaries) with the tie bars 972, 973. Four recesses 984 are provided for each of the P terminal 91, the N terminal 92, and the O terminal 93. The recesses 984 are provided on both ends in the width direction of each of the P terminal 91, the N terminal 92, and the O terminal 93. The recesses 984 are provided at positions adjacent to the connecting portions with the corresponding tie bars 972, 973 of each of the P terminal 91, the N terminal 92, and the O terminal 93.

[0114] The dashed line in Fig. 21 indicates the punch 105. Providing the recess 984 can prevent the punch 105 from coming into contact with portions of the external connection terminal 90 other than the cutting portion. Interference between the external connection terminal 90 and the punch 105 can be avoided, thereby preventing burrs from being generated due to interference. This can prevent poor insulation from occurring.

[0115] (Third embodiment) This embodiment is a modification based on the previous embodiment, and the description of the previous embodiment can be used. In the previous embodiment, the non-plated region 904 was formed by removing the plating film 902. Alternatively, the plating film may be formed partially.

[0116] Fig. 22 is a flowchart showing an example of a manufacturing method, which illustrates part of the manufacturing process of a semiconductor device.

[0117] The partial plating step (step S210) corresponds to steps S10 and S110 described in the preceding embodiment. In this embodiment, partial plating is performed by masking or the like so that the plating film 902 is formed on a portion of the surface of a single external connection terminal 90 and is not formed on other portions. As an example, partial plating is performed so that the plating film 902 is not formed on the surfaces of the portions to be bent 913a, 923a, and 933a, and the plating film 902 is formed on other portions.

[0118] The connecting step (step S220) is the same as steps S20 and S120 described in the preceding embodiment. The sealing step (step S230) is the same as steps S30 and S130 described in the preceding embodiment. The bending step (step S240) is the same as steps S50 and S150 described in the preceding embodiment. As such, a removing step is not provided. The other configurations are the same as those described in the preceding embodiment. The semiconductor device 20 obtained by the above-described manufacturing method has a plated region 903 and a non-plated region 904. The non-plated region 904 is a region on whose surface a plating film 902 is not formed in the plating step. The non-plated region 904 includes the surfaces of the bent portions 913, 923, and 933. It includes at least one of the plate surfaces 905 and 906 and the side surface 907.

[0119] <Summary of the third embodiment> As shown in the example, when forming the plating film 902, partial plating may be performed so that the plating film 902 is not formed on at least a portion of the portions to be bent 913a, 923a, and 933a. Because the plating film 902 is not formed on the surfaces of the portions to be bent 913a, 923a, and 933a, peeling of the plating film 902 during bending can be prevented. Therefore, insulation defects can be prevented.

[0120] (Other embodiments) The disclosure in this specification and drawings, etc. is not limited to the exemplified embodiments. The disclosure encompasses the exemplified embodiments and modifications thereto by those skilled in the art. For example, the disclosure is not limited to the combinations of parts and / or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure encompasses the omission of parts and / or elements from the embodiments. The disclosure encompasses the substitution or combination of parts and / or elements between one embodiment and another embodiment. The disclosed technical scope is not limited to the description of the embodiments. Some disclosed technical scopes are defined by the claims, and should be interpreted as including all modifications within the meaning and scope equivalent to the claims.

[0121] The disclosure in the specification, drawings, etc. is not limited by the claims. The disclosure in the specification, drawings, etc. encompasses the technical ideas described in the claims, and extends to more diverse and broader technical ideas than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification, drawings, etc. without being bound by the claims.

[0122] When an element or layer is referred to as being "on," "coupled," "connected," or "bonded," it may be directly on, coupled, connected, or bonded to another element or layer, and intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly coupled," "directly connected," or "directly bonded" to another element or layer, no intervening elements or layers are present. Other terms used to describe relationships between elements should be construed in a similar manner (e.g., "between" vs. "directly between," "adjacent" vs. "directly adjacent," etc.). As used in this specification, the term "and / or" includes any and all combinations of one or more of the associated listed items. That is, reference to A and / or B means at least one of A and B.

[0123] Spatially relative terms such as "inside," "outside," "back," "below," "low," "top," "top," and the like are used herein to facilitate the description of one element or feature's relationship to other elements or features, as illustrated. Spatially relative terms may be intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures were turned over, elements described as "below" or "directly below" other elements or features would then be oriented "above" the other elements or features. Thus, the term "bottom" can encompass both an orientation of top and bottom. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in this specification would be interpreted accordingly.

[0124] Although an example has been shown in which the semiconductor device 20 includes two substrates 50 and 60, the present invention is not limited to this. The semiconductor device 20 may include only the substrate 50. Instead of the substrate 60, a metal plate clip, a wiring member such as a bonding wire, etc. may be used. This is also applicable to a semiconductor device 20 with a single-sided heat dissipation structure. As described above, a heat sink (metal plate) may be used instead of the substrates 50 and 60.

[0125] Although an example of a 2-in-1 package that provides upper and lower arm circuits 9 for one phase has been shown as the semiconductor device 20, the semiconductor device 20 is not limited to this. For example, the semiconductor device 20 may be a 1-in-1 package that provides one arm, or a 6-in-1 package.

[0126] (Disclosure of technical ideas) This specification discloses multiple technical ideas described in the following multiple clauses. Some clauses may be written in a multiple dependent form, with the subsequent clause referring to the preceding clause as an alternative. Furthermore, some clauses may be written in a multiple dependent form, referring to another multiple dependent clause. These multiple dependent clauses define multiple technical ideas.

[0127] <Technical philosophy 1> A semiconductor element (40); a sealing body (30) that seals the semiconductor element; an external connection terminal (90) including a portion electrically connected to the semiconductor element and having a covering portion (911, 921, 931) covered by the sealing body and a protruding portion (912, 922, 932) protruding outside the sealing body; Equipped with The external connection terminal has a plated region (903) on the surface of which a plated film (902) is provided, and a non-plated region (904) on which the plated film is not provided, The protrusion includes a bent portion (913, 923, 933), The non-plated region includes at least a portion of the surface of the bent portion.

[0128] <Technical philosophy 2> The semiconductor device according to Technical Idea 1, wherein the non-plated area includes a plate surface of the external connection terminal in the bent portion.

[0129] <Technical philosophy 3> The semiconductor device according to Technical Idea 1 or 2, wherein the non-plated region includes a side surface of the external connection terminal at the bent portion.

[0130] <Technical philosophy 4> the non-plated region is a removal region where the plating film has been removed, The semiconductor device according to Technical Concept 2, wherein the external connection terminal has a laser mark (961) that is a mark left by removing the plating film.

[0131] <Technical philosophy 5> the non-plated region is a removal region where the plating film has been removed, The semiconductor device according to Technical Concept 3, wherein the external connection terminal has a tie bar mark (962) that is a mark left by removing the plating film.

[0132] <Technical philosophy 6> the external connection terminal includes a first terminal (92) and a second terminal (93) arranged alongside the first terminal in a predetermined direction; The semiconductor device according to any one of Technical Ideas 1 to 5, wherein the lengths from the surface of the sealing body from which the first terminal and the second terminal protrude to the bent portion are different between the first terminal and the second terminal. [Explanation of symbols]

[0133] 1... drive system, 2... DC power supply, 3... motor generator, 3a... winding, 4... power conversion circuit, 5... smoothing capacitor, 6... inverter, 7... P line, 8... N line, 9... upper and lower arm circuits, 9H... upper arm, 9L... lower arm, 10... output line, 11... MOSFET, 12... diode, 20... semiconductor device, 30... sealing body, 30a... one side, 30b... back side, 30c, 30d, 30e, 30f... side , 31... recess, 32... gate trace, 40, 40H, 40L... semiconductor element, 41... drain electrode, 42... source electrode, 43... pad, 50, 60... substrate, 51, 61... insulating base material, 52, 62... surface metal body, 52a, 62a... exposed surface, 521... P wiring, 621... N wiring, 522, 622... relay wiring, 53, 63... back metal body, 53a, 63a... exposed surface, 70... conductive spacer, 80... joint portion, 90... external connection Connection terminal, 901...base material, 902...plated film, 903...plated area, 904...non-plated area, 905, 906...plate surface, 907...side surface, 91...P terminal, 911...coating portion, 912...protruding portion, 913...bending portion, 913a...portion to be bent, 92...N terminal, 921...coating portion, 922...protruding portion, 923...bending portion, 923a...portion to be bent, 93...O terminal, 931...coating portion, 932...protruding portion, 933...bending portion, 933a ...portion to be bent, 94...signal terminal, 95...hanging lead, 96...removal mark, 961...laser mark, 962...tie bar mark, 97...lead frame, 971...peripheral frame, 972, 973, 974...tie bar, 975, 976...extension portion, 981...through hole, 982, 984...recess, 983...burr, 100...bonding wire, 101...bonding material, 110...power conversion module, 111...cooler, 115...punch

Claims

1. A semiconductor element (40); an encapsulant (30) that encapsulates the semiconductor element; an external connection terminal (90) including a portion electrically connected to the semiconductor element and having a covering portion (911, 921, 931) covered by the sealing body and a protruding portion (912, 922, 932) protruding outside the sealing body; Equipped with The external connection terminal has a plated region (903) on the surface of which a plated film (902) is provided, and a non-plated region (904) on which the plated film is not provided, The protrusion includes a bent portion (913, 923, 933), The non-plated region includes at least a portion of the surface of the bent portion.

2. 2. The semiconductor device according to claim 1, wherein said non-plated region includes a surface of said external connection terminal at said bent portion.

3. 3. The semiconductor device according to claim 1, wherein the non-plated region includes a side surface of the external connection terminal at the bent portion.

4. the non-plated region is a removal region where the plating film has been removed, 3. The semiconductor device according to claim 2, wherein the external connection terminal has a laser mark (961) which is a mark resulting from removal of the plating film.

5. the non-plated region is a removal region where the plating film has been removed, 4. The semiconductor device according to claim 3, wherein said external connection terminals have tie bar marks (962) which are marks formed by removing said plating film.

6. The external connection terminal includes a first terminal (92) and a second terminal (93) arranged alongside the first terminal in a predetermined direction, 6. The semiconductor device according to claim 5, wherein the lengths from the surface of the sealing body from which the first terminal and the second terminal protrude to the bent portion are different between the first terminal and the second terminal.

7. Plating is performed to form a plating film (902) on the surface of the external connection terminal (90); electrically connecting the external connection terminal on which the plating film is formed to a semiconductor element (40); forming a sealing body (30) that seals the external connection terminals and the semiconductor element; a bending process is performed on a portion of the external connection terminal that protrudes from the sealing body to form a bent portion (913, 923, 933); A method for manufacturing a semiconductor device, comprising removing at least a part of the plating film from a portion of the external connection terminal that corresponds to the bent portion before forming the bent portion.

8. 8. The method for manufacturing a semiconductor device according to claim 7, further comprising the step of irradiating a portion of the plate surface (905, 906) of the external connection terminal corresponding to the bent portion with a laser to remove the plating film before forming the bent portion.

9. a lead frame (97) provided with tie bars (972, 973) connected to the portions corresponding to the bent portions; and forming the plating film on the surface of the lead frame including the external connection terminals; 9. The method for manufacturing a semiconductor device according to claim 7, wherein the tie bar is cut before forming the bent portion, thereby removing the plating film from the side surface (907) of the external connection terminal in a portion corresponding to the bent portion.

10. Plating is performed to form a plating film (902) on the surface of the external connection terminal (90); electrically connecting the external connection terminal on which the plating film is formed to a semiconductor element (40); forming a sealing body (30) that seals the external connection terminals and the semiconductor element; a bending process is performed on a portion of the external connection terminal that protrudes from the sealing body to form a bent portion (913, 923, 933); When forming the plating film, partial plating is performed so that the plating film is not formed on at least a part of the portion of the external connection terminal that corresponds to the bent portion.

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