Memory system

Abstract

To provide a memory system capable of improving the reliability of a memory.SOLUTION: A memory system 1 which can be connected to a host comprises a first nonvolatile memory 100 and a controller 200. The first nonvolatile memory includes a plurality of blocks BLK which are units of erasing operation respectively. The controller is electrically connected to the first nonvolatile memory to control the first nonvolatile memory, receives first data from the host 300, and performs randomization processing on the first data using second data differing according to the number of times of erasing operation performed on a first block, which is one of the plurality of blocks so as to generate third data from the first data. The controller writes the third data to the first block.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to a memory system. [Background technology]

[0002] 2. Description of the Related Art A memory system is known that includes a nonvolatile memory such as a NAND flash memory and a memory controller that controls the nonvolatile memory. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6499065 [Patent Document 2] Patent Publication No. 2021-189912 [Patent Document 3] U.S. Patent Application Publication No. 2020 / 0410102 [Patent Document 4] US Patent Application Publication No. 2004 / 0034785 [Patent Document 5] US Patent Application Publication No. 2022 / 0107797 Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment provides a memory system that can improve memory reliability. [Means for solving the problem]

[0005] According to one embodiment, a memory system is connectable to a host. The memory system includes a first nonvolatile memory and a controller. The first nonvolatile memory includes a plurality of blocks, each of which is a unit of an erase operation. The controller is electrically connected to the first nonvolatile memory and controls the first nonvolatile memory. The controller receives first data from the host. The controller generates third data from the first data by randomizing the first data using second data that varies depending on the number of erase operations performed on a first block, which is one of the plurality of blocks. The controller writes the third data to the first block. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 shows the configuration of a memory system according to the first embodiment. [Figure 2] FIG. 2 shows the circuit configuration of the block according to the first embodiment. [Figure 3] FIG. 3 shows a schematic configuration of data stored in a block according to the first embodiment. [Figure 4] FIG. 4 shows the internal configuration of the firmware block according to the first embodiment. [Figure 5] FIG. 5 shows a detailed configuration of the randomization circuit according to the first embodiment. [Figure 6] FIG. 6 shows an example of data processing for firmware update processing by the memory controller according to the first embodiment. [Figure 7] FIG. 7 shows an overview of the firmware update process according to the first embodiment. [Figure 8] FIG. 8 shows a flow of firmware update processing according to the first embodiment. [Figure 9] FIG. 9 shows the flow of firmware restoration processing according to the first embodiment. [Figure 10] FIG. 10 shows an overview of the header information change process according to the modified example of the first embodiment. [Figure 11]FIG. 11 shows the internal configuration of a firmware block according to the second embodiment. [Figure 12] FIG. 12 shows an overview of the process of reading header information, changing header information, and setting a seed value according to the second embodiment. [Figure 13] FIG. 13 shows a flow of firmware update processing according to the second embodiment. [Figure 14] FIG. 14 shows a flow of firmware restoration processing according to the second embodiment. [Figure 15] FIG. 15 shows the internal configuration of a firmware block according to the third embodiment. [Figure 16] FIG. 16 shows the configuration of a memory controller according to the third embodiment. [Figure 17] FIG. 17 shows an overview of the header information changing process and the seed value setting process according to the third embodiment. [Figure 18] FIG. 18 shows the flow of firmware update processing according to the third embodiment. [Figure 19] FIG. 19 shows the flow of firmware restoration processing according to the third embodiment. [Figure 20] FIG. 20 shows the internal configuration of a firmware block according to the fourth embodiment. [Figure 21] FIG. 21 shows an overview of the header information changing process and the seed value setting process according to the fourth embodiment. [Figure 22] FIG. 22 shows the flow of firmware update processing according to the fourth embodiment. [Figure 23] FIG. 23 shows a flow of firmware restoration processing according to the fourth embodiment. [Figure 24] FIG. 24 shows a schematic configuration of data stored in a block according to the fifth embodiment. [Figure 25] FIG. 25 shows the internal structure of a firmware block according to the fifth embodiment. [Figure 26] FIG. 26 shows an overview of the firmware update process according to the fifth embodiment. [Figure 27]FIG. 27 shows the flow of firmware update processing according to the fifth embodiment. [Figure 28] FIG. 28 shows an overview of the header information writing process according to the sixth embodiment. [Figure 29] FIG. 29 shows a flow of header information writing processing according to the sixth embodiment. [Figure 30] FIG. 30 shows a flow of a header information read process according to the sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having substantially the same functions and configurations are designated by the same reference numerals, and repeated explanations may be omitted. All descriptions of one embodiment also apply to descriptions of other embodiments, unless explicitly or obviously excluded.

[0008] It should be noted that the size of figures in the drawings or the size relationship of figures does not indicate the size or size relationship of the configurations and data that those figures represent.

[0009] Each functional block can be realized as either hardware or computer software, or a combination of both. Therefore, to make it clear that each functional block can be either of these, it will be generally described in terms of its function. Furthermore, it is not necessary for each functional block to be distinguished as in the following example. For example, some functions may be performed by a functional block other than the illustrated functional block. Furthermore, the illustrated functional block may be further divided into smaller functional sub-blocks.

[0010] Additionally, any steps in the flow of the method of the embodiments are not limited to the illustrated order and may be performed in an order different from the illustrated order and / or in parallel with other steps unless otherwise indicated.

[0011] In this specification and claims, when a first element is "connected" to another second element, it includes the first element being connected to the second element directly or via an element that is always or selectively conductive.

[0012] 1. First embodiment A memory system according to a first embodiment will be described below, taking a NAND flash memory as a nonvolatile memory and a memory system including the NAND flash memory as an example.

[0013] 1.1 Overview In memory systems that use NAND flash memory as a storage medium, repeated programming of the same cell data into the same memory cell can reduce memory reliability. Cell data is data stored in a single memory cell. In particular, in memory cells in a block where updated data is repeatedly written to the same physical address within the NAND flash memory, such as a block storing firmware, there is a high probability that the cell data to be programmed will be the same as the cell data programmed before the update. Furthermore, when one of multiple data stored in such a block is updated, the data that is not being updated is rewritten with the same data as before the erase operation for that block. This can further reduce memory reliability. One approach to this problem is for a memory controller or other device that controls the write to process the data to be written and convert it into different data before writing to the block.

[0014] Randomization is a known process performed on data before it is written. Randomization is performed to prevent data pattern concentration. In this process, a pseudorandom number sequence is generated, and a logical operation (e.g., exclusive OR, addition, or multiplication) is performed between the data to be written and the pseudorandom number sequence. When writing or reading data to or from a NAND flash memory, a pseudorandom number sequence is generated using a randomization key (hereinafter also referred to as a key or a seed value). The generated pseudorandom number is used to randomize and de-randomize the data (hereinafter referred to as a de-randomization process). Due to the nature of pseudorandom numbers, pseudorandom number sequences generated using the same randomization key and randomization circuit are identical. Since the results of logical operations between the same data to be written and the same pseudorandom number sequence are also identical, the aforementioned problem cannot be solved if the same randomization key is always used for randomization.

[0015] Therefore, in the first embodiment, the memory controller performs randomization processing on the data written to a block using a different randomization key for each erase operation of the block, thereby preventing the same cell data from being repeatedly programmed into the same memory cell.

[0016] In the following, an example will be described in which a memory controller writes, reads, and erases firmware. However, similar effects can be obtained with a similar configuration even when the memory controller writes, reads, and erases data other than firmware. Note that the memory controller may also be referred to as a controller in this application.

[0017] 1.2 Configuration The configuration of the memory system according to the first embodiment will be described.

[0018] 1.2.1 Memory System Configuration First, an outline of the configuration of the memory system according to the first embodiment will be described with reference to FIG.

[0019] As shown in FIG. 1, the memory system 1 includes a nonvolatile memory (NAND flash memory) 100 and a memory controller 200. The memory system 1 may be configured with multiple semiconductor chips. The NAND flash memory 100 and the memory controller 200 may be combined to configure one memory system 1. Examples of such memory systems include a UFS (Universal Flash Storage) device, SD TM Examples include memory cards, SSDs (Solid State Drives), and eMMCs (embedded Multi Media Cards).

[0020] The NAND flash memory 100 includes a plurality of memory cells (hereinafter also referred to as memory cell transistors MT) and stores data in a nonvolatile manner. The NAND flash memory 100 may have a structure in which, for example, a memory chip MC and a CMOS chip CC are bonded together.

[0021] The memory controller 200 is connected to the NAND flash memory 100 via a NAND bus, and is connected to the host 300 via a host bus. The memory controller 200 controls the NAND flash memory 100. The memory controller 200 also accesses the NAND flash memory 100 in response to commands received from the host 300.

[0022] The host 300 is, for example, a mobile phone, a tablet, a personal computer, a server, an automobile, etc. The host 300 is, for example, an SD TM Interface: SAS (Serial Attached SCSI (Small Computer System Interface)), SATA (Serial ATA (Advanced Technology Attachment)), PCIe (PCI Express TM(Peripheral Component Interconnect express)), or NVMe (NVM EXPRESS TM (Non-Volatile Memory express)).

[0023] The NAND bus transmits and receives signals according to the NAND interface. Specific examples of NAND interface signals are the chip enable signal CEn, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, read enable signal REn, ready / busy signal RBn, and input / output signal DQ. In the following explanation, when the suffix "n" is added to a signal name, the signal is negative logic. In other words, this indicates that the signal is asserted at the L (low) level.

[0024] The signal CEn is a signal for enabling the NAND flash memory 100 and is asserted at an “L” level. The signals CLE and ALE are signals for notifying the NAND flash memory 100 that the signal DQ to the NAND flash memory 100 is a command and an address, respectively. The signal WEn is asserted at an “L” level and is a signal for causing the NAND flash memory 100 to take in the signal DQ. The signal REn is also asserted at an “L” level and is a signal for reading the signal DQ from the NAND flash memory 100. The signal RBn is a signal that indicates whether the NAND flash memory 100 is in a ready state (e.g., a state in which it can receive commands from the memory controller 200) or a busy state (e.g., a state in which it cannot receive commands from the memory controller 200), with an “L” level indicating a busy state. The signal DQ is, for example, an 8-bit signal. The signal DQ is the substance of the data exchanged between the NAND flash memory 100 and the memory controller 200, and includes a command CMD, an address ADD, and data DAT such as write data and read data.

[0025] 1.2.2 NAND flash memory configuration Next, a description will be given of the configuration of the NAND flash memory 100. As shown in FIG.

[0026] The memory cell array 110 includes a plurality of blocks BLK, each including a plurality of nonvolatile memory cells associated with a row and a column. Data stored in the memory cell array 110 is erased in units of blocks BLK. FIG. 1 shows four blocks BLK0 to BLK3 as an example. The memory cell array 110 stores data provided by the memory controller 200.

[0027] The row decoder 120 selects one of the blocks BLK0 to BLK3 based on the block address in the address register 150, and further selects a word line in the selected block BLK.

[0028] The driver 130 supplies a voltage to the selected block BLK via the row decoder 120 based on the page address in the address register 150 .

[0029] When sensing data, the sense amplifier module 140 judges the data based on the threshold voltage of the memory cell transistor MT in the memory cell array 110. Then, the sense amplifier module 140 outputs the judgment result as read data DAT to the memory controller 200. When programming data, the sense amplifier module 140 transfers write data DAT received from the memory controller 200 to the memory cell array 110.

[0030] The address register 150 temporarily stores an address ADD received from the memory controller 200. This address ADD includes the above-mentioned block address and page address. The address ADD is, for example, a number. The command register 160 temporarily stores a command CMD received from the memory controller 200.

[0031] The sequencer 170 controls the overall operation of the NAND flash memory 100 based on the command CMD stored in the command register 160 .

[0032] Next, the circuit configuration of the block BLK will be described with reference to Fig. 2. Fig. 2 is a circuit diagram of one of the blocks BLK.

[0033] 2, the block BLK includes, for example, four string units SU (SU0 to SU3), each of which includes a plurality of NAND strings NS.

[0034] Each of the NAND strings NS includes, for example, eight memory cell transistors MT (MT0 to MT7) and select transistors ST1 and ST2. The memory cell transistors MT have a control gate and a charge storage layer, and store data in a non-volatile manner. The memory cell transistors MT are connected in series between the source of the select transistor ST1 and the drain of the select transistor ST2. Each memory cell transistor MT can store two or more bits of data.

[0035] The gates of the select transistors ST1 included in the multiple NAND strings NS of each of the string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. In contrast, the gates of the select transistors ST2 included in the multiple NAND strings NS of each of the string units SU0 to SU3 are commonly connected to, for example, a select gate line SGS. Alternatively, the gates of the select transistors ST2 included in the multiple NAND strings NS of each of the string units SU0 to SU3 may be connected to different select gate lines SGS0 to SGS3 for each string unit. Furthermore, the control gates of the memory cell transistors MT0 to MT7 included in the multiple NAND strings NS in the same block BLK are commonly connected to word lines WL0 to WL7, respectively.

[0036] Furthermore, the drains of the select transistors ST1 of the NAND strings NS in the same column included in multiple blocks BLK in the memory cell array 110 are commonly connected to a bit line BL (BL0 to BLm, where m is a natural number equal to or greater than 1). That is, the bit line BL commonly connects the NAND strings NS in the same column across multiple blocks BLK. Furthermore, the sources of the select transistors ST2 are commonly connected to a source line SL.

[0037] A set of memory cell transistors MT included in the same string unit SU and connected to the same word line WL is called, for example, a cell unit CU. The cell unit CU includes N pages, which are storage areas, depending on the number N of bits of cell data stored in each memory cell transistor MT. For example, one page stores a set of one-bit data located at the same bit position in the cell data stored in each memory cell transistor MT of the cell unit CU. Hereinafter, the storage capacity of one page is referred to as the page size.

[0038] When programming data into the memory cell array 110, for example, data stored in each of N pages included in the cell unit CU is programmed into the cell unit CU at one time. Data is sensed from the memory cell array 110 page by page. The page to be programmed and sensed is specified by a page address included in the address ADD received from the memory controller 200.

[0039] The memory controller 200 may also perform various processes on data in units of divided pages (hereinafter referred to as frames) obtained by dividing one page into predetermined units. Hereinafter, the storage capacity of one frame will be referred to as the frame size.

[0040] The memory cell array 110 may have a circuit configuration other than the above. For example, the number of blocks in the memory cell array 110, the number of string units SU included in a block BLK, and the number of memory cell transistors MT and select transistors ST1 and ST2 included in a NAND string NS can be designed to any number.

[0041] Next, the schematic configuration of data stored in block BLK according to the first embodiment will be described with reference to Fig. 3. The NAND flash memory 100 can store multiple firmware. Fig. 3 shows an example in which the memory system 1 is configured to store three pieces of firmware.

[0042] Blocks 1 to 3 are blocks for storing firmware (hereinafter referred to as firmware blocks). In the firmware block in the first embodiment, one slot and one header area are provided in each block. A slot is an area for storing firmware. For example, one piece of firmware is stored in one slot. A header area is an area for storing header information. The header information will be described later. A header area is set in, for example, one page in a firmware block. In the example of FIG. 3, slot 1 and header area 1 for storing the first of three pieces of firmware are provided in block 1. Similarly, slot 2 and header area 2 for storing the second of the three pieces of firmware are provided in block 2. Slot 3 and header area 3 for storing the third firmware are provided in block 3.

[0043] The firmware stored in slot 1 may be different from the firmware stored in slot 2 and the firmware stored in slot 3, or may be the same firmware. The firmware stored in slot 2 may be different from the firmware stored in slot 3, or may be the same firmware. The firmware is randomized by a randomization circuit 280, which will be described later, and then stored.

[0044] Blocks 4 to n (where n is a natural number equal to or greater than 5) are blocks for user data.

[0045] If the memory cell transistor MT can store two or more bits of data, the firmware block is used as, for example, a pSLC area (pseudo single level cell area). The pSLC area is a storage area in which one bit of data is stored in a memory cell transistor MT that can store two or more bits of data.

[0046] Next, the internal configuration of the firmware block according to the first embodiment will be described with reference to FIG. 4. As shown in FIG. 4, the header information stored in the header area includes information used in firmware update or restoration processing. The header information includes, for example, slot allocation information and a value relating to the number of erase operations performed on the block (hereinafter referred to as erase count information). The slot allocation information indicates the location of an area set as a slot, and includes, for example, a page address corresponding to the slot, or a page address and a frame address. The erase count information is changed, for example, every time an erase operation is performed on the block. For example, the erase count information is set to "0" when the memory system 1 is shipped.

[0047] The general configuration of the block BLK and the internal configuration of the firmware block do not need to be achieved by the circuit configuration of the memory cell array 110; it is sufficient that the memory controller 200 or the sequencer 170 recognizes the purpose of each area at least in various processes.

[0048] 1.2.3 Memory Controller Configuration 1, the following describes the configuration of the memory controller 200. Note that each function of the memory controller 200 may be implemented by a dedicated circuit, or may be implemented by the processor 260 executing firmware.

[0049] The memory controller 200 is, for example, a System-on-a-Chip (SoC). The memory controller 200 may be configured with multiple semiconductor chips. The memory controller 200 includes a host interface circuit (host I / F) 210, a Random Access Memory (RAM) 220, a Read Only Memory (ROM) 230, a buffer memory 240, a NAND interface circuit (NAND I / F) 250, a processor (CPU) 260, an ECC circuit 270, and a randomization circuit (R / D) 280.

[0050] The host interface circuit 210 is connected to the host 300 via a host bus. The host interface circuit 210 transfers commands and data received from the host 300 to the buffer memory 240 and the processor 260, respectively. In addition, the host interface circuit 210 transfers data in the buffer memory 240 to the host 300 in response to commands from the processor 260.

[0051] The RAM 220 is, for example, a static random access memory (SRAM). The RAM 220 is used as a working area for the processor 260. The RAM 220 temporarily stores, for example, firmware read from the NAND flash memory 100, an update program UDP, and an address table AT.

[0052] The update program UDP is a program for updating firmware according to the first embodiment. The update program UDP is stored in the NAND flash memory 100. The update program UDP is read from the NAND flash memory 100 to the RAM 220 as needed. When the memory controller 200 executes a firmware update, the processor 260 executes the update program UDP read to the RAM 220. The update program UDP may be part of the firmware.

[0053] The address table AT is a table for managing storage destination addresses (logical addresses) of data specified by the host 300 and locations (physical addresses) in the NAND flash memory 100 that correspond to these storage destination addresses. For example, in a firmware update process, the logical addresses are slot addresses and the physical addresses are block addresses.

[0054] The ROM 230 is configured by, for example, a mask ROM. Alternatively, the ROM 230 may be a serial flash ROM provided in the memory system 1. The ROM 230 stores an IPL (Initial Program Loader). The IPL is a program for reading firmware from the NAND flash memory 100.

[0055] The buffer memory 240 is, for example, a dynamic random access memory (DRAM), and temporarily stores write data and read data.

[0056] The NAND interface circuit 250 is connected to the NAND flash memory 100 via a NAND bus and controls communication with the NAND flash memory 100. The NAND interface circuit 250 outputs signals CEn, ALE, CLE, WEn, and REn to the NAND flash memory 100 based on instructions received from the processor 260. During writing, the NAND interface circuit 250 transfers a write command and a write target address issued by the processor 260, as well as write data in the buffer memory 240, to the NAND flash memory 100 as a signal DQ. During reading, the NAND interface circuit 250 transfers a read command and a read target address issued by the processor 260 to the NAND flash memory 100 as a signal DQ. Furthermore, the NAND interface circuit 250 receives data read from the NAND flash memory 100 as a signal DQ and transfers it to the buffer memory 240.

[0057] The processor 260 controls the overall operation of the memory controller 200. For example, the processor 260 executes firmware loaded from the NAND flash memory 100 onto the RAM 220 to perform various processes.

[0058] The processor 260 functions as, for example, a block control unit 262, a seed value setting unit 264, and a data management unit 266. The processor 260 functions as each of these units by, for example, executing firmware.

[0059] The block control unit 262 performs write, read, and erase processes on the NAND flash memory 100 based on commands received from, for example, the host 300. At this time, the block control unit 262 refers to, for example, an address table AT stored in the RAM 220 to identify the location in the NAND flash memory 100 that is the target of each process. Furthermore, when the memory system 1 starts up, the block control unit 262 reads firmware from the NAND flash memory 100 based on the IPL.

[0060] The seed value setting unit 264 supplies a seed value used to generate a pseudo-random number sequence to a random number generation circuit 282, which will be described later.

[0061] The data management unit 266 manages and edits various data stored in the RAM 220 and the buffer memory 240. Specifically, the data management unit 266 performs calculations and other processes on the data stored in the buffer memory 240. The data management unit 266 also divides or combines data to be written, received from the host 300, into data of the same size as the frame size or a size that will be equal to the frame size after error correction encoding. The error correction encoding process will be described later. Hereinafter, the term "frame size" may refer to the size that will be equal to the frame size after error correction encoding. The data management unit 266 also divides or combines data to be written into data of the same size as the page size. The data management unit 266 also pads the data to be written so that it is the same size as the frame size or the page size. Hereinafter, data having the same size as the frame size will be referred to as frame data FD. Data having the same size as the page size will be referred to as page data PD.

[0062] The ECC circuit 270 encodes data to be written to the NAND flash memory 100. The ECC circuit 270 also decodes data read from the NAND flash memory 100. This encoding and decoding is necessary for error detection and correction. Specifically, the ECC circuit 270 performs error correction encoding on data to be written to the NAND flash memory 100. Based on the error correction code generation method, data containing information for error correction may be generated from the data to be written by error correction encoding. The data after error correction encoding is written to the NAND flash memory 100. In the error correction decoding process, the ECC circuit 270 detects errors in the data read from the NAND flash memory 100 and attempts to correct the errors if any are found.

[0063] The randomize circuit (R / D) 280 performs randomize processing on data to be written to the NAND flash memory 100. The randomize circuit 280 also performs de-randomize processing on data read from the NAND flash memory 100.

[0064] FIG. 5 shows a more detailed configuration of the randomization circuit 280. As shown in FIG. 5, the randomization circuit 280 includes a random number generation circuit 282 and an XOR circuit 284. The random number generation circuit 282 is, for example, a linear feedback shift register or a nonlinear conversion circuit. The random number generation circuit 282 outputs a pseudo-random number sequence according to an input seed value. The example of FIG. 5 shows a case where three seed values ​​are input to the random number generation circuit 282. The randomization circuit 280 performs randomization processing and de-randomization processing by performing an exclusive OR (XOR) of the pseudo-random number sequence output from the random number generation circuit 282 and the input data. Note that there may be two or more random number generation circuits 282 and two or more XOR circuits 284.

[0065] In this description, the seed value is a value for setting the initial state of the random number generation circuit 282 that generates a pseudo-random number sequence. The number of seed values ​​used to generate a pseudo-random number sequence is not limited to three, and may be one, two, four or more. In the first embodiment, the seed value is supplied from the processor 260.

[0066] The generation of pseudorandom number sequences and the exclusive OR operation of the pseudorandom number sequences and input data in a randomization circuit using a linear feedback shift register are described, for example, in Japanese Patent Application No. 2015-237706 filed on December 4, 2015. Furthermore, the generation of pseudorandom number sequences and the exclusive OR operation of the pseudorandom number sequences and input data in a randomization circuit using a nonlinear conversion circuit are described, for example, in Japanese Patent Application No. 2020-96429 filed on June 2, 2020. These patent applications are incorporated herein by reference in their entirety.

[0067] In the following, an example will be described in which the memory controller 200 divides one page into four frames and performs randomization and derandomization, as well as encoding and decoding, of data for each divided frame. That is, in this example, the number of frames per page is four.

[0068] 1.3 Operation Next, the operation of the memory system according to the first embodiment will be described.

[0069] 1.3.1 Firmware update process The firmware update process according to the first embodiment will be described.

[0070] 6 shows an example of data processing for firmware update processing by the memory controller 200 in the first embodiment. As shown in the top row of FIG. 6, the memory controller 200 receives update firmware UFW having a certain data size from the host 300. When the update firmware UFW is received by the memory controller 200, it is temporarily stored in, for example, the buffer memory 240. Note that the firmware may be encrypted before being transmitted from the host. In this description, firmware also includes such encrypted firmware.

[0071] As shown in the second row of Fig. 6, the data management unit 266 divides and / or pads the update firmware UFW to generate multiple frame data FDs. In the example of Fig. 6, eight frame data FDs (FD1 to FD8) are generated from the update firmware UFW. Note that the frame data FD1 to FD8 can be arranged in this order within the update firmware UFW, for example. Furthermore, the frame data FD1 to FD8 can be located at any position within the update firmware UFW.

[0072] In addition, if the number of frame data FDs to be generated is not an integer multiple of the number of frames per page (4 in this example), the data management unit 266 generates frame data FDs consisting of padding data (hereinafter referred to as padding frame data) so that the total number of frame data FDs to be generated is an integer multiple of the number of frames per page.

[0073] The data management unit 266 associates the frame data FD with a pair of a page address and a frame address in the storage slot where the updated firmware is stored. Hereinafter, the pair of page address α and frame address β may be referred to as (α, β). In the example of Fig. 6, the data management unit 266 associates (1,1) to (1,4) in order with frame data FD1 to FD4, and associates (2,1) to (2,4) in order with frame data FD5 to FD8.

[0074] As shown in the third row of Fig. 6, the randomization circuit 280 performs a randomization process on the frame data FD to generate randomized frame data ranFD. The seed value used by the randomization circuit 280 to perform the randomization process is supplied from the seed value setting unit 264. The seed value used will be described later. The randomized frame data ranFD is then encoded by the ECC circuit 270.

[0075] As shown in the fourth row of FIG. 6, the data management unit 266 combines randomized frame data ranFD associated with the same page address to generate page data PD. Specifically, the data management unit 266 combines, for example, the randomized frame data ranFD in ascending order of the associated frame addresses. Hereinafter, page data PD associated with page address α may be simply referred to as PDα. In the example of FIG. 6, the data management unit 266 combines ranFD1 to ranFD4 associated with page address "1" in ascending order of the associated frame addresses (i.e., in the order of 1 to 4) to generate PD1, and combines ranFD5 to ranFD8 associated with page address "2" in ascending order of the associated frame addresses (i.e., in the order of 1 to 4) to generate PD2.

[0076] The block control unit 262 writes the generated page data PD (PD1 and PD2) to the NAND flash memory 100.

[0077] Next, an overview of firmware update processing according to the first embodiment will be described with reference to Fig. 7. In Fig. 7, solid arrows indicate data flow, and dashed arrows and squares indicate processing by the memory controller 200. In Fig. 7, two buffer memories 240 are shown for convenience, but this does not mean that two buffer memories 240 need to be provided.

[0078] When the update process is started, the block control unit 262 reads header information from the header area of ​​the firmware block (corresponding to the storage destination block FSB described later) that includes the storage destination slot where the updated firmware UFW is stored ((i) in FIG. 7). The read header information is decoded by the ECC circuit 270 and temporarily stored in the buffer memory 240, for example.

[0079] The block control unit 262 performs an erase process on the storage destination block.

[0080] The data management unit 266 changes the read header information. In particular, the data management unit 266 changes the erase count information included in the header information ((ii) in FIG. 7). Specifically, the data management unit 266 increments the erase count information by 1, for example. However, the difference between the value before and after the change of the erase count information is not limited to 1, and it is sufficient that at least the value is changed.

[0081] The data management unit 266 also divides and / or pads the updated firmware received from the host to generate frame data FD ((iii) in FIG. 7). Furthermore, the data management unit 266 associates the generated frame data FD with a pair of a page address and a frame address in the storage destination slot ((iv) in FIG. 7). When associating, the data management unit 266 refers to slot allocation information included in the header information.

[0082] The randomization circuit 280 sequentially performs randomization processing on the generated frame data FD to generate randomized frame data ranFD (FIG. 7(v)).

[0083] When randomizing the frame data FD, the seed value setting unit 264 references the changed header information and supplies the erase count information as a seed value to the random number generation circuit 282. The seed value setting unit 264 also supplies the page address and frame address associated with each frame data FD to the random number generation circuit 282 as a seed value. In the randomization process, the random number generation circuit 282 generates a pseudo-random number sequence using the seed value supplied from the seed value setting unit 264 and supplies it to the XOR circuit 284. The XOR circuit 284 performs an XOR operation on the pseudo-random number sequence supplied from the random number generation circuit 282 and the frame data FD to generate randomized frame data ranFD. The randomized frame data ranFD is encoded by the ECC circuit 270.

[0084] The data management unit 266 combines the generated randomized frame data ranFD to generate page data PD ((vi) of FIG. 7).

[0085] The block control unit 262 writes the page data PD to the corresponding page in the storage destination slot ((vii) in FIG. 7). The block control unit 262 also writes the changed header information to the header area of ​​the storage destination block.

[0086] The above is an overview of the firmware update process according to the first embodiment. As explained above, in the firmware update process according to the first embodiment, the memory controller 200 changes the erase count information included in the header information and performs randomization processing of the updated firmware using the changed erase count information as a seed value. That is, in the firmware randomization processing, a different seed value is used for each firmware update process (or erase operation of the storage destination block).

[0087] In the encoding and decoding of the header information, the data management unit 266 divides, pads, and combines the header information as necessary.

[0088] Fig. 8 shows the flow of firmware update processing according to the first embodiment. Fig. 8 particularly shows the flow when performing the processing described with reference to Figs. 6 and 7. The memory controller 200 starts the firmware update processing upon receiving a firmware update request from the host 300. Specifically, in response to receiving the firmware update request, the processor 260 executes the update program UDP.

[0089] In step S100, the memory controller 200 receives the update firmware UFW and information for identifying the update firmware UFW (hereinafter referred to as update firmware identification information) from the host 300. The update firmware identification information includes, for example, a storage destination slot address and version information for the update firmware UFW. The update firmware UFW and update firmware identification information are temporarily stored in, for example, the buffer memory 240. Note that at least one of the update firmware UFW and the update firmware identification information may be received from the host 300 before the update program UDP is executed. In this case, the data of the update firmware UFW and the update firmware identification information received before the update program UDP is executed may be received from the host 300 included in a firmware update request.

[0090] In step S102, the memory controller 200 identifies the physical address of the storage destination slot where the updated firmware UFW is stored, from the updated firmware identification information. The memory controller 200 identifies the physical address of the storage destination slot, for example, by referring to the address table AT.

[0091] In step S104, the memory controller 200 (particularly the block control unit 262) reads the header information of the block corresponding to the physical address of the storage slot (hereinafter referred to as the storage block FSB). The read header information is decoded by the ECC circuit 270 and temporarily stored in the buffer memory 240, for example.

[0092] In step S106, the memory controller 200 divides and / or pads the updated firmware UFW to generate frame data FD.

[0093] In step S108, the memory controller 200 refers to the slot allocation information in the header information, and associates any pair of page address and frame address in the storage destination slot with the frame data FD generated in step S106.

[0094] In step S110, the memory controller 200 performs an erase process on the storage destination block FSB.

[0095] In step S112, the memory controller 200 changes the header information stored in the buffer memory 240 (particularly, the erase count information).

[0096] In step S114, the memory controller 200 determines the order in which the randomization process is to be performed on the frame data FD. Note that the randomization process may be performed on several frame data FDs in parallel.

[0097] In step S116, the memory controller 200 performs randomization processing on the frame data FD in accordance with the processing order determined in step S114, and generates randomized frame data ranFD. The memory controller 200 uses the changed erase count information and the page address and frame address associated with the frame data FD as seed values. The generated randomized frame data ranFD is associated with the page address and frame address associated with the original frame data FD. Note that the memory controller 200 may generate a seed value by performing processing such as calculation on the erase count information, page address, and / or frame address, and use the seed value for the randomization processing. The randomized frame data ranFD is encoded by the ECC circuit 270.

[0098] In step S118, the memory controller 200 combines the randomized frame data ranFD associated with the same page address to generate page data PD. The page data PD is generated, for example, in ascending order of the page addresses included in the storage destination slot.

[0099] In step S120, the memory controller 200 (particularly the block control unit 262) writes the page data PD to the NAND flash memory 100. The page data PD is written to an area of ​​the storage destination block FSB indicated by the page address corresponding to each page data PD.

[0100] In step S122, the memory controller 200 writes the changed header information to the NAND flash memory 100. The changed header information is encoded by the ECC circuit 270 and written to the header area of ​​the storage destination block FSB.

[0101] The firmware update process is completed.

[0102] In the firmware update process, when generating frame data FD from the update firmware UFW, padding frame data is generated according to the number of FDs generated, but this is not limited to this. That is, padding frame data may not be generated when generating frame data FD, but may be generated when generating page data PD and combined with randomized frame data ranFD.

[0103] Furthermore, in the firmware update process, the randomized frame data ranFD and the header information are encoded and written to the NAND flash memory 100, but this is not limiting. That is, at least one of the randomized frame data ranFD and the header information may be written to the NAND flash memory 100 without being encoded. Furthermore, the frame data FD may be encoded and then randomized.

[0104] Furthermore, in the firmware update process, the page data PD is generated and written after randomization processing is performed on all frame data FD, but this is not limiting. For example, page data PD may be generated and written each time randomization processing is completed on some frame data FD.

[0105] Furthermore, in the firmware update process, the memory controller 200 changes the erase count information included in the header information and then supplies the changed erase count information as a seed value to the random number generation circuit 282, but this is not limited to this. That is, for example, the memory controller 200 may perform a randomization process using the erase count information before changing the header information as a seed value, and then change the erase count information. In this case, during the de-randomization process in the firmware restoration process described below, the memory controller 200 performs an inverse operation on the erase count information acquired from the header information to the operation performed in the erase count information change process, and supplies the erase count information after the inverse operation to the random number generation circuit 282 as a seed value.

[0106] Furthermore, before changing the header information, or in parallel with changing the header information, the memory controller 200 may perform the same processing, such as calculations, as performed in the header information change process on the acquired erase count information before the change, and supply it to the random number generation circuit 282 as a seed value.

[0107] 1.3.2 Firmware restoration process Next, a firmware restoration process according to the first embodiment will be described. Fig. 9 shows a flow of firmware restoration according to the first embodiment. Fig. 9 particularly shows a flow of processing when restoring firmware written to the NAND flash memory 100 by the processing described with reference to Figs. 7 and 8.

[0108] When power supply to the memory system 1 is started and the memory system 1 is started, the memory controller 200 starts the firmware restoration process. Specifically, the processor 260 reads the IPL from the ROM 230 and executes it.

[0109] In step S150, the memory controller 200, in accordance with the IPL, reads the header information of the block in which the firmware to be restored is stored (hereinafter referred to as the read target block RFB) from the NAND flash memory 100. The read header information is decoded by the ECC circuit 270 and temporarily stored in the buffer memory 240, for example.

[0110] In step S152, the memory controller 200 refers to the slot allocation information in the read header information and identifies the page address (hereinafter referred to as the read target page address) and frame address of the read target slot in the read target block RFB.

[0111] In step S154, the memory controller 200 reads the page data PD from the area corresponding to the read target page address in the NAND flash memory 100. The read page data PD is temporarily stored in the buffer memory 240, for example.

[0112] In step S156, the memory controller 200 divides the page data PD read in step S154 to generate randomized frame data ranFD. Each randomized frame data ranFD is associated with a page address corresponding to the original page data PD and a frame address indicating a position in the original page data PD. Each randomized frame data ranFD is decoded by the ECC circuit 270.

[0113] In step S158, the memory controller 200 determines the order in which the de-randomization process is to be performed on the randomized frame data ranFD. Note that the de-randomization process may be performed in parallel on several pieces of randomized frame data ranFD.

[0114] In step S160, the memory controller 200 performs de-randomization processing on the randomized frame data ranFD in accordance with the processing order determined in step S158, to generate frame data FD. The memory controller 200 uses the erase count information included in the header information, and the page address and frame address associated with the randomized frame data ranFD as seed values. Note that the memory controller 200 may generate a seed value by performing processing such as calculation on the erase count information, page address, and / or frame address, and use the seed value in the de-randomization processing.

[0115] In step S162, the memory controller 200 combines the frame data FD restored in step S160 to generate firmware FW. The firmware FW restored here corresponds to the update firmware UFW in the firmware update process.

[0116] The firmware restoration process is complete.

[0117] In step S162, the memory controller 200 may combine the frame data FD excluding the padding frame data.

[0118] In the randomization process and the de-randomization process, the page address and the frame address are used as the seed value in addition to the erase count information, but this is not limited to this. That is, only the erase count information may be used as the seed value. Furthermore, in addition to the erase count information, a value other than the page address or the frame address may be used as the seed value.

[0119] The slot allocation information may be included in the update program UDP or the IPL. In this case, the memory controller 200 may perform various processes by referring to the slot allocation information included in the update program UDP during the firmware update process, and may perform various processes by referring to the slot allocation information included in the IPL during the firmware restoration process.

[0120] 1.4 Effects The memory system according to the first embodiment has the following advantages.

[0121] In conventional memory systems, firmware randomization and de-randomization are performed using a seed value included in the IPL. Because the IPL is stored in ROM, it is difficult to change the data. Therefore, in such memory systems, a fixed value is used as the seed value when randomizing and de-randomizing firmware.

[0122] In the first embodiment, since the value stored in the NAND flash memory is used as the seed value, it is easy to make the seed value variable.

[0123] In the first embodiment, the erase count information of the block to be written or read is used as a seed value. The erase count information is changed every time an erase process is performed on the block, so the seed value used in the randomization process performed on the data to be written can be changed before and after the erase operation.

[0124] As a result, the memory system according to the first embodiment can prevent the same value from being repeatedly programmed into the same memory cell of the NAND flash memory, thereby suppressing a decrease in the reliability of the NAND flash memory.

[0125] In the first embodiment, the erase count information of the storage destination block of the firmware is written to the storage destination block, which eliminates the need to provide a block for storing the erase count information of the firmware block group separately from the firmware block, thereby reducing the number of blocks.

[0126] Furthermore, in the first embodiment, when updating firmware, only the storage block of the updated firmware needs to be rewritten, which is expected to reduce the update processing time and the number of erasure operations when updating firmware.

[0127] 1.5 Variations Next, a description will be given of a modified example of the first embodiment. In the firmware update process in the modified example of the first embodiment, when changing the erase count information included in the header information, the memory controller 200 refers to a table (hereinafter referred to as a block table BT) that associates the block address of each block with the erase count information performed on the block.

[0128] The block table BT is a table for managing the correspondence between the block addresses of blocks included in the memory cell array 110 and erase count information of the blocks. The block table BT is stored in the NAND flash memory 100. For example, when the memory system is started up, the block table BT is read from the NAND flash memory 100 to the RAM 220 and temporarily stored therein. The block table BT stored in the RAM 220 is updated, for example, every time an erase process is performed on any of the blocks included in the memory cell array 110. However, the block table BT stored non-volatilely in the NAND flash memory 100 does not necessarily need to be updated every time the block table BT stored in the RAM 220 is updated.

[0129] An overview of header information change processing according to a modified example of the first embodiment will be described with reference to Fig. 10. Fig. 10 shows an overview of header information change processing according to a modified example of the first embodiment. In Fig. 10, arrows drawn with solid lines indicate data flow, and arrows drawn with dashed lines indicate processing by the memory controller 200.

[0130] In response to the erasure process being performed on the storage destination block, the data management unit 266 changes the erase count information in the block table BT corresponding to the block address of the storage destination block ((i) in FIG. 10). Specifically, the data management unit 266 increments the erase count information by 1. In the example of FIG. 10, in response to the erasure process being performed on block 1, which is the storage destination block, the erase count information in the block table BT corresponding to block address 1 is changed.

[0131] The data management unit 266 refers to the block table BT and changes the header information (especially the erase count information) read out to the buffer memory 240 ((ii) in FIG. 10). Specifically, the data management unit 266 changes the erase count information in the header information to the erase count information in the block table BT that corresponds to the block address of the storage destination block, for example. Alternatively, the data management unit 266 may perform processing such as calculation on the erase count information acquired from the block table BT, and change the erase count information in the header information to the processed value.

[0132] The above is an overview of the header information change process according to the modified example of the first embodiment. The memory system 1 according to this modified example has the same effects as that of the first embodiment. Furthermore, in this modified example, processing such as calculation for changing the erase count information can be performed before reading the header information. This is expected to reduce the update processing time when updating firmware. The header information change process that involves referencing the block table BT, as explained in this modified example, is not limited to the first embodiment and can be applied to other embodiments as well.

[0133] 2. Second embodiment Next, a memory system according to a second embodiment will be described. In the first embodiment, information regarding the number of erase operations of the storage destination block of the target firmware was used as a seed value in the firmware randomization process. In the second embodiment, information regarding the total number of erase operations of a plurality of blocks including the storage destination block of the target firmware is used as a seed value in the firmware randomization process. In particular, an example will be described below in which information regarding the total number of erase operations of all firmware blocks included in the memory cell array 110 (hereinafter referred to as total erase operation information) is used. Furthermore, in the following, descriptions of configurations and operations equivalent to those of the first embodiment may be omitted.

[0134] 2.1 Internal structure of the firmware block First, the internal configuration of a firmware block according to the second embodiment will be described. FIG. 11 shows the internal configuration of a firmware block according to the second embodiment. As shown in FIG. 11, the header information includes, for example, slot allocation information and total erase count information. The total erase count information is updated, for example, by referring to the total erase count information included in the header information of all firmware blocks each time an erase operation is performed on the block. For example, the total erase count information is set to "0" when the memory system 1 is shipped.

[0135] 2.2 Firmware update process Next, an overview of firmware update processing according to the second embodiment will be described. An example of data processing for firmware update processing by the memory controller 200 in the second embodiment is the same as that in the first embodiment (for example, that described with reference to FIG. 6), and therefore description thereof will be omitted. FIG. 12 shows an overview of header information reading processing, header information change processing, and seed value setting processing in the firmware update processing according to the second embodiment. FIG. 12 particularly shows an example in which the memory cell array 110 includes three firmware blocks (blocks 1 to 3). Processing not shown in FIG. 12 is the same as that described in the first embodiment, and therefore description thereof will be omitted. Note that in FIG. 12, arrows drawn with solid lines indicate the flow of data, and arrows drawn with dashed lines indicate processing by the memory controller 200.

[0136] When the update process starts, the block control unit 262 reads the header information of all firmware blocks ((i) in FIG. 12). Hereinafter, information read from block x, which is a firmware block, may be suffixed with x. In the example of FIG. 12, header information 1 to 3 are read from the header areas of blocks 1 to 3. The read header information is decoded by the ECC circuit 270 and temporarily stored in the buffer memory 240, for example.

[0137] The data management unit 266 changes the header information read from the storage destination block FSB of the updated firmware ((ii) in FIG. 12). Hereinafter, the header information read from the storage destination block FSB and the information contained therein may be prefixed with "FSB" to distinguish it from other header information and information contained therein. In the example of FIG. 12, the storage destination block FSB is block 1, and header information 1, which is FSB header information, is changed.

[0138] The data management unit 266 particularly changes the FSB total erase count information included in the FSB header information. At this time, the data management unit 266 refers to all of the total erase count information included in all of the read header information (including the FSB header information) and changes the FSB total erase count information. Specifically, the data management unit 266 changes the FSB total erase count information to, for example, the maximum value of the total erase count information + 1. That is, the data management unit 266 sets FSB total erase count information = Max ([all total erase count information]) + 1. However, the difference between the maximum value and the value of the changed FSB total erase count information is not limited to 1, as long as the value is at least increased. In FIG. 12, example values ​​of each total erase count information are shown in parentheses. That is, in the example of FIG. 12, "total erase count information 1" is 2, "total erase count information 2" is 5, and "total erase count information 3" is 4. In this case, since the maximum value of the total erase count information is 5, the FSB total erase count information (total erase count information 1) is changed to 6 (= 5 + 1).

[0139] When randomizing the frame data FD, the seed value setting unit 264 refers to the changed FSB header information and supplies the FSB total erase count information as a seed value to the random number generation circuit 282 ((iii) in FIG. 12). In addition, the seed value setting unit 264 supplies the page address and frame address associated with each frame data FD to the random number generation circuit 282 as a seed value ((iii) in FIG. 12).

[0140] The block control unit 262 writes the changed FSB header information to the header area of ​​the storage destination block FSB ((iv) in FIG. 12). In the example in FIG. 12, changed header information 1, which is the changed FSB header information, is written to header area 1 of block 1.

[0141] The above is an overview of the firmware update process according to the second embodiment. As explained above, in the firmware update process according to the second embodiment, the memory controller 200 references the total erase count information included in the header information of all firmware blocks, and changes the total erase count information included in the header information of the storage destination block. The memory controller 200 also uses the changed total erase count information as a seed value to perform a randomization process for the updated firmware. That is, in the firmware randomization process, a different seed value is used for each firmware update process (or each firmware block erase operation).

[0142] Next, the flow of firmware update processing according to the second embodiment will be described with reference to FIG. 13. FIG. 13 particularly shows the flow when performing the processing described with reference to FIGS. 6 and 12. In FIG. 13, steps having the same step numbers as those in the first embodiment (FIG. 8) perform processing equivalent to that described in the first embodiment. Description of these steps will be omitted. Below, the reading of header information (step S204), processing to change the header information (step S212), processing to randomize the frame data FD (step S216), and writing of header information (step S222) will be described.

[0143] In step S204, the memory controller 200 reads the header information of all firmware blocks. The read header information is decoded by the ECC circuit 270. For header information other than the FSB header information, the memory controller 200 may read only the total erase count information. For header information other than the FSB header information, the memory controller 200 may read and decode the header information, and then store only the total erase count information in the buffer memory 240.

[0144] In step S212, the memory controller 200 refers to all the header information read in step S204, and changes the FSB header information stored in the buffer memory 240 (particularly, the FSB total erase count information).

[0145] In step S216, the memory controller 200 performs randomization processing on the frame data FD in accordance with the processing order determined in step S114, and generates randomized frame data ranFD. The memory controller 200 uses the changed FSB total erase count information and the page address and frame address associated with the frame data FD as seed values. The generated randomized frame data ranFD is associated with the page address and frame address associated with the original frame data FD. Note that the memory controller 200 may generate a seed value by performing processing such as calculation on the FSB total erase count information, page address, and / or frame address, and use the seed value for the randomization processing. The randomized frame data ranFD is encoded by the ECC circuit 270.

[0146] In step S222, the memory controller 200 writes the changed FSB header information to the NAND flash memory 100. The changed FSB header information is encoded by the ECC circuit 270 and written to the header area of ​​the storage destination block FSB.

[0147] 2.3 Firmware restoration process Next, firmware restoration processing according to the second embodiment will be described with reference to FIG. 14. FIG. 14 shows the flow of firmware restoration processing according to the second embodiment. FIG. 14 particularly shows the flow of processing when restoring firmware written to the NAND flash memory 100 by the processing described with reference to FIGS. 12 and 13. In FIG. 14, steps having the same step numbers as those in the first embodiment (FIG. 9) perform processing equivalent to that described in the first embodiment. Description of these steps will be omitted. Below, the derandomization processing of the randomized frame data ranFD (step S260) will be described.

[0148] In step S260, the memory controller 200 performs de-randomization processing on the randomized frame data ranFD in accordance with the processing order determined in step S158, to generate frame data FD. The memory controller 200 uses the total erase count information included in the header information, and the page address and frame address associated with the randomized frame data ranFD as seed values. Note that the memory controller 200 may generate a seed value by performing processing such as calculation on the total erase count information, the page address, and / or the frame address, and use the seed value in the de-randomization processing.

[0149] In the second embodiment, an example was described in which information regarding the total number of erase counts of all firmware blocks was used as the seed value, but this is not limited to this. That is, for example, all firmware blocks may be divided into multiple groups, and information regarding the total number of erase counts for each group to which each firmware block belongs may be used as the seed value. In this case, the memory system 1 stores information indicating which group each firmware block belongs to as part of the header information, or manages a table that associates the block address of a block with the group to which the block belongs.

[0150] 2.4 Effects The memory system according to the second embodiment has the same effects as those of the first embodiment. In addition, the memory system according to the second embodiment has the following effects.

[0151] In the second embodiment, when a firmware update process is performed, information regarding the total number of erase operations for multiple blocks, including the block to be written, is used as a seed value. That is, the value of the seed value used when a firmware update process is performed also changes when an erase operation is performed on a block other than the storage destination block. Therefore, the seed value used in the randomization process performed on the data to be written can be significantly changed before and after the erase operation.

[0152] 3. Third embodiment Next, a memory system according to a third embodiment will be described. In the first embodiment, information regarding the number of times the storage destination block of the target firmware was erased was used as a seed value in the firmware randomization process. In the third embodiment, information regarding the time when erasure was performed on the storage destination block is used as a seed value in the firmware randomization process. In the following, descriptions of configurations and operations equivalent to those of the first embodiment may be omitted.

[0153] 3.1 Configuration 3.1.1 Internal structure of the firmware block First, the internal structure of a firmware block according to the third embodiment will be described. Fig. 15 shows the internal structure of a firmware block according to the third embodiment. As shown in Fig. 15, the header information includes, for example, slot allocation information and information relating to when erasure was performed on the block (hereinafter referred to as erasure time information). The erasure time information is changed, for example, every time an erasure operation is performed on the block.

[0154] 3.1.2 Memory Controller Configuration Next, the configuration of the memory controller according to the third embodiment will be described with reference to Fig. 16. Note that a description of the configuration equivalent to that of the first embodiment will be omitted. Below, the configuration of the processor 260 will be described.

[0155] The processor 260 functions as, for example, a block control unit 262, a seed value setting unit 264, a data management unit 266, and a processing time measurement unit 268. The processor 260 functions as each of these units by, for example, executing firmware.

[0156] The processing time measurement unit 268 includes, for example, a clock, and outputs the time at which a specific process is performed as processing time information. Specifically, for example, the processing time measurement unit 268 supplies the time as erase time information to the data management unit 266 each time an erase process is performed on any block in the NAND flash memory 100. Alternatively, the processing time measurement unit 268 may output the time as erase time information in response to the memory controller 200 receiving from the NAND flash memory 100 a signal indicating that erasure of data from that block has been completed.

[0157] 3.2 Firmware update process Next, an overview of firmware update processing according to the third embodiment will be described. An example of data processing for firmware update processing in the memory controller 200 in the third embodiment is the same as that in the first embodiment (for example, that described with reference to FIG. 6), and therefore description thereof will be omitted. FIG. 17 shows an overview of header information change processing and seed value setting processing, which are part of the firmware update processing according to the third embodiment. Description of processing not shown in FIG. 17 is omitted, as it is the same as that in the first embodiment. Note that in FIG. 17, arrows drawn with solid lines indicate the flow of data, and arrows drawn with dashed lines and squares indicate processing by the memory controller 200.

[0158] When the update process starts, the block control unit 262 reads header information from the header area of ​​the storage destination block FSB. The read header information is decoded by the ECC circuit 270 and temporarily stored in the buffer memory 240, for example.

[0159] The block control unit 262 performs an erase process on the storage destination block.

[0160] When the block control unit 262 performs the erasure process, the processing time measurement unit 268 supplies the erasure time information to the data management unit 266 ((i) in FIG. 17).

[0161] The data management unit 266 changes the read header information (especially the erasure time information) ((ii) in FIG. 17). At this time, the data management unit 266 refers to the erasure time information supplied from the processing time measurement unit 268. Specifically, the data management unit 266 changes the erasure time information in the header information to the value of the erasure time information supplied from the processing time measurement unit 268, for example. Alternatively, the data management unit 266 may perform processing such as calculation on the supplied erasure time information, and change the erasure time information in the header information to the processed value.

[0162] When randomizing the frame data FD, the seed value setting unit 264 refers to the changed header information and supplies the erasure time information as a seed value to the random number generation circuit 282 ((iii) in FIG. 17). In addition, the seed value setting unit 264 supplies the page address and frame address associated with each frame data FD as a seed value to the random number generation circuit 282 ((iii) in FIG. 17).

[0163] The above is an overview of the firmware update process according to the third embodiment. As explained above, in the firmware update process according to the third embodiment, the memory controller 200 changes the erasure time information included in the header information by referring to the time when the block control unit 262 performed the erasure process on the storage destination block. The memory controller 200 then uses the changed erasure time information as a seed value to perform the randomization process on the updated firmware. That is, in the firmware randomization process, a different seed value is used depending on the erasure time of the storage destination block.

[0164] Next, the flow of firmware update processing according to the third embodiment will be described with reference to FIG. 18. FIG. 18 particularly shows the flow when processing such as that described with reference to FIGS. 6 and 17 is performed. In FIG. 18, steps having the same step numbers as those in the first embodiment (FIG. 8) perform processing equivalent to that described in the first embodiment. Description of these steps will be omitted. Below, the process of determining erasure time information (step S311), the process of changing header information (step S312), and the process of randomizing frame data FD (step S316) will be described.

[0165] In step S311, the memory controller 200 (particularly the processing time measurement unit 268) determines the erasure time information in response to the erasure processing being performed on the storage destination block FSB.

[0166] In step S312, the memory controller 200 refers to the erase time information determined in step S311 and changes the header information (particularly the erase time information) stored in the buffer memory 240.

[0167] In step S316, the memory controller 200 performs randomization processing on the frame data FD in accordance with the processing order determined in step S114, and generates randomized frame data ranFD. The memory controller 200 uses the changed erase time information and the page address and frame address associated with the frame data FD as seed values. The generated randomized frame data ranFD is associated with the page address and frame address associated with the original frame data FD. Note that the memory controller 200 may generate a seed value by performing processing such as calculation on the erase time information, page address, and / or frame address, and use the seed value for the randomization processing. The randomized frame data ranFD is encoded by the ECC circuit 270.

[0168] 3.3 Firmware restoration process Next, firmware restoration processing according to the third embodiment will be described with reference to FIG. 19. FIG. 19 shows the flow of firmware restoration processing according to the third embodiment. FIG. 19 particularly shows the flow of processing when restoring firmware written to the NAND flash memory 100 by the processing described with reference to FIGS. 17 and 18. In FIG. 19, steps having the same step numbers as those in the first embodiment (FIG. 9) perform processing equivalent to that described in the first embodiment. Description of these steps will be omitted. Below, the derandomization processing of the randomized frame data ranFD (step S360) will be described.

[0169] In step S360, the memory controller 200 performs de-randomization processing on the randomized frame data ranFD in accordance with the processing order determined in step S158, to generate frame data FD. The memory controller 200 uses the erase time information included in the header information, and the page address and frame address associated with the randomized frame data ranFD as seed values. Note that the memory controller 200 may generate a seed value by performing processing such as calculation on the erase time information, page address, and / or frame address, and use the seed value in the de-randomization processing.

[0170] As the erasure time information, for example, the power-on time of the memory controller 200 at the time the erasure process is performed may be used. When the power-on time is used as the erasure time information, the process time measurement unit 268 is provided with a timer, and measures the power-on time up to that point each time the erasure process is performed, and outputs the power-on time as the erasure time information. Also, information other than the time and the power-on time can be used as long as it can identify the erasure time.

[0171] 3.4 Effects The memory system according to the third embodiment has the same effects as those of the first embodiment. In addition, the memory system according to the third embodiment has the following effects.

[0172] In the third embodiment, information about when erasure was performed on the storage block is used as the seed value. The erasure time information varies depending on the time the erasure process was performed, for example. This allows the seed value to have randomness without requiring random number generation or the like to generate the seed value.

[0173] 4. Fourth embodiment Next, a memory system according to a fourth embodiment will be described. In the first embodiment, information regarding the number of erases of the storage destination block of the target firmware was used as a seed value in the firmware randomization process. In the fourth embodiment, information regarding the target firmware is used as a seed value in the firmware randomization process. The information regarding the target firmware differs each time update firmware is received. In the following, an example in which information regarding the version of the target firmware is used as a seed value will be particularly described. In the following, descriptions of configurations and operations equivalent to those of the first embodiment may be omitted.

[0174] 4.1 Internal structure of the firmware block First, the internal configuration of the firmware block according to the fourth embodiment will be described. Fig. 20 shows the internal configuration of the firmware block according to the fourth embodiment. As shown in Fig. 20, the header information includes, for example, slot allocation information and information on the version of the firmware stored in the block (hereinafter referred to as FW version information). The FW version information is updated, for example, every time a firmware update process is performed. The FW version information is set to "1", for example, when the memory system 1 is shipped.

[0175] 4.2 Firmware update process Next, an overview of firmware update processing according to the fourth embodiment will be described. An example of data processing for firmware update processing in the memory controller 200 in the fourth embodiment is the same as that in the first embodiment (for example, that described with reference to FIG. 6), and therefore description thereof will be omitted. FIG. 21 shows an overview of header information change processing and seed value setting processing, which are part of the firmware update processing according to the fourth embodiment. Processing not shown in FIG. 21 is the same as that in the first embodiment, and therefore description thereof will be omitted. Note that in FIG. 21, arrows drawn with solid lines indicate data flow, and arrows drawn with dashed lines indicate processing by the memory controller 200. Also, although two buffer memories 240 are shown in FIG. 21, this is for convenience and does not mean that two buffer memories 240 need to be provided.

[0176] When the update process starts, the block control unit 262 reads header information from the header area of ​​the storage destination block FSB. The read header information is decoded by the ECC circuit 270 and temporarily stored in the buffer memory 240, for example.

[0177] The data management unit 266 changes the read header information (particularly, the FW version information) ((i) in FIG. 21). At this time, the data management unit 266 references the update firmware identification information received from the host. Specifically, the data management unit 266 changes the FW version information in the header information to the value of the version information of the update firmware included in the update firmware identification information, for example. Alternatively, the data management unit 266 may perform processing such as calculation on the acquired version information of the update firmware, and change the FW version information in the header information to the processed value.

[0178] When randomizing the frame data FD, the seed value setting unit 264 refers to the changed header information and supplies the FW version information as a seed value to the random number generation circuit 282 ((ii) in FIG. 21). The seed value setting unit 264 also supplies the page address and frame address associated with each frame data FD as a seed value to the random number generation circuit 282 ((ii) in FIG. 21).

[0179] The above is an overview of the firmware update process according to the fourth embodiment. As described above, in the firmware update process according to the fourth embodiment, the memory controller 200 changes the FW version information included in the header information and performs randomization processing of the updated firmware using the changed FW version information as a seed value. That is, in the firmware randomization processing, a different seed value is used for each firmware update processing.

[0180] Next, the flow of firmware update processing according to the fourth embodiment will be described with reference to Fig. 22. Fig. 22 particularly shows the flow when performing the processing described with reference to Figs. 6 and 21. In Fig. 22, steps having the same step numbers as those in the first embodiment (Fig. 8) perform processing equivalent to that described in the first embodiment. Description of these steps will be omitted. Below, the header information change processing (step S412) and the frame data FD randomization processing (step S416) will be described.

[0181] In step S412, the memory controller 200 refers to the update firmware identification information received from the host, and changes the header information (particularly, the FW version information) stored in the buffer memory 240.

[0182] In step S416, the memory controller 200 performs randomization processing on the frame data FD in accordance with the processing order determined in step S114, and generates randomized frame data ranFD. The memory controller 200 uses the changed FW version information and the page address and frame address associated with the frame data FD as seed values. The generated randomized frame data ranFD is associated with the page address and frame address associated with the original frame data FD. Note that the memory controller 200 may generate a seed value by performing processing such as calculation on the FW version information, page address, and / or frame address, and use the seed value for the randomization processing. The randomized frame data ranFD is encoded by the ECC circuit 270.

[0183] 4.3 Firmware restoration process Next, firmware restoration processing according to the fourth embodiment will be described with reference to FIG. 23. FIG. 23 shows the flow of firmware restoration processing according to the fourth embodiment. FIG. 23 particularly shows the flow of processing when restoring firmware written to the NAND flash memory 100 by the processing described with reference to FIGS. 21 and 22. In FIG. 23, steps having the same step numbers as those in the first embodiment (FIG. 9) perform processing equivalent to that described in the first embodiment. Description of these steps will be omitted. Below, the derandomization processing of the randomized frame data ranFD (step S460) will be described.

[0184] In step S460, the memory controller 200 performs de-randomization processing on the randomized frame data ranFD in accordance with the processing order determined in step S158, and generates frame data FD. The memory controller 200 uses the FW version information included in the header information, and the page address and frame address associated with the randomized frame data ranFD as seed values. Note that the memory controller 200 may generate a seed value by performing processing such as calculation on the FW version information, page address, and / or frame address, and use the seed value for the de-randomization processing.

[0185] 4.4 Effects The memory system according to the fourth embodiment has the same effects as those of the first embodiment. In addition, the memory system according to the fourth embodiment has the following effects.

[0186] In the fourth embodiment, information about the firmware version is used as a seed value. Since the FW version information is changed every time the firmware is updated, the seed value used in the randomization process performed on the data to be written can be changed before and after the erasure operation in the firmware update process.

[0187] In the fourth embodiment, the case where FW version information is used as a seed value is described as an example of information related to the target firmware. However, this is not limiting. That is, for example, the memory controller 200 may refer to other information included in the identification information of the updated firmware or at least a portion of the updated firmware and use it as a seed value. Alternatively, the memory controller 200 may use the number of firmware updates or the firmware update time as a seed value. The randomization process using the number of firmware updates as a seed value can be realized, for example, by a configuration similar to that described in the first embodiment. Furthermore, the randomization process using the firmware update time as a seed value can be realized, for example, by a configuration similar to that described in the third embodiment.

[0188] 5. Fifth embodiment Next, a memory system according to a fifth embodiment will be described. In the memory systems according to the above embodiments, one firmware block is provided with one slot for storing firmware. In the memory system according to the fifth embodiment, one firmware block is provided with multiple slots. In the following, an example in which erase count information of the storage block is used as a seed value during firmware randomization processing in such a memory system will be described in comparison with the first embodiment. In addition, in the following, descriptions of configurations and operations equivalent to those of the first embodiment may be omitted.

[0189] 5.1 Configuration First, a schematic configuration of data stored in blocks BLK according to the fifth embodiment will be described with reference to Fig. 24. Fig. 24 shows an example in which the memory system 1 is configured so that six pieces of firmware are stored in three firmware blocks.

[0190] Blocks 1 to 3 are firmware blocks. In the firmware block in the fifth embodiment, two slots and one header area are provided within one block. In the example of FIG. 24, slots 1 and 2 for storing firmware 1 and 2 and header area 1 are provided in block 1. Similarly, slots 3 and 4 for storing firmware 3 and 4 and header area 2 are provided in block 2. Furthermore, slots 5 and 6 for storing firmware 5 and 6 and header area 3 are provided in block 3.

[0191] Blocks 4 to n (where n is a natural number equal to or greater than 5) are blocks for user data.

[0192] Next, the internal configuration of a firmware block according to the fifth embodiment will be described with reference to Fig. 25. As shown in Fig. 25, the header information includes, for example, the number of slots included in the block (hereinafter referred to as the number of slots), FW information read at startup, slot allocation information, and erase count information. The FW information read at startup is information indicating which firmware is read from the firmware block when the memory system is started up. The slot allocation information indicates the location of an area set as each slot included in the firmware block, and includes, for example, a pair of a slot address and a page address corresponding to the slot address. Alternatively, the slot allocation information includes a pair of a slot address and a page address and frame address corresponding to the slot address.

[0193] The number of slots provided in one firmware block is not limited to two, but may be three or more.

[0194] 5.2 Firmware update process Next, an overview of firmware update processing according to the fifth embodiment will be described. An example of data processing for firmware update processing in the memory controller 200 in the fifth embodiment is the same as that in the first embodiment (for example, that described with reference to FIG. 6), and therefore a description thereof will be omitted. FIG. 26 shows an overview of firmware update processing according to the fifth embodiment. FIG. 26 particularly shows an example in which one firmware block has two slots (slots 1 and 2). Note that in FIG. 26, solid arrows indicate data flow, and dashed arrows and squares indicate processing by the memory controller 200. Also, although two buffer memories 240 are shown in FIG. 26, this is for convenience and does not mean that two buffer memories 240 are required. Also, a description of the processing described in the first embodiment may be omitted.

[0195] When the update process is started, the block control unit 262 reads header information from the header area of ​​the firmware block (storage destination block FSB) that includes the storage destination slot where the updated firmware UFW is stored ((i) in FIG. 26). The read header information is decoded by the ECC circuit 270 and temporarily stored in, for example, the buffer memory 240. Note that in FIG. 26, the number of slots, startup read FW information, and slot allocation information included in the header information are omitted.

[0196] The block control unit 262 reads page data PD from a slot (hereinafter referred to as a non-updated slot) other than the storage destination slot included in the storage destination block FSB ((ii) in FIG. 26). Hereinafter, during the firmware update process, data read from a non-updated slot and data derived from that data may be suffixed with "rd". In the example of FIG. 26, page data PDrd is read from slot 2, which is a slot other than the storage destination slot (slot 1). The read page data PD is temporarily stored in, for example, the buffer memory 240. Note that if there are multiple non-updated slots in the storage destination block FSB, the above process is performed for all of the non-updated slots (the same applies hereinafter).

[0197] The data management unit 266 divides the read page data PDrd to generate randomized frame data ranFDrd ((iii) in FIG. 26). The randomized frame data ranFDrd is decoded by the ECC circuit 270.

[0198] The randomization circuit 280 sequentially performs de-randomization processing on the randomized frame data ranFDrd to generate frame data FDrd (FIG. 26(iv)).

[0199] When de-randomizing the randomized frame data ranFDrd, the seed value setting unit 264 references the header information and supplies the erase count information as a seed value to the randomization circuit 280 (particularly the random number generation circuit 282). That is, the de-randomization process of the randomized frame data ranFDrd is performed using the erase count information before it is changed. The seed value setting unit 264 also supplies the page address and frame address associated with each piece of randomized frame data ranFDrd to the randomization circuit 280 as seed values.

[0200] The block control unit 262 performs an erase process on the storage destination block.

[0201] The data management unit 266 changes the read header information, particularly the erase count information included in the header information ((v) in FIG. 26).

[0202] The randomization circuit 280 sequentially performs randomization processing on the frame data FDrd to generate randomized frame data ranFDrd# (FIG. 26(vi)).

[0203] When randomizing the frame data FDrd, the seed value setting unit 264 references the changed header information and supplies the erase count information as a seed value to the random number generation circuit 282. That is, the frame data FDrd is randomized using the changed erase count information. The seed value setting unit 264 also supplies the page address and frame address associated with each frame data FDrd to the random number generation circuit 282 as a seed value. The randomized frame data ranFDrd# is encoded by the ECC circuit 270.

[0204] The data management unit 266 combines the generated randomized frame data ranFDrd# to generate page data PDrd# ((vii) in FIG. 26).

[0205] The block control unit 262 writes the page data PDrd# to the corresponding page in the storage destination block ((viii) in FIG. 26). In the example of FIG. 26, the page data PDrd# is written to the corresponding page in slot 2.

[0206] Furthermore, the block control unit 262 writes the changed header information into the header area of ​​the storage destination block.

[0207] The updated firmware UFW undergoes various processes by the memory controller 200 before or after the above processes, or in parallel with the above processes, and is written to the storage destination slot. The processing for the updated firmware is the same as that in the first embodiment, so a description thereof will be omitted.

[0208] The above is an overview of the firmware update process according to the fifth embodiment. As explained above, in the firmware update process according to the fifth embodiment, the memory controller 200 reads firmware (page data PD) stored in a non-update slot. The memory controller 200 also performs a de-randomization process on the read firmware using the erase count information before the change, and restores the firmware. The restored firmware is then randomized using the erase count information after the change, and written to the original slot. That is, even in the randomization process of firmware stored in a non-update slot, a different seed value is used for each firmware update process (or erase operation of the storage destination block).

[0209] Next, the flow of firmware update processing according to the fifth embodiment will be described with reference to Fig. 27. In particular, Fig. 27 shows the flow when performing the processing described with reference to Figs. 6 and 26.

[0210] In addition, in Figure 27, the processing steps for update firmware (steps S106, S108, S114, S116, S118 and S120 in the first embodiment (Figure 8)) are not shown. These steps are performed before or after the flow described below, or in parallel with the flow. For these steps, the same processing as that described in the first embodiment is performed, so the explanation will be omitted. Also, for steps in Figure 27 that are numbered the same as the step numbers in the first embodiment (Figure 8), the same processing as that described in the first embodiment is performed. Explanation of these steps may be omitted. Below, the processing for firmware stored in a non-update slot will be mainly explained.

[0211] In step S524, the memory controller 200 refers to the destination slot address included in the update firmware identification information and the slot allocation information of the header information read from the destination block FSB, and identifies the page address (hereinafter referred to as the non-update page address) and frame address of the non-update slot in the destination block FSB.

[0212] In step S526, the memory controller 200 reads the page data PDrd from the area corresponding to the non-update page address in the NAND flash memory 100. The read page data PD is temporarily stored in the buffer memory 240, for example.

[0213] In step S528, the memory controller 200 divides the page data PDrd read in step S526 to generate randomized frame data ranFDrd. Each randomized frame data ranFDrd is associated with a page address corresponding to the original page data PDrd and a frame address indicating a position within the original page data PDrd. Each randomized frame data ranFDrd is decoded by the ECC circuit 270.

[0214] In step S530, the memory controller 200 determines the order in which the de-randomization process is to be performed on the randomized frame data ranFDrd. Note that the de-randomization process may be performed in parallel on several pieces of randomized frame data ranFDrd.

[0215] In step S532, the memory controller 200 performs de-randomization processing on the randomized frame data ranFDrd in accordance with the processing order determined in step S530, to generate frame data FDrd. The memory controller 200 uses the erase count information included in the header information and the page address and frame address associated with the randomized frame data ranFDrd as seed values. Note that the memory controller 200 may generate a seed value by performing processing such as calculation on the erase count information, page address, and / or frame address, and use the seed value in the de-randomization processing.

[0216] In step S110, the memory controller 200 performs an erase process on the storage destination block FSB.

[0217] In step S112, the memory controller 200 changes the header information stored in the buffer memory 240 (particularly, the erase count information).

[0218] In step S534, the memory controller 200 determines the order in which randomization processing is to be performed on the frame data FDrd. Note that the randomization processing may be performed on several frame data FDrds in parallel. The memory controller 200 may also apply the processing order determined in step S530 to the randomization processing on the frame data FDrd.

[0219] In step S536, the memory controller 200 performs randomization processing on the frame data FDrd in accordance with the processing order determined in step S534, and generates randomized frame data ranFDrd#. The memory controller 200 uses the changed erase count information and the page address and frame address associated with the frame data FDrd as seed values. The generated randomized frame data ranFDrd# is associated with the page address and frame address associated with the original frame data FDrd. Note that the memory controller 200 may generate a seed value by performing processing such as calculation on the erase count information, page address, and / or frame address, and use the seed value for the randomization processing. The randomized frame data ranFDrd# is encoded by the ECC circuit 270.

[0220] In step S538, the memory controller 200 combines the randomized frame data ranFDrd# associated with the same page address to generate page data PDrd#. The page data PDrd# is generated, for example, in ascending order of the page addresses included in the storage destination slot.

[0221] In step S540, the memory controller 200 writes the page data PDrd# to the NAND flash memory 100. The page data PDrd# is written to an area of ​​the storage destination block FSB indicated by the page address corresponding to each page data PDrd#.

[0222] Note that, when multiple pieces of update firmware are received from the host at once and are stored in different storage destination slots within the same storage destination block FSB, the memory controller 200 does not need to perform a series of firmware update processes for each piece of update firmware. Specifically, for example, in a firmware update process involving a single erase process of the storage destination block FSB, the memory controller 200 may perform data processing on multiple pieces of update firmware and write the update firmware to the storage destination slots corresponding to each piece of update firmware. In other words, the memory controller 200 does not need to perform erase processes on the storage destination block FSB a number of times equal to the number of update firmware pieces stored in the storage destination block FSB. In this case, the memory controller 200 performs the firmware update process by regarding the remaining slots included in the storage destination block FSB, excluding the storage destination slots for the multiple pieces of update firmware, as non-update slots.

[0223] 5.3 Firmware restoration process The firmware restoration process is the same as that described in the first embodiment, and therefore a detailed description thereof will be omitted. Note that in the process of identifying the page address and frame address of the read target slot (corresponding to step S152 in the first embodiment (FIG. 9)), the memory controller 200 refers to the startup read FW information in addition to the slot allocation information in the header information.

[0224] In the firmware randomization and de-randomization processes, the memory controller 200 uses common erase count information as a seed value for multiple firmwares stored in the storage destination block FSB, but this is not limited to this. That is, for example, multiple erase count information corresponding to each slot may be stored as header information, and randomization and de-randomization processes may be performed using different erase count information for each slot. Alternatively, a seed value may be generated by performing a different calculation or other process for each slot on the common erase count information, and used for the randomization and de-randomization processes.

[0225] 5.4 Effects The memory system according to the fifth embodiment has the same effects as those of the first embodiment. In addition, the memory system according to the fifth embodiment has the following effects.

[0226] When one of the multiple firmwares stored in a firmware block is updated, the firmware that is not the target of the update is rewritten with the same firmware as before the erase operation for that block. Therefore, if the firmware randomization process is performed using a fixed value as a seed value, the same cell data will be programmed before and after the erase operation for each memory cell corresponding to the slot where the firmware that is not the target of the update is stored.

[0227] In the fifth embodiment, the erase count information of the block to be written or read is used as a seed value. Therefore, the seed value used in the randomization process performed on firmware that is not the target of update can be changed before and after the erase operation. This prevents the same value from being repeatedly programmed into the same memory cell in slots other than the storage slot during the firmware update process, thereby suppressing a decrease in the reliability of the NAND flash memory.

[0228] Furthermore, in the fifth embodiment, firmware for a plurality of slots is stored in one block, so the number of blocks that need to be reserved as firmware blocks can be reduced.

[0229] In the fifth embodiment, an example has been described in which erase count information is used as a seed value in a memory system 1 in which a firmware block has multiple slots, but this is not limiting. That is, in such a memory system 1, total erase count information, erase time, or information related to firmware can be used as a seed value, as described in the second to fourth embodiments. In addition, when information related to firmware is used as a seed value, for example, the effect of the fifth embodiment can be obtained by using the total value of information related to multiple firmware pieces stored in the firmware block as the seed value.

[0230] 6. Sixth embodiment Next, a memory system according to a sixth embodiment will be described. In the sixth embodiment, header information is randomized and stored in the header area. In the following, the description of the same configuration and operation as the first embodiment may be omitted.

[0231] 6.1 Overview The randomized and stored header information is de-randomized when it is read. However, the header information of the firmware block may be the first data read from the NAND flash memory 100 after the memory system 1 is started up. Therefore, the seed value used for the header information de-randomization process needs to be data stored in an area other than the NAND flash memory 100. In the sixth embodiment, an example will be described in which a randomization key (hereinafter referred to as a ROM key) included in the IPL is used as the header information randomization process and the seed value for the de-randomization process.

[0232] 6.2 Header Information Writing Process First, the header information write process according to the sixth embodiment will be described. In the sixth embodiment, the memory controller 200 performs a randomization process on the header information when writing the header information to the NAND flash memory 100. At this time, the memory controller 200 performs the randomization process using the ROM key as a seed value. An example of the data processing performed on the header information is the same as the data processing performed on the update firmware in the first embodiment (for example, the one described with reference to FIG. 6).

[0233] An overview of the header information write process according to the sixth embodiment will be described with reference to Fig. 28. Below, an example will be described in which the header area is set to one page in the firmware block. Note that, below, data derived from header information may have an "h" added to the end.

[0234] When the header information write process starts, the data management unit 266 divides and / or pads the header information to generate frame data FDh ((i) in FIG. 28).

[0235] The randomization circuit 280 sequentially performs randomization processing on the generated frame data FDh to generate randomized frame data ranFDh ((ii) in FIG. 28). When randomizing the frame data FDh, the seed value setting unit 264 references the IPL and supplies the ROM key as a seed value to the randomization circuit 280. The randomized frame data ranFDh is encoded by the ECC circuit 270.

[0236] The data management unit 266 combines the generated randomized frame data ranFDh to generate page data PDh ((iii) in FIG. 28).

[0237] The block control unit 262 writes the page data PDh to the header area ((iv) in FIG. 28).

[0238] The above is an overview of the header information write process according to embodiment 6. As described above, in the header information write process according to embodiment 6, the memory controller 200 performs randomization processing on the header information using a ROM key.

[0239] Next, the flow of header information writing processing according to the sixth embodiment will be described with reference to Fig. 29. Fig. 29 particularly shows the flow when performing the processing described with reference to Fig. 28. The following flow is performed, for example, in firmware update processing. Specifically, for example, writing of header information in the firmware update processing according to the first embodiment (step S122 in Fig. 8) is replaced with the following write processing flow.

[0240] In step S600, the memory controller 200 divides and / or pads the header information to generate frame data FDh.

[0241] In step S602, the memory controller 200 determines the order in which the randomization process is to be performed on the frame data FDh. Note that the randomization process may be performed on several frame data FDh in parallel.

[0242] In step S604, the memory controller 200 performs randomization processing on the frame data FDh in accordance with the processing order determined in step S602, to generate randomized frame data ranFDh. The memory controller 200 uses the ROM key included in the IPL as a seed value. Note that the memory controller 200 may also generate a seed value by performing processing such as calculation on the ROM key, and use the seed value for the randomization processing. The randomized frame data ranFD is encoded by the ECC circuit 270.

[0243] In step S606, the memory controller 200 combines the randomized frame data ranFDh to generate page data PDh.

[0244] In step S608, the memory controller 200 writes the page data PDh to the NAND flash memory 100. The page data PD is written to the header area of ​​the storage destination block FSB.

[0245] The header information writing process is completed.

[0246] In step S606, the memory controller 200 acquires the ROM key by referring to the IPL and performs the randomization process, but this is not limiting. For example, the ROM key may be included in the update program UDP, and the memory controller 200 may acquire the ROM key by referring to the update program UDP.

[0247] 6.3 Header information reading process Next, a header information read process according to the sixth embodiment will be described with reference to Fig. 30. Fig. 30 shows a flow of the header information read process according to the sixth embodiment. Fig. 30 particularly shows a process flow for reading header information written to the NAND flash memory 100 by the process described with reference to Figs. 28 and 29. The following flow is performed, for example, in firmware restoration processing. Specifically, for example, reading the header information in the firmware restoration processing according to the first embodiment (step S150 in Fig. 9) is replaced with the following read processing flow.

[0248] In step S650, the memory controller 200 reads the page data PDh from the header area of ​​the storage destination block. The address of the header area is specified by referring to the IPL.

[0249] In step S652, the memory controller 200 divides the page data PDh read in step S650 to generate randomized frame data ranFDh. Each randomized frame data ranFDh is decoded by the ECC circuit 270.

[0250] In step S654, the memory controller 200 determines the order in which the de-randomization process is to be performed on the randomized frame data ranFDh. Note that the de-randomization process may be performed in parallel on several pieces of randomized frame data ranFDh.

[0251] In step S656, the memory controller 200 performs de-randomization processing on the randomized frame data ranFDh in accordance with the processing order determined in step S654, to generate frame data FDh. The memory controller 200 uses the ROM key included in the IPL as a seed value. Note that the memory controller 200 may generate a seed value by performing processing such as calculation on the ROM key, and use the seed value in the de-randomization processing.

[0252] In step S658, the memory controller 200 combines the frame data FDh restored in step S656 to generate header information.

[0253] The header information reading process is completed.

[0254] 6.4 Effects The memory system according to the sixth embodiment has the following advantages.

[0255] In the sixth embodiment, header information is subjected to a randomization process before being written to the NAND flash memory 100. This makes it possible to prevent concentration of data patterns in the data written to the header area.

[0256] The header information write and read processes described in the sixth embodiment can be applied to any of the configurations described in the first to fifth embodiments.

[0257] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are intended to be included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0258] 1...Memory system, 100...NAND flash memory, 200...Memory controller, 300...Host, 110...Memory cell array, 120...Row decoder, 130...Driver, 140...Sense amplifier module, 150...Address register, 160...Command register, 170...Sequencer, 210...Host interface circuit, 220...RAM, 230...ROM, 240...Buffer memory, 250...NAND interface circuit, 260...Processor, 262...Block control unit, 264...Seed value setting unit, 266...Data management unit, 268...Processing time measurement unit, 270...ECC circuit, 280...Randomization circuit, 282...Random number generation circuit, 284...XOR circuit

Claims

1. 1. A memory system connectable to a host, comprising: a first nonvolatile memory including a plurality of blocks, each of which is a unit of a data erase operation; a controller electrically connected to the first non-volatile memory and configured to control the first non-volatile memory; The controller receives first data from the host; generating third data from the first data by randomizing the first data using second data that varies depending on the number of times the erase operation has been performed on a first block that is one of the plurality of blocks; configured to write the third data to the first block; Memory system.

2. the second data also differs depending on the number of times the erase operation has been performed on a second block of the plurality of blocks; 10. The memory system of claim 1.

3. 1. A memory system connectable to a host, comprising: a first nonvolatile memory including a plurality of blocks, each of which is a unit of a data erase operation; a controller electrically connected to the first non-volatile memory and configured to control the first non-volatile memory; The controller receives first data from the host; generating third data from the first data by randomizing the first data using second data that varies depending on the timing of the erase operation executed on a first block that is one of the plurality of blocks; configured to write the third data to the first block; Memory system.

4. 1. A memory system connectable to a host, comprising: a first nonvolatile memory including a plurality of blocks, each of which is a unit of erasing data; a controller electrically connected to the first non-volatile memory and configured to control the first non-volatile memory; The controller receives first data from the host; generating third data from the first data by randomizing the first data using second data that differs each time the first data is received; configured to write the third data to a first block that is one of the plurality of blocks; Memory system.

5. the second data is at least a part of identification information of the first data; 5. The memory system of claim 4.

6. the second data is version information of the first data; 6. The memory system of claim 5.

7. the first data is first firmware; the second data is included in information used in an update process or a restoration process of the first firmware; 7. The memory system according to claim 1.

8. the controller is further configured to write the second data to the first non-volatile memory.

7. The memory system according to claim 1.

9. the controller is configured to write the second data to the first block; 9. The memory system of claim 8.

10. The controller writing the third data to a first area of ​​the first block; configured to write the second data to a second area of ​​the first block, the second area being different from the first area; 10. The memory system of claim 9.

11. The controller further comprises: reading the written second data and the third data from the first nonvolatile memory; The readout second data is used to derandomize the third data, thereby restoring the first data from the third data.

9. The memory system of claim 8.

12. The controller further comprises: generating fifth data from the fourth data by randomizing the fourth data using the second data; writing the third data to a first area of ​​the first block; The fifth data is configured to be written to a third area of ​​the first block, the third area being different from the first area.

12. The memory system of claim 11.

13. In response to receiving an update request for data stored in the first area from the host, the controller: receiving sixth data from the host; generating eighth data from the sixth data by randomizing the sixth data using seventh data different from the second data used in the randomization process of the first data; generating ninth data from the fourth data by randomizing the fourth data using the seventh data; writing the seventh data to the first block; writing the eighth data to the first area of ​​the first block; configured to write the ninth data to the third area of ​​the first block; 13. The memory system of claim 12.

14. The controller reading the written second data and the fifth data from the first block; derandomizing the fifth data using the read second data to restore the fourth data from the fifth data; The method is configured to generate the ninth data from the fourth data by randomizing the fourth data using the seventh data.

14. The memory system of claim 13.

15. further comprising a second non-volatile memory in which the first key is stored; The controller further comprises: electrically connected to the second nonvolatile memory; generating tenth data from the second data by randomizing the second data using the first key; configured to write the tenth data to the first non-volatile memory; 7. The memory system according to claim 1.

16. The controller reading the first key from the second non-volatile memory; reading the third data from the first block; reading the tenth data from the first nonvolatile memory; recovering the second data from the tenth data by derandomizing the tenth data using the first key; configured to recover the first data from the third data by derandomizing the third data using the second data; 16. The memory system of claim 15.

17. Each of the plurality of blocks includes a memory cell; the plurality of blocks includes a third block different from the first block, The controller configured to write data having a number of bits smaller than the number of bits of data written to the memory cells of the third block to the memory cells of the first block; 7. The memory system according to claim 1.

18. In response to receiving a command from the host instructing writing of the first data, the controller: configured to write the third data to the first block after performing an erase operation on the first block; 7. The memory system according to claim 1.

19. 1. A memory system connectable to a host, comprising: a first nonvolatile memory including a plurality of blocks, each of which is a unit of a data erase operation; a controller electrically connected to the first non-volatile memory and configured to control the first non-volatile memory; each of the plurality of blocks includes a first memory cell and a second memory cell; The controller receives first data from the host; generating third data from the first data by randomizing the first data using a second key; writing at least a portion of the second key into the first memory cell of a first block that is one of the plurality of blocks; configured to write at least a portion of the third data to the second memory cells of the first block; the second key is variable; Memory system.

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