Memory system

Abstract

To provide a memory system that improves data readout performance.SOLUTION: A memory system comprises a nonvolatile memory 10, and a memory controller 20 including a first cache 23, a second cache 24 and a first controller 202. The first cache includes a first memory part 32 and a first cache control part 301. A second cache includes a second memory part 42 and a second cache control part 401. The first memory part includes a plurality of entries each having a cache tag and a cache line including a first field. When receiving a first prefetch request PR for first data in a first logical address, the first cache control part stores the first data in a cache line of a first entry included in the first memory part, stores a first value in a first field of the first entry, and maintains the first entry until a read request RR or write request WR for the first logical address is received from a host.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to a memory system. [Background technology]

[0002] 2. Description of the Related Art A memory system is known that includes a NAND flash memory as a nonvolatile memory and a memory controller that controls the nonvolatile memory. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2023 / 0214326 [Patent Document 2] US Patent Application Publication No. 2023 / 0185740 [Patent Document 3] US Patent Application Publication No. 2023 / 0017643 Summary of the Invention [Problem to be solved by the invention]

[0004] A memory system capable of improving data read performance is provided. [Means for solving the problem]

[0005] A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The memory controller includes a first cache connectable to a host, a second cache connected to the first cache, and a first controller that controls the nonvolatile memory. The first cache includes a first memory unit that has SRAM as a storage element and stores prefetch data and read data from the nonvolatile memory, and a first control unit that controls the first memory unit. The second cache includes a second memory unit that has DRAM as a storage element and stores read data and write data from the host, and a second control unit that controls the second memory unit. Multiple logical addresses specified by the host are mapped to the first memory unit using indexes. The first memory unit includes multiple entries, each having tag information of the index and including a cache tag including a first field and a cache line. When the first control unit receives a first prefetch request for first data at a first logical address, the first control unit stores the prefetched first data in a cache line of a first entry included in the first memory unit, and stores a first value indicating that the first data is prefetched data in a first field of the first entry. The first control unit maintains the first entry until it receives a read request or a write request for the first logical address from the host. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of an information processing system including a memory system according to a first embodiment. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of a nonvolatile memory included in the memory system according to the first embodiment. [Figure 3] FIG. 2 is a block diagram showing an example of the hardware configuration of a memory controller included in the memory system according to the first embodiment. [Figure 4] FIG. 2 is a diagram showing an example of the configuration of an L2P table used in the memory system according to the first embodiment. [Figure 5]FIG. 2 is a diagram showing an example of the configuration of a memory unit of a first cache included in the memory system according to the first embodiment. [Figure 6] FIG. 2 is a diagram showing an example of the configuration of a memory unit of a second cache included in the memory system according to the first embodiment. [Figure 7] FIG. 2 is a block diagram showing an example of the functional configuration of a memory controller included in the memory system according to the first embodiment. [Figure 8] FIG. 2 is a diagram showing an example of state transition of a cache tag of a target entry in a memory unit of a first cache included in the memory system according to the first embodiment. [Figure 9] FIG. 10 is a block diagram showing an example of the functional configuration of a memory controller included in a memory system according to a first modification of the first embodiment. [Figure 10] FIG. 10 is a block diagram showing an example of the functional configuration of a memory controller included in a memory system according to a second modification of the first embodiment. [Figure 11] FIG. 10 is a block diagram showing an example of the hardware configuration of a memory controller included in a memory system according to a second embodiment. [Figure 12] FIG. 10 is a diagram showing an example of the configuration of a memory unit of a first cache included in a memory system according to a second embodiment. [Figure 13] FIG. 10 is a block diagram showing an example of the functional configuration of a memory controller included in a memory system according to a second embodiment. [Figure 14] FIG. 11 is a diagram showing an example of state transition of a cache tag of a target entry in a memory unit of a first cache included in a memory system according to a second embodiment. [Figure 15] FIG. 11 is a diagram showing an example of the configuration of a memory unit of a first cache included in a memory system according to a third embodiment. [Figure 16] 10A and 10B are diagrams illustrating the relationship between the management size of the L2P table and the size of a cache line in the memory unit of the first cache in the memory system according to the third embodiment. [Figure 17] 10 is a flowchart showing an example of the operation of a first cache included in the memory system according to the fourth embodiment. [Figure 18]10 is a flowchart showing an example of the operation of a second cache included in the memory system according to the fourth embodiment. [Figure 19] 10 is a flowchart showing an example of the operation of a second cache included in the memory system according to the fourth embodiment. [Figure 20] 10 is a flowchart showing an example of the operation of a second cache included in the memory system according to the fourth embodiment. [Figure 21] 10 is a flowchart showing an example of the operation of a first cache included in the memory system according to the fourth embodiment. [Figure 22] 10 is a flowchart showing an example of the operation of a first cache included in the memory system according to the fourth embodiment. [Figure 23] 10 is a flowchart showing an example of the operation of a first cache included in the memory system according to the fourth embodiment. [Figure 24] 10 is a flowchart showing an example of the operation of a first cache included in the memory system according to the fourth embodiment. [Figure 25] 10 is a flowchart showing an example of the operation of a second cache included in the memory system according to the fourth embodiment. [Figure 26] 10 is a flowchart showing an example of the operation of a first cache included in the memory system according to the fourth embodiment. [Figure 27] 10 is a flowchart showing an example of the operation of a second cache included in the memory system according to the fourth embodiment. [Figure 28] 13 is a flowchart showing an example of the operation of a first cache included in the memory system according to the fifth embodiment. [Figure 29] 13 is a flowchart showing an example of the operation of a first cache included in the memory system according to the sixth embodiment. [Figure 30] 13 is a flowchart showing an example of the operation of a second cache included in the memory system according to the sixth embodiment. [Figure 31] 13 is a flowchart showing an example of the operation of a first cache included in the memory system according to the sixth embodiment. [Figure 32]13 is a flowchart showing an example of the operation of a second cache included in the memory system according to the sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having substantially the same functions and configurations will be designated by the same reference numerals. When particularly distinguishing between elements having similar configurations, different letters or numbers may be added to the end of the same reference numerals.

[0008] 1. First embodiment 1.1 Configuration 1.1.1 Information Processing System Configuration The configuration of an information processing system including a memory system according to the first embodiment will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the configuration of an information processing system including a memory system according to the first embodiment. As shown in Fig. 1, the information processing system 1 includes a host 2 and a memory system 3. The host 2 and the memory system 3 are connected via a host bus HB.

[0009] The host 2 is a device that controls the memory system 3. The host 2 is a system including a processor and main memory provided in an information processing device that operates as a host, and is configured to be able to access the memory system 3. The processor that constitutes the host 2 is, for example, a multi-core processor, and is configured to execute multiple programs (application programs) in parallel.

[0010] The memory system 3 is a memory device that stores various data that is accessed (loaded or stored) by the host 2 that executes, for example, an application program. A bus (host bus HB) that connects the host 2 and the memory system 3 is, for example, a CXL (Compute Express Link TMThe memory system 3 is a CXL bus that complies with the PCI Express (PCIe) standard. CXL is a standard based on PCI Express (PCIe), and the memory system 3 is accessed by the host 2 in accordance with a protocol that allows access to a PCIe device called CXL.mem by a load command or a store command. In the explanation of this specification, a load command is referred to as a "read request from the host (or simply a read request)" and a store command is referred to as a "write request from the host (or simply a write request)."

[0011] In this embodiment, the description will be mainly focused on the memory system 3 connected to the host 2 via a CXL bus, but the memory system 3 may also be a memory device connected to the host 2 via a bus conforming to another standard.

[0012] The memory system 3 has a nonvolatile memory and has intermediate performance between a main memory mainly composed of DRAM (Dynamic Random Access Memory) and a storage device (e.g., SSD (Solid State Drive)) composed of NAND flash memory. Specifically, the storage capacity of the memory system 3 is larger than that of the main memory, and the access speed to the memory system 3 is faster than that of the storage device. In this embodiment, by using such a memory system 3, it is possible to substantially increase the capacity of the main memory. However, since the memory system 3 has a longer latency (delay time) when reading data from the nonvolatile memory than the DRAM that mainly constitutes the main memory, a mechanism for improving the read performance of the memory system 3 is required.

[0013] The host 2 and memory system 3 are configured to communicate a minimum of 64 bytes (B) of data. Hereinafter, the minimum data transfer unit in data communication between the host 2 and memory system 3 will also be referred to as "access granularity."

[0014] The host 2 manages the logical address space with a logical address LA corresponding to the access granularity. The logical address space is a memory address space used by the host 2 to access the memory system 3. When the access granularity is 64B (=2 6 B), the capacity of the logical address space (i.e., the capacity of the memory system 3 visible to the host 2) is 256 GB (= 2 38 In the case of B), the logical address space is expressed by a logical address LA of 32 (=38-6) bits or more. In the following description, it is assumed that the bit width of the logical address LA is K bits (K is an integer of 2 or more).

[0015] 1.1.2 Memory System Configuration Next, the internal configuration of the memory system 3 will be described. As shown in Fig. 1, the memory system 3 includes a nonvolatile memory 10 and a memory controller 20. The nonvolatile memory 10 and the memory controller 20 are connected via a memory bus MB. Communication between the nonvolatile memory 10 and the memory controller 20 complies with, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0016] The nonvolatile memory 10 includes, for example, one or more NAND chips (NAND flash memories). The nonvolatile memory 10 has a physical memory area associated with a physical address space. The physical address space is an address space indicating multiple storage locations in the physical memory area in the nonvolatile memory 10 (one or more NAND chips). A physical address PA is an address used by the memory controller 20 to access the physical address space. The following description will be given taking as an example a case where the nonvolatile memory 10 includes multiple NAND chips.

[0017] FIG. 2 is a block diagram showing an example of the configuration of the nonvolatile memory 10. As shown in FIG. 2, the nonvolatile memory 10 includes a plurality of NAND chips CP0 to CPm (m is an integer equal to or greater than 1). Hereinafter, when the NAND chips CP0 to CPm are not distinguished from one another, they will simply be referred to as NAND chips CP. Each of the NAND chips CP includes a memory cell array MCA. The memory cell array MCA includes a plurality of blocks BLK0 to BLKn (n is an integer equal to or greater than 1). Hereinafter, when the blocks BLK0 to BLKn are not distinguished from one another, they will simply be referred to as blocks BLK. Each of the plurality of blocks BLK includes a plurality of pages PG. Each of the plurality of pages PG includes a plurality of memory cells MC. The plurality of memory cells MC store data in a nonvolatile manner. A block BLK is, for example, a unit for erasing data. A page PG is, for example, a unit for writing and reading data. The size of a page PG is, for example, 4 KB or 16 KB.

[0018] Referring again to FIG. 1, the memory controller 20 will be described. The memory controller 20 is configured, for example, by an integrated circuit such as an SoC (System-on-a-Chip). The memory controller 20 controls the nonvolatile memory 10 based on a request from the host 2. Specifically, when the memory controller 20 receives a write request WR from the host 2, it writes data to be written (write data WD) to the nonvolatile memory 10. When the memory controller 20 receives a read request RR from the host 2, it reads data to be read (read data RD) from the nonvolatile memory 10 and transmits it to the host 2. Furthermore, when the memory controller 20 receives a prefetch (read-ahead) request PR from the host 2, it executes a prefetch process. The prefetch process is a process in which data that is expected to receive a read request RR from the host 2 or data that is likely to receive a read request RR is read from the nonvolatile memory 10 in advance and stored in a cache memory before the read request RR arrives. Hereinafter, data read by the prefetch process will be referred to as "data to be read-ahead (prefetch data PD)."

[0019] The memory controller 20 may execute internal processing without relying on a request from the host 2. For example, the memory controller 20 may execute prefetch processing internally. Another example of internal processing is GC (Garbage Collection) processing. GC processing is processing in which valid data stored fragmentarily in one or more blocks BLK is written back to one free block BLK (a block BLK in which valid data is not stored), thereby releasing one or more blocks BLK in which valid data was stored fragmentarily as free blocks BLK.

[0020] 1.1.3 Memory Controller Hardware Configuration Next, the hardware configuration of the memory controller 20 will be described with reference to Fig. 3. Fig. 3 is a block diagram showing an example of the hardware configuration of the memory controller 20. Fig. 3 also shows the nonvolatile memory 10. As shown in Fig. 3, the memory controller 20 includes a host interface circuit (host I / F) 21, a control circuit 22, a first cache 23, a second cache 24, a management memory 25, and a memory interface circuit (memory I / F) 26.

[0021] The host interface circuit 21 is hardware that controls communication between the memory controller 20 and the host 2. The host interface circuit 21 is connected to the host 2 via a host bus HB.

[0022] The control circuit 22 is a circuit that controls the entire memory controller 20. The control circuit 22 includes, for example, a processor such as a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory). The processor controls the operation of the entire memory controller 20 by executing a program (firmware) stored in the ROM. The ROM is a non-volatile memory. The ROM stores programs such as firmware. The RAM is a volatile memory. The RAM is used as a working area for the processor.

[0023] The first cache 23 is, for example, a cache memory. As shown in FIG. 3, the first cache 23 includes a control circuit 31 and a memory unit 32. The control circuit 31 is a circuit that controls the entire first cache 23. The control circuit 31 includes, for example, a processor such as a CPU, a ROM, and a RAM. The memory unit 32 is, for example, an SRAM (Static Random Access Memory). The memory unit 32 stores, for example, prefetch data PD and read data RD. In other words, the memory unit 32 (first cache 23) is a read-only cache. Details of the memory unit 32 will be described later.

[0024] The second cache 24 is, for example, a cache memory. As shown in FIG. 3, the second cache 24 includes a control circuit 41 and a memory unit 42. The control circuit 41 is a circuit that controls the entire second cache 24. The control circuit 41 includes, for example, a processor such as a CPU, a ROM, and a RAM. The memory unit 42 is, for example, a DRAM. The memory unit 42 stores, for example, prefetch data PD, read data RD, and write data WD. In other words, the memory unit 42 (second cache 24) is a dual-purpose read / write cache. Details of the memory unit 42 will be described later.

[0025] Here, the first cache 23 and the second cache 24 have different read and write latencies due to differences in the storage elements. Specifically, the first cache 23 is configured to have a shorter latency and operate faster than the second cache 24.

[0026] The management memory 25 temporarily stores system data for managing the nonvolatile memory 10. The system data is, for example, an L2P table 51. The L2P table 51 is a table that maps (converts) logical addresses LA and physical addresses PA. The L2P table 51 will be described in detail later. The management memory 25 may also be used to temporarily store data transferred to or from the nonvolatile memory 10 in units of reads or writes to or from the nonvolatile memory 10.

[0027] The memory interface circuit 26 is hardware that controls communication between the memory controller 20 and the nonvolatile memory 10. The memory interface circuit 26 is connected to the nonvolatile memory 10 via a memory bus MB.

[0028] 1.1.4 L2P Table Configuration The configuration of the L2P table 51 will be described with reference to FIG. 4. FIG. 4 is a diagram illustrating an example of the configuration of the L2P table 51. As illustrated in FIG. 4, the L2P table 51 includes multiple entries. Each entry includes a logical address LA and a physical address PA corresponding to the logical address LA. For example, the L2P table 51 is managed in 256-B units, each consisting of four consecutive data items in address order, for data with an access granularity of 64 B. Such a management unit that aggregates data of multiple access granularities is referred to as an "L2P management size." Each of the multiple entries is uniquely identified by the corresponding logical address LA. In the example of FIG. 4, the logical address LA(A) corresponds to the physical address PA(A). The logical address LA(A+1) corresponds to the physical address PA(A+1). The logical address LA(A+2) corresponds to the physical address PA(A+2).

[0029] The L2P table 51 is stored, for example, in a management data area of ​​a memory cell array MCA in an arbitrary NAND chip CP included in the nonvolatile memory 10. The L2P table 51 is loaded into the management memory 25 by the memory controller 20, for example, immediately after power-on. The L2P table 51 loaded into the management memory 25 is updated by the memory controller 20, for example, when a physical address PA corresponding to a logical address LA is assigned based on a write request WR from the host 2 or when a GC process is performed. When the L2P table 51 in the management memory 25 is updated, the L2P table 51 in the management data area in the nonvolatile memory 10 is updated by the memory controller 20 at an arbitrary timing.

[0030] 1.1.5 Configuration of the memory section of the first cache The configuration of the memory unit 32 of the first cache 23 will be described with reference to FIG. 5. FIG. 5 is a diagram showing an example of the configuration of the memory unit 32. As shown in FIG. 5, the memory unit 32 includes a plurality of entries. Each entry includes a cache tag CT and a cache line CL. The cache tag CT is an area for storing various tag information. The cache line CL is an area for storing prefetch data PD and read data RD. The line size of the cache line CL is, for example, 64B. That is, the cache line CL stores 64B of data.

[0031] In this embodiment, for example, a plurality of logical addresses LA specified by the host 2 are grouped by the lowest two bits of the logical addresses LA ("00", "01", "10", "11"), and each group is assigned to one entry in the memory unit 32. That is, the memory unit 32 includes four entries. Each entry manages the lowest two bits of the logical address LA as an index number. In this way, a plurality of logical addresses LA specified by the host 2 are mapped to the memory unit 32 by their respective indexes.

[0032] The cache tag CT includes an E / V field F1, a Lock flag field F2, and a logical address field F3.

[0033] The E / V field F1 is a field that stores information indicating whether or not there is data in the cache line CL. If there is no data in the cache line CL, the E / V field F1 stores "E" (Empty). If there is data in the cache line CL, the E / V field F1 stores "V" (Valid).

[0034] The Lock flag field F2 is a field that stores information indicating whether or not there is prefetch data PD in the cache line CL. When there is no data in the cache line CL (Empty), the value of the Lock flag field F2 is unset (-). When there is data in the cache line CL (Valid) and the data is read data RD, the Lock flag field F2 stores "0" (Unlock). "0" indicates that the data is not prefetch data PD. When there is data in the cache line CL (Valid) and the data is prefetch data PD, the Lock flag field F2 stores "1" (Lock). "1" indicates that the data is prefetch data PD. In the following description, the state in which there is data in the cache line CL (Valid) and the data is prefetch data PD (Lock) will be referred to as the Lock state, abbreviating the Valid state.

[0035] The logical address field F3 is a field that stores the upper bit value excluding the address bits used for the index number from the logical address LA. In the example of Fig. 5, the logical address field F3 stores the upper bits ((K-2) bits) excluding the lower 2 bits of the logical address LA.

[0036] 5, in an entry having tag information of index "00", 64B data is stored in the cache line CL (Lock), "V" is stored in the E / V field F1, "1" is stored in the Lock flag field F2, and "0x000000" is stored in the logical address field F3. That is, the entry to which the address value "0x00000000" (=logical address LA) obtained by concatenating the address value of the logical address field F3 and the index number is assigned stores prefetch data PD.

[0037] In the entry having tag information of index "01", 64B data is stored in the cache line CL (Valid), "V" is stored in the E / V field F1, "0" is stored in the Lock flag field F2, and "0x000001" is stored in the logical address field F3. That is, the read data RD is stored in the entry to which the address value "0x00000101" (=logical address LA) obtained by concatenating the address value of the logical address field F3 and the index number is assigned.

[0038] In the entry having tag information of index "10", the cache line CL is in a state where no data is set (-) (Empty), "E" is stored in the E / V field F1, and values ​​are set (-) in the Lock flag field F2 and the logical address field F3. In other words, no data is stored in the entry having tag information of index "10".

[0039] In the entry having tag information of index "11", 64B data is stored in the cache line CL (Valid), "V" is stored in the E / V field F1, "0" is stored in the Lock flag field F2, and "0x000001" is stored in the logical address field F3. That is, the read data RD is stored in the entry to which the address value "0x00000111" (=logical address LA) obtained by concatenating the address value of the logical address field F3 and the index number is assigned.

[0040] 5, a direct map (1-way set associative) allocation method is shown as a method for allocating a plurality of logical addresses LA to entries included in the memory unit 32, but an L-way set associative (L is an integer equal to or greater than 2) allocation method may also be used. Also, the number of index numbers is not limited to four, and may be increased to any number (a power of 2).

[0041] In the following, in an entry in the memory unit 32, a state in which the value of field F1 of the cache tag CT is "E" is also referred to as "the entry is in an empty state." A state in which the value of field F1 of the cache tag CT is "V" and the value of field F2 is "0" is also referred to as "the entry is in a valid state." A state in which the value of field F1 of the cache tag CT is "V" and the value of field F2 is "1" is also referred to as "the entry is in a locked state."

[0042] 1.1.6 Secondary cache memory configuration The configuration of the memory unit 42 of the second cache 24 will be described with reference to FIG. 6. FIG. 6 is a diagram showing an example of the configuration of the memory unit 42. As shown in FIG. 6, the memory unit 42 includes a plurality of entries. Each entry includes a cache tag CT and a cache line CL. The cache line CL is an area for storing prefetch data PD, read data RD, and write data WD. The line size of the cache line CL is, for example, 512 B. That is, one cache line CL stores eight pieces of 64 B data. Each of the eight pieces of 64 B data corresponds to the lower three bits ("000", "001", "010", "011", "100", "101", "110", and "111") of the logical address LA, respectively.

[0043] In this embodiment, for example, a plurality of logical addresses LA are grouped by the most significant two bits ("00", "01", "10", "11") of the least significant five bits of the logical address LA, and each group is assigned to one entry in the memory unit 42. That is, the memory unit 42 includes four entries. Each entry manages the most significant two bits of the least significant five bits of the logical address LA as an index number. In this way, a plurality of logical addresses LA specified by the host 2 are mapped to the memory unit 42 by their respective indexes.

[0044] The cache tag CT includes an E / V field F1, a C / D field F4, and a logical address field F3.

[0045] The E / V field F1 is similar to the memory section 32 of the first cache 23, except that it includes eight subfields 0 to 7. The eight subfields 0 to 7 correspond to the lower three bits of the logical address LA, respectively.

[0046] The C / D field F4 is a field that stores information indicating whether the data written in the nonvolatile memory 10 matches the data stored in the memory unit 42. If the two match (Clean), "C" (Clean) is stored in the C / D field F4. In other words, in this case, the stored data is in a clean state. If the two do not match (Dirty), "D" (Dirty) is stored in the C / D field F4. In other words, in this case, the stored data is in a dirty state. The C / D field F4 includes eight subfields 0 to 7. The eight subfields 0 to 7 each correspond to the lower three bits of the logical address LA.

[0047] The logical address field F3 is similar to the memory section 32 of the first cache 23. In the example of Fig. 6, the logical address field F3 stores the upper bits ((K-5) bits) of the logical address LA excluding the lower 5 bits.

[0048] 6, in an entry having tag information of index "00", eight pieces of 64B data are stored in the cache line CL (Dirty), "V" is stored in subfields 0 to 7 of the E / V field F1, "D" is stored in subfields 0 to 7 of the C / D field F4, and "0x000" is stored in the logical address field F3. That is, in an entry to which address values ​​"0x00000000" to "0x00000111" (=logical address LA) obtained by concatenating the address value of the logical address field F3, the index number, and the lower 3 bits of the logical address LA are assigned, write data WD is stored in a Dirty state.

[0049] In an entry having tag information of index "01", eight pieces of 64B data are stored in the cache line CL (Clean), "V" is stored in subfields 0 to 7 of the E / V field F1, "C" is stored in subfields 0 to 7 of the C / D field F4, and "0x001" is stored in the logical address field F3. That is, in an entry assigned an address value "0x00101000" to "0x00101111" (=logical address LA) obtained by concatenating the address value of the logical address field F3, the index number, and the lower 3 bits of the logical address LA, prefetch data PD, read data RD, or write data WD is stored in a Clean state.

[0050] In the entry with tag information of index "10", the cache line CL is in an empty state (-) with no data set, subfields 0 to 7 of the E / V field F1 store "E", and subfields 0 to 7 of the C / D field F4 and the logical address field F3 store no values ​​(-). In other words, no data is stored in the entry with tag information of index "10".

[0051] In the entry having tag information of index "11", eight pieces of 64B data are stored in the cache line CL (Clean), "V" is stored in subfields 0 to 7 of the E / V field F1, "C" is stored in subfields 0 to 7 of the C / D field F4, and "0x001" is stored in the logical address field F3. That is, the entry to which the address value "0x00111000" to "0x00111111" (=logical address LA) obtained by concatenating the address value of the logical address field F3, the index number, and the lower 3 bits of the logical address LA is assigned stores prefetch data PD, read data RD, or write data WD in a Clean state.

[0052] 6, a direct map (1-way set associative) allocation method is shown as a method for allocating a plurality of logical addresses LA to entries included in the memory unit 42, but an L-way set associative (L is an integer equal to or greater than 2) allocation method may also be used. Also, the number of index numbers is not limited to four, and may be increased to any number (a power of 2).

[0053] In the following, a state in which the value of the subfield corresponding to the logical address LA in field F1 of the cache tag CT in an entry of memory unit 42 is "E" will also be referred to as "the entry is in an empty state." A state in which the value of the subfield corresponding to the logical address LA in field F1 of the cache tag CT is "V" and the value of the subfield corresponding to the logical address LA in field F4 is "C" will also be referred to as "the entry is in a clean state." A state in which the value of the subfield corresponding to the logical address LA in field F1 of the cache tag CT is "V" and the value of the subfield corresponding to the logical address LA in field F4 is "D" will also be referred to as "the entry is in a dirty state."

[0054] 1.1.7 Memory Controller Functional Configuration Next, the functional configuration of the memory controller 20 will be described with reference to FIG. 7. FIG. 7 is a block diagram showing an example of the functional configuration of the memory controller 20. As shown in FIG. 7, the memory controller 20 includes, as functional blocks, a prefetch controller 201 and a NAND controller 202. The first cache 23 includes, as a functional block, a first cache control unit 301. The second cache 24 includes, as a functional block, a second cache control unit 401. The control circuit 22 of the memory controller 20 functions as the prefetch controller 201 and the NAND controller 202. The control circuit 31 of the first cache 23 functions as the first cache control unit 301. The control circuit 41 of the second cache 24 functions as the second cache control unit 401. Note that in FIG. 7, functional blocks corresponding to the host interface circuit 21, management memory 25, and memory interface circuit 26 of the memory controller 20 are omitted from the illustration.

[0055] Hereinafter, the logical address LA and physical address PA to be pre-read, read, and write are respectively referred to as "target logical address LAt" and "target physical address PAt." In addition, in the memory unit 32, an entry having an index corresponding to the target logical address LAt is referred to as "target entry E3t." In the memory unit 42, an entry having an index corresponding to the target logical address LAt is referred to as "target entry E4t."

[0056] (Prefetch Controller 201) The prefetch controller 201 controls the prefetch process. A submission queue SQ and a completion queue CQ for prefetching, which can be controlled by user software of the host 2, are configured in the main memory MM in the host 2. The prefetch controller 201 periodically reads the submission queue SQ using the CXL.IO protocol to check for the presence of a new entry. When the prefetch controller 201 detects that a prefetch request PR has been entered in the submission queue SQ, it transmits the prefetch request PR and the target logical address LAt to the first cache control unit 301. That is, in this embodiment, the prefetch request PR is transmitted to the first cache control unit 301 by the prefetch controller 201 based on a user's specification of the prefetch process. This allows the memory system 3 to control the prefetch process based on the user's specification of the prefetch process. By issuing a prefetch request PR for the data before a read request RR from the host 2, the data can be stored in the first cache 23. This makes it possible to reduce the read latency for a read request RR for the data from the read time to the non-volatile memory 10 to the read time to the first cache 23, thereby significantly improving the read performance of the memory system 3. Note that the submission queue SQ and the completion queue CQ are generally configured on the main memory MM, but this is not limitative.

[0057] (First cache control unit 301) The first cache control unit 301 controls the memory unit 32. Below, the cases where the first cache control unit 301 receives a prefetch request PR, a read request RR, and a write request WR will be described.

[0058] [When a prefetch request PR is received] The first cache control unit 301 receives a prefetch request PR and a target logical address LAt from the prefetch controller 201. The first cache control unit 301 searches the memory unit 32 based on the target logical address LAt.

[0059] If no data is stored in the cache line CL of the target entry E3t (the target entry E3t is in an Empty state), a cache miss occurs, and the first cache control unit 301 transmits a prefetch request PR and the target logical address LAt to the second cache control unit 401. The first cache control unit 301 receives the data of the target logical address LAt, which has been acquired from the second cache 24 or the nonvolatile memory 10, from the second cache control unit 401, and stores the received data in the target entry E3t in a Lock state as prefetch data PD.

[0060] If the data of the target logical address LAt is stored in the cache line CL of the target entry E3t (the target entry E3t is in a valid state or a locked state), a cache hit occurs, and the first cache control unit 301 performs the following operations: If the data of the target entry E3t is in an unlocked state, the first cache control unit 301 updates the data to a locked state; If the data of the target entry E3t is in a locked state, the first cache control unit 301 maintains the data in a locked state.

[0061] If data at another logical address LA is stored in the cache line CL of the target entry E3t (the target entry E3t is in a Valid state or a Lock state), a cache miss occurs, and the first cache control unit 301 evicts the data from the target entry E3t and transmits it to the second cache control unit 401. Thereafter, the first cache control unit 301 acquires prefetch data PD and stores the prefetch data PD in the target entry E3t in a Lock state, just as when the target entry E3t is in an Empty state.

[0062] [When a read request RR is received] The first cache control unit 301 receives a read request RR and a target logical address LAt using the CXL.mem protocol from the host 2. The first cache control unit 301 searches the memory unit 32 based on the target logical address LAt.

[0063] If no data is stored in the cache line CL of the target entry E3t (the target entry E3t is in an Empty state), a cache miss occurs, and the first cache control unit 301 transmits a read request RR and the target logical address LAt to the second cache control unit 401. The first cache control unit 301 receives the data of the target logical address LAt, acquired from the second cache 24 or the nonvolatile memory 10, from the second cache control unit 401, and transmits the received data to the host 2 as read data RD, while also storing it in the target entry E3t in an Unlocked state.

[0064] If the data of the target logical address LAt is stored in the cache line CL of the target entry E3t (the target entry E3t is in a Valid state or a Lock state), a cache hit occurs, and the first cache control unit 301 transmits the data of the target entry E3t as read data RD to the host 2. If the data of the target entry E3t is in an Unlock state, the first cache control unit 301 maintains the data in an Unlock state. If the data of the target entry E3t is in a Lock state, the first cache control unit 301 clears the target entry E3t.

[0065] If data at another logical address LA is stored in the cache line CL of the target entry E3t (the target entry E3t is in a Valid state or a Lock state), a cache miss occurs, and the first cache control unit 301 acquires the read data RD and sends the read data RD to the host 2, just as when the target entry E3t is in an Empty state. If the data in the target entry E3t is in an Unlock state, the first cache control unit 301 evicts the data from the target entry E3t and sends it to the second cache control unit 401, and then stores the read data RD in an Unlock state in the target entry E3t. If the data in the target entry E3t is in a Lock state, the first cache control unit 301 maintains the data in a Lock state.

[0066] [When a write request WR is received] The first cache control unit 301 receives a write request WR, a target logical address LAt, and write data WD from the host 2 using the CXL.mem protocol. The first cache control unit 301 transmits the write request WR, the target logical address LAt, and the write data WD to the second cache control unit 401. The first cache control unit 301 searches the memory unit 32 based on the target logical address LAt.

[0067] When no data is stored in the cache line CL of the target entry E3t (the target entry E3t is in the Empty state), the first cache control unit 301 maintains the target entry E3t in the Empty state.

[0068] If the data of the target logical address LAt is stored in the cache line CL of the target entry E3t (the target entry E3t is in the Valid state or the Lock state), the first cache control unit 301 clears the target entry E3t.

[0069] If data at another logical address LA is stored in the cache line CL of the target entry E3t (the target entry E3t is in the Valid state or Lock state), the first cache control unit 301 maintains the target entry E3t.

[0070] The first cache control unit 301 does not store the write data WD in the target entry E3t.

[0071] (Second cache control unit 401) The second cache control unit 401 controls the memory unit 42. Below, the cases where the second cache control unit 401 receives a prefetch request PR, a read request RR, and a write request WR will be described.

[0072] [When a prefetch request PR is received] The second cache control unit 401 receives the prefetch request PR and the target logical address LAt from the first cache control unit 301. The second cache control unit 401 searches the memory unit 42 based on the target logical address LAt.

[0073] If no data is stored in the target entry E4t (the target entry E4t is in an empty state), a cache miss occurs, and the second cache control unit 401 transmits a prefetch request PR and a target logical address LAt to the NAND controller 202. The NAND controller 202 converts the target logical address LAt into a target physical address PAt by referring to the L2P table 51. The second cache control unit 401 receives, from the nonvolatile memory 10, the data at the target physical address PAt that has been read from the nonvolatile memory 10, and transmits the received data as prefetch data PD to the first cache control unit 301. At this time, the second cache control unit 401 may store the prefetch data PD in the target entry E4t.

[0074] If the data of the target logical address LAt is stored in the target entry E4t (the target entry E4t is in a Clean or Dirty state), a cache hit occurs, and the second cache control unit 401 sends the data of the target entry E4t to the first cache control unit 301 as prefetch data PD.

[0075] If data at another logical address LA is stored in the target entry E4t (the target entry E4t is in the Clean state or the Dirty state), a cache miss occurs, and the second cache control unit 401 acquires prefetch data PD from the nonvolatile memory 10 and transmits the prefetch data PD to the first cache control unit 301, just as when the target entry E4t is in the Empty state. At this time, the second cache control unit 401 may store the prefetch data PD in the target entry E4t. If the data in the target entry E4t is in the Dirty state, the second cache control unit 401 evicts the data from the target entry E4t and performs write-back processing. That is, the second cache control unit 401 transmits a write request WR, the target logical address LAt, and the data to the NAND controller 202. Then, the prefetch data PD is stored in the target entry E4t. If the data in the target entry E4t is in the Clean state, the second cache control unit 401 clears the target entry E4t and then stores the prefetch data PD in the target entry E4t.

[0076] [When a read request RR is received] The second cache control unit 401 receives the read request RR and the target logical address LAt from the first cache control unit 301. The second cache control unit 401 searches the memory unit 42 based on the target logical address LAt.

[0077] If no data is stored in the target entry E4t (the target entry E4t is in an empty state), a cache miss occurs, and the second cache control unit 401 transmits the read request RR and the target logical address LAt to the NAND controller 202. The NAND controller 202 converts the target logical address LAt into a target physical address PAt by referring to the L2P table 51. The second cache control unit 401 receives the data at the target physical address PAt that has been read from the nonvolatile memory 10, and transmits the received data as read data RD to the first cache control unit 301. At this time, the second cache control unit 401 may store the read data RD in the target entry E4t.

[0078] If the data of the target logical address LAt is stored in the target entry E4t (the target entry E4t is in a Clean or Dirty state), a cache hit occurs, and the second cache control unit 401 sends the data of the target entry E4t to the first cache control unit 301 as read data RD.

[0079] If data at another logical address LA is stored in the target entry E4t (the target entry E4t is in a clean or dirty state), a cache miss occurs, and the second cache control unit 401 acquires the read data RD from the nonvolatile memory 10 and transmits the read data RD to the first cache control unit 301, just as when the target entry E4t is in an empty state. At this time, the second cache control unit 401 may store the read data RD in the target entry E4t. If the data in the target entry E4t is in a dirty state, write-back processing is performed, just as when a prefetch request PR is received. Thereafter, the read data RD is stored in the target entry E4t. If the data in the target entry E4t is in a clean state, the second cache control unit 401 clears the target entry E4t and then stores the read data RD in the target entry E4t.

[0080] [When a write request WR is received] The second cache control unit 401 receives a write request WR, a target logical address LAt, and write data WD from the first cache control unit 301. The second cache control unit 401 stores the received write data WD in the target entry E4t and sets the cache tag CT to a dirty state. Thereafter, if a write-back occurs when the second cache control unit 401 receives a read request RR, a prefetch request PR, or a write request WR for another logical address LA for the target entry E4t, the second cache control unit 401 transmits the write request WR, the target logical address LAt, and the data of the target entry E4t to the NAND controller 202.

[0081] Below, each state of the target entry E4t will be explained. When the second cache control unit 401 receives a write request WR, a target logical address LAt, and write data WD from the first cache control unit 301, the second cache control unit 401 searches the memory unit 42 based on the target logical address LAt.

[0082] When no data is stored in the target entry E4t (the target entry E4t is in an empty state), the second cache control unit 401 stores the write data WD in the target entry E4t in a dirty state. After that, if a write-back occurs when the second cache control unit 401 receives a read request RR, a prefetch request PR, or a write request WR for another logical address LA for the target entry E4t, the second cache control unit 401 transmits the write request WR, the target logical address LAt, and the data of the target entry E4t to the NAND controller 202.

[0083] When data of the target logical address LAt is stored in the target entry E4t (the target entry E4t is in a clean state or a dirty state), the second cache control unit 401 clears the target entry E4t and then stores the write data WD in the target entry E4t in a dirty state. After that, if a write-back occurs when the second cache control unit 401 receives a read request RR, a prefetch request PR, or a write request WR for another logical address LA for the target entry E4t, the second cache control unit 401 transmits the write request WR, the target logical address LAt, and the data of the target entry E4t to the NAND controller 202.

[0084] If data of another logical address LA is stored in the target entry E4t (the target entry E4t is in the Clean state or the Dirty state), the second cache control unit 401 performs the following operation. If the data of the target entry E4t is in the Dirty state, the second cache control unit 401 performs a write-back process, as when a prefetch request PR is received. Thereafter, the second cache control unit 401 stores the write data WD in the target entry E4t in the Dirty state. If the data of the target entry E4t is in the Clean state, the second cache control unit 401 clears the target entry E4t and then stores the write data WD in the target entry E4t in the Dirty state. Thereafter, if a write-back occurs when the second cache control unit 401 receives a read request RR, a prefetch request PR, or a write request WR for another logical address LA for the target entry E4t, the second cache control unit 401 transmits the write request WR, the target logical address LAt, and the data of the target entry E4t to the NAND controller 202.

[0085] (NAND controller 202) The NAND controller 202 controls the nonvolatile memory 10. Below, the cases where the NAND controller 202 receives a prefetch request PR, a read request RR, and a write request WR will be described respectively.

[0086] [When a prefetch request PR is received] The NAND controller 202 receives a prefetch request PR and a target logical address LAt from the second cache control unit 401. The NAND controller 202 converts the target logical address LAt into a target physical address PAt by referring to the L2P table 51. The NAND controller 202 transmits a command of the prefetch request PR and the target physical address PAt to the nonvolatile memory 10. The nonvolatile memory 10 executes a read operation based on the command and the target physical address PAt. The NAND controller 202 transmits the data at the target physical address PAt, which has been read from the nonvolatile memory 10, to the second cache control unit 401 as prefetch data PD.

[0087] [When a read request RR is received] The NAND controller 202 receives a read request RR and a target logical address LAt from the second cache control unit 401. The NAND controller 202 converts the target logical address LAt into a target physical address PAt by referring to the L2P table 51. The NAND controller 202 transmits a command of the read request RR and the target physical address PAt to the nonvolatile memory 10. The nonvolatile memory 10 executes a read operation based on the command and the target physical address PAt. The NAND controller 202 transmits the data at the target logical address PAt, which has been read from the nonvolatile memory 10, to the second cache control unit 401 as read data RD.

[0088] [When a write request WR is received] The NAND controller 202 receives a write request WR and write data WD from the second cache control unit 401. The NAND controller 202 converts the target logical address LAt into a target physical address PAt by referring to the L2P table 51. The NAND controller 202 transmits the write request WR command, the target physical address PAt, and the write data WD to the nonvolatile memory 10. The nonvolatile memory 10 executes a write operation based on the command, the target physical address PAt, and the write data WD. Note that the write data WD may be temporarily stored in the management memory 25, and then transferred from the management memory 25 to the nonvolatile memory 10.

[0089] 1.2 First cache operation Next, the operation of the first cache 23 will be described with reference to Fig. 5 and Fig. 8. Fig. 8 is a diagram showing an example of the state transition of the cache tag CT of the target entry E3t in the memory unit 32. In Fig. 8, "Empty" indicates a state in which the value of field F1 of the cache tag CT of the target entry E3t is "E". "Valid" indicates a state in which the value of field F1 of the cache tag CT of the target entry E3t is "V" and the value of field F2 is "0". "Lock" indicates a state in which the value of field F1 of the cache tag CT of the target entry E3t is "V" and the value of field F2 is "1".

[0090] First, a case will be described in which the first cache control unit 301 of the first cache 23 receives a prefetch request PR for data at the target logical address LAt. In this case, the first cache control unit 301 stores the prefetched data in the cache line CL of the target entry E3t included in the memory unit 32, and stores "1" in the field F2 of the target entry E3t. Furthermore, the first cache control unit 301 maintains the target entry E3t until it receives a read request RR or a write request WR for the target logical address LAt from the host 2. The specific operation is as follows.

[0091] When the first cache control unit 301 receives the prefetch request PR and the target logical address LAt from the prefetch controller 201, it searches the memory unit 32 and checks the cache tag CT of the target entry E3t.

[0092] Assume that the target entry E3t is the third entry in the memory unit 32 shown in FIG. 5, and the target logical address LAt is X1. In the third entry, the value of field F1 is “E.” That is, no data is stored in the cache line CL of the third entry (Empty). This is a case where no data exists in the target entry E3t in the memory unit 32, and data at the target logical address LAt is received from the second cache 24 and stored in the target entry E3t as prefetch data PD. In this case, the first cache control unit 301 transmits a prefetch request PR and the target logical address LAt (=X1) to the second cache control unit 401. The first cache control unit 301 receives the data at the target logical address LAt (=X1), which has been acquired from the memory unit 42 or the non-volatile memory 10, from the second cache control unit 401. In the third entry, the first cache control unit 301 stores the received data in the cache line CL as prefetch data PD, stores “V” in field F1, and stores “1” in field F2. The above state transition of the cache tag CT of the target entry E3t corresponds to the transition (4) in FIG.

[0093] Assume that the target entry E3t is the second entry in the memory unit 32 shown in FIG. 5, and the target logical address LAt is X2=0x00000101. In the second entry, the value of field F1 is “V,” the value of field F2 is “0,” and the logical address LA corresponding to the stored data is the same as the target logical address LAt (=X2). That is, the data of the target logical address LAt is stored (Valid) in the cache line CL of the second entry, and “1” is not stored in field F2 of the second entry. This is a case where the data of the target logical address LAt exists in the target entry E3t of the memory unit 32 and is in a Valid state, and the data is stored in the target entry E3t as prefetch data PD. In this case, the first cache control unit 301 updates the value of field F2 in the second entry to “1.” The above state transition of the cache tag CT of the target entry E3t corresponds to the transition (5) in FIG. 8.

[0094] Assume that the target entry E3t is the first entry in the memory unit 32 shown in FIG. 5, and the target logical address LAt is X3=0x00000000. In the first entry, the value of field F1 is “V,” the value of field F2 is “1,” and the logical address LA corresponding to the stored data is the same as the target logical address LAt (=X3). That is, the data of the target logical address LAt is stored (locked) in the cache line CL of the first entry, and “1” is stored in field F2 of the first entry. This is a case where the data of the target logical address LAt exists in the target entry E3t of the memory unit 32 and is in a locked state, and the data is stored in the target entry E3t as prefetch data PD. In this case, the first cache control unit 301 maintains the first entry.

[0095] Assume that the target entry E3t is the second entry in the memory unit 32 shown in FIG. 5, and the target logical address LAt is X4=0x00000001. In the second entry, the value of field F1 is "V," the value of field F2 is "0," and the logical address LA corresponding to the stored data is different from the target logical address LAt (=X4). That is, data at a logical address different from the target logical address LAt is stored (Valid) in the cache line CL of the second entry, and "1" is not stored in field F2 of the second entry. This is a case where data at another logical address LA exists in the target entry E3t of the memory unit 32 and is in a Valid state, so that the data is evicted, and data at the target logical address LAt is received from the second cache 24 and stored in the target entry E3t as prefetch data PD. In this case, the first cache control unit 301 evicts the data stored in the second entry, acquires the prefetch data PD in the same way as when the value of field F1 is “E”, and stores the prefetch data PD in the cache line CL, stores “V” in field F1, and stores “1” in field F2 in the second entry. The above state transition of the cache tag CT of the target entry E3t corresponds to the transition (5) in FIG. 8.

[0096] In response to a read request RR from the host 2, the prefetch data PD is preferentially stored in the memory unit 32 so that the data in the memory unit 32 can be sent from the first cache 23 to the host 2. Therefore, the cache tag CT of the second entry transitions as shown in (5) of FIG.

[0097] Assume that the target entry E3t is the first entry in the memory unit 32 shown in FIG. 5, and the target logical address LAt is X5=0x00000100. In the first entry, the value of field F1 is "V," the value of field F2 is "1," and the logical address LA corresponding to the stored data is different from the target logical address LAt (=X5). That is, data at a logical address different from the target logical address LAt is stored (locked) in the cache line CL of the first entry, and "1" is stored in field F2 of the first entry. This is a case where data at another logical address LA exists in the target entry E3t of the memory unit 32 and is in a locked state, so that the data is evicted, and data at the target logical address LAt is received from the second cache 24 and stored in the target entry E3t as prefetch data PD. In this case, the first cache control unit 301 evicts the data stored in the first entry, acquires the prefetch data PD in the same way as when the value of field F1 is “E”, and stores the prefetch data PD in the cache line CL, stores “V” in field F1, and stores “1” in field F2 in the first entry. The above state transition of the cache tag CT of the target entry E3t corresponds to the transition (7) in FIG. 8.

[0098] When a prefetch request PR is received, it is highly likely that a read request RR for the prefetch data PD will come from the host 2. Therefore, the cache tag CT of the first entry transitions as shown in (7) of Figure 8. Note that instead of transitioning as shown in (7) of Figure 8, the first entry may be maintained.

[0099] Next, a case will be described where the first cache control unit 301 receives a read request RR for data at the target logical address LAt from the host 2. When the first cache control unit 301 receives the read request RR and the target logical address LAt from the host 2, it searches the memory unit 32 and checks the cache tag CT of the target entry E3t.

[0100] Assume that the target entry E3t is the third entry in the memory unit 32 shown in FIG. 5, and the target logical address LAt is X1. No data is stored in the cache line CL of the third entry (Empty). This is a case where no data exists in the target entry E3t in the memory unit 32, and the data at the target logical address LAt is received from the second cache 24 and sent to the host 2 as read data RD. In this case, the first cache control unit 301 sends a read request RR and the target logical address LAt (=X1) to the second cache control unit 401. The first cache control unit 301 receives the data at the target logical address LAt (=X1) from the second cache 24 or the non-volatile memory 10 from the second cache control unit 401. The first cache control unit 301 sends the received data as read data RD to the host 2. In the third entry, the first cache control unit 301 stores the received data as read data RD in the cache line CL, stores “V” in field F1, and stores “0” in field F2. The above state transition of the cache tag CT of the target entry E3t corresponds to the transition (2) in FIG.

[0101] Assume that the target entry E3t is the second entry in the memory unit 32 shown in FIG. 5, and the target logical address LAt is X2=0x00000101. The data of the target logical address LAt is stored in the cache line CL of the second entry (Valid), and "1" is not stored in the field F2 of the second entry. This is a case where the data of the target logical address LAt exists in the target entry E3t of the memory unit 32 and is in a Valid state, and the data is to be sent to the host 2 as read data RD. In this case, the first cache control unit 301 sends the data of the second entry to the host 2 as read data RD. The first cache control unit 301 maintains the second entry.

[0102] Assume that the target entry E3t is the first entry in the memory unit 32 shown in FIG. 5, and the target logical address LAt is X3=0x00000000. The data of the target logical address LAt is stored (Locked) in the cache line CL of the first entry, and “1” is stored in field F2 of the first entry. This is a case where the data of the target logical address LAt exists in the target entry E3t of the memory unit 32 and is in the Locked state, and the data is to be sent to the host 2 as read data RD. In this case, the first cache control unit 301 sends the data of the first entry to the host 2 as read data RD. In the first entry, the first cache control unit 301 clears the cache line CL, stores “E” in field F1, and clears field F2. The above state transition of the cache tag CT of the target entry E3t corresponds to the transition (6) in FIG. 8.

[0103] After reading is performed based on the read request RR from the host 2, the read data RD is stored in a cache (not shown) in the host 2. For this reason, it is considered that a read request RR for that data from the host 2 to the first cache 23 will not come for a while. Therefore, it is considered that the data may not be stored in the first entry for a while. For this reason, the cache tag CT of the first entry transitions as shown in (6) of FIG. 8.

[0104] Assume that the target entry E3t is the second entry in the memory unit 32 shown in FIG. 5, and the target logical address LAt is X4=0x00000001. Data at a logical address different from the target logical address LAt is stored in the cache line CL of the second entry (Valid), and “1” is not stored in the field F2 of the second entry. This is a case where data at another logical address LA exists in the target entry E3t of the memory unit 32 and is in a Valid state, and the data at the target logical address LAt is received from the second cache 24 and sent to the host 2 as read data RD. In this case, the first cache control unit 301 acquires the read data RD and sends the read data RD to the host 2, just as when the value of field F1 is “E.” The first cache control unit 301 evicts the data stored in the second entry, stores the read data RD in the cache line CL of the second entry, stores “V” in field F1, and stores “0” in field F2. The above state transition of the cache tag CT of the target entry E3t corresponds to the transition (3) in FIG.

[0105] Assume that the target entry E3t is the first entry in the memory unit 32 shown in FIG. 5, and the target logical address LAt is X5=0x00000100. Data at a logical address different from the target logical address LAt is stored (locked) in the cache line CL of the first entry, and "1" is stored in field F2 of the first entry. This is a case where data at another logical address LA exists in the target entry E3t of the memory unit 32 and is in a lock state, and the data at the target logical address LAt is received from the second cache 24 and sent to the host 2 as read data RD. In this case, the first cache control unit 301 acquires the read data RD and sends the read data RD to the host 2, just as when the value of field F1 is "E." The first cache control unit 301 maintains the first entry.

[0106] In response to a read request RR from the host 2, the prefetch data PD is preferentially stored in the memory unit 32 so that the data in the memory unit 32 can be sent from the first cache 23 to the host 2. For this reason, the first entry is maintained.

[0107] Next, a case will be described where the first cache control unit 301 receives a write request WR for the target logical address LAt from the host 2. When the first cache control unit 301 receives the write request WR, the target logical address LAt, and the write data WD from the host 2, it transmits the write request WR, the target logical address LAt, and the write data WD to the second cache control unit 401. The first cache control unit 301 searches the memory unit 32 and checks the cache tag CT of the target entry E3t.

[0108] Assume that the target entry E3t is the third entry in the memory unit 32 shown in FIG. 5, and the target logical address LAt is X1. No data is stored in the cache line CL of the third entry (Empty). This is a case where no data exists in the target entry E3t of the memory unit 32, and a write request WR, the target logical address LAt, and the write data WD are sent to the second cache 24. In this case, the first cache control unit 301 maintains the third entry.

[0109] Assume that the target entry E3t is the second entry in the memory unit 32 shown in FIG. 5, and the target logical address LAt is X2=0x00000101. The data of the target logical address LAt is stored in the cache line CL of the second entry (Valid), and “1” is not stored in field F2 of the second entry. This is a case where the data of the target logical address LAt exists in the target entry E3t of the memory unit 32 and is in a Valid state, and the data is cleared, and a write request WR, the target logical address LAt, and the write data WD are sent to the second cache 24. In this case, the first cache control unit 301 clears the cache line CL in the second entry, stores “E” in field F1, and clears field F2. The above state transition of the cache tag CT of the target entry E3t corresponds to the transition (1) in FIG. 8.

[0110] Assume that the target entry E3t is the first entry in the memory unit 32 shown in FIG. 5, and the target logical address LAt is X3=0x00000000. The data of the target logical address LAt is stored (Locked) in the cache line CL of the first entry, and “1” is stored in field F2 of the first entry. This is a case where the data of the target logical address LAt exists in the target entry E3t of the memory unit 32 and is in the Locked state, and the data is cleared, and a write request WR, the target logical address LAt, and the write data WD are sent to the second cache 24. In this case, the first cache control unit 301 clears the cache line CL in the first entry, stores “E” in field F1, and clears field F2. The above state transition of the cache tag CT of the target entry E3t corresponds to the transition (6) in FIG. 8.

[0111] After writing is performed based on the write request WR from the host 2, the write data WD is evicted from the cache in the host 2. In other words, this state is one in which the host 2 has determined that the data is unnecessary. For this reason, it is thought that a read request RR for the data from the host 2 to the first cache 23 will not arrive for some time. For this reason, the cache tag CT of the first entry transitions as shown in (6) of Figure 8.

[0112] Assume that the target entry E3t is the second entry in the memory unit 32 shown in FIG. 5, and the target logical address LAt is X4=0x00000001. Data at a logical address different from the target logical address LAt is stored in the cache line CL of the second entry (Valid), and "1" is not stored in the field F2 of the second entry. This is a case where data at another logical address LA exists in the target entry E3t of the memory unit 32 and is in a Valid state, and a write request WR, the target logical address LAt, and the write data WD are sent to the second cache 24. In this case, the first cache control unit 301 maintains the second entry.

[0113] Assume that the target entry E3t is the first entry in the memory unit 32 shown in FIG. 5, and the target logical address LAt is X5=0x00000100. Data at a logical address different from the target logical address LAt is stored (Lock) in the cache line CL of the first entry, and "1" is stored in the field F2 of the first entry. This is a case where data at another logical address LA exists in the target entry E3t of the memory unit 32 and is in a Lock state, and a write request WR, the target logical address LAt, and the write data WD are sent to the second cache 24. In this case, the first cache control unit 301 maintains the first entry.

[0114] 1.3 Effects of this embodiment In a memory system including a nonvolatile memory and a memory controller, when the memory controller receives a read request from a host, if prefetch data is stored in a cache in the memory controller, the memory controller transmits the prefetch data stored in the cache to the host.

[0115] However, when data is flushed from the cache and the prefetched data is flushed from the cache, the prefetched data may not be stored in the cache when the memory controller receives a read request from the host. In this case, the memory controller rereads the data from the nonvolatile memory and sends the read data to the host. This results in a decrease in data read performance compared to when the prefetched data is stored in the cache.

[0116] Therefore, the memory system 3 according to this embodiment includes a nonvolatile memory 10 and a memory controller 20. The memory controller 20 includes a prefetch controller 201, a first cache 23 having a first memory unit 32 and a first cache control unit 301, a second cache 24 having a second memory unit 42 and a second cache control unit 401, and a NAND controller 202. That is, the memory system 3 is configured in three layers: the first cache 23, the second cache 24, and the nonvolatile memory 10. The first cache 23 is connectable to a host. The second cache 24 is connected to the first cache 23. The memory unit 32 of the first cache 23 includes a Lock flag field F2 in the cache tag CT. Field F2 stores prefetch data PD in a Lock state and stores read data RD in an Unlock state.

[0117] The prefetch controller 201 controls the prefetch process based on the submission queue SQ stored in the memory in the host 2. Specifically, when the prefetch controller 201 detects that a prefetch request PR has been entered in the submission queue SQ, it transmits the prefetch request PR and the target logical address LAt to the first cache control unit 301.

[0118] When the first cache control unit 301 receives a prefetch request PR and a target logical address LAt from the prefetch controller 201, it stores the prefetched data at the target logical address LAt as prefetch data PD in the memory unit 32 in a locked state. The first cache control unit 301 maintains the prefetch data PD stored in the memory unit 32 until it receives a read request RR or a write request WR for the target logical address LAt from the host 2. Furthermore, the first cache control unit 301 does not evict the prefetch data PD stored in a locked state from the memory unit 32 using read data RD for another target logical address LAt. This significantly reduces the probability of a cache miss for the prefetch data PD compared to when the prefetch data PD is not stored in the memory unit 32 using the above method. Furthermore, the memory unit 32 includes, for example, an SRAM as a storage element. This improves latency during a cache hit compared to storage elements other than SRAM. As described above, this embodiment improves data read performance.

[0119] Furthermore, when the first cache control unit 301 receives a read request or write request from the host 2 for the prefetch data PD stored in the memory unit 32 in a locked state, it clears the prefetch data PD in the memory unit 32 and sets the entry for the corresponding index to an empty state (transition (6) in FIG. 8). On the other hand, when the first cache control unit 301 receives a read request from the host 2, if the entry for the corresponding index in the memory unit 32 is in an empty state, it can store the read data RD in the memory unit 32 (transition (2) in FIG. 8). Therefore, according to this embodiment, it is possible to improve the utilization efficiency of the cache.

[0120] Furthermore, the memory controller 20 includes a second cache 24 capable of storing read data RD and write data WD. When prefetched data PD is evicted from the first cache 23 by other prefetched data PD, the data can be stored in the second cache 24 as read data RD. When prefetched data PD is evicted from the first cache 23 by write data WD for the same data, the data can be stored in the second cache 24 as write data WD. In this situation, a read request RR from the host 2 for the prefetched data PD can be responded to by reading it from the second cache 24. Therefore, according to this embodiment, the probability of a cache miss can be reduced compared to when the memory controller 20 does not include the second cache 24.

[0121] 1.4 First variant A memory system according to a first modified example of the first embodiment will be described. In the memory system 3 according to the first modified example of the first embodiment, the functional configuration of the prefetch controller 201 is different from that of the first embodiment. In the following explanation, the differences from the first embodiment will be mainly described.

[0122] 1.4.1 Memory Controller Functional Configuration The functional configuration of the memory controller 20 will be described with reference to Fig. 9. Fig. 9 is a block diagram showing an example of the functional configuration of the memory controller 20.

[0123] (Prefetch Controller 201) The prefetch controller 201 learns in advance the access pattern from the host 2 to the memory system 3 using the CXL.mem protocol and creates an access sequence AS. The prefetch controller 201 monitors access from the host 2 to the first cache control unit 301 using the CXL.mem protocol. When the prefetch controller 201 detects a logical address LA that triggers the learned access pattern in the access, it transmits a prefetch request PR and a target logical address LAt to the first cache control unit 301. That is, in this embodiment, the prefetch request PR is transmitted by the prefetch controller 201 to the first cache control unit 301. At this time, the prefetch controller 201 reproduces the access sequence AS that was created in advance. This allows the prefetch process to be performed.

[0124] In the memory controller 20, the functional configuration other than the prefetch controller 201 is the same as the functional configuration of FIG. 7 shown in the first embodiment.

[0125] 1.4.2 Effects of this Modification This modification provides the same effects as those of the first embodiment. Furthermore, this modification allows the memory system 3 to autonomously control the prefetch process.

[0126] 1.5 Second Variant A memory system according to a second modified example of the first embodiment will be described. The memory system 3 according to the second modified example of the first embodiment differs from the first embodiment in that the prefetch controller 201 is eliminated from the memory controller 20. Furthermore, in the memory system 3 according to the second modified example of the first embodiment, the functional configuration of the first cache control unit 301 differs from that of the first embodiment. In the following explanation, the differences from the first embodiment will be mainly described.

[0127] 1.5.1 Memory Controller Functional Configuration The functional configuration of the memory controller 20 will be described with reference to Fig. 10. Fig. 10 is a block diagram showing an example of the functional configuration of the memory controller 20.

[0128] (First cache control unit 301) The host 2 transmits a Memory Speculative Read command (MemSpecRd) using the CXL.mem protocol. MemSpecRd is a speculative read command (a command to transfer data to a cache) that does not receive a response from the host 2, and is defined in the CXL standard. When the first cache control unit 301 receives MemSpecRd and the target logical address LAt from the host 2 using the CXL.mem protocol, it transmits a prefetch request PR and the target logical address LAt to the second cache control unit 401. MemSpecRd corresponds to the prefetch request PR. That is, in this embodiment, the prefetch request PR is transmitted by the host 2 to the first cache control unit 301. This causes the prefetch process to be performed.

[0129] In the memory controller 20, the functional configuration other than the first cache control unit 301 is the same as the functional configuration of FIG. 7 shown in the first embodiment.

[0130] 1.5.2 Effects of this Modification This modification provides the same effects as those of the first embodiment. Furthermore, this modification allows the host 2 to directly control the prefetch process.

[0131] 2. Second embodiment A memory system according to the second embodiment will be described. In the memory system 3 according to the second embodiment, the hardware configuration and functional configuration of the first cache 23 and the configuration of the memory unit 32 of the first cache 23 are different from those of the first embodiment. The following explanation will mainly focus on the differences from the first embodiment.

[0132] 2.1 Memory Controller Hardware Configuration The hardware configuration of the memory controller 20 will be described with reference to Fig. 11. Fig. 11 is a block diagram showing an example of the hardware configuration of the memory controller 20. As shown in Fig. 11, the first cache 23 includes a control circuit 31, a memory unit 32, and a timer circuit 33.

[0133] The timer circuit 33 is a circuit that acquires the current time and measures the elapsed time T1 from the time when the prefetch data PD is stored in the memory unit 32 to the current time. Hereinafter, the function that measures the elapsed time T1 will be referred to as the "WDT (Watch Dog Timer) function."

[0134] In the memory controller 20, the hardware configuration other than the timer circuit 33 is the same as the hardware configuration shown in FIG. 3 in the first embodiment.

[0135] 2.2 Configuration of the memory section of the first cache The configuration of the memory unit 32 of the first cache 23 will be described with reference to Fig. 12. Fig. 12 is a diagram showing an example of the configuration of the memory unit 32. As shown in Fig. 12, the cache tag CT includes an E / V field F1, a Lock flag field F2, an entry time field F5, and a logical address field F3.

[0136] The entry time field F5 is a field that stores the time when data is stored in the cache line CL in a locked state (entry time ET), i.e., the time when "1" is stored in the lock flag field F2. When there is no data in the cache line CL (Empty), or when data is stored in the cache line CL in an unlocked state (Valid), the entry time field F5 has an unset value (-). When data is stored in the cache line CL in a locked state (Lock), the entry time field F5 stores the entry time ET (for example, yyyy / mm / dd hh:mm:ss). The format of the entry time ET may be any format that the controller can manage time, and is not limited to this.

[0137] In the memory unit 32, the configuration of the check tag CT other than the entry time field F5 and the configuration of the cache line CL are the same as those shown in Fig. 5 in the first embodiment. Also, the method of allocating multiple logical addresses LA to entries included in the memory unit 32 is the same as in the first embodiment.

[0138] 2.3 Memory Controller Functional Configuration The functional configuration of the memory controller 20 will be described with reference to FIG. 13. FIG. 13 is a block diagram showing an example of the functional configuration of the memory controller 20. As shown in FIG. 13, the memory controller 20 includes, as functional blocks, a prefetch controller 201 and a NAND controller 202. The first cache 23 includes, as functional blocks, a first cache control unit 301 and a measurement unit 302. The second cache 24 includes, as a functional block, a second cache control unit 401. The timer circuit 33 of the first cache 23 functions as the measurement unit 302.

[0139] (First cache control unit 301) When storing the prefetch data PD in the target entry E3t in a Lock state, the first cache control unit 301 also stores the entry time ET at which the prefetch data PD was stored in the target entry E3t.

[0140] For example, when the first cache control unit 301 receives a read request RR and a target logical address LAt from the host 2 using the CXL.mem protocol, it searches the memory unit 32 based on the target logical address LAt.

[0141] If data of another logical address LA is stored in the target entry E3t (the target entry E3t is in a valid state or a locked state), the first cache control unit 301 acquires the read data RD and transmits the read data RD to the host 2, as in the first embodiment. If the data in the target entry E3t is in a locked state (the target entry E3t is in a locked state), the first cache control unit 301 performs a WDT determination process. The WDT determination process is as follows.

[0142] The first cache control unit 301 transmits an instruction IM to the measurement unit 302 to measure the elapsed time T1. The first cache control unit 301 receives a measurement result RST of the elapsed time T1 from the measurement unit 302. If the measurement result RST (elapsed time T1) exceeds a predetermined fixed time TT, the first cache control unit 301 updates the data of the target entry E3t to an Unlock state and clears the entry time ET of the target entry E3t. If the measurement result RST is less than the fixed time TT, the first cache control unit 301 maintains the target entry E3t.

[0143] Other than the above, the functional configuration of the first cache control unit 301 is the same as that of the first embodiment.

[0144] (Measurement unit 302) The measurement unit 302 has a WDT function. The measurement unit 302 receives an instruction IM to measure an elapsed time T1 from the first cache control unit 301. Based on the instruction IM, the measurement unit 302 measures the elapsed time T1 from the time when "1" was stored in the field F2 of the target entry E3t to the current time. The measurement unit 302 transmits the measurement result RST to the first cache control unit 301.

[0145] In the memory controller 20, the functional configuration other than the first cache control unit 301 and the measurement unit 302 is the same as the functional configuration of FIG. 7 shown in the first embodiment.

[0146] 2.4 First Cache Operation The operation of the first cache 23 will be described with reference to Fig. 12 and Fig. 14. Fig. 14 is a diagram showing an example of the state transition of the cache tag CT of the target entry E3t in the memory unit 32.

[0147] For example, when the first cache control unit 301 of the first cache 23 receives a read request RR and a target logical address LAt from the host 2, it searches the memory unit 32 and checks the cache tag CT of the target entry E3t.

[0148] Assume that the target entry E3t is the first entry in the memory unit 32 shown in FIG. 12, and the target logical address LAt is X5=0x00000100. Data at a logical address different from the target logical address LAt is stored (locked) in the cache line CL of the first entry, "1" is stored in field F2 of the first entry, and entry time ET is stored in field F5 of the first entry. This is a case where data at another logical address LA exists in the target entry E3t of the memory unit 32 and is in a lock state, and data at the target logical address LAt is received from the second cache 24 and sent to the host 2 as read data RD. In this case, the first cache control unit 301 performs WDT determination processing. In the WDT determination processing, if the measurement result RST exceeds a certain time TT (WDT Expired), the first cache control unit 301 updates the value of field F2 in the first entry to "0" and clears field F5. The above state transition of the cache tag CT of the target entry E3t corresponds to the transition (6) in Fig. 14. If the measurement result RST is less than the certain time TT, the first cache control unit 301 maintains the first entry.

[0149] 2.5 Effects of this embodiment According to the second embodiment, the same effects as those of the first embodiment are achieved.

[0150] Furthermore, if the prefetch request PR is a speculative request such as in the second modified example of the first embodiment, a read request RR is not necessarily issued from the host 2 to the prefetch data PD. In this case, the prefetch data PD may continue to be maintained in a locked state, possibly resulting in a deadlock.

[0151] Therefore, in this embodiment, the first cache 23 further includes a measurement unit 302. The memory unit 32 of the first cache 23 further includes an entry time field F5 in the cache tag CT. Field F5 stores the entry time ET at which the prefetch data PD was stored in the Lock state.

[0152] For example, when the first cache control unit 301 receives a read request RR and a target logical address LAt from the host 2, if data at another logical address LA is stored in a locked state in the target entry E3t, the first cache control unit 301 performs a WDT determination process. In the WDT determination process, the measurement unit 302 measures the elapsed time T1 from the entry time ET to the current time. If the measurement result RST exceeds a certain time TT, the first cache control unit 301 updates field F2 of the target entry E3t to "0" and clears field F5. This makes it possible to avoid the occurrence of a deadlock according to this embodiment.

[0153] Of course, the first and second modified examples of the first embodiment can also be applied to this embodiment.

[0154] 3. Third embodiment A memory system according to the third embodiment will be described. In the memory system 3 according to the third embodiment, the configuration of the memory unit 32 of the first cache 23 is different from that of the first embodiment. In the following description, the differences from the first embodiment will be mainly described.

[0155] 3.1 Configuration of the memory section of the first cache The configuration of the memory unit 32 of the first cache 23 will be described with reference to FIG. 15. FIG. 15 is a diagram showing an example of the configuration of the memory unit 32. As shown in FIG. 15, the line size of a cache line CL is, for example, 256 B. That is, one cache line CL stores four 64 B data items. Each of the four 64 B data items corresponds to the lower two bits ("00", "01", "10", "11") of the logical address LA.

[0156] In this embodiment, for example, a plurality of logical addresses LA are grouped by the upper two bits ("00", "01", "10", "11") of the lower four bits of the logical address LA, and each group is assigned to one entry in the memory unit 32. That is, the memory unit 32 includes four entries. Each entry manages the upper two bits of the lower four bits of the logical address LA as an index number.

[0157] 5 shown in the first embodiment, except that the E / V field F1 includes four subfields 0 to 3. The four subfields 0 to 3 each correspond to the lower two bits of the logical address LA.

[0158] 5 shown in the first embodiment, except that the Lock flag field F2 includes four subfields 0 to 3. The four subfields 0 to 3 each correspond to the lower two bits of the logical address LA.

[0159] The logical address field F3 is similar to the memory unit 32 shown in Fig. 5 in the first embodiment. In the example of Fig. 15, the logical address field F3 stores the upper bits ((K-4) bits) of the logical address LA excluding the lower 4 bits.

[0160] 15, in an entry having tag information of index "00", four pieces of 64B data are stored in the cache line CL (Lock), "V" is stored in subfields 0 to 3 of the E / V field F1, "1" is stored in subfields 0 to 3 of the Lock flag field F2, and "0x0000" is stored in the logical address field F3. That is, prefetch data PD is stored in an entry to which address values ​​"0x00000000" to "0x00000011" (=logical address LA) obtained by concatenating the address value of the logical address field F3, the index number, and the lower two bits of the logical address LA are assigned.

[0161] In the entry having tag information of index "01", four 64B data are stored in the cache line CL (Valid), "V" is stored in subfields 0 to 3 of the E / V field F1, "0" is stored in subfields 0 to 3 of the Lock flag field F2, and "0x0001" is stored in the logical address field F3. That is, the read data RD is stored in the entry to which the address value "0x00010100" to "0x00010111" (=logical address LA) obtained by concatenating the address value of the logical address field F3, the index number, and the lower two bits of the logical address LA is assigned.

[0162] In the entry having tag information of index "10", the cache line CL is in a state where no data is set (-) (Empty), "E" is stored in subfields 0 to 3 of the E / V field F1, and values ​​are set (-) in subfields 0 to 3 of the Lock flag field F2 and the logical address field F3. In other words, no data is stored in the entry having tag information of index "10".

[0163] In the entry having tag information of index "11", four 64B data are stored in the cache line CL (Valid), "V" is stored in subfields 0 to 3 of the E / V field F1, "0" is stored in subfields 0 to 3 of the Lock flag field F2, and "0x0001" is stored in the logical address field F3. That is, the read data RD is stored in the entry to which the address value "0x00011100" to "0x00011111" (=logical address LA) obtained by concatenating the address value of the logical address field F3, the index number, and the lower 3 bits of the logical address LA is assigned.

[0164] 15, a direct map (1-way set associative) allocation method is shown as a method for allocating a plurality of logical addresses LA to entries included in the memory unit 32, but an L-way set associative (L is an integer equal to or greater than 2) allocation method may also be used. Also, the number of index numbers is not limited to four, and may be increased to any number (a power of 2).

[0165] FIG. 16 is a diagram illustrating the relationship between the management size of the L2P table (L2P management size) and the size of the cache line CL of the memory unit 32 of the first cache 23. Assume that the L2P management size is 256 B and the page PG of the NAND chip CP is 4 KB. Data is stored in the page PG in units of 256 B. If the page PG is divided into four FEC (Forward Error Correction) frames in units of 1 KB, one FEC frame contains, for example, four pieces of 256 B data. The FEC is a unit of error correction performed by an error correction circuit (not shown) in the memory controller 20.

[0166] Furthermore, when writing data to the nonvolatile memory 10, the data is written in 256B units to page PG of a selected NAND chip CP in the nonvolatile memory 10. When reading data from the nonvolatile memory 10, the data is read in 256B units in a single read from page PG of a selected NAND chip CP in the nonvolatile memory 10. The 256B data read in a single read includes four 64B data pieces with consecutive logical addresses LA. Therefore, if the line size of the cache line CL in the memory unit 32 is set to be equal to or smaller than the L2P management size (256B), it is guaranteed that the size of the data stored in the cache line CL will fit within a single read of 256B data.

[0167] When the line size is 64B, 64B data at the target logical address LAt out of the 256B data read in one read is stored in the cache line CL. When the line size is 256B, 256B data read in one read (64B data at the target logical address LAt and 192 (=64×3)B data corresponding to the three logical addresses LA consecutive to the target logical address LAt) is stored in the cache line CL.

[0168] In this embodiment, the line size of the cache line CL of the memory unit 32 is the same as the L2P management size.

[0169] 3.2 Memory Controller Functional Configuration The following describes the functional configuration of the memory controller 20. In the memory controller 20, the functional configuration other than the first cache control unit 301 is the same as the functional configuration of FIG. 7 shown in the first embodiment.

[0170] The first cache control unit 301 receives from the second cache control unit 401 256B data (64B data corresponding to the target logical address LAt and 192 (=64×3)B data corresponding to three logical addresses LA consecutive to the target logical address LAt) acquired from the second cache 24 or the nonvolatile memory 10, and stores the received 256B data in the target entry E3t in the unlocked or locked state. That is, in the target entry E3t, the received 256B data is stored in the cache line CL, "V" is stored in subfields 0 to 3 of field F1, and "0" or "1" is stored in subfields 0 to 3 of field F2.

[0171] When 64B of data at the target logical address LAt stored in the target entry E3t is evicted, the 256B of data in the cache line CL is cleared in the target entry E3t, "E" is stored in subfields 0 to 3 of field F1, and subfields 0 to 3 of field F2 are cleared.

[0172] Other than the above, the functional configuration of the first cache control unit 301 is the same as that of the first embodiment.

[0173] 3.3 Effects of this embodiment According to the third embodiment, the same effects as those of the first embodiment are achieved.

[0174] Furthermore, in this embodiment, the size of the cache line CL in the memory unit 32 of the first cache 23 is the same as the L2P management size. This allows 64B of data at the target logical address LAt and 192B of data corresponding to the three logical addresses LA consecutive to the target logical address LAt, which are read in a single 256B data read, to be stored in the cache line CL in the memory unit 32. Considering data locality in a program executed by the host 2, data whose logical addresses are close to the target logical address LAt is considered to be relatively likely to be accessed by the host 2. Therefore, according to this embodiment, the amount of data that can be stored in one cache line CL matches the amount of data read from the nonvolatile memory 10 at one time, which is efficient in that neither too much nor too little data can be read from the nonvolatile memory 10. Furthermore, since the cache capacity is larger than when the line size is smaller than 256B, the probability of a cache miss can be reduced.

[0175] Of course, the second embodiment and the first and second modified examples of the first embodiment can also be applied to this embodiment. When the second embodiment is applied to this embodiment, the number of entry time fields F5 may be the same as the number of subfields, or only one representative entry time field F5 may be included. When one entry time field F5 is included, the field F5 stores the time when the prefetch data PD of the last logical address LA of the consecutive logical addresses LA was stored.

[0176] 4. Fourth embodiment A memory system according to the fourth embodiment will be described. In the memory system 3 according to the fourth embodiment, the operations of the first cache 23 and the second cache 24 are partially different from those of the first embodiment. The following description will mainly focus on the differences from the first embodiment.

[0177] In this embodiment, the memory section 42 of the second cache 24 does not have a copy of the data stored in the memory section 32 of the first cache 23. The operation of the first cache 23 and the second cache 24 is as follows.

[0178] 4.1 Operation of the primary and secondary caches (Operation for prefetch request PR) The operation in response to a prefetch request PR will be described with reference to Figures 17 to 20. Figure 17 is a flowchart showing an example of the operation of the first cache 23. Figures 18 to 20 are flowcharts showing an example of the operation of the second cache 24.

[0179] Here, an example will be described in which there is a prefetch request PR for data at target logical address LAt=X. Hereinafter, the prefetch request PR for data at target logical address LAt=X will be referred to as "prefetch request PR(X)". The data at target logical address LAt=X will be referred to as "data DAT(X)".

[0180] As shown in FIG. 17, when the first cache control unit 301 of the first cache 23 receives a prefetch request PR(X) from the prefetch controller 201, it searches the memory unit 32 and checks the cache tag CT of the target entry E3t (S101).

[0181] If the target entry E3t is in the Empty state (S101_Empty), the first cache control unit 301 requests the data DAT(X) from the second cache 24. Specifically, the first cache control unit 301 causes the second cache control unit 401 to execute process 1 (process of acquiring the data DAT(X)), and receives the data DAT(X) from the second cache control unit 401. Details of process 1 will be described later. After executing process 1, the first cache control unit 301 stores the received data DAT(X) in the target entry E3t in the Lock state (S111).

[0182] If the target entry E3t is in the Valid state (S101_Valid), the first cache control unit 301 determines whether the logical address LA of the target entry E3t is X (S121).

[0183] If the logical address LA of the target entry E3t is X (S121_Yes), the first cache control unit 301 updates the target entry E3t to the Lock state (S122).

[0184] If the logical address LA of the target entry E3t is not X (S121_No), the first cache control unit 301 causes the second cache control unit 401 to execute process 1 and receives data DAT(X) from the second cache control unit 401. After executing process 1, the first cache control unit 301 evicts the data in the Unlocked state from the target entry E3t and stores the received data DAT(X) in the Locked state in the target entry E3t (S123). After executing step S123, the first cache control unit 301 causes the second cache control unit 401 to execute process 3 (processing the evicted data in the Unlocked state in the second cache 24). Details of process 3 will be described later.

[0185] When the target entry E3t is in the Lock state (S101_Lock), the first cache control unit 301 determines whether the logical address LA of the target entry E3t is X (S131).

[0186] If the logical address LA of the target entry E3t is X (S131_Yes), the first cache control unit 301 ends the process.

[0187] If the logical address LA of the target entry E3t is not X (S131_No), the first cache control unit 301 causes the second cache control unit 401 to execute process 1 and receives data DAT(X) from the second cache control unit 401. After executing process 1, the first cache control unit 301 evicts the data in Lock state from the target entry E3t and stores the received data DAT(X) in Lock state in the target entry E3t (S132). After executing step S132, the first cache control unit 301 causes the second cache control unit 401 to execute process 2 (processing the evicted Lock state data in the second cache 24). Details of process 2 will be described later. Note that, instead of step S132, the first cache control unit 301 may maintain the target entry E3t in Lock state without evicting the Lock state data from the target entry E3t. In other words, the first cache 23 may preferentially store the previous Lock state data.

[0188] (Process 1) 18, when the second cache control unit 401 of the second cache 24 receives a request for data DAT(X) from the first cache 23, it searches the memory unit 42 and checks the cache tag CT of the target entry E4t (S1001).

[0189] If the target entry E4t is in the Empty state (S1001_Empty), the second cache control unit 401 reads the data DAT(X) from the nonvolatile memory 10 via the NAND controller 202, and transmits the read data DAT(X) to the first cache 23 (S1002). After execution of step S1002, the target entry E4t is in the Empty state.

[0190] If the target entry E4t is in the Clean state (S1001_Clean), the second cache control unit 401 determines whether the logical address LA of the target entry E4t is X (S1003).

[0191] If the logical address LA of the target entry E4t is X (S1003_Yes), the second cache control unit 401 transmits the Clean state data of the target entry E4t to the first cache 23, and updates the target entry E4t to the Empty state (S1004).

[0192] If the logical address LA of the target entry E4t is not X (S1003_No), the second cache control unit 401 executes step S1002. After execution of step S1002, the data at the logical address LA (≠X) is maintained in the clean state in the target entry E4t.

[0193] If the target entry E4t is in the dirty state (S1001_Dirty), the second cache control unit 401 determines whether the logical address LA of the target entry E4t is X (S1005).

[0194] If the logical address LA of the target entry E4t is X (S1005_Yes), the second cache control unit 401 evicts the dirty data from the target entry E4t and transmits it to the nonvolatile memory 10 via the NAND controller 202. This causes the dirty data to be written to the nonvolatile memory 10. Then, the second cache control unit 401 transmits the dirty data from the target entry E4t to the first cache 23, and updates the target entry E4t to an empty state (S1006).

[0195] If the logical address LA of the target entry E4t is not X (S1005_No), the second cache control unit 401 executes step S1002. After execution of step S1002, the data at the logical address LA (≠X) is maintained in a dirty state in the target entry E4t.

[0196] (Process 2) 19, when the second cache control unit 401 of the second cache 24 receives data in the Lock state that has been evicted from the first cache 23, it searches the memory unit 42 and checks the cache tag CT of the target entry E4t (S2001).

[0197] If the target entry E4t is in the Empty state (S2001_Empty), the second cache control unit 401 stores the received data in the Lock state in the target entry E4t in the Clean state (S2002).

[0198] If the target entry E4t is in the Clean state (S2001_Clean), the second cache control unit 401 discards the Clean state data of the target entry E4t and stores the received Lock state data in the target entry E4t in the Clean state (S2003). That is, the second cache 24 preferentially stores Lock state data.

[0199] If the target entry E4t is in a dirty state (S2001_Dirty), the second cache control unit 401 evicts the dirty data from the target entry E4t and transmits it to the nonvolatile memory 10 via the NAND controller 202. As a result, the dirty data is written to the nonvolatile memory 10. Then, the second cache control unit 401 stores the received locked data in the target entry E4t in a clean state (S2004). That is, the second cache 24 preferentially stores locked data. Note that if the amount of data written to the nonvolatile memory 10 is reduced, the second cache control unit 401 may, instead of step S2004, not evict the dirty data from the target entry E4t, but maintain the target entry E4t in a dirty state, and discard the received locked data. That is, the second cache 24 may preferentially store dirty data.

[0200] (Process 3) 20, when the second cache control unit 401 of the second cache 24 receives data in the Unlocked state that has been evicted from the first cache 23, it searches the memory unit 42 and checks the cache tag CT of the target entry E4t (S3001).

[0201] If the target entry E4t is in the Empty state (S3001_Empty), the second cache control unit 401 stores the received data in the Unlocked state in the target entry E4t in the Clean state (S3002).

[0202] If the target entry E4t is in the Clean state (S3001_Clean), the second cache control unit 401 selects either the Clean state data of the target entry E4t or the received Unlock state data, stores the selected data in the target entry E4t in the Clean state, and discards the unselected data (S3003).

[0203] If the target entry E4t is in the Dirty state (S3001_Dirty), the second cache control unit 401 discards the received data in the Unlocked state (S3004). That is, the second cache 24 preferentially stores data in the Dirty state. After execution of step S3004, the data at the logical address LA (≠X) is maintained in the Dirty state in the target entry E4t.

[0204] (Operation for read request RR) The operation in response to a read request RR will be described with reference to Fig. 21 to Fig. 25. Fig. 21 to Fig. 24 are flowcharts showing an example of the operation of the first cache 23. Fig. 25 is a flowchart showing an example of the operation of the second cache 24.

[0205] Here, an example will be described in which there is a read request RR for data at target logical address LAt=X. Hereinafter, the read request RR for target logical address LAt=X will be referred to as "read request RR(X)".

[0206] As shown in FIG. 21, when the first cache control unit 301 of the first cache 23 receives a read request RR(X) from the host 2, it searches the memory unit 32 and checks the cache tag CT of the target entry E3t (S201).

[0207] If the target entry E3t is in the Empty state (S201_Empty), the first cache control unit 301 requests the data DAT(X) from the second cache 24. Specifically, the first cache control unit 301 causes the second cache control unit 401 to execute process 4 (process of acquiring the data DAT(X)), and receives the data DAT(X) from the second cache control unit 401. Details of process 4 will be described later.

[0208] After the execution of process 4, as shown in FIG. 22, the first cache control unit 301 determines whether or not the second cache 24 has the ownership of the data DAT(X) (S211).

[0209] If the second cache 24 has ownership of the data DAT(X) (S211_Yes), the first cache control unit 301 transmits the data DAT(X) to the host 2 and maintains the target entry E3t in an Empty state (S212).

[0210] If the second cache 24 does not have ownership of the data DAT(X) (S211_No), the first cache control unit 301 transmits the data DAT(X) to the host 2 and stores it in the target entry E3t in an Unlocked state (S213).

[0211] As shown in FIG. 21, when the target entry E3t is in the Valid state (S201_Valid), the first cache control unit 301 determines whether the logical address LA of the target entry E3t is X (S221).

[0212] If the logical address LA of the target entry E3t is X (S221_Yes), the first cache control unit 301 transmits the data of the target entry E3t in the Unlocked state to the host 2, and maintains the target entry E3t in the Unlocked state (S222).

[0213] If the logical address LA of the target entry E3t is not X (S221_No), the first cache control unit 301 causes the second cache control unit 401 to execute Process 4 and receives the data DAT(X) from the second cache control unit 401.

[0214] After the execution of process 4, as shown in FIG. 23, the first cache control unit 301 determines whether or not the second cache 24 has the ownership of the data DAT(X) (S223).

[0215] If the second cache 24 has ownership of the data DAT(X) (S223_Yes), the first cache control unit 301 transmits the data DAT(X) to the host 2 and maintains the target entry E3t in the Unlock state (S224).

[0216] If the second cache 24 does not have ownership of the data DAT(X) (S223_No), the first cache control unit 301 transmits the data DAT(X) to the host 2, evicts the data in Unlock state from the target entry E3t, and stores the data DAT(X) in Unlock state in the target entry E3t (S225). After executing step S225, the first cache control unit 301 causes the second cache control unit 401 to execute the above-mentioned process 3.

[0217] As shown in FIG. 21, when the target entry E3t is in the Lock state (S201_Lock), the first cache control unit 301 determines whether the logical address LA of the target entry E3t is X (S231).

[0218] If the logical address LA of the target entry E3t is X (S231_Yes), the first cache control unit 301 transmits the Locked state data of the target entry E3t to the host 2 and also transmits it as Unlocked state data to the second cache 24, and updates the target entry E3t to the Empty state (S232). After executing step S232, the first cache control unit 301 causes the second cache control unit 401 to execute the above-mentioned process 3.

[0219] If the logical address LA of the target entry E3t is not X (S231_No), the first cache control unit 301 causes the second cache control unit 401 to execute Process 4 and receives the data DAT(X) from the second cache control unit 401.

[0220] After the execution of process 4, as shown in FIG. 24, the first cache control unit 301 determines whether or not the second cache 24 has the ownership of the data DAT(X) (S233).

[0221] If the second cache 24 has ownership of the data DAT(X) (S233_Yes), the first cache control unit 301 transmits the data DAT(X) to the host 2 and maintains the target entry E3t in a Lock state (S234).

[0222] If the second cache 24 does not have ownership of the data DAT(X) (S233_No), the first cache control unit 301 transmits the data DAT(X) to the host 2, transmits the Locked data of the target entry E3t to the second cache 24 as Unlocked data, and maintains the target entry E3t in the Locked state (S235). After executing step S235, the first cache control unit 301 causes the second cache control unit 401 to execute the above-mentioned process 3.

[0223] (Process 4) 25, when the second cache control unit 401 of the second cache 24 receives a request for data DAT(X) from the first cache 23, it searches the memory unit 42 and checks the cache tag CT of the target entry E4t (S4001).

[0224] If the target entry E4t is in the Empty state (S4001_Empty), the second cache control unit 401 reads the data DAT(X) from the non-volatile memory 10 via the NAND controller 202, transmits the read data DAT(X) to the first cache 23, and maintains the target entry E4t in the Empty state (S4002).

[0225] If the target entry E4t is in the Clean state (S4001_Clean), the second cache control unit 401 determines whether the logical address LA of the target entry E4t is X (S4003).

[0226] If the logical address LA of the target entry E4t is X (S4003_Yes), the second cache control unit 401 transmits the Clean state data of the target entry E4t to the first cache 23 and updates the target entry E4t to an Empty state (S4004). The target entry E4t is temporarily set to an Empty state, but when data DAT(X) is received from the first cache 23, it is updated to a Clean state with the received data DAT(X). Note that this process of moving data DAT(X) may be omitted.

[0227] If the logical address LA of the target entry E4t is not X (S4003_No), the second cache control unit 401 reads the data DAT(X) from the non-volatile memory 10 via the NAND controller 202, transmits the read data DAT(X) to the first cache 23, and maintains the target entry E4t in a Clean state (S4005).

[0228] If the target entry E4t is in the dirty state (S4001_Dirty), the second cache control unit 401 determines whether the logical address LA of the target entry E4t is X (S4006).

[0229] If the logical address LA of the target entry E4t is X (S4006_Yes), the second cache control unit 401 transmits the dirty data of the target entry E4t to the first cache 23 and maintains the target entry E4t in a dirty state. That is, the second cache 24 preferentially stores dirty data. Then, the second cache control unit 401 grants ownership of the data DAT(X) to the second cache 24 and notifies the first cache 23 (S4007). As a result, a copy of the data DAT(X) is not created in the first cache 23.

[0230] If the logical address LA of the target entry E4t is not X (S4006_No), the second cache control unit 401 reads the data DAT from the non-volatile memory 10 via the NAND controller 202, sends the read data DAT(X) to the first cache 23, and maintains the target entry E4t in a dirty state (S4008).

[0231] (Operation in response to a write request WR) The operation in response to a write request WR will be described with reference to Fig. 26 and Fig. 27. Fig. 26 is a flowchart showing an example of the operation of the first cache 23. Fig. 27 is a flowchart showing an example of the operation of the second cache 24.

[0232] Here, an example will be described in which there is a write request WR for the target logical address LAt=X. Hereinafter, the write request WR for the target logical address LAt=X will be referred to as a "write request WR(X)".

[0233] As shown in FIG. 26, when the first cache control unit 301 of the first cache 23 receives a write request WR(X) and write data WD from the host 2, it searches the memory unit 32 and checks the cache tag CT of the target entry E3t (S301).

[0234] If the target entry E3t is in the Empty state (S301_Empty), the first cache control unit 301 transmits the write data WD to the second cache 24 (S311). After execution of step S311, the target entry E3t is in the Empty state. After execution of step S311, the first cache control unit 301 causes the second cache control unit 401 to execute process 5 (process the write data WD in the second cache 24). Details of process 5 will be described later.

[0235] If the target entry E3t is in the Valid state (S301_Valid), the first cache control unit 301 determines whether the logical address LA of the target entry E3t is X (S321).

[0236] If the logical address LA of the target entry E3t is X (S321_Yes), the first cache control unit 301 discards the data in the Unlocked state of the target entry E3t, updates the target entry E3t to the Empty state, and transmits the write data WD to the second cache 24 (S322). After executing step S322, the first cache control unit 301 causes the second cache control unit 401 to execute process 5.

[0237] If the logical address LA of the target entry E3t is not X (S321_No), the first cache control unit 301 executes step S311. After execution of step S311, the data at the logical address LA (≠X) is maintained in the unlocked state in the target entry E3t.

[0238] When the target entry E3t is in the Lock state (S301_Lock), the first cache control unit 301 determines whether the logical address LA of the target entry E3t is X (S331).

[0239] If the logical address LA of the target entry E3t is X (S331_Yes), the first cache control unit 301 discards the data in the Lock state of the target entry E3t, updates the target entry E3t to the Empty state, and transmits the write data WD to the second cache 24 (S332). After executing step S332, the first cache control unit 301 causes the second cache control unit 401 to execute process 5.

[0240] If the logical address LA of the target entry E3t is not X (S331_No), the first cache control unit 301 executes step S311. After execution of step S311, the data at the logical address LA (≠X) is maintained in a locked state in the target entry E3t.

[0241] (Process 5) The following describes process 5. When the second cache control unit 401 of the second cache 24 receives the write data WD from the first cache 23, it searches the memory unit 42 and checks the cache tag CT of the target entry E4t (S5001).

[0242] If the target entry E4t is in the Empty state (S5001_Empty), the second cache control unit 401 stores the write data WD in the target entry E4t in the Dirty state (S5002).

[0243] If the target entry E4t is in the Clean state (S5001_Clean), the second cache control unit 401 determines whether the logical address LA of the target entry E4t is X (S5003).

[0244] If the logical address LA of the target entry E4t is X (S5003_Yes), the second cache control unit 401 overwrites the Clean state data of the target entry E4t with the write data WD, and updates the target entry E4t to a Dirty state (S5004).

[0245] If the logical address LA of the target entry E4t is not X (S5003_No), the second cache control unit 401 discards the data in the Clean state of the target entry E4t and stores the write data WD in the Dirty state in the target entry E4t (S5005).

[0246] If the target entry E4t is in the dirty state (S5001_Dirty), the second cache control unit 401 determines whether the logical address LA of the target entry E4t is X (S5006).

[0247] If the logical address LA of the target entry E4t is X (S5006_Yes), the second cache control unit 401 overwrites the dirty data of the target entry E4t with the write data WD, and maintains the target entry E4t in a dirty state (S5007).

[0248] If the logical address LA of the target entry E4t is not X (S5006_No), the second cache control unit 401 evicts the dirty data from the target entry E4t and transmits it to the nonvolatile memory 10 via the NAND controller 202. This causes the dirty data to be written to the nonvolatile memory 10. Then, the second cache control unit 401 stores the write data WD in the target entry E4t in the dirty state (S5008).

[0249] 4.2 Effects of this embodiment According to the fourth embodiment, the same effects as those of the first embodiment are achieved.

[0250] Furthermore, the memory unit 42 of the second cache 24 does not have a copy of the data stored in the memory unit 32 of the first cache 23. Therefore, according to this embodiment, the data is kept in the first cache 23 and the second cache 24, while the utilization efficiency of the second cache 24 can be improved.

[0251] Of course, the third embodiment and the first and second modifications of the first embodiment can also be applied to this embodiment.

[0252] 5. Fifth embodiment A memory system according to the fifth embodiment will be described. The memory system 3 according to the fifth embodiment differs from the fourth embodiment in that the second embodiment is applied to the fourth embodiment. The following description will mainly focus on the differences from the fourth embodiment.

[0253] 5.1 Operation of the primary and secondary caches (Operation for prefetch request PR) The operation in response to a prefetch request PR will now be described. The flowchart of the operation of the first cache 23 is the same as the flowchart of Fig. 17 shown in the fourth embodiment. The flowchart of the operation of the second cache 24 is the same as the flowcharts of Figs. 18 to 20 shown in the fourth embodiment.

[0254] (Operation for read request RR) The operation in response to the read request RR will be described with reference to Fig. 28. Fig. 28 is a flowchart showing an example of the operation of the first cache 23.

[0255] In the flowchart of the operation of the first cache 23 shown in Fig. 28, steps S236 and S237 are added to the flowcharts of Fig. 21 to 24 shown in the fourth embodiment. The flowchart of the operation of the second cache 24 is the same as the flowchart of Fig. 25 shown in the fourth embodiment.

[0256] As shown in FIG. 28, if the second cache 24 does not have ownership of the data DAT(X) (S233_No), the first cache control unit 301 performs the WDT determination process (S236).

[0257] If it is determined in the WDT determination process that the elapsed time T1 has exceeded the fixed time TT (S236_Yes), the first cache control unit 301 transmits the data DAT(X) to the host 2, transmits the data in Lock state of the target entry E3t to the second cache 24 as data in Unlock state, and stores the data DAT(X) in Unlock state in the target entry E3t (S237). After executing step S237, the first cache control unit 301 causes the second cache control unit 401 to execute the above-mentioned process 3.

[0258] (Operation in response to a write request WR) The operation in response to a write request WR will now be described. The flowchart of the operation of the first cache 23 is the same as the flowchart of Fig. 26 shown in the fourth embodiment. The flowchart of the operation of the second cache 24 is the same as the flowchart of Fig. 27 shown in the fourth embodiment.

[0259] 5.2 Effects of this embodiment According to the fifth embodiment, the same effects as those of the second and fourth embodiments can be achieved. Of course, the third embodiment and the first and second modified examples of the first embodiment can also be applied to this embodiment.

[0260] 6. Sixth embodiment A memory system according to the sixth embodiment will be described. In the memory system 3 according to the sixth embodiment, the operations of the first cache 23 and the second cache 24 are partially different from those of the fourth embodiment. The following description will mainly focus on the differences from the fourth embodiment.

[0261] In this embodiment, the memory section 42 of the second cache 24 has a copy of the data stored in the memory section 32 of the first cache 23. The operation of the first cache 23 and the second cache 24 is as follows.

[0262] 6.1 Operation of the primary and secondary caches (Operation for prefetch request PR) The operation in response to a prefetch request PR will be described with reference to Fig. 29 and Fig. 30. Fig. 29 is a flowchart showing an example of the operation of the first cache 23. Fig. 30 is a flowchart showing an example of the operation of the second cache 24.

[0263] In the flowchart of the operation of the first cache 23 shown in FIG. 29, process 1 in the flowchart of FIG. 17 shown in the fourth embodiment is replaced with process 11.

[0264] (Process 11) 30, when the second cache control unit 401 receives a request for data DAT(X) from the first cache 23, it searches the memory unit 42 and checks the cache tag CT of the target entry E4t (S6001).

[0265] If the target entry E4t is in the Empty state (S6001_Empty), the second cache control unit 401 reads the data DAT(X) from the non-volatile memory 10 via the NAND controller 202, stores the read data DAT(X) in the target entry E4t in the Clean state, and transmits it to the first cache 23 (S6002).

[0266] If the target entry E4t is in the Clean state (S6001_Clean), the second cache control unit 401 determines whether the logical address LA of the target entry E4t is X (S6003).

[0267] If the logical address LA of the target entry E4t is X (S6003_Yes), the second cache control unit 401 transmits the Clean state data of the target entry E4t to the first cache 23, and maintains the target entry E4t in the Clean state (S6004).

[0268] If the logical address LA of the target entry E4t is not X (S6003_No), the second cache control unit 401 discards the data in the Clean state of the target entry E4t, reads the data DAT(X) from the nonvolatile memory 10 via the NAND controller 202, stores the read data DAT(X) in the target entry E4t in the Clean state, and transmits it to the first cache 23 (S6005). Note that, instead of step S6005, the second cache control unit 401 may read the data DAT(X) from the nonvolatile memory 10 and transmit the read data DAT(X) to the first cache 23, thereby maintaining the target entry E4t in the Clean state. In this case, two different data can be stored in the first cache 23 and the second cache 24, which is likely to improve cache efficiency.

[0269] If the target entry E4t is in the dirty state (S6001_Dirty), the second cache control unit 401 determines whether the logical address LA of the target entry E4t is X (S6006).

[0270] If the logical address LA of the target entry E4t is X (S6006_Yes), the second cache control unit 401 transmits the dirty data of the target entry E4t to the first cache 23 and maintains the target entry E4t in the dirty state (S6007).

[0271] If the logical address LA of the target entry E4t is not X (S6006_No), the second cache control unit 401 evicts the data in the Clean state from the target entry E4t and transmits it to the non-volatile memory 10 via the NAND controller 202. Then, the second cache control unit 401 reads the data DAT(X) from the non-volatile memory 10 via the NAND controller 202, stores the read data DAT(X) in the target entry E4t in the Clean state, and transmits it to the first cache 23 (S6008). Note that, instead of step S6008, the second cache control unit 401 may read the data DAT(X) from the non-volatile memory 10 and transmit the read data DAT(X) to the first cache 23, and maintain the target entry E4t in the Dirty state. In this case, there is a high possibility that cache efficiency will improve, as in the case where the target entry E4t is in the Clean state.

[0272] (Operation for read request RR) The operation in response to a read request RR will be described with reference to Fig. 31 and Fig. 32. Fig. 31 is a flowchart showing an example of the operation of the first cache 23. Fig. 32 is a flowchart showing an example of the operation of the second cache 24.

[0273] In the flowchart of the operation of the first cache 23 shown in Figure 31, process 4 in the flowcharts of Figures 21 to 24 shown in the fourth embodiment is replaced with process 12, steps S211 to S213 are replaced with step S214, steps S222 to S225 are replaced with steps S226 and S227, and steps S232 to S235 are replaced with steps S236 and S237.

[0274] 31, when the target entry E3t is in the Empty state (S201_Empty), the first cache control unit 301 requests the data DAT(X) from the second cache 24. Specifically, the first cache control unit 301 causes the second cache control unit 401 to execute process 12 (processing to acquire the data DAT(X)), and receives the data DAT(X) from the second cache control unit 401. Details of process 12 will be described later. After executing process 12, the first cache control unit 301 transmits the data DAT(X) to the host 2 and stores it in the target entry E3t in the Unlocked state (S214).

[0275] If the target entry E3t is in a Valid state (S201_Valid) and the logical address LA of the target entry E3t is X (S221_Yes), the first cache control unit 301 sends the data of the target entry E3t in an Unlocked state to the host 2 and maintains the target entry E3t in an Unlocked state (S226).

[0276] If the target entry E3t is in a Valid state (S201_Valid) and the logical address LA of the target entry E3t is not X (S221_No), the first cache control unit 301 causes the second cache control unit 401 to execute process 12 and receives data DAT(X) from the second cache control unit 401. After executing process 12, the first cache control unit 301 discards the data in the Unlocked state of the target entry E3t, sends the data DAT(X) to the host 2, and stores it in the Unlocked state in the target entry E3t (S227).

[0277] If the target entry E3t is in the Lock state (S201_Lock) and the logical address LA of the target entry E3t is X (S231_Yes), the first cache control unit 301 sends the Lock state data of the target entry E3t to the host 2 and updates the target entry E3t to the Empty state (S236).

[0278] If the target entry E3t is in the Lock state (S201_Lock) and the logical address LA of the target entry E3t is not X (S231_No), the first cache control unit 301 causes the second cache control unit 401 to execute process 12 and receives data DAT(X) from the second cache control unit 401. After executing process 12, the first cache control unit 301 transmits the data DAT(X) to the host 2 and maintains the target entry E3t in the Lock state (S237).

[0279] (Process 12) 32, when the second cache control unit 401 of the second cache 24 receives a request for data DAT(X) from the first cache 23, it searches the memory unit 42 and checks the cache tag CT of the target entry E4t (S7001).

[0280] If the target entry E4t is in the Empty state (S7001_Empty), the second cache control unit 401 reads the data DAT(X) from the non-volatile memory 10 via the NAND controller 202, sends the read data DAT(X) to the first cache 23, and stores it in the target entry E4t in the Clean state (S7002).

[0281] If the target entry E4t is in the Clean state (S7001_Clean), the second cache control unit 401 determines whether the logical address LA of the target entry E4t is X (S7003).

[0282] If the logical address LA of the target entry E4t is X (S7003_Yes), the second cache control unit 401 transmits the Clean state data of the target entry E4t to the first cache 23, and maintains the target entry E4t in the Clean state (S7004).

[0283] If the logical address LA of the target entry E4t is not X (S7003_No), the second cache control unit 401 discards the data in the Clean state of the target entry E4t, reads the data DAT(X) from the nonvolatile memory 10 via the NAND controller 202, transmits the read data DAT(X) to the first cache 23, and stores it in the target entry E4t in the Clean state (S7005). Note that instead of step S7005, the second cache control unit 401 may read the data DAT(X) from the nonvolatile memory 10, transmit the read data DAT(X) to the first cache 23, and maintain the target entry E4t in the Clean state.

[0284] If the target entry E4t is in the dirty state (S7001_Dirty), the second cache control unit 401 determines whether the logical address LA of the target entry E4t is X (S7006).

[0285] If the logical address LA of the target entry E4t is X (S7006_Yes), the second cache control unit 401 transmits the dirty data of the target entry E4t to the first cache 23, and maintains the target entry E4t in the dirty state.

[0286] If the logical address LA of the target entry E4t is not X (S7006_No), the second cache control unit 401 evicts the dirty data from the target entry E4t and transmits it to the nonvolatile memory 10 via the NAND controller 202. As a result, the dirty data is written to the nonvolatile memory 10. Then, the second cache control unit 401 reads the data DAT(X) from the nonvolatile memory 10 via the NAND controller 202, transmits the read data DAT(X) to the first cache 23, and stores it in the clean state in the target entry E4t (S7008). Note that instead of step S7008, the second cache control unit 401 may read the data DAT(X) from the nonvolatile memory 10 and transmit the read data DAT(X) to the first cache 23, and maintain the target entry E4t in the dirty state.

[0287] (Operation in response to a write request WR) The operation in response to a write request WR will now be described. The flowchart of the operation of the first cache 23 is the same as the flowchart of Fig. 26 shown in the fourth embodiment. The flowchart of the operation of the second cache 24 is the same as the flowchart of Fig. 27 shown in the fourth embodiment.

[0288] 6.2 Effects of this embodiment According to the sixth embodiment, the same effects as those of the first embodiment are achieved.

[0289] Furthermore, the memory unit 42 of the second cache 24 has a copy of the data stored in the memory unit 32 of the first cache 23. Therefore, according to this embodiment, the first cache 23 can unconditionally discard data, thereby simplifying the operations of the first cache 23 and the second cache 24.

[0290] Furthermore, when a set of a prefetch request PR and a read request RR is repeatedly sent for the same data, if the prefetch data PD is stored in the second cache 24, it can be sent from the second cache 24 to the first cache 23. Therefore, according to this embodiment, the number of accesses to the nonvolatile memory 10 can be reduced.

[0291] Of course, the second embodiment, the third embodiment, and the first and second modified examples of the first embodiment can also be applied to this embodiment.

[0292] 7. Modifications As described above, the memory system (3) according to the embodiment includes a nonvolatile memory (10) and a memory controller (20). The memory controller (20) includes a first cache (23) connectable to a host (2), a second cache (24) connected to the first cache, and a first controller (202) that controls the nonvolatile memory. The first cache (23) has an SRAM as a storage element and includes a first memory unit (32) that stores prefetch data and read data from the nonvolatile memory, and a first control unit (301) that controls the first memory unit. The second cache (24) has a DRAM as a storage element and includes a second memory unit (42) that stores read data and write data from the host, and a second control unit (401) that controls the second memory unit. Multiple logical addresses designated by the host (2) are mapped to the first memory unit (32) using indexes. The first memory unit (32) includes a plurality of entries, each having index tag information and including a cache tag (CT) including a first field (F2) and a cache line (CL). When the first control unit (301) receives a first prefetch request (PR) for first data at a first logical address, the first control unit stores the prefetched first data in a cache line of a first entry included in the first memory unit and stores a first value indicating that the first data is prefetched data in a first field of the first entry. The first control unit (301) maintains the first entry until it receives a read request (RR) or a write request (WR) for the first logical address from the host (2).

[0293] The embodiment is not limited to the above-described embodiment, and various modifications are possible.

[0294] Furthermore, in the flowcharts described in the above embodiments, the order of the processes can be changed as much as possible.

[0295] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0296] 1...information processing system, 2...host, 3...memory system, 10...non-volatile memory, 20...memory controller, 21...host interface circuit, 22...control circuit, 23...first cache, 24...second cache, 25...management memory, 26...memory interface circuit, 31...control circuit, 32...memory unit, 33...timer circuit, 41...control circuit, 42...memory unit, 51...L2P table, 201...prefetch controller, 202...NAND controller, 301...first cache control unit, 302...measurement unit, 401...second cache control unit

Claims

1. a non-volatile memory; a first cache connectable to a host, the first cache including a first memory unit having an SRAM as a storage element and storing prefetch data and read data from the nonvolatile memory, and a first control unit controlling the first memory unit; a second cache connected to the first cache, the second cache including a second memory unit having a DRAM as a storage element and storing the read data and write data from the host, and a second control unit controlling the second memory unit; a first controller that controls the nonvolatile memory; a memory controller, Equipped with a plurality of logical addresses designated by the host are mapped to the first memory unit by indexes, the first memory unit includes a plurality of entries, each having tag information of the index and including a cache tag and a cache line, the cache tag including a first field; When the first control unit receives a first prefetch request for first data at a first logical address, the first control unit stores the prefetched first data in the cache line of a first entry included in the first memory unit, and stores a first value indicating that the first data is the prefetched data in the first field of the first entry; the first control unit maintains the first entry until a read request or a write request for the first logical address is received from the host; Memory system.

2. when the first control unit receives the first prefetch request, if no data is stored in the cache line of the first entry, the first control unit stores the first data obtained from the second cache or the nonvolatile memory in the cache line of the first entry, and stores the first value in the first field of the first entry; 10. The memory system of claim 1.

3. when the first control unit receives the first prefetch request, if the first data is stored in the cache line of the first entry and the first value is not stored in the first field of the first entry, the first control unit updates the first field of the first entry to the first value; 10. The memory system of claim 1.

4. when the first control unit receives the first prefetch request, if the first data is stored in the cache line of the first entry and the first value is stored in the first field of the first entry, the first control unit maintains the first entry; 10. The memory system of claim 1.

5. when the first control unit receives the first prefetch request, if second data at a second logical address different from the first logical address is stored in the cache line of the first entry, the first control unit evicts the second data from the first entry, stores the first data acquired from the second cache or the nonvolatile memory in the cache line of the first entry, and stores the first value in the first field of the first entry; 10. The memory system of claim 1.

6. When the first control unit receives a read request for the first data at the first logical address from the host, if data is not stored in the cache line of the first entry, the first control unit transmits the first data obtained from the second cache or the nonvolatile memory to the host, stores the first data in the cache line of the first entry, and stores a second value indicating that the first data is not the prefetch data in the first field of the first entry.

10. The memory system of claim 1.

7. when the first control unit receives a read request for the first data at the first logical address from the host, if the first data is stored in the cache line of the first entry and the first value is not stored in the first field of the first entry, the first control unit transmits the first data of the first entry to the host and maintains the first entry; 10. The memory system of claim 1.

8. when the first control unit receives a read request for the first data at the first logical address from the host, if the first data is stored in the cache line of the first entry and the first value is stored in the first field of the first entry, the first control unit transmits the first data of the first entry to the host and clears the cache line and the first field of the first entry; 10. The memory system of claim 1.

9. When the first control unit receives a read request for the first data at the first logical address from the host, if second data at a second logical address different from the first logical address is stored in the cache line of the first entry and the first value is not stored in the first field of the first entry, the first control unit evicts the second data from the first entry, transmits the first data obtained from the second cache or the nonvolatile memory to the host, stores it in the cache line of the first entry, and stores a second value indicating that the first data is not the prefetch data in the first field of the first entry.

10. The memory system of claim 1.

10. when the first control unit receives a read request for the first data at the first logical address from the host, if second data at a second logical address different from the first logical address is stored in the cache line of the first entry and the first value is stored in the first field of the first entry, the first control unit transmits the first data obtained from the second cache or the nonvolatile memory to the host and maintains the first entry; 10. The memory system of claim 1.

11. when the first control unit receives a write request for the first logical address from the host, if no data is stored in the cache line of the first entry, the first control unit maintains the first entry; 10. The memory system of claim 1.

12. when the first control unit receives a write request for the first logical address from the host, if the first data is stored in the cache line of the first entry, the first control unit clears the cache line and the first field of the first entry; 10. The memory system of claim 1.

13. when the first control unit receives a write request for the first logical address from the host, if second data of a second logical address different from the first logical address is stored in the cache line of the first entry, the first control unit maintains the first entry; 10. The memory system of claim 1.

14. The memory controller A second controller that controls the prefetch process Further comprising: the first prefetch request is transmitted by the second controller to the first control unit based on a user's designation of the prefetch process; 10. The memory system of claim 1.

15. The memory controller A second controller that controls the prefetch process Further comprising: the first prefetch request is sent by the second controller to the first control unit; 10. The memory system of claim 1.

16. the first prefetch request is sent by the host to the first control unit; 10. The memory system of claim 1.

17. The first cache a measuring unit that measures the elapsed time from the time when the first value was stored in the first field of the first entry to the current time; Further provided with When the result measured by the measurement unit exceeds a certain time, the first control unit updates the first field of the first entry to a second value indicating that the first data is not the prefetch data.

10. The memory system of claim 1.

18. The memory controller A table for converting the logical address to a physical address of the nonvolatile memory Further provided with the line size of the cache line in the first memory unit is the same as the management size of the table; 10. The memory system of claim 1.

19. the second memory unit does not have a copy of the data stored in the first memory unit; 10. The memory system of claim 1.

20. the second memory unit has a copy of the data stored in the first memory unit; 10. The memory system of claim 1.

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