Semiconductor storage device and control method for semiconductor storage device

Abstract

To provide a semiconductor storage device capable of suppressing spreading of threshold distribution, even when affected by a NWI.SOLUTION: A semiconductor storage device of this embodiment includes: a memory cell array having a plurality of memory cells; a word line connected to the gates of the plurality of memory cells; a plurality of bit lines, each connected to one end of each of the plurality of memory cells; a sense amplifier circuit applying a bit line voltage to the plurality of bit lines; and a control circuit that executes a write sequence in which a loop consisting of a set of program and verify operations is repeated multiple times. In the write sequence, the control circuit adjusts a threshold value of the memory cell connected to the selected word line based on threshold value information of the memory cell connected to an adjacent word line adjacent to the selected word line, when data is written to the memory cell connected to the selected word line to be written.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor memory device and a method for controlling the semiconductor memory device. [Background technology]

[0002] In recent years, NAND type memories have become popular as semiconductor memory devices. In such semiconductor memory devices, when data is written to a word line WLn and then written to a word line WLn+1, neighbor word-line interference (NWI) occurs, which increases the threshold voltage of each memory cell on the word line WLn to which data has already been written.

[0003] The effect of NWI is that the threshold distribution of each memory cell on word line WLn becomes wider, reducing the margin between threshold distributions and increasing the fail bit count (FBC). The effect of NWI becomes greater as the spacing between gates becomes smaller to increase memory density and as multi-level data becomes more common. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent Application Publication No. 2020 / 0312415 [Patent Document 2] US Patent Application Publication No. 2022 / 0076752 [Patent Document 3] US Patent Application Publication No. 2023 / 0091314 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present embodiment is to provide a semiconductor memory device and a method for controlling the semiconductor memory device that can suppress the spread of the threshold distribution even when affected by NWI. [Means for solving the problem]

[0006] The semiconductor memory device of this embodiment includes a memory cell array having a plurality of memory cells, each of which can be set to one of a plurality of threshold voltage levels, word lines connected to gates of the plurality of memory cells, a plurality of bit lines connected to one end of each of the plurality of memory cells, a sense amplifier circuit that applies a bit line voltage to the plurality of bit lines, and a control circuit that executes a write sequence that repeats a loop consisting of a set of a program operation for writing data to the memory cells and a verify operation for verifying the data written in the memory cells multiple times. In the write sequence, when writing data to a memory cell connected to a selected word line to be written, the control circuit adjusts the threshold of the memory cell connected to the selected word line based on threshold information of a memory cell connected to an adjacent word line adjacent to the selected word line. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram illustrating an example of a configuration of a memory system. [Figure 2] 2 is a block diagram showing an example of the configuration of a nonvolatile memory 2 in FIG. 1. FIG. [Figure 3] FIG. 2 is a diagram showing an example of the configuration of a block of a memory cell array 20 having a three-dimensional structure. [Figure 4] 3 is a block diagram showing an example of the configuration of a sense amplifier unit group 28 and a data register 29 in FIG. 2. FIG. [Figure 5] 5 is a circuit diagram showing an example of a specific configuration of a sense amplifier unit SAU in FIG. 4. FIG. [Figure 6] FIG. 10 is an explanatory diagram showing 2-3-2 coding as an example of coding. [Figure 7] FIG. 10 is a diagram showing an example of a basic command sequence when writing data. [Figure 8] FIG. 10 is a diagram showing an example of potential changes in a bit line and a selected word line during a program operation. [Figure 9] FIG. 10 is an explanatory diagram showing an example of a write sequence from states A to G. [Figure 10] 4 is a flowchart illustrating the operation of the present embodiment. [Figure 11] 10A and 10B are diagrams for explaining changes in threshold distribution due to the operation of the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In this embodiment, when writing data to a memory cell on word line WLn, the data to be written to the memory cell on word line WLn+1 is checked in advance, and the threshold value of the data to be written to the memory cell on word line WLn is adjusted to match that data pattern, thereby suppressing the effects of NWI.

[0009] (Memory system configuration) 1 is a block diagram showing an example of the configuration of a memory system. The memory system 1 of this embodiment includes a nonvolatile memory 2 and a memory controller 3. The nonvolatile memory 2 may include multiple memory chips. The memory system 1 is connectable to a host device 4. The host device 4 is, for example, an electronic device such as a personal computer or a mobile terminal.

[0010] The memory system 1 may be configured by mounting multiple chips that make up the memory system 1 on a motherboard on which the host device 4 is mounted, or may be configured as a system LSI (Large-Scale Integrated Circuit) or SoC (System-on-a-Chip) that realizes the memory system 1 in a single module. Examples of the memory system 1 include memory cards such as SD cards, SSDs (Solid-State Drives), and eMMCs (embedded-Multi-Media-Cards).

[0011] The nonvolatile memory 2 is a NAND type memory having a plurality of memory cells, and stores data in a nonvolatile manner. The specific configuration of the nonvolatile memory 2 will be described later.

[0012] The memory controller 3 issues commands to write (also called program), read, erase, etc. to the nonvolatile memory 2 in response to commands from, for example, a host device 4. The memory controller 3 also manages the memory space of the nonvolatile memory 2. The memory controller 3 includes a host interface (host I / F) circuit 10, a processor 11, a RAM (Random Access Memory) 12, a buffer memory 13, a memory interface circuit (memory I / F) circuit 14, an ECC (Error Checking and Correcting) circuit 15, etc.

[0013] The host I / F circuit 10 is connected to the host device 4 via a host bus, and performs interface processing with the host device 4. The host I / F circuit 10 also transmits and receives commands, addresses, and data to and from the host device 4.

[0014] The processor 11 is composed of, for example, a CPU (Central Processing Unit). The processor 11 controls the overall operation of the memory controller 3. For example, when the processor 11 receives a write command from the host device 4, it issues a write command to the nonvolatile memory 2 via the memory I / F circuit 14 in response to the write command from the host device 4. The same applies to read and erase operations. The processor 11 also executes various processes for managing the nonvolatile memory 2, such as wear leveling.

[0015] The RAM 12 is used as a work area for the processor 11, and stores firmware data loaded from the nonvolatile memory 2 and various tables created by the processor 11. The RAM 12 is configured from, for example, a DRAM or an SRAM.

[0016] The buffer memory 13 temporarily stores data transmitted from the host device 4 and also temporarily stores data transmitted from the nonvolatile memory 2 .

[0017] The memory I / F circuit 14 is connected to the nonvolatile memory 2 via a bus, and performs interface processing with the nonvolatile memory 2. The memory I / F circuit 14 also transmits and receives commands, addresses, and data to and from the nonvolatile memory 2.

[0018] When writing data, the ECC circuit 15 generates an error correction code for the write data, adds this error correction code to the write data, and sends the data to the memory I / F circuit 14. When reading data, the ECC circuit 15 performs error detection and / or error correction on the read data using the error correction code included in the read data. The ECC circuit 15 may be provided within the memory I / F circuit 14.

[0019] (Non-volatile memory configuration) Fig. 2 is a block diagram showing an example of the configuration of the nonvolatile memory 2 in Fig. 1. The nonvolatile memory 2 includes a memory cell array 20, an input / output circuit 21, a logic control circuit 22, a register 23, a control circuit 24, a voltage generation circuit 25, a row decoder 26, a column decoder 27, a sense amplifier unit group 28, and a data register (data cache) 29.

[0020] The memory cell array 20 includes j blocks BLK0 to BLK(j-1) and a block BLKX, where j is an integer equal to or greater than 1. Each of the blocks BLK includes a plurality of memory cell transistors. The memory cell transistors constitute electrically rewritable memory cells. The memory cell array 20 includes a plurality of bit lines BL, a plurality of word lines WL, a source line CELSRC, and the like, for controlling the voltages applied to the memory cell transistors. The specific configuration of the block BLK will be described later.

[0021] The input / output circuit 21 and the logic control circuit 22 are connected to the memory controller 3 via a bus. The input / output circuit 21 transmits and receives signals DQ (for example, DQ0 to DQ7) to and from the memory controller 3 via the bus.

[0022] The logic control circuit 22 receives external control signals (e.g., chip enable signal CEn, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, read enable signal REn, and write protect signal WPn) from the memory controller 3 via the bus. The "n" added to the signal name indicates active low. The logic control circuit 22 also sends a ready / busy signal R / Bn to the memory controller 3 via the bus.

[0023] The chip enable signal CEn is a signal for selecting and enabling a specific nonvolatile memory 2 in a system configuration in which multiple nonvolatile memories 2 are used. The chip enable signal CLE enables the command transmitted as the signal DQ to be latched in the register 23. The address latch enable signal ALE enables the address transmitted as the signal DQ to be latched in the register 23. The write enable signal WEn enables writing. The read enable signal REn enables reading. The write protect signal WPn prohibits writing and erasing. When a basic operation command is being used, the ready / busy signal R / Bn indicates whether the nonvolatile memory 2 is in a ready state (a state in which it is capable of accepting commands from the outside) in which it is not performing write, read, or erase operations, or in a busy state (a state in which it is not capable of accepting commands from the outside).

[0024] The register 23 includes a command register, an address register, and a status register. The command register temporarily holds a command. The address register temporarily holds an address. The status register temporarily holds data necessary for the operation of the nonvolatile memory 2. The register 23 is configured, for example, from an SRAM.

[0025] The control circuit 24 receives a command from the register 23 and controls the nonvolatile memory 2 in an integrated manner in accordance with a sequence based on this command.

[0026] The voltage generation circuit 25 receives a power supply voltage from outside the nonvolatile memory 2 and uses this power supply voltage to generate a plurality of voltages required for write, read, and erase operations. The voltage generation circuit 25 supplies the generated voltages to the memory cell array 20, the row decoder 26, the sense amplifier unit group 28, etc.

[0027] The row decoder 26 receives a row address from the register 23 and decodes this row address. The row decoder 26 selects a word line based on the decoded row address. The word line to which the memory cell transistor MT to be written or read is connected is called a selected word line. The row decoder 26 then transfers multiple voltages required for write, read, and erase operations to the selected block BLK.

[0028] The column decoder 27 receives a column address from the register 23 and decodes the column address, and supplies a predetermined voltage to each bit line BL based on the decoded column address.

[0029] When reading data, the sense amplifier unit group 28 senses and amplifies data read from the memory cell transistors MT onto the bit lines BL, and when writing data, the sense amplifier unit group 28 supplies write data to the bit lines BL.

[0030] When reading data, the data register 29 temporarily holds the data transferred from the sense amplifier unit group 28 and transfers it serially to the input / output circuit 21. When writing data, the data register 29 temporarily holds the data transferred serially from the input / output circuit 21 and transfers it to the sense amplifier unit group 28. The data register 29 is configured with an SRAM or the like.

[0031] (Block configuration of memory cell array) 3 is a diagram showing an example of the configuration of a block of a three-dimensional memory cell array 20. Fig. 3 shows one block BLK among the multiple blocks that make up the memory cell array 20. The other blocks in the memory cell array have the same configuration as Fig. 3.

[0032] As shown in the figure, the block BLK includes, for example, four string units SU0 to SU3 (hereinafter, these will be collectively referred to as string unit SU). Each string unit SU has a NAND string NS including multiple memory cell transistors MT (MT0 to MT7) and select gate transistors ST1 and ST2. While the number of memory cell transistors MT included in the NAND string NS is eight in FIG. 3, it may be greater. Although the select gate transistors ST1 and ST2 are shown as a single transistor in the electrical circuit, they may be structurally the same as the memory cell transistors. Furthermore, multiple select gate transistors may be used as the select gate transistors ST1 and ST2, respectively. Furthermore, dummy cell transistors may be provided between the memory cell transistors MT and the select gate transistors ST1 and ST2.

[0033] The memory cell transistors MT are arranged so as to be connected in series between the select gate transistors ST1 and ST2. The memory cell transistor MT7 on one end (the bit line side) is connected to the select gate transistor ST1, and the memory cell transistor MT0 on the other end (the source line side) is connected to the select gate transistor ST2.

[0034] The gates of the select gate transistors ST1 of the string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3 (hereinafter, these will be collectively referred to as select gate line SGD), respectively. The gates of the select gate transistors ST2 of the string units SU0 to SU3 are connected to select gate lines SGS0 to SGS3 (hereinafter, these will be collectively referred to as select gate line SGS), respectively. Note that the gates of the multiple select gate transistors ST2 in each block BLK may be connected to a common select gate line SGS.

[0035] The gates of memory cell transistors MT0 to MT7 in the same block BLK are commonly connected to word lines WL0 to WL7, respectively. That is, the word lines WL0 to WL7 are commonly connected among multiple string units SU0 to SU3 in the same block BLK, whereas the select gate lines SGD are independent for each string unit SU0 to SU3 even within the same block BLK. The gates of memory cell transistors MTi in the same row in a block BLK are connected to the same word line WLi.

[0036] Each NAND string NS is connected to a corresponding bit line. Therefore, each memory cell transistor MT is connected to a bit line via select gate transistors ST1, ST2 and other memory cell transistors MT included in the NAND string NS. Generally, data in the memory cell transistors MT in the same block BLK is erased collectively. On the other hand, data is typically read and written collectively from multiple memory cell transistors MT commonly connected to one word line WL arranged in one string unit SU. Such a set of memory cell transistors MT sharing a word line WL in one string unit SU is called a cell unit CU.

[0037] A write operation to a cell unit CU is performed in units of pages. For example, if each cell is a triple-level cell (TLC) that can hold 3 bits (8 values), one cell unit CU can hold 3 pages of data. The 3 bits that each memory cell transistor MT can hold correspond to the 3 pages.

[0038] (Configuration of sense amplifier unit and data register) FIG. 4 is a block diagram showing an example of the configuration of the sense amplifier unit group 28 and the data register 29 in FIG.

[0039] The sense amplifier unit group 28 includes sense amplifier units SAU0 to SAU(m-1) (hereinafter collectively referred to as sense amplifier unit SAU) corresponding to the bit lines BL0 to BL(m-1). Each sense amplifier unit SAU includes a sense amplifier SA and data latch circuits SDL, ADL, BDL, and CDL. The sense amplifier SA and the data latch circuits SDL, ADL, BDL, and CDL are connected to each other so that data can be transferred between them.

[0040] The data latch circuits SDL, ADL, BDL, and CDL temporarily hold data. During a write operation, the sense amplifier SA controls the voltage of the bit line BL according to the data held by the data latch circuit SDL. The data latch circuits ADL, BDL, and CDL are used for multi-value operations in which the memory cell transistor MT holds two or more bits of data. That is, the data latch circuit ADL is used to hold write data for the Lower page. The data latch circuit BDL is used to hold write data for the Middle page. The data latch circuit CDL is used to hold write data for the Upper page. The number of data latch circuits included in the sense amplifier unit SAU is determined according to the number of bits held by one memory cell transistor MT.

[0041] During a read operation, the sense amplifier SA detects the data read out to the corresponding bit line BL and determines whether the data is 0 or 1. During a write operation, the sense amplifier SA applies a voltage to the bit line BL based on the write data.

[0042] The data register 29 includes data latch circuits XDL, the number of which corresponds to the sense amplifier units SAU0 to SAU(m-1). The data latch circuits XDL are connected to the input / output circuit 21. The data latch circuits XDL temporarily hold write data sent from the input / output circuit 21 and also temporarily hold read data sent from the sense amplifier units SAU. More specifically, data transfer between the input / output circuit 21 and the sense amplifier unit group 28 is performed via one page of data latch circuits XDL. Write data received by the input / output circuit 21 is transferred to one of the data latch circuits ADL, BDL, and CDL via the data latch circuit XDL. Read data read by the sense amplifier SA is transferred to the input / output circuit 21 via the data latch circuit XDL.

[0043] As will be described later, when writing data to a memory cell on word line WLn, the data latch circuit XDL holds threshold information according to the data pattern on word line WLn+1.

[0044] (Sense amplifier circuit) FIG. 5 is a circuit diagram showing an example of a specific configuration of the sense amplifier unit SAU in FIG.

[0045] 5, the sense amplifier unit SAU includes a sense amplifier section SA and data latch circuits SDL, ADL, BDL, and CDL. The sense amplifier section SA and the data latch circuits SDL, ADL, BDL, CDL, and XDL are connected by a bus LBUS so as to be able to receive data from each other.

[0046] The data latch circuit SDL includes, for example, inverters 60 and 61 and n-channel MOS transistors 62 and 63. The input node of the inverter 60 and the output node of the inverter 61 are connected to a node LAT. The input node of the inverter 61 and the output node of the inverter 60 are connected to a node / LAT. The inverters 60 and 61 hold the data at the nodes / LAT and LAT. Write data is supplied to the node LAT. The data held at the node / LAT is the inverted data of the data held at the node LAT.

[0047] One end of the drain-source path of transistor 62 is connected to node / LAT, and the other end is connected to bus LBUS. One end of the drain-source path of transistor 63 is connected to node LAT, and the other end is connected to bus LBUS. A control signal STL is input to the gate of transistor 63, and a control signal STI is input to the gate of transistor 62.

[0048] The circuit configurations of the data latch circuits ADL, BDL, CDL and XDL are the same as that of the data latch circuit SDL, and therefore description thereof will be omitted. Various control signals supplied to the sense amplifier unit SAU are provided by the control circuit 24.

[0049] The sense amplifier section SA includes, for example, a p-channel MOS transistor 50, n-channel MOS transistors 51 to 58, and a capacitor 59.

[0050] In a read operation, the sense amplifier unit SA senses the data read out to the corresponding bit line BL and determines whether the read data is "0" or "1." In a program operation, the sense amplifier unit SA sets the corresponding bit line BL to a voltage value according to the data "0" or "1" to be written.

[0051] In the sense amplifier section SA, transistors 50 to 54 are involved in the program operation. The source-drain path of transistor 50 serving as a second transistor and the drain-source path of transistor 51 are connected in series between a power supply line that supplies voltage VDD, which is the internal power supply voltage, and node COM. The drain-source path of transistor 54 serving as a third transistor is connected between node COM and node CELSRC, which supplies voltage VSS, which is the ground voltage. The drain-source path of transistor 52 serving as a first transistor and the drain-source path of transistor 53 are connected in series between node COM and bit line BL.

[0052] The gates of transistors 50 and 54 are connected to node / LAT. Therefore, when node LAT is at a low level (hereinafter referred to as an L level) corresponding to data "0," node / LAT is maintained at a high level (hereinafter referred to as an H level), transistor 50 is off, and transistor 54 is on. Conversely, when node LAT is at an H level corresponding to data "1," node / LAT is maintained at an L level, transistor 50 is on, and transistor 54 is off.

[0053] During a program operation, control signals HLL and XXL supplied to the gates of transistors 55 and 56, respectively, are at L level, turning transistors 55 and 56 off. A control signal BLX supplied to transistor 51 is at H level, turning transistor 51 on. During a normal program operation, control signals BLC and BLS cause transistors 52 and 53 to conduct.

[0054] Therefore, when "0" data is held at node LAT, transistor 50 is turned off and transistor 54 is turned on, and a bit line voltage such as voltage VSS (e.g., 0V) from node CELSRC is supplied to bit line BL. Also, when "1" data is held at node LAT, transistor 50 is turned on and transistor 54 is turned off, and a bit line voltage such as 2.5V is supplied to bit line BL in accordance with control signals BLC and BLS given to transistors 52 and 53.

[0055] Fig. 6 is an explanatory diagram showing 2-3-2 coding as an example of coding, which shows the values ​​of the UPPER (upper) bit, MIDDLE (middle) bit, and LOWER (lower) bit of data for each threshold distribution.

[0056] In the example of Figure 6, memory cell transistors at Er level store data (1,1,1), memory cell transistors at A level store data (1,1,0), memory cell transistors at B level store data (1,0,0), memory cell transistors at C level store data (0,0,0), memory cell transistors at D level store data (0,1,0), memory cell transistors at E level store data (0,1,1), memory cell transistors at F level store data (0,0,1), and memory cell transistors at G level store data (1,0,1).

[0057] Along with the data to be written to the memory cell of word line WLn, threshold information corresponding to the data pattern to be written to the memory cell of word line WLn+1 is transferred to the data latch circuit XDL. The data pattern to be written to the memory cell of word line WLn+1 is binarized into one with a "high" threshold and one with a "low" threshold. For example, if the data pattern to be written to the memory cell of word line WLn+1 is between Er level and C level, the threshold is determined to be "low," and if it is between D level and G level, the threshold is determined to be "high." If the threshold of the data to be written to the memory cell of word line WLn+1 is "low," a "1" is input as the threshold information, and if the threshold of the data to be written to the memory cell of word line WLn+1 is "high," a "0" is input as the threshold information. The threshold information is calculated by the memory controller 3 based on the data pattern to be written to the memory cell of word line WLn+1. The data pattern to be written to the memory cells of word line WLn+1 may be temporarily stored in the memory cells of memory cell array 20, and the control circuit 24 of nonvolatile memory 2 may calculate threshold information based on the stored data pattern. The control circuit 24 may also temporarily store the calculated threshold information in the memory cells.

[0058] Input of threshold information according to the data pattern of word line WLn+1 is performed by the command sequence shown in Fig. 7. Fig. 7 is a diagram showing an example of a basic command sequence when writing data.

[0059] 7, in the command sequence, lower bit data, middle bit data, and upper bit data are input in that order. After the upper bit data is input, threshold information indicating whether the threshold of word line WLn+1 is "high" or "low" is input.

[0060] As described above, the lower bit data, middle bit data, and upper bit data are temporarily held in the data latch circuit XDL, and then transferred to the data latch circuits ADL, BDL, and CDL, respectively.

[0061] Therefore, when writing data, once the write data is transferred from the data latch circuit XDL to the data latch circuits ADL, BDL, and CDL, the data latch circuit XDL is not used and remains empty. Therefore, after inputting the upper bit data, the threshold information for the word line WLn+1 is input and stored in the empty (unused) data latch circuit XDL. This eliminates the need to provide a new data latch circuit to store the threshold information for the word line WLn+1, and prevents an increase in circuit size.

[0062] In this embodiment, when writing data to word line WLn, which is the selected word line to be written to, a determination is made as to whether or not to apply a weak program pulse based on the threshold information of word line WLn+1, which is the adjacent word line adjacent to word line WLn, and the threshold is adjusted when writing data to word line WLn.

[0063] This weak program pulse is applied by adjusting the voltage of the bit line BL, similar to the QPW (Quick Pass Write) operation. In the QPW operation, a voltage higher than the "L" level (ground voltage Vss, e.g., 0V) and lower than the "H" level (write inhibit voltage Vdd, e.g., 2.5V) is applied to the bit line BL corresponding to the memory cell whose threshold value is to be increased by a small amount. As a result, the QPW operation performs three types of control for multiple memory cells included in a memory cell group: increasing the threshold value, maintaining the threshold value, or increasing the threshold value by a small amount.

[0064] FIG. 8 is a diagram showing an example of potential changes on the bit line and the selected word line during a program operation.

[0065] During a program operation (write operation), a ground voltage Vss is applied to the bit line BL connected to the memory cell to which writing has not been completed. During a program operation, a program voltage VPGM is applied to the selected word line. The program voltage VPGM increases stepwise by a predetermined voltage step (ΔVPGM) as the loop progresses. A write pass voltage VPASS is applied to unselected word lines. The write pass voltage VPASS is a voltage lower than the program voltage VPGM.

[0066] Here, the loop that has passed the verify is called loop N. In loop N+1, the next loop after loop N, threshold information corresponding to the data pattern of word line WLn+1 is confirmed. In loop N+1, the voltage of the bit line BL connected to the memory cell of word line WLn that is adjacent to the memory cell with a high threshold of word line WLn+1 is increased to write inhibit voltage Vdd to prevent additional writing from occurring.

[0067] Meanwhile, the bit line BL connected to the memory cell on word line WLn, adjacent to the memory cell on word line WLn+1 with a low threshold voltage, has its voltage slightly increased to voltage Vm in loop N+1, reducing the potential difference with the program voltage VPGM compared to loop N, thereby applying a weak program pulse. In this way, similar to the QPW operation, controlling the voltage applied to the bit line BL allows the threshold voltage to be increased with a small change. Voltage Vm is higher than ground voltage Vss and lower than write inhibit voltage Vdd. This allows an additional program operation (application of a weak program pulse) to be achieved simply by adding one loop to the number of loops required for the normal program operation.

[0068] A more detailed explanation will be given. FIG. 9 is an explanatory diagram showing an example of a write sequence from state A to state G. For example, assume that a memory cell connected to word line WLn has passed the verify test with a threshold voltage of A in the third loop. This memory cell is designated as memory cell M. A memory cell adjacent to memory cell M and connected to word line WLn+1 is designated as memory cell X. In this comparative example, when program voltage VPGM_4 is applied to WLn in the fourth loop, write inhibit voltage Vdd is applied to bit line B connected to memory cell M, regardless of the threshold voltage to be written to memory cell X. In this embodiment, if the threshold voltage to be written to memory cell X is low, voltage Vm is applied to bit line B to perform weak write to memory cell M. If the threshold voltage to be written to memory cell X is high, write inhibit voltage Vdd is applied to bit line B, and writing to memory cell M is inhibited.

[0069] Assume that the memory cell connected to word line WLn passes the verify of threshold voltage G in the 18th loop, which is the scheduled final loop. This memory cell is called memory cell N. The memory cell adjacent to memory cell N and connected to word line WLn+1 is called memory cell Y. Because this is the final loop, regardless of the threshold voltage to be written to memory cell Y, weak writing to memory cell N is not performed in the 19th loop.

[0070] In this way, in this embodiment, the number of loops is not added to the planned number of loops, so the write time is not increased.

[0071] Alternatively, weak programming according to the threshold voltage to be written to memory cell Y may be performed on memory cell N as the 19th loop.

[0072] Fig. 10 is a flowchart for explaining the operation of this embodiment, and Fig. 11 is a diagram for explaining the change in threshold distribution due to the operation of this embodiment.

[0073] First, data to be written to the memory cell of word line WLn is input (S1). The data to be written to the memory cell of word line WLn is transferred to the data latch circuits ADL, BDL, and CDL via the data latch circuit XDL, and is held by the data latch circuits ADL, BDL, and CDL. Next, threshold information for the memory cell of word line WLn+1 is input (S2). The threshold information for the memory cell of word line WLn+1 is held by an unused data latch circuit XDL.

[0074] Next, a program pulse (program voltage VPGM) is applied to the word line corresponding to the page to be written (S3), and a program operation is performed. After the program operation, a program verify is performed to determine whether the threshold voltage has reached the desired target voltage, and the program verify result is determined to be verify pass or verify fail (S4).

[0075] If the verify is determined to be fail (S4: NG), the process returns to S3, and the loop of program operation and program verify is executed multiple times. On the other hand, if the verify is determined to be pass (S4: OK), the process proceeds to S5. The threshold distribution D1 in Figure 11 shows the threshold distribution when the memory cell of word line WLn is determined to be verify pass.

[0076] Subsequently, if the verify is determined to be passed in the process of S4, the threshold information of the word line WLn+1 is confirmed (S5).

[0077] If it is determined that the threshold value of the memory cell on word line WLn+1 is low based on the threshold value information of word line WLn+1, a weak program pulse is applied to the memory cell on word line WLn (S6), and the process ends.On the other hand, if it is determined that the threshold value of the memory cell on word line WLn+1 is high based on the threshold value information of word line WLn+1, the process ends.

[0078] 11, when a weak program pulse is applied and additional writing is performed, the threshold of the memory cell to which additional writing has been performed increases. Threshold distribution D2 shows the threshold distribution of the memory cell to which additional writing has been performed.

[0079] On the other hand, if a weak program pulse is not applied and no additional programming is performed, the thresholds of the memory cells that have not been programmed remain unchanged. Threshold distribution D3 shows the threshold distribution of memory cells that have not been programmed. As a result, when the programming operation for word line WLn is completed, the threshold distribution for word line WLn has widened.

[0080] Once the programming operation for word line WLn is completed, the programming operation for word line WLn+1 is performed. If the threshold value of the data to be written to the memory cell for word line WLn+1 is low, the effect of NWI is small, and the threshold value of the memory cell for word line WLn remains almost unchanged. Threshold distribution D4 shows the threshold distribution of the memory cell for word line WLn, which was little affected by NWI.

[0081] On the other hand, if the threshold value of the data written to the memory cell on word line WLn+1 is high, the NWI will cause the threshold value of the memory cell on word line WLn to increase. Threshold distribution D5 shows the threshold distribution of the memory cell on word line WLn whose threshold value has increased due to the NWI.

[0082] In this way, when the program operation of word line WLn+1 is completed, the threshold of the memory cell of word line WLn adjacent to the memory cell with a high threshold of word line WLn+1 becomes higher due to the influence of NWI. As a result, when the program operation of word line WLn+1 is completed, the threshold distribution of word line WLn becomes narrower.

[0083] As described above, after the verify pass, the threshold information corresponding to the data pattern of word line WLn+1 is checked, and if the threshold is "high," the process is terminated, and if the threshold is "low," a weak program pulse is applied. As a result of this process, after the write (program) operation of word line WLn+1 is completed, the threshold of the memory cell of word line WLn, to which the weak program pulse was not applied, becomes high due to the influence of NWI.

[0084] This allows the threshold voltage of the memory cell on word line WLn to be approximately the same whether the threshold voltage of the memory cell on word line WLn+1 is low or high, thereby preventing the threshold voltage distribution from widening (thickening of the distribution).In addition, since a margin between the threshold voltage distributions can be secured, an increase in the fail bit count (FBC) can be prevented.

[0085] Although several embodiments of the present invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0086] 1...memory system, 2...non-volatile memory, 3...memory controller, 4...host device, 10...host I / F circuit, 11...processor, 12...RAM, 13...buffer memory, 14...memory I / F circuit, 15...ECC circuit, 20...memory cell array, 21...input / output circuit, 22...logic control circuit, 23...register, 24...control circuit, 25...voltage generation circuit, 26...row decoder, 27...column decoder, 28...sense amplifier unit group, 29...data register

Claims

1. a memory cell array including a plurality of memory cells each of which can be set to one of a plurality of threshold voltage levels; a word line connected to the gates of the plurality of memory cells; a plurality of bit lines respectively connected to one end of the plurality of memory cells; a sense amplifier circuit that applies a bit line voltage to the plurality of bit lines; a control circuit that executes a write sequence that repeats a loop consisting of a set of a program operation for writing data into the memory cells and a verify operation for verifying the data written into the memory cells a plurality of times; and The control circuit, in the write sequence, when writing data to a memory cell connected to a selected word line to be written to, adjusts the threshold of the memory cell connected to the selected word line based on threshold information of a memory cell connected to an adjacent word line adjacent to the selected word line.

2. 2. The semiconductor memory device according to claim 1, wherein the control circuit adjusts the threshold value of the memory cell connected to the selected word line in a loop next to a loop in which the verify operation is determined to be verify pass.

3. 3. The semiconductor memory device according to claim 2, wherein when the control circuit determines based on the threshold information that the threshold of the memory cell connected to the adjacent word line is low, it applies a voltage higher than the ground voltage and lower than the write inhibit voltage to the bit line connected to the memory cell connected to the selected word line to perform additional writing.

4. 2. The semiconductor memory device according to claim 1, wherein the threshold information is calculated based on a data pattern of memory cells connected to the adjacent word line.

5. a data pattern of memory cells connected to the adjacent word lines is held in a part of the plurality of memory cell arrays; 2. The semiconductor memory device according to claim 1, wherein the control circuit calculates the threshold information based on the data pattern.

6. 6. The semiconductor memory device according to claim 5, wherein the control circuit stores the threshold information in a part of the memory cell array.

7. a memory cell array including a plurality of memory cells each of which can be set to one of a plurality of threshold voltage levels; a word line connected to the gates of the plurality of memory cells; a plurality of bit lines respectively connected to one end of the plurality of memory cells; a sense amplifier circuit that applies a bit line voltage to the plurality of bit lines; a control circuit that executes a write sequence that repeats a loop consisting of a set of a program operation for writing data into the memory cells and a verify operation for verifying the data written into the memory cells a plurality of times; A method for controlling a semiconductor memory device having A control method for a semiconductor memory device, in which, in the write sequence, when writing data to a memory cell connected to a selected word line to be written to, the threshold of the memory cell connected to the selected word line is adjusted based on threshold information of a memory cell connected to an adjacent word line adjacent to the selected word line.

8. 8. The method for controlling a semiconductor memory device according to claim 7, wherein the threshold value of a memory cell connected to the selected word line is adjusted in a loop next to a loop in which the verify operation is determined to be verify pass.

9. 9. A method for controlling a semiconductor memory device according to claim 8, wherein, when it is determined based on the threshold information that the threshold of the memory cell connected to the adjacent word line is low, a voltage higher than the ground voltage and lower than the write inhibit voltage is applied to the bit line connected to the memory cell connected to the selected word line to perform additional writing.

10. 8. The method for controlling a semiconductor memory device according to claim 7, wherein the threshold information is calculated based on a data pattern of memory cells connected to the adjacent word line.

11. a data pattern of memory cells connected to the adjacent word lines is held in a part of the plurality of memory cell arrays; 8. The method for controlling a semiconductor memory device according to claim 7, wherein the control circuit calculates the threshold information based on the data pattern.

12. 12. The method for controlling a semiconductor memory device according to claim 11, wherein the control circuit stores the threshold information in a part of the memory cell array.

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