Semiconductor device and storage medium

Abstract

To provide a semiconductor device and a storage medium to realize efficient logical operations using a memory device.SOLUTION: A semiconductor device according to the embodiment includes a first bit line, a plurality of strings, and a first control circuit. The plurality of strings are connected to the first bit line. Each of the plurality of strings includes a selection transistor and a plurality of memory cells connected in series. The first control circuit is configured to perform a logical operation. In the logical operation, the first control circuit is configured to perform a read operation by applying a first voltage to selection transistors of at least two of the plurality of strings, applying a second voltage lower than the first voltage to selection transistors of strings other than the at least two strings, applying a third voltage to at least two of the plurality of memory cells in each of the plurality of strings, and applying a fourth voltage higher than the third voltage to memory cells other than the at least two memory cells.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device and a storage medium. [Background technology]

[0002] NAND flash memories capable of storing data in a nonvolatile manner are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2021-508906 Summary of the Invention [Problem to be solved by the invention]

[0004] To realize efficient logical operations using memory devices. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a first bit line, a plurality of strings, and a first control circuit. The plurality of strings are connected to the first bit line. Each of the plurality of strings includes a selection transistor and a plurality of memory cells connected in series. The first control circuit is configured to perform a logical operation. In the logical operation, the first control circuit is configured to perform a read operation by applying a first voltage to the selection transistors of at least two of the plurality of strings, applying a second voltage lower than the first voltage to the selection transistors of strings other than the at least two strings, applying a third voltage to at least two of the plurality of memory cells in each of the plurality of strings, and applying a fourth voltage higher than the third voltage to memory cells other than the at least two memory cells. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of an information processing system according to a first embodiment. [Figure 2] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device according to a first embodiment. [Figure 3] FIG. 2 is a block diagram showing an example of the configuration of an information processing unit included in the semiconductor device according to the first embodiment. [Figure 4] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the semiconductor device according to the first embodiment. [Figure 5] 5 is a flowchart showing an example of information processing of the semiconductor device according to the first embodiment. [Figure 6] FIG. 3 is a schematic diagram showing an example of a read operation of the semiconductor device according to the first embodiment. [Figure 7] FIG. 10 is a block diagram showing an example of the configuration of an information processing unit included in the semiconductor device according to the second embodiment. [Figure 8] 10 is a flowchart showing an example of information processing of the semiconductor device according to the second embodiment. [Figure 9] FIG. 10 is a block diagram showing an example of the configuration of a semiconductor device according to a third embodiment. [Figure 10] 10 is a flowchart showing an example of information processing of the semiconductor device according to the third embodiment. [Figure 11] FIG. 11 is a schematic diagram showing an example of threshold voltage distribution of a memory cell transistor included in a semiconductor device according to a fourth embodiment. [Figure 12] 10A and 10B are schematic diagrams showing a specific example of storage processing in the semiconductor device according to the fourth embodiment. [Figure 13] 10A and 10B are schematic diagrams showing a specific example of storage processing in the semiconductor device according to the fourth embodiment. [Figure 14] 10A and 10B are schematic diagrams showing a specific example of storage processing in the semiconductor device according to the fourth embodiment. [Figure 15] 10A and 10B are schematic diagrams showing a specific example of a comparison process of a semiconductor device according to a fourth embodiment. [Figure 16] 10A and 10B are schematic diagrams showing a specific example of a comparison process of a semiconductor device according to a fourth embodiment. [Figure 17] 10A and 10B are schematic diagrams showing a specific example of addition processing in the semiconductor device according to the fourth embodiment. [Figure 18] 10A and 10B are schematic diagrams showing a specific example of addition processing in the semiconductor device according to the fourth embodiment. [Figure 19] 10A and 10B are schematic diagrams showing a specific example of addition processing in the semiconductor device according to the fourth embodiment. [Figure 20] FIG. 10 is a schematic diagram showing an example of a method of arranging data in a memory cell array included in a semiconductor device according to a fourth embodiment. [Figure 21] 10A and 10B are schematic diagrams showing a specific example of an exclusive OR (XOR) process in the semiconductor device according to the fourth embodiment. [Figure 22] 10A and 10B are schematic diagrams showing a specific example of an exclusive OR (XOR) process in the semiconductor device according to the fourth embodiment. [Figure 23] 10A and 10B are schematic diagrams showing a specific example of an exclusive OR (XOR) process in the semiconductor device according to the fourth embodiment. [Figure 24] FIG. 10 is a schematic diagram showing an example of parallel processing of exclusive OR (XOR) processing in the semiconductor device according to the fourth embodiment. [Figure 25] 10A and 10B are schematic diagrams showing a specific example of exclusive NOR (XNOR) processing in the semiconductor device according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Each embodiment will be described below with reference to the drawings. Each embodiment illustrates an apparatus or method for embodying the technical idea of ​​the invention. The drawings are schematic or conceptual. In this specification, components having substantially the same function and configuration are assigned the same reference numerals. Numbers and letters added to the reference numerals are used to refer to the same reference numerals and to distinguish between similar elements.

[0008] <1> First embodiment The first embodiment relates to an information processing system 1 that executes logical operations using a memory device. The information processing system 1 according to the first embodiment will be described below.

[0009] <1-1> Configuration First, the configuration of an information processing system 1 according to the first embodiment will be described.

[0010] <1-1-1> Configuration of information processing system 1 FIG. 1 is a block diagram showing an example of the configuration of an information processing system 1 according to the first embodiment. As shown in FIG. 1, the information processing system 1 includes, for example, a semiconductor device 10 and a host device 20. The semiconductor device 10 operates based on instructions from the host device 20. The host device 20 is, for example, an information terminal such as a PC (Personal Computer). The semiconductor device 10 and the host device 20 are configured to be able to communicate with each other. For example, the host device 20 transmits input data, commands, queries, etc. to the semiconductor device 10. The semiconductor device 10 transmits output data, responses to queries, etc. to the host device 20.

[0011] The semiconductor device 10 is a memory device that has the function of executing logical operations. The semiconductor device 10 includes, for example, a configuration similar to that of a NAND flash memory having memory cells stacked three-dimensionally. The semiconductor device 10 can store input data received from the host device 20 in an internal storage area. The semiconductor device 10 can also execute operations based on commands, queries, etc. received from the host device 20. When the semiconductor device 10 receives a query from the host device 20, it can execute information processing corresponding to the query using the storage area and transmit the results of the information processing as a response to the host device 20.

[0012] <1-1-2> Configuration of the semiconductor device 10 2 is a block diagram showing an example of the configuration of the semiconductor device 10 according to the first embodiment. As shown in Fig. 2, the semiconductor device 10 includes, for example, a plurality of information processing units 11 (11-1, 11-2, and 11-3), a control circuit 12, a plane management circuit 13, an external access management circuit 14, a memory circuit 15, and an input / output circuit 16.

[0013] The information processing unit 11 has a plane corresponding to a circuit capable of storing data. The plane is configured, for example, by a memory cell array including a set of multiple memory cells, and wiring and peripheral circuits for controlling the memory cell array. The information processing unit 11 is configured to be able to perform logical operations by reading data from the plane. Note that each of the multiple information processing units 11 included in the semiconductor device 10 may be assigned a specific logical operation function. In the following, a case will be described in which the semiconductor device 10 has three information processing units 11-1, 11-2, and 11-3.

[0014] The control circuit 12 controls the overall operation of the semiconductor device 10. Specifically, the control circuit 12 controls the external access management circuit 14 according to the operating state of each information processing unit 11, thereby restricting access by the host device 20 to the semiconductor device 10. The control circuit 12 can transfer data between the memory circuit 15 and each information processing unit 11. Data transferred from the memory circuit 15 to the information processing unit 11 includes input data received from the host device 20 and data used for logical operations. Data transferred from the information processing unit 11 to the memory circuit 15 includes output data read from the plane of the information processing unit 11 and operation results. The control circuit 12 can generate commands such as read operations, write operations, and erase operations based on command and address information stored in the memory circuit 15 and plane information acquired from the plane management circuit 13, and transmit the generated commands to any of the multiple information processing units 11.

[0015] The plane management circuit 13 manages each plane of the multiple information processing units 11. The plane management circuit 13 collects information related to the plane of each information processing unit 11. The plane management circuit 13 stores the collected information as plane information in an internal storage circuit. The plane information is accessed by the control circuit 12 and used as configuration data related to logical operations. For example, the control circuit 12 selects memory cells connected to which word lines WL, select gate lines SGD, and bit lines BL are to be used for logical operations based on the plane information. The selection of such memory cells is determined, for example, by software such as a linker using configuration data.

[0016] The external access management circuit 14 manages access from the host device 20 to the semiconductor device 10. The external access management circuit 14 controls the transmission and reception of data and the like between the semiconductor device 10 and the host device 20 using the input / output circuit 16, for example, based on a control signal input from the host device 20. The external access management circuit 14 also has an external access flag. The external access flag holds "1" when an instruction related to a logical operation is accepted or when the result of the logical operation can be output, and holds "0" when an instruction related to a logical operation is not accepted. The value of the external access flag can be changed by the control circuit 12. An external access flag may be provided for each information processing unit 11.

[0017] The memory circuit 15 temporarily stores information used in the operation of the semiconductor device 10. The memory circuit 15 includes, for example, a register circuit and a cache memory. For example, the memory circuit 15 temporarily stores input data, commands, queries, and address information. The input data is, for example, data used in logical operations by the semiconductor device 10 or data stored in a database. The commands include instructions related to various operations of the semiconductor device 10. The queries are instruction statements related to logical operations to be executed by the information processing unit 11. The address information includes, for example, a block address, a page address, a column address, etc.

[0018] The input / output circuit 16 is an interface circuit that controls the transmission and reception of signals such as data between the semiconductor device 10 and the host device 20. For example, under the control of the external access management circuit 14, the input / output circuit 16 transmits input data, commands, queries, etc. received from the host device 20 to the memory circuit 15, and transmits output data, responses, etc. received from the memory circuit 15 to the host device 20. Note that the input / output circuit 16 may also directly transmit and receive data, queries, responses, etc. to and from each information processing unit 11.

[0019] <1-1-3> Configuration of information processing unit 11 3 is a block diagram showing an example of the configuration of the information processing unit 11 included in the semiconductor device 10 according to the first embodiment. As shown in FIG. 3, the information processing unit 11 includes, for example, a memory cell array 110, a driver circuit 111, a row decoder module 112, a sense amplifier module 113, a read control circuit 114, a write control circuit 115, an erase control circuit 116, an output holding register 117, and a register output circuit 118. A plane corresponds to, for example, a set of the memory cell array 110, the driver circuit 111, the row decoder module 112, and the sense amplifier module 113. Note that a plane only needs to include at least the memory cell array 110.

[0020] The memory cell array 110 includes a plurality of blocks BLK0 to BLKn ("n" is an integer equal to or greater than 1). A block BLK is a collection of a plurality of memory cells. A block BLK corresponds, for example, to a unit of data erasure. A block BLK includes a plurality of pages. A page corresponds to a unit in which data is read and written. Although not shown, the memory cell array 110 is provided with a plurality of bit lines BL0 to BLm ("m" is an integer equal to or greater than 1), a plurality of word lines WL, and a plurality of select gate lines SGD. Each memory cell is associated with, for example, one bit line BL and one word line WL. Each block BLK is associated with at least one select gate line SGD.

[0021] The driver circuit 111 generates voltages used in read operations, write operations, erase operations, etc. The driver circuit 111 then supplies the generated voltages to the row decoder module 112, the sense amplifier module 113, etc.

[0022] The row decoder module 112 is a circuit used to select a block BLK to be operated and to transfer voltages to wiring such as the select gate line SGD, the word line WL, and the select gate line SGS. The row decoder module 112 includes a plurality of row decoders RD0 to RDn. The row decoders RD0 to RDn are associated with the blocks BLK0 to BLKn, respectively, and are used to select the blocks BLK. Each row decoder RD transfers a voltage generated by the driver circuit 111 to various wirings provided in the memory cell array 110.

[0023] The sense amplifier module 113 is a circuit used to transfer voltages to each bit line BL and read data. The sense amplifier module 113 includes a plurality of sense amplifier units SAU0 to SAUm. The sense amplifier units SAU0 to SAUm are associated with a plurality of bit lines BL0 to BLm, respectively. Each sense amplifier unit SAU includes a sense amplifier capable of determining data based on the voltage of the associated bit line BL, a latch circuit for temporarily holding data, and the like.

[0024] The read control circuit 114 executes a read operation based on a read operation command (hereinafter referred to as a read command) received from the control circuit 12. The read command corresponding to a logical operation is configured to individually control the voltages applied to at least all word lines WL and all select gate lines SGD that are the target of the read operation. In a read operation corresponding to a logical operation, the voltages applied to the word lines WL are set to the same value for each layer in multiple blocks BLK. That is, the read command includes voltage data in a number corresponding to the number of select gate lines SGD included in the memory cell array 110 and voltage data in a number corresponding to the number of layers of the word lines WL. Furthermore, when controlling whether or not to execute a read operation for each sense amplifier unit SAU, the read command for the logical operation includes an instruction to control whether or not to execute a read operation for each sense amplifier unit SAU. When the read control circuit 114 executes a read operation based on the read command based on the clock input from the control circuit, the read result is output to the sense amplifier module 113.

[0025] The write control circuit 115 controls the plane and executes the write operation based on a write operation command (hereinafter referred to as a write command) received from the control circuit 12. In the write operation, the write control circuit 115 writes data received from the memory circuit 15, data read from other information processing units 11, etc., to an address specified by the write command.

[0026] The erase control circuit 116 controls the planes and executes the erase operation based on an erase operation command (hereinafter referred to as an erase command) received from the control circuit 12. In the erase operation, the erase control circuit 116 erases data at an address (e.g., block BLK) specified by the erase command. The erase control circuit 116 may be configured to be able to erase data stored in a specific memory cell.

[0027] The output holding register 117 holds the output value of each sense amplifier unit SAU of the sense amplifier module 113. In the semiconductor device 10 according to the first embodiment, the result of a logical operation is obtained as the output value of the sense amplifier unit SAU in a read operation.

[0028] The register output circuit 118 performs an operation related to the output of the result of the logical operation held in the output holding register 117. The value held in the output holding register 117 is output via the register output circuit 118.

[0029] <1-1-4> Circuit configuration of memory cell array 110 4 is a circuit diagram showing an example of a circuit configuration of the memory cell array 110 included in the semiconductor device 10 according to the first embodiment. Fig. 4 shows two blocks BLK0 and BLK1 among the multiple blocks BLK included in the memory cell array 110. As shown in Fig. 4, in the memory cell array 110, for example, select gate lines SGD and SGS and word lines WL0 to WL(N-1) (N is an integer of 2 or more) are provided for each block BLK. Bit lines BL0 to BLm and source lines SL are shared by, for example, multiple blocks BLK.

[0030] Each block BLK includes a plurality of NAND strings NS. The plurality of NAND strings NS are associated with bit lines BL0 to BLm, respectively. Each NAND string NS is connected between the associated bit line BL and a source line SL. Each NAND string NS includes, for example, N memory cell transistors MT0 to MT(N-1) and select transistors ST1 and ST2. Each memory cell transistor MT is a memory cell having a control gate and a charge storage layer, and retains (stores) data in a non-volatile manner. Each of the select transistors ST1 and ST2 is used to select the block BLK.

[0031] In each NAND string NS, a select transistor ST1, memory cell transistors MT0 to MT(N-1), and a select transistor ST2 are connected in series in this order. Specifically, the drain and source of the select transistor ST1 are connected to the associated bit line BL and the drain of the memory cell transistor MT0, respectively. The drain and source of the select transistor ST2 are connected to the source of the memory cell transistor MT(N-1) and a source line SL, respectively. The memory cell transistors MT0 to MT(N-1) are connected in series between the select transistors ST1 and ST2.

[0032] Each select gate line SGD is connected to the gates of the select transistors ST1 included in the associated block BLK. Each select gate line SGS is connected to the gates of the select transistors ST2 included in the associated block BLK. Each word line WL0 to WL(N-1) is connected to the control gates of the memory cell transistors MT0 to MT(N-1) included in the associated block BLK. A "page" corresponds to, for example, a set of memory cell transistors MT connected to a common word line WL within the same block BLK.

[0033] The memory cell array 110 may have other circuit configurations. Each block BLK may be provided with a plurality of independently controllable select gate lines SGD. In this case, each block BLK is configured to be selectable in units of a plurality of units each corresponding to a plurality of select gate lines SGD. When each block BLK has a plurality of select gate lines SGD, the number of voltage data of the select gate lines SGD included in a read command corresponding to a logical operation corresponds to the product of the number of blocks BLK and the number of select gate lines SGD in the block BLK.

[0034] <1-2> Operation Next, the operation of the semiconductor device 10 according to the first embodiment will be described.

[0035] <1-2-1> Information processing 5 is a flowchart showing an example of information processing of the semiconductor device 10 according to the first embodiment. The semiconductor device 10 according to the first embodiment executes information processing as a logical operation using a plane. The control circuit 12 of the semiconductor device 10 according to the first embodiment receives, for example, a read command corresponding to the logical operation from the host device 20, and starts (starts) the series of processes shown in FIG. 5 based on the change of the value of the external access flag of the external access management circuit 14 from "1" to "0."

[0036] First, the control circuit 12 executes a read operation in response to an input read command (step S11). This read operation corresponds to a logical operation using a plane. In the read operation, the read control circuit 114 applies a voltage VSGD_ON to a plurality of select gate lines SGD. In the read operation, the select transistor ST1 to whose gate VSGD_ON is applied is turned on. In the read operation executed in information processing (logical operation), it is sufficient that VSGD_ON is applied to two or more select gate lines SGD depending on the content of the logical operation. Details of the read operation corresponding to the logical operation will be described later.

[0037] Next, the control circuit 12 writes the output value of each sense amplifier unit SAU to the output holding register 117 (step S12). Specifically, first, the result of the read operation executed in step S11, that is, the result of the logical operation using the plane (hereinafter referred to as the information processing result), is read out to each sense amplifier unit SAU. Then, the information processing result is transferred from each sense amplifier unit SAU to the output holding register 117 and held in the output holding register 117.

[0038] Next, the control circuit 12 outputs the information processing result to the outside (step S13). That is, the information processing result held in the output holding register 117 is output to the host device 20 via the register output circuit 118 and the input / output circuit 16.

[0039] Next, the control circuit 12 changes the value of the external access flag of the external access management circuit 14 from "0" to "1" (step S14). When the process of step S14 is completed, the control circuit 12 ends the series of processes shown in FIG. 5 (end).

[0040] <1-2-2> Read operation FIG. 6 is a schematic diagram showing an example of a read operation of the semiconductor device 10 according to the first embodiment. FIG. 6 shows voltages applied to three NAND strings NS0 to NS2 connected to the same bit line BL in a read operation corresponding to a logical operation. In this example, the NAND strings NS0 to NS2 belong to different blocks BLK. In a read operation corresponding to a logical operation, word lines WL provided in the same layer between blocks BLK are controlled at the same potential, so each word line WL is shown as being shared by the NAND strings NS. As shown in FIG. 6, in this example, the NAND strings NS0 and NS1 are selected as operation targets, and the NAND string NS2 is not selected.

[0041] A selected NAND string NS includes at least one memory cell transistor MT whose threshold voltage is to be read in the read operation, whereas an unselected NAND string NS does not include any memory cell transistor MT whose threshold voltage is to be read in the read operation.

[0042] In this case, VSGD_ON is applied to the select gate lines SGD of the selected NAND strings NS0 and NS1, and VSGD_OFF is applied to the select gate line SGD of the unselected NAND string NS2. In a read operation, the select transistor ST1 with VSGD_ON applied to its gate is turned on, and the select transistor ST1 with VSGD_OFF applied to its gate is turned off. That is, a voltage that turns on the select transistor ST1 is applied to the select gate line SGD corresponding to the selected NAND string NS, and a voltage that turns off the select transistor ST1 is applied to the select gate line SGD corresponding to the unselected NAND strings NS.

[0043] Furthermore, VSGS_ON is applied to the select gate lines SGS of the selected NAND strings NS0 and NS1, and VSGS_OFF is applied to the select gate line SGS of the unselected NAND string NS2. In a read operation, the select transistor ST2 with VSGS_ON applied to its gate is turned on, and the select transistor ST2 with VSGS_OFF applied to its gate is turned off. Note that in a read operation, VSGS_ON may be applied to the select gate line SGS of each NAND string NS regardless of whether the NAND string NS is selected or unselected.

[0044] Then, for example, a voltage corresponding to the query is applied to each word line WL. Specifically, a voltage associated with the bit of the query to be compared is applied to each of the word lines WL0 to WL(N-1) of the selected NAND string NS. Then, if the query and the data of the selected NAND string NS all match, a current flows between the bit line BL and the source line SL through the NAND string NS. Furthermore, a voltage for comparing data within the selected NAND string NS may be applied to each word line WL. Details of this will be described in the fourth embodiment.

[0045] As described above, in a read operation, a current flows between the bit line BL and the source line SL through each of the selected NAND strings NS0 and NS1 in accordance with the voltage applied to each word line WL. Meanwhile, a current does not flow between the bit line BL and the source line SL through the unselected NAND string NS2. As a result, the result of a logical operation using the data stored in the selected NAND string NS is read onto the bit line BL depending on whether a current flows through the NAND string NS0 and whether a current flows through the NAND string NS1.

[0046] <1-3> Effects of the first embodiment According to the semiconductor device 10 of the first embodiment, efficient logical operations using memory devices can be realized. The effects of the first embodiment will be described in detail below.

[0047] In a read operation of a NAND flash memory, one select gate line SGD is typically selected. A read voltage is applied to one word line WL connected to the memory cell transistor MT to be read, and a read pass voltage is applied to all other word lines WL. That is, in a normal read operation, one NAND string NS for each bit line BL is either conductive or non-conductive between the bit line BL and the source line SL depending on the threshold voltage of the memory cell transistor MT to be read.

[0048] In contrast, the semiconductor device 10 according to the first embodiment has a configuration similar to that of a NAND flash memory (the plane of the information processing unit 11) and is configured to be able to execute a read operation corresponding to a logical operation. The content of the logical operation is determined based on the value of an input read command and the value of the threshold voltage of the memory cell transistor MT that is set prior to the read operation. In addition, unlike the read operation of a normal NAND flash memory, in a read operation corresponding to a logical operation, NAND strings NS of multiple blocks BLK connected to the same bit line BL may be simultaneously made conductive.

[0049] As described above, the semiconductor device 10 according to the first embodiment can execute logical operations using the planes of the information processing unit 11. Furthermore, the semiconductor device 10 has a structure in which memory cells are stacked three-dimensionally, thereby realizing a large storage capacity and enabling it to handle more complex logical operations and data than existing FPGAs (Field Programmable Gate Arrays). Furthermore, the semiconductor device 10 can execute a large number of logical operations with lower power consumption than SRAM (Static Random Access Memory)-based FPGAs. Therefore, the semiconductor device 10 according to the first embodiment can implement efficient logical operations using memory devices.

[0050] <2> Second embodiment In the second embodiment, each information processing unit 11 of the semiconductor device 10 is configured to execute the next read operation based on the read result. The information processing system 1 according to the second embodiment will be described below, focusing on the differences from the first embodiment.

[0051] <2-1> Configuration Fig. 7 is a block diagram showing an example of the configuration of an information processing unit 11A included in the semiconductor device 10 according to the second embodiment. As shown in Fig. 7, the information processing unit 11A has a configuration in which the read control circuit 114 of the information processing unit 11 of the first embodiment is replaced with a read control circuit 114A, and a register input circuit 200, a read command generation circuit 201, a table holding circuit 202, and a table input circuit 203 are added.

[0052] The read control circuit 114A executes a read operation based on a read command generated by the read command generation circuit. When the read control circuit 114A executes a read operation based on the read command based on a clock input from the control circuit, a read result is output to the sense amplifier module 113. Then, the output value of each sense amplifier unit SAU of the sense amplifier module 113 is held in the output holding register 117. In the semiconductor device 10 according to the second embodiment, the output value of each sense amplifier unit SAU obtained by the read operation may include information that forms the basis of the read command.

[0053] The register input circuit 200 is configured to input data, information related to the initial read command, etc. to the output holding register 117. The control circuit 12 of the second embodiment inputs at least a part of the initial read command to the register input circuit 200 and causes the output holding register 117 to hold at least a part of the initial read command. The "initial read command" corresponds to a read command input from outside the information processing unit 11A, among multiple logical operations (read operations) that can be executed by the read control circuit 114A in the second embodiment.

[0054] The read instruction generation circuit 201 generates a read instruction based on the information on which the read instruction is based that is held in the output holding register 117 and the information (read instruction correspondence table) that is held in the table holding circuit 202. Then, the read instruction generation circuit 201 outputs the generated read instruction to the read control circuit 114A. The read instruction generated by the read instruction generation circuit 201 is not necessarily a complete read instruction, and may be a subset of the read instruction. The read instruction generation circuit 201 may update the subset of the read instruction and use the value of the read instruction received from the control circuit 12 for the missing part.

[0055] The table holding circuit 202 is a storage circuit such as a register or a memory. The table holding circuit 202 stores a read instruction correspondence table input from the table input circuit 203. The read instruction correspondence table stores information that associates the bit values ​​held in the output holding register 117 with the bit values ​​of the read instruction. Note that this correspondence does not have to be one-to-one. For example, if the number of bits of the information on which the read instruction is based, held in the output holding register 117, is fewer than the number of bits of the read instruction, a one-to-one correspondence is not possible. In such a case, the read instruction generation circuit 201 may determine the values ​​of multiple bits of the read instruction based on the value of a certain bit of the output holding register 117.

[0056] The table input circuit 203 inputs the read command correspondence table to the table holding circuit 202. The table input circuit 203 may acquire the read command correspondence table by reading it from a predetermined address of a specific memory cell array 110, or by reading it from another memory device included in the semiconductor device 10.

[0057] In the semiconductor device 10 according to the second embodiment, data is written to the planes of each information processing unit 11 so that the read result includes the next read command. In the information processing unit 11A, data may be added to the read result from each plane in addition to the next read command. The added data may be output to the outside of the information processing unit 11A via the register output circuit 118. Other configurations of the information processing system 1 according to the second embodiment are the same as those of the information processing system 1 according to the first embodiment.

[0058] <2-2> Operation Fig. 8 is a flowchart showing an example of information processing in the semiconductor device 10 according to the second embodiment. The control circuit 12 of the semiconductor device 10 according to the first embodiment receives, for example, a read command corresponding to a logical operation from the host device 20, writes the initial read command to the output holding register 117, and starts (starts) the series of processes shown in Fig. 8 based on the change of the value of the external access flag of the external access management circuit 14 from "1" to "0."

[0059] First, the read command generation circuit 201 refers to the table holding circuit 202 and generates a read command based on the data in the output holding register 117 (step S21). The read command generation circuit 201 may acquire data related to the read command by referring to a predetermined address, or may detect it based on a predetermined character string. The read command generation circuit 201 extracts a command corresponding to the data in the output holding register 117 from the read command correspondence table in the table holding circuit 202, and generates a read command.

[0060] Next, the read control circuit 114A executes a read operation in accordance with the read command generated by the read command generation circuit 201 (step S22). Details of the read operation executed in step S22 are similar to the read operation corresponding to the logical operation described in step S11 of FIG.

[0061] Next, the control circuit 12 writes the output value of each sense amplifier unit SAU to the output holding register 117 (step S23). Specifically, first, the result of the read operation executed in step S22, i.e., the information processing result, is read out to each sense amplifier unit SAU. Then, the information processing result is transferred from each sense amplifier unit SAU to the output holding register 117 and held in the output holding register 117. The information processing result in the second embodiment may include data of the logical operation and a read command.

[0062] Next, the read command generation circuit 201 checks whether the output holding register 117 contains the next read command (step S24).

[0063] If the output holding register 117 contains the next read command (step S24: YES), the control circuit 12 proceeds to the process of step S21. That is, the read control circuit 114 executes a read operation based on the next read command contained in the output holding register 117, and writes the output value of each sense amplifier unit SAU based on the execution result to the output holding register 117. The control circuit 12 repeats the processes of steps S21 to S24 until the output holding register 117 no longer contains the next read command.

[0064] If the output holding register 117 does not contain the next read command (step S24: NO), the control circuit 12 proceeds to the processing of step S13. In the processing of step S13, the control circuit 12 outputs the information processing result to the outside, as in the first embodiment. Then, as in the first embodiment, the control circuit 12 changes the value of the external access flag of the external access management circuit 14 from "0" to "1" (step S14). When the processing of step S14 is completed, the control circuit 12 ends the series of processes shown in FIG. 8 (end).

[0065] The read command may include an acceptance flag. The acceptance flag indicates whether the output holding register 117 accepts input. For example, the acceptance flag is configured so that it can be read from outside the information processing unit 11 but cannot be written from outside the information processing unit 11. Read commands other than the acceptance flag can be written from outside when the acceptance flag is set to a value corresponding to on. The read command may also include an operation flag. The operation flag indicates whether a read operation is to be executed in the next clock. For example, the operation flag enables the calculation result of the previous clock to be executed in a subsequent clock, not immediately after it. The output holding register 117 in which a read command has already been written is configured so that, for example, only the operation flag can be rewritten in a later clock. The operation flag may be rewritten by an external input or based on an output from the plane. A read command read from a plane may include a read command for another information processing unit 11. In this case, a read command read from a plane of one information processing unit 11 is transferred to the output holding register 117 of the other information processing unit 11.

[0066] <2-3> Effects of the second embodiment The semiconductor device 10 according to the second embodiment has a function in which the output of each sense amplifier unit SAU during a read operation includes the next read command and stores the next read command in the output holding register 117. Then, in the next clock or later, the semiconductor device 10 according to the second embodiment handles this read result as a read command and executes a read operation corresponding to a logical operation.

[0067] As a result, the semiconductor device 10 according to the second embodiment can continuously execute desired arithmetic processing in each data processing unit 11A. As a result, the semiconductor device 10 according to the second embodiment can implement logical operations using memory devices more efficiently than the first embodiment. Furthermore, each data processing unit 11A of the semiconductor device 10 according to the second embodiment can feed back the read result of a certain NAND string NS to a read operation for another block BLK or another plane. As a result, the semiconductor device 10 according to the second embodiment can execute more complex logical operations using multiple data processing units 11A.

[0068] <3> Third embodiment In the third embodiment, the control circuit 12 of the semiconductor device 10 is configured to perform logical operations based on the readout results of each information processing unit 11. The information processing system 1 according to the third embodiment will be described below, focusing on the differences from the first and second embodiments.

[0069] <3-1> Configuration Fig. 9 is a block diagram showing an example of the configuration of a semiconductor device 10A according to the third embodiment. As shown in Fig. 9, the semiconductor device 10A has a configuration in which the control circuit 12 includes a post-processing instruction execution circuit 301, and further includes a table holding circuit 302 and a table input circuit 303, in addition to the semiconductor device 10 according to the first embodiment. Note that Fig. 9 omits the illustration of some of the configuration of the semiconductor device 10A.

[0070] The post-processing instruction execution circuit 301 generates a post-processing instruction based on information (read operation results) stored in the output holding register 117 of each information processing unit 11, and executes post-processing based on the generated post-processing instruction. The post-processing executed by the post-processing instruction execution circuit 301 may be a single operation or multiple types of operations. The output holding register 117 of the third embodiment may store information that serves as the basis for an instruction corresponding to an operation executed as post-processing. Examples of post-processing include writing back the absolute value of a value stored in a register to the same register, writing back the sum of value A and value B in a register to value A, and calculating the inner product of multiple sets of data (hereinafter referred to as data sets) by treating the sets as vectors. The post-processing may also be writing and reading data to and from a volatile memory (e.g., the storage circuit 15) or a non-volatile memory (e.g., the memory cell array 110).

[0071] The table holding circuit 302 is a storage circuit such as a register or a memory. The table holding circuit 302 stores a post-processing instruction correspondence table input from the table input circuit 303. The post-processing instruction correspondence table stores information that associates the bit values ​​held in the output holding register 117 with the bit values ​​of the post-processing instruction. Note that this correspondence does not have to be one-to-one. For example, if the number of bits of the information on which the post-processing instruction is based that is held in the output holding register 117 is fewer than the number of bits of the post-processing instruction, a one-to-one correspondence is not possible. In such a case, the post-processing instruction execution circuit 301 may determine the values ​​of multiple bits of the post-processing instruction based on the value of a certain bit of the output holding register 117.

[0072] The table input circuit 303 inputs the post-processing command correspondence table to the table holding circuit 302. The table input circuit 303 may acquire the post-processing command correspondence table by reading it from a predetermined address of a specific memory cell array 110, or by reading it from another storage device included in the semiconductor device 10A.

[0073] The semiconductor device 10A may generate a read command for a specific information processing unit 11 based on the post-processing command and store the read command in the corresponding output holding register 117. The post-processing command execution circuit 301 may use the memory circuit 15 as a working area to execute a logical operation using each information processing unit 11 and its own post-processing. The other configurations of the information processing system 1 according to the third embodiment are the same as those of the information processing system 1 according to the first embodiment.

[0074] <3-2> Operation Fig. 10 is a flowchart showing an example of information processing of the semiconductor device 10A according to the third embodiment. The control circuit 12 of the semiconductor device 10A according to the third embodiment receives, for example, a read command corresponding to a logical operation from the host device 20, and starts (starts) the series of processes shown in Fig. 10 based on the change of the value of the external access flag of the external access management circuit 14 from "1" to "0".

[0075] First, the control circuit 12 executes a read operation in response to an input read command, as in the first embodiment (step S11).

[0076] Next, the control circuit 12 writes the output value of each sense amplifier unit SAU to the output holding register 117, as in the first embodiment (step S12).

[0077] Next, the control circuit 12 checks whether or not a post-processing instruction is included in the output holding register 117 (step S31). Specifically, first, the post-processing instruction execution circuit 301 obtains, from the post-processing instruction correspondence table, the address of a register that can hold a post-processing instruction among the output holding registers 117 of the information processing unit 11 that executed the read operation. Then, the post-processing instruction execution circuit 301 references the data stored in the address in the output holding register 117 that can hold a post-processing instruction, and checks whether or not a post-processing instruction is included.

[0078] If the output holding register 117 does not contain a post-processing instruction (step S31: NO), the control circuit 12 proceeds to the process of step S13.

[0079] If the output holding register 117 contains a post-processing instruction (step S31: YES), the post-processing instruction execution circuit 301 of the control circuit 12 executes the post-processing instruction (step S32). The post-processing instruction may, for example, use the calculation result held in the output holding register 117 that holds the post-processing instruction, or may use data stored in another block BLK or plane. When the processing of step S32 is completed, the control circuit 12 proceeds to the processing of step S13. Note that the processing of step S32 may be completed based on a post-processing instruction that ends the post-processing.

[0080] In the process of step S13, the control circuit 12 outputs the information processing result to the outside, as in the first embodiment. Then, as in the first embodiment, the control circuit 12 changes the value of the external access flag of the external access management circuit 14 from "0" to "1" (step S14). When the process of step S14 is completed, the control circuit 12 ends the series of processes shown in FIG. 10 (end).

[0081] The post-processing instruction may include a read operation and a write operation for each information processing unit 11. In the post-processing instruction, after a specified logical operation is executed, the operation result may be written to the output holding register 117 of the information processing unit 11 specified by the post-processing instruction. In the process of step S32, if the output holding register 117 contains multiple post-processing instructions, the post-processing instruction execution circuit 301 may execute all of the post-processing instructions contained in the output holding register 117. Furthermore, if the post-processing instruction executed in the process of step S32 contains the address of the next post-processing instruction, the post-processing instruction execution circuit 301 may obtain the next post-processing instruction from the address of the next post-processing instruction and execute the next post-processing instruction.

[0082] <3-3> Effects of the third embodiment In the semiconductor device 10 according to the third embodiment, the output of each sense amplifier unit SAU in a read operation includes a post-processing instruction executed by a post-processing instruction execution circuit 301 outside the information processing unit 11. Then, the post-processing instruction execution circuit 301 executes, for example, a logical operation that is inefficient when executed by each information processing unit 11.

[0083] This allows the semiconductor device 10 according to the third embodiment to perform more advanced and more efficient logical operations than when only the information processing unit 11 is used. As a result, the semiconductor device 10 according to the third embodiment can realize logical operations using memory devices more efficiently than the first embodiment.

[0084] <4> Fourth embodiment The fourth embodiment relates to preparations for the semiconductor device 10 to execute logical operations and specific examples of logical operations that can be executed by the semiconductor device 10. The following describes the information processing system 1 according to the fourth embodiment, focusing on differences from the first to third embodiments.

[0085] <4-1> Configuration The configuration of the information processing system 1 according to the fourth embodiment is similar to that of the information processing system 1 according to the first embodiment. In the fourth embodiment, the threshold voltage distribution of the memory cell transistors MT and the allocation of data are applied as described below.

[0086] (Threshold voltage distribution of memory cell transistor MT) FIG. 11 is a schematic diagram showing an example of the threshold voltage distribution of memory cell transistors MT included in the semiconductor device 10 according to the fourth embodiment. As shown in FIG. 11, "NMTs" on the vertical axis indicates the number of memory cell transistors MT. "Vth" on the horizontal axis indicates the threshold voltage of the memory cell transistors MT. As shown in FIG. 11, in the semiconductor device 10 according to the fourth embodiment, the threshold voltage distribution of the multiple memory cell transistors MT can form three states. In this specification, these three states are referred to as the "1" state, the "0" state, and the "VHH" state, in order from lowest to highest threshold voltage.

[0087] "1" data (True) is assigned to the "1" state. "0" data (False) is assigned to the "0" state. "1" data and "0" data are each used as valid data. Invalid data is assigned to the "VHH" state. A memory cell transistor MT having a threshold voltage in the "VHH" state can be used as a reference indicating the division of a data set, which will be described later.

[0088] A read voltage VM is set between the "1" state and the "0" state. A read pass voltage VREAD is set between the "0" state and the "VHH" state. The read pass voltage VRH is set to a voltage higher than that of the "VHH" state. When the read voltage VM is applied, the memory cell transistor MT is turned on or off depending on the data to be stored. When the read pass voltage VREAD is applied, the memory cell transistor MT that stores valid data is turned on, and the memory cell transistor MT that stores invalid data is turned off. When the read pass voltage VRH is applied, the memory cell transistor MT is turned on regardless of the data to be stored.

[0089] The threshold voltage value corresponding to the data to be written to the memory cell transistor MT is determined according to the content of a logical operation by, for example, software such as a compiler or linker executed by the host device 20. The host device 20 stores the determined threshold voltage value of the memory cell transistor MT in an electronic file or the like as a memory image. The host device 20 then reads out this electronic file of the memory image using software such as a loader, and inputs the information to the semiconductor device 10.

[0090] The semiconductor device 10 stores the threshold voltage value of the memory cell transistor MT specified by the host device 20 in a predetermined memory cell transistor MT by a known erase operation or write operation of a NAND flash memory. In the semiconductor device 10, the memory cell transistor MT that stores data used in logical operations stores data in binary form ("1" data and "0" data shown in FIG. 11). Then, when the semiconductor device 10 stores the data in binary form, k When handling data of eight values ​​(k is an integer equal to or greater than 1), the data is coded in k pages of an SLC (Single Level Cell). Specifically, eight-value data is coded in three pages of an SLC. When coded in three pages of an SLC, one piece of data is represented by three bits of data stored in a total of three memory cell transistors MT. When complementary data used for a logic operation described later is stored in the memory cell array 110, two k The number of memory cell transistors MT for storing data of a value is k × 2. In this specification, complementary data corresponds to data in which 0 or 1 is inverted.

[0091] <4-2>Operation Next, the operation of the semiconductor device 10 according to the fourth embodiment will be described. In the semiconductor device 10 according to the fourth embodiment, different roles are assigned to the information processing units 11-1, 11-2, and 11-3. Hereinafter, the memory cell arrays 110 of the information processing units 11-1, 11-2, and 11-3 will be referred to as memory cell arrays 110-1, 110-2, and 110-3, respectively. Hereinafter, a case will be described in which purchase data is used as data handled in information processing. The purchase data is L-bit (L is an integer equal to or greater than 2) data including, for example, a personal code, a region code, an age code, and a gender code. In the drawings referred to below, the select transistors ST1 and ST2 and the select gate lines SGD and SGS are not shown.

[0092] <4-1-1> Memory processing The semiconductor device 10 according to the fourth embodiment executes a storage process as a preparation for a logical operation using a plane, for example. The storage process of the semiconductor device 10 will be described below with reference to FIGS. 12, 13, and 14.

[0093] 12, 13, and 14 are schematic diagrams showing specific examples of storage processing in the semiconductor device 10 according to the fourth embodiment. Each of FIGS. 12 and 13 shows a plurality of sense amplifier units SAU, a plurality of bit lines BL, word lines WLi and WL(i+1) (i is an integer equal to or greater than 0), and data stored in memory cell transistors MT, all of which are associated with a certain block BLK of the memory cell array 110-1. FIG. 14 shows a plurality of sense amplifier units SAU, a plurality of bit lines BL, word lines WL1 to WL(2L), and data stored in memory cell transistors MT, all of which are associated with a certain block BLK of the memory cell array 110-2. The content of the data stored in the memory cell transistors MT is indicated at the intersections of the word lines WL and the bit lines BL.

[0094] First, the control circuit 12 stores purchase data in the memory cell array 110-1 of the information processing unit 11-1, as shown in FIG. 12. In this example, the memory cell transistors MT connected to the word line WL(i+1) correspond to an initial state before data is stored by the storage process. The threshold voltage of each memory cell transistor MT in the initial state corresponds to an erased state. That is, each memory cell transistor MT in the initial state holds data "1."

[0095] Purchase data is written to a plurality of memory cell transistors MT connected to word lines WLi. The purchase data is written to the memory cell array 110-1 in input order. When writing a plurality of purchase data, the semiconductor device 10 converts the data into units called data sets DS. A data set DS is a collection of a plurality of purchase data based on predetermined conditions. Each page can include a plurality of data sets DS. A data set DS includes M (M is an integer of 2 or greater) data units DU1 to DUM. A data unit DU includes L bits of data (L is an integer of 2 or greater) associated with one purchase data.

[0096] The L bits of data included in the data unit DU are written bit by bit to memory cell transistors MT associated with the same page but different bit lines BL. Specifically, the data unit DU1 includes, for example, data D1_1 to D1_L associated with the bit lines BL1 to BL(L), respectively. The data unit DU2 includes, for example, data D2_1 to D2_L associated with the bit lines BL(L+1) to BL(2L), respectively. Similarly, the data unit DUM includes, for example, data DM_1 to DM_L associated with the bit lines BL(L*(M-1)+1) to BL(L*M), respectively. Each piece of data included in the data unit DU is either "1" data or "0" data.

[0097] The beginning and end of each data set DS are distinguished by memory cell transistors MT written to the "VHH" state. In this example, the memory cell transistors MT connected to bit line BL0 and word line WLi and the memory cell transistors MT connected to bit line BL(L*M+1) and word line WLi are written to the "VHH" state as separator cells CS. When purchase data is input continuously, separator cells CS are inserted, for example, as separators on a daily basis.

[0098] Note that multiple data sets DS may be stored in each page of the memory cell array 110-1. The sizes of the data sets DS and data units DU may be changed depending on the type of data being handled. When the data type is the same, the size of the data units DU is unified. On the other hand, the size of the data set DS may vary depending on the number of data units DU included. The position of the separator cell CS may be the same for each word line WL or may be different.

[0099] Next, the control circuit 12 reads out the purchase data from the memory cell array 110-1 of the information processing unit 11-1 as shown in FIG. 13, and writes it to the memory cell array 110-2 of the information processing unit 11-2 as shown in FIG.

[0100] First, when reading a page including a data set DS, the read control circuit 114 of the data processing unit 11-1 applies a read pass voltage VREAD to the word line WLi to be read. Then, the latch circuit of the sense amplifier unit SAU connected to the bit line BL through which no cell current flows via the NAND string NS latches (holds) the information. As a result, the position of the separator (separator cell CS) of the data set DS is stored in the sense amplifier module 113. The read control circuit 114 also applies VRH to the word line WL (e.g., WL(i+1)) that is not the read target. As a result, the memory cell transistor MT connected to the word line WL that is not the read target is turned on regardless of the state of its threshold voltage.

[0101] The read control circuit 114 of the information processing unit 11-1 then applies a read voltage VM to the word line WLi to read every L bits from the first bit of the data set DS. The data read every L bits is transferred to the information processing unit 11-2. The write control circuit 115 of the information processing unit 11-2 then writes the data read every L bits to, for example, the first word line WL in the order of the bit lines BL. In this example, the bit line BL1 is used as the first bit line BL. The write control circuit 115 of the information processing unit 11-2 also writes complementary data of the data read every L bits to the next word line WL. This operation is performed for each bit included in the data unit DU.

[0102] Specifically, data D1_1 of data unit DU1, data D2_1, ... of data unit DU2, and data DM_1 of data unit DUM stored in memory cell array 110-1 are read ((1) in FIG. 13). The read data D1_1, D2_1, ..., DM_1 are written to a page corresponding to word line WL1 of memory cell array 110-2, as shown in FIG. 14. Complementary data of data D1_1, D2_1, ..., DM_1 are written to a page corresponding to word line WL2 of memory cell array 110-2. Note that in FIG. 14, memory cell transistors MT into which complementary data has been written are distinguished by hatching.

[0103] Data D1_2 of data unit DU1, data D2_2, ... of data unit DU2, and data DM_2 of data unit DUM stored in memory cell array 110-1 are read ((2) in FIG. 13). The read data D1_2, D2_2, ..., DM_2 are written to a page corresponding to word line WL3 of memory cell array 110-2, as shown in FIG. 14. Complementary data of data D1_2, D2_2, ..., DM_2 are written to a page corresponding to word line WL4 of memory cell array 110-2.

[0104] Similarly, data D1_L of data unit DU1, data D2_L, ..., data DM_L of data unit DUM are read ((L) of FIG. 13). The read data D1_L, D2_L, ..., DM_L are written to a page corresponding to word line WL(2L-1) of memory cell array 110-2, as shown in FIG. 14. Complementary data of data D1_L, D2_L, ..., DM_L are written to a page corresponding to word line WL(2L) of memory cell array 110-2.

[0105] As a result, in the memory cell array 110-2, the data units DU1 to DUM are associated with the bit lines BL1 to BLM, respectively. The initial state of each memory cell transistor MT in the memory cell array 110-2 is set to, for example, a threshold voltage of the "VHH" state. Therefore, the threshold voltage of each memory cell transistor MT in the NAND string NS connected to the bit line BL(M+1) is in the "VHH" state.

[0106] As described above, in the storage process, purchase data written to a page in the memory cell array 110-1 is converted to vertical writing in the memory cell array 110-2. Furthermore, data is written in complementary format in the memory cell array 110-2. Therefore, the data unit DU, which is an L-bit unit in the memory cell array 110-1, changes to a 2L-bit unit in the memory cell array 110-2. Note that a read operation of the memory cell array 110-1 for inputting data to the memory cell array 110-2 may be executed before data input to the memory cell array 110-1 is completed. The settings of the first word line WL and the first bit line BL may be changed as appropriate.

[0107] <4-1-2> Comparison processing The semiconductor device 10 according to the fourth embodiment executes a comparison process, for example, as an operation of comparing a query with purchase data stored in a plane. The comparison process can be used for searching under conditions specified by the host device 20. The comparison process of the semiconductor device 10 will be described below with reference to FIGS. 15 and 16.

[0108] 15 and 16 are schematic diagrams showing a specific example of a comparison process of the semiconductor device 10 according to the fourth embodiment. Each of FIGS. 15 and 16 shows a plurality of sense amplifier units SAU, a plurality of bit lines BL, word lines WL1 to WL(2L), and data stored in memory cell transistors MT, which are associated with a certain block BLK of the memory cell array 110-2. The contents of the data stored in the memory cell transistors MT are the same as those in FIG. 14. Each of FIGS. 15 and 16 also shows the data stored in the latch circuits of the sense amplifier units SAU.

[0109] As shown in FIG. 15, before the comparison process is performed, all latch circuits of each sense amplifier unit SAU hold "1" data. The memory cell array 110-2 stores purchase data when it is desired to tally the number of products purchased by a certain customer. As shown in FIG. 16, in the comparison process, a voltage corresponding to the coding of the customer condition is applied to one or more selected word lines WL as an external query. For example, a read voltage VM is associated with "1" data. A read voltage VREAD is associated with "0" data. Furthermore, VREAD is applied to word lines WL corresponding to conditions not of interest. When the data corresponding to the voltage applied to the selected word line WL matches the data stored in the memory cell transistor MT, the memory cell transistor MT is turned on. On the other hand, when the data corresponding to the voltage applied to the selected word line WL does not match the data stored in the memory cell transistor MT, the memory cell transistor MT is turned off.

[0110] Note that, for example, a voltage corresponding to the complementary data of the associated query is applied to the memory cell transistor MT in which complementary data is stored. Specifically, in this example, the voltage applied to the word line WL1 and the voltage applied to the word line WL2 have a complementary relationship. The voltage applied to the word line WL(2L-1) and the voltage applied to the word line WL2L have a complementary relationship. In this example, the read voltage VM and the read voltage VREAD are defined to have a complementary relationship. That is, when the query at a certain address is “1” data, the voltage applied to the word line WL having the complementary relationship is VREAD. When the query at a certain address is “0” data, the voltage applied to the word line WL having the complementary relationship is VM. Note that the read voltage VREAD may be applied to the memory cell transistor MT in which complementary data is stored, regardless of the data of the associated query.

[0111] As a result, a cell current Icell flows in the NAND string NS storing a data unit DU whose data matches the query. A cell current Icell does not flow in the NAND string NS storing a data unit DU whose data does not match the query. In other words, a NAND string NS whose Icell is on matches the query. A NAND string NS whose Icell is off does not match the query. Furthermore, a NAND string NS into which no data has been written does not flow a cell current Icell because it is composed of memory cell transistors MT in the “VHH” state. Figure 16 shows a case where data units DU2 and DU3 each match the query, and data units DU1 and DUM each do not match the query. Each sense amplifier unit SAU latches (holds) “0” data when connected to a bit line BL through which a cell current Icell flows.

[0112] When the comparison process is completed, the data (comparison process result) held in the latch circuit of each sense amplifier unit SAU is transferred to the output holding register 117. Then, the comparison process result is output from the output holding register 117 to the outside via the register output circuit 118. Thereafter, the number of "0" data among the comparison process results output to the outside is counted by, for example, the control circuit 12. The counting of the comparison process results may be performed by a counter provided in the information processing unit 11 or the like.

[0113] <4-1-3> Addition process The semiconductor device 10 according to the fourth embodiment performs an addition process, for example, as an operation for recording information obtained by a comparison process. The addition process of the semiconductor device 10 will be described below with reference to FIGS. 17, 18, and 19.

[0114] 17, 18, and 19 are schematic diagrams showing specific examples of addition processing in the semiconductor device 10 according to the fourth embodiment. Each of FIGS. 17, 18, and 19 shows data stored in a plurality of sense amplifier units SAU, a plurality of bit lines BL, word lines WL1 to WL6, and memory cell transistors MT associated with a certain block BLK of the memory cell array 110-3. Each of FIGS. 17, 18, and 19 also shows data stored in the latch circuits of the sense amplifier units SAU.

[0115] As shown in FIG. 17, the initial state of each memory cell transistor MT in the memory cell array 110-3 is set to, for example, a threshold voltage of the "VHH" state. Furthermore, all latch circuits in each sense amplifier unit SAU hold "1" data. Furthermore, each bit line BL is associated with a binary number. For example, the first bit line BL0 is associated with the binary number "1." The second bit line BL1 is associated with the binary number "10." The third bit line BL2 is associated with the binary number "11." The fourth bit line BL3 is associated with the binary number "100." The fifth bit line BL4 is associated with the binary number "101." The sixth bit line BL5 is associated with the binary number "110." The seventh bit line BL6 is associated with the binary number "111." The eighth bit line BL7 is associated with the binary number "1000." Similarly, binary numbers are associated with the following bit lines BL. The first bit line BL may be changed.

[0116] In the addition process, the control circuit 12 first inputs the result of the comparison process of query QC1 to the information processing unit 11-3, and stores "0" data in the latch circuits in order (for example, from left to right in FIG. 18). Then, the control circuit 12 writes the code of query QC1 to the bit line BL connected to the rightmost sense amplifier unit SAU that latches the "0" data. Next, the control circuit 12 inputs the result of the comparison process of query QC2 to the information processing unit 11-3, and stores "0" data in the latch circuits in order, starting from the latch circuit next to the latch circuit that stored the "0" data. Then, the control circuit 12 writes the code of query QC2 to the bit line BL connected to the rightmost sense amplifier unit SAU that latches the "0" data. This process is repeated in the same manner as many times as the number of queries QC that are the targets of the addition process.

[0117] For example, the comparison process using the query QC1 counts three "0" data. In this case, as shown in FIG. 18, the information processing unit 11-3 causes the latch circuits of the three sense amplifier units SAU connected to the first three bit lines BL (bit lines BL0 to BL2) to hold "0" data. Then, the code of the query QC1 is stored in the NAND string NS connected to the bit line BL2 connected to the sense amplifier unit SAU that last held the "0" data. In this example, the code of the query QC1 is written in six memory cell transistors MT connected to word lines WL1 to WL6, respectively, of the NAND string NS connected to the bit line BL2.

[0118] Thereafter, a comparison process using query QC2 counts four "0" data. In this case, as shown in FIG. 19, the information processing unit 11-3 causes the latch circuits of the four sense amplifier units SAU connected to four bit lines BL (bit lines BL3 to BL6) starting from the bit line BL3 next to the bit line BL2 to which the sense amplifier unit SAU holding "0" data is connected to hold "0" data. Then, the code of query QC2 is stored in the NAND string NS connected to the bit line BL6 connected to the sense amplifier unit SAU that last held "0" data. In this example, the code of query QC2 is written in six memory cell transistors MT connected to word lines WL1 to WL6, respectively, of the NAND string NS connected to bit line BL6.

[0119] As described above, when the comparison results using each query QC are sequentially stored in the latch circuit, the binary number associated with the bit line BL connected to the rightmost sense amplifier unit SAU holding data “0” corresponds to the sum of the count results of each query QC. For example, the sum of the counts of “0” data based on queries QC1 and QC2 can be obtained based on the binary number (111) associated with bit line BL6.

[0120] The associated binary value may be stored in a memory cell transistor MT at a predetermined address in the memory cell array 110-3. In this case, the control circuit 12 can obtain the binary value associated with each bit line BL by reading data from the predetermined address. Then, the result of the comparison process, i.e., the count result of the number of latch circuits whose data is "0" in the comparison process, is input to the information processing unit 11-3.

[0121] <4-1-4> Exclusive OR (XOR) processing The exclusive OR (XOR) processing of the semiconductor device 10 according to the fourth embodiment will be described below.

[0122] (Data placement method) 20 is a schematic diagram showing an example of a method of arranging data in the memory cell array 110 included in the semiconductor device 10 according to the fourth embodiment. Fig. 20 shows two NAND strings NSa and NSb connected to a bit line BL connected to a sense amplifier unit SAU in the memory cell array 110-2, word lines WL0 to WL11, a source line SL, and data stored in the memory cell transistors MT. Note that in Fig. 20, the memory cell transistors MT into which complementary data has been written are distinguished by hatching.

[0123] As shown in FIG. 20, the NAND string NSa stores “A” data and “bB” data, and the NAND string NSb stores “bA” data and “B” data. The “bA” data corresponds to the complementary data of the “A” data. The “bB” data corresponds to the complementary data of the “B” data. In this example, the “A” data and the “B” data each consist of 3 bits of data. That is, the “A” data consists of “A1” data, “A2” data, and “A3” data stored in different memory cell transistors MT. The “B” data consists of “B1” data, “B2” data, and “B3” data stored in different memory cell transistors MT. In this example, as described with reference to FIG. 14, complementary data is stored for each piece of data. The complementary data of the “bA” data is “A” data. The complementary data of the “bB” data is “B” data.

[0124] The word lines WL0 to WL5 associated with the memory cell transistors MT storing the "A" data of the NAND string NSa are shared with the memory cell transistors MT storing the "bA" data of the NAND string NSb. The word lines WL6 to WL11 associated with the memory cell transistors MT storing the "bB" data of the NAND string NSa are shared with the memory cell transistors MT storing the "B" data of the NAND string NSb.

[0125] Specifically, in the NAND string NSa, three memory cell transistors MT connected to word lines WL0, WL2, and WL4 store data "A1," "A2," and "A3," respectively. In the NAND string NSa, three memory cell transistors MT connected to word lines WL1, WL3, and WL5 store complementary data of "A1," "A2," and "A3," respectively. In the NAND string NSa, three memory cell transistors MT connected to word lines WL6, WL8, and WL10 store data "bB1," "bB2," and "bB3," respectively. In the NAND string NSa, three memory cell transistors MT connected to word lines WL7, WL9, and WL11 store complementary data of "bB1," "bB2," and "bB3," respectively.

[0126] On the other hand, in the NAND string NSb, three memory cell transistors MT connected to word lines WL0, WL2, and WL4 store data "bA1," "bA2," and "bA3," respectively. In the NAND string NSb, three memory cell transistors MT connected to word lines WL1, WL3, and WL5 store complementary data of "bA1," "bA2," and "bA3," respectively. In the NAND string NSb, three memory cell transistors MT connected to word lines WL6, WL8, and WL10 store data "B1," "B2," and "B3," respectively. In the NAND string NSb, three memory cell transistors MT connected to word lines WL7, WL9, and WL11 store complementary data of "B1," "B2," and "B3," respectively.

[0127] As described above, the data stored in each of the NAND strings NSa and NSb is configured in pairs. This data arrangement allows the control circuit 12 to perform XOR and XNOR operations on the "A" data and the "B" data. In the data arrangement described above, the first word line WL does not have to be word line WL0 and may be changed. When an XOR or XNOR operation is performed on the "A" data and each of a plurality of data including the "B" data, complementary data of the plurality of data including the "B" data is stored in the NAND string NSa, and a plurality of data including the "B" data is stored in the NAND string NSb.

[0128] (Example of XOR processing) 21, 22, and 23 are schematic diagrams showing specific examples of exclusive OR processing in the semiconductor device 10 according to the fourth embodiment. Each of FIGS. 21, 22, and 23 shows a configuration similar to that of FIG. 20 and voltages applied to each word line WL. The following describes a case where an XOR processing is performed on "A" data and "B" data when "A1", "A2", and "A3" data are "1", "1", and "0", respectively, and "B1", "B2", and "B3" data are "0", "1", and "1", respectively.

[0129] First, the control circuit 12 executes a read operation targeting the comparison source data "A1" and the comparison target data "B1". Specifically, as shown in FIG. 21, a read operation is executed by selecting the word line WL0 connected to the memory cell transistor MT storing the "A1" data and the word line WL6 connected to the memory cell transistor MT storing the "B1" data. In the read operation executed by the XOR process, a read voltage VM is applied to the selected word line WL, and a read pass voltage VREAD is applied to the unselected word lines WL. That is, the read voltage VM is applied to each of the word lines WL0 and WL6, and the read pass voltage VREAD is applied to the other word lines WL.

[0130] Then, in the NAND string NSa, when the read voltage VM is applied, the memory cell transistor MT storing the "A1" data (="1" data) and the memory cell transistor MT storing the "bB1" data (="1" data) are both turned on. On the other hand, in the NAND string NSb, when the read voltage VM is applied, the memory cell transistor MT storing the "bA1" data (="0" data) and the memory cell transistor MT storing the "B1" data (="0" data) are both turned off.

[0131] As a result, a cell current Icell flows between the bit line BL and the source line SL via the NAND string NSa, and a cell current Icell does not flow via the NAND string NSb. That is, the read result of the NAND string NSa corresponds to "1" data, and the read result of the NAND string NSb corresponds to "0" data. Then, the sense amplifier unit SAU detects that the cell current Icell has flowed in at least one NAND string NS, and latches "1" data (Icell ON), which is the result of the XOR operation of the "1" data and the "0" data.

[0132] Next, the control circuit 12 executes a read operation targeting the comparison source data "A2" and the comparison target data "B2." Specifically, as shown in FIG. 22, a read operation is executed by selecting the word line WL2 connected to the memory cell transistor MT storing the "A2" data and the word line WL8 connected to the memory cell transistor MT storing the "B2" data. That is, a read voltage VM is applied to each of the word lines WL2 and WL8, and a read pass voltage VREAD is applied to the other word lines WL.

[0133] Then, in the NAND string NSa, when the read voltage VM is applied, the memory cell transistor MT that stores the "A2" data (="1" data) is turned on, and the memory cell transistor MT that stores the "bB2" data (="0" data) is turned off. On the other hand, in the NAND string NSb, when the read voltage VM is applied, the memory cell transistor MT that stores the "bA2" data (="0" data) is turned off, and the memory cell transistor MT that stores the "B2" data (="1" data) is turned on.

[0134] As a result, the cell current Icell through the NAND string NSa and the cell current Icell through the NAND string NSb do not flow between the bit line BL and the source line SL. That is, the read results of the NAND strings NSa and NSb correspond to "0" data. The sense amplifier unit SAU then detects that the cell current Icell does not flow and latches "0" data, which is the result of the XOR operation between the "1" data and the "1" data.

[0135] Next, the control circuit 12 executes a read operation targeting the comparison source data "A3" and the comparison target data "B3." Specifically, as shown in FIG. 23, a read operation is executed by selecting the word line WL4 connected to the memory cell transistor MT storing the "A3" data and the word line WL10 connected to the memory cell transistor MT storing the "B3" data. That is, a read voltage VM is applied to each of the word lines WL4 and WL10, and a read pass voltage VREAD is applied to the other word lines WL.

[0136] Then, in the NAND string NSa, when the read voltage VM is applied, the memory cell transistor MT storing the "A3" data (="0" data) and the memory cell transistor MT storing the "bB3" data (="0" data) are both turned off. On the other hand, in the NAND string NSb, when the read voltage VM is applied, the memory cell transistor MT storing the "bA3" data (="1" data) and the memory cell transistor MT storing the "B3" data (="1" data) are both turned on.

[0137] As a result, the cell current Icell flows between the bit line BL and the source line SL via the NAND string NSb, and the cell current Icell does not flow via the NAND string NSa. That is, the read result of the NAND string NSa corresponds to "0" data, and the read result of the NAND string NSb corresponds to "1" data. Then, the sense amplifier unit SAU detects that the cell current Icell has flowed in at least one NAND string NS, and latches "1" data (Icell ON), which is the result of the XOR operation of the "0" data and the "1" data.

[0138] As described above, in the XOR process, one bit (one word line WL) is selected for each of the two pieces of data to be compared, and a read operation is performed. This allows the difference in the data to be checked for each bit. The sense amplifier unit SAU latches "1" data when there is a difference between the two pieces of data to be compared, and latches "0" data when the two pieces of data to be compared are the same. In this example, since "0" data is latched once, it is determined that two bits of data differ between "A" data and "B" data.

[0139] In the above explanation, the "A" data is composed of 3 bits, but this is not limiting. The "A" data may be 1 bit, 2 bits, or 4 or more bits. In the XOR process, the number of bits that make up the "A" data and the number of bits that make up the "B" data to be compared are set to the same number.

[0140] (Parallel processing) FIG. 24 is a schematic diagram showing an example of parallel processing of exclusive OR (XOR) processing in the semiconductor device 10 according to the fourth embodiment. When XOR processing is performed in parallel, data is arranged as shown in FIG. 24. Specifically, first, two blocks BLKa and BLKb included in multiple blocks BLK of the memory cell array 110-2 are associated with each other. Block BLKa includes multiple NAND strings NSa0, NSa1, NSa2, ..., NSam. Block BLKb includes multiple NAND strings NSb0, NSb1, NSb2, ..., NSbm. NAND string NSa and NAND string NSb, which have the same reference numerals, form a pair similar to the two NAND strings NSa and NSb shown in FIG. 20 and are connected to the same bit line BL.

[0141] For example, the NAND string NSa0 stores "A" data, "bB-1" data, "bC-1" data, and "bD-1" data in this order. The NAND string NSb0 stores complementary data of the data stored in the NAND string NSa0, i.e., "bA" data, "B-1" data, "C-1" data, and "D-1" data, in this order. The NAND string NSa1 stores "A" data, "bB-2" data, "bC-2" data, and "bD-2" data, in this order. The NAND string NSb1 stores complementary data of the data stored in the NAND string NSa1, i.e., "bA" data, "B-2" data, "C-2" data, and "D-2" data, in this order. Note that the "Bj" data corresponds to data associated with the same word line WL and may differ for each bit line BL. The "Cj" data corresponds to data associated with the same word line WL and may be different for each bit line BL. The "Dj" data corresponds to data associated with the same word line WL and may be different for each bit line BL.

[0142] Similarly, each NAND string NSa stores "A" data and "bB" data, "bC" data, and "bD" data that are different for each NAND string NSa. On the other hand, each NAND string NSb stores "bA" data and "B" data, "C" data, and "D" data that are different for each NAND string NSb.

[0143] By using the data array described above, the control circuit 12 can simultaneously execute XOR processing of the comparison source data "A" and the comparison target data "B-1" to "Bm", "C-1" to "Cm", or "D-1" to "Dm" in parallel. In other words, the data array of the memory cell array 110-2 enables parallel processing of large amounts of data.

[0144] <4-1-5> Exclusive Negative OR (XNOR) processing FIG. 25 is a schematic diagram showing a specific example of an exclusive NOR operation performed by the semiconductor device 10 according to the fourth embodiment. FIG. 25 is a schematic diagram showing a specific example of an exclusive NOR operation performed by the semiconductor device 10 according to the fourth embodiment. FIG. 25 shows a configuration similar to that shown in FIG. 20 and voltages applied to each word line WL. The following describes a case in which an XNOR operation is performed on "A" data and "B" data when "A1", "A2", and "A3" data are "1", "1", and "0", respectively, and "B1", "B2", and "B3" data are "0", "1", and "1", respectively. The XNOR operation differs from the XOR operation in that the word line WL selected corresponding to the comparison target is changed to the word line WL associated with the complementary data.

[0145] For example, the control circuit 12 executes a read operation targeting the comparison source "A1" data and the complementary data of the comparison target "B1" data. Specifically, as shown in FIG. 25, a read operation is executed by selecting the word line WL0 connected to the memory cell transistor MT storing the "A1" data and the word line WL7 connected to the memory cell transistor MT storing the complementary data of the "B1" data. In a read operation executed by XNOR processing, a read voltage VM is applied to the selected word line WL, and a read pass voltage VREAD is applied to the unselected word lines WL. That is, the read voltage VM is applied to each of the word lines WL0 and WL7, and the read pass voltage VREAD is applied to the other word lines WL.

[0146] Then, in the NAND string NSa, when the read voltage VM is applied, the memory cell transistor MT that stores the "A1" data (="1" data) is turned on, and the memory cell transistor MT that stores the complementary data of the "bB1" data (="0" data) is turned off. On the other hand, in the NAND string NSb, when the read voltage VM is applied, the memory cell transistor MT that stores the "bA1" data (="0" data) is turned off, and the memory cell transistor MT that stores the complementary data of the "B1" data (="1" data) is turned on.

[0147] As a result, neither the cell current Icell through the NAND string NSa nor the cell current Icell through the NAND string NSb flows between the bit line BL and the source line SL. That is, the read results of the NAND strings NSa and NSb correspond to "0" data. The sense amplifier unit SAU then detects that the cell current Icell does not flow and latches "0" data, which is the result of the XNOR operation between the "1" data and the "0" data.

[0148] Similarly, in the XNOR process, one bit (one word line WL) is selected at a time from the comparison source data and the complementary data of the comparison target data, and a read operation is performed. This allows the difference between the "A" data and the complementary data of the "B" data to be checked bit by bit. The sense amplifier unit SAU then latches (holds) "0" data if there is a difference between the comparison source data and the complementary data of the comparison target data, and latches "1" data if the comparison source data and the complementary data of the comparison target data are the same.

[0149] In the above description, the "A" data is composed of 3 bits, but this is not limiting. The "A" data may be 1 bit, 2 bits, or 4 or more bits. In the XNOR process, the number of bits constituting the "A" data and the number of bits constituting the "B" data to be compared are set to the same number. By applying the data arrangement described with reference to FIG. 24, the XNOR process between the source data and multiple target data can be performed simultaneously in parallel, similar to the XOR process.

[0150] <4-3> Effects of the fourth embodiment As described above, the semiconductor device 10 according to the fourth embodiment can perform storage processing to execute logical operations. Furthermore, by using data rearranged by the storage processing, the semiconductor device 10 according to the fourth embodiment can implement comparison processing, addition processing, XOR processing, and XNOR processing through read operations. In this way, the semiconductor device 10 according to the fourth embodiment can execute various logical operations by utilizing the structure of the NAND flash memory.

[0151] Furthermore, the semiconductor device 10 according to the fourth embodiment stores complementary data in each NAND string NS when writing purchase data to the memory cell array 110-2. This allows the semiconductor device 10 according to the fourth embodiment to selectively use XOR processing and XNOR processing simply by changing the selected word line WL.

[0152] <5> Modifications etc. The information processing system 1 described above can be modified in various ways.

[0153] The host device 20 shown in FIG. 1 may be replaced with a memory controller that controls the semiconductor device 10. In this case, the memory controller controls the semiconductor device 10 based on instructions from the external host device. If the semiconductor device 10 does not have the function of executing the read instruction held in the output holding register 117 as in the second embodiment, the read result including the read instruction may be output to such a memory controller. The memory controller may be configured to input a read instruction based on the read instruction received from the semiconductor device 10 to the semiconductor device 10. Similarly, if the semiconductor device 10 does not have the function of executing the post-processing instruction held in the output holding register 117 as in the third embodiment, the read result including the post-processing instruction may be output to the memory controller. The memory controller may be configured to execute the post-processing instruction received from the semiconductor device 10 and input the post-processing result to the semiconductor device 10.

[0154] In the above embodiments, the flowcharts used to explain the operation are merely examples. Other processes may be added to the flowcharts. In this specification, "connected" refers to being electrically connected, and does not exclude, for example, the presence of another element between them. "Electrically connected" may also refer to being connected via an insulator as long as it can operate in the same way as electrically connected devices. The sense amplifier unit SAU may be configured to perform simple arithmetic processing. In the fourth embodiment, purchase data is used as the data on which logical operations are performed, but this is not limiting. The data on which logical operations are performed may be changed as appropriate according to user requests.

[0155] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0156] 1...information processing system, 1A...information processing unit, 10, 10A...semiconductor device, 11, 11A, 11-1, 11-2, 11-3...information processing unit, 12...control circuit, 13...plane management circuit, 14...external access management circuit, 15...memory circuit, 16...input / output circuit, 20...host device, 110, 110-1, 110-2, 110-3...memory cell array, 111...driver circuit, 112...row decoder module, 113...sense amplifier module, 114...read control circuit, 114A...read control circuit, 115...write control circuit, 116...erase control circuit, 117... Output holding register, 118...register output circuit, 200...register input circuit, 201...read command generation circuit, 202...table holding circuit, 203...table input circuit, 301...post-processing command execution circuit, 302...table holding circuit, 303...table input circuit, BLK...block, NS, NSa, NSb...NAND string, BL...bit line, WL...word line, DS...data set, DU...data unit, QC1, QC2...query, RD...row decoder, SAU...sense amplifier unit, MT...memory cell transistor, ST1, ST2...selection transistor

Claims

1. a first bit line; a plurality of strings connected to the first bit line, each string including a select transistor and a plurality of memory cells connected in series; a first control circuit configured to perform a logical operation; In the logical operation, the first control circuit is configured to perform a read operation of applying a first voltage to select transistors of at least two strings among the plurality of strings, applying a second voltage lower than the first voltage to select transistors of strings other than the at least two strings, applying a third voltage to at least two memory cells among the plurality of memory cells of each of the plurality of strings, and applying a fourth voltage higher than the third voltage to memory cells other than the at least two memory cells. Semiconductor device.

2. a plurality of bit lines including the first bit line, each of which is connected to one of the plurality of strings; a plurality of sense amplifiers connected to the plurality of bit lines; an output holding register for holding data output from each of the plurality of sense amplifiers; the first control circuit is further configured to, after executing the read operation, execute a read command based on the read result held in the output holding register. The semiconductor device according to claim 1 .

3. a plurality of bit lines including the first bit line, each of which is connected to one of the plurality of strings; a plurality of sense amplifiers connected to the plurality of bit lines; an output holding register that holds data output from each of the plurality of sense amplifiers; a second control circuit configured to execute a post-processing instruction including a logical operation based on the read result held in the output holding register after the read operation is executed; The semiconductor device according to claim 1 .

4. first and second memory cell arrays each including the plurality of strings and configured to store data in pages; a third control circuit configured to write input data to a first page of the first memory cell array and to write the input data read from the first page to a first string included in the plurality of strings of the second memory cell array, The semiconductor device according to claim 1 .

5. the third control circuit is further configured to, when a query is input from outside, execute a read operation of applying a voltage based on the query to each of the plurality of memory cells of the first string. The semiconductor device according to claim 4 .

6. further comprising a third memory cell array connected to a plurality of sense amplifiers each having a latch circuit; The third control circuit further includes: counting the number of first values ​​obtained as a result of executing a read operation based on a first query, and changing the values ​​held in the latch circuits of a number of sense amplifiers corresponding to the first count result based on the first query from a head of the plurality of sense amplifiers from the second value to a third value; counting the number of the first values ​​obtained as a result of executing a read operation based on a second query, and changing values ​​held in the latch circuits of sense amplifiers corresponding to a second count result based on the second query from the second value to the third value, starting from the sense amplifier next to the sense amplifier whose latch circuit holds the third value among the plurality of sense amplifiers; The latch circuit is configured to acquire the sum of the first count result and the second count result according to the binary number assigned to the last sense amplifier that holds the third value. The semiconductor device according to claim 5 .

7. the third control circuit, when writing the input data read from the first page to the first string of the second memory cell array, further writes complementary data of the input data to the first string; The semiconductor device according to claim 4 .

8. the plurality of strings of the second memory cell array further includes a second string connected to the same bit line as the first string; the third control circuit writes complementary data of the data stored in the first string to the second string; The semiconductor device according to claim 7 .

9. the third control circuit is configured to perform an exclusive-or operation; the plurality of memory cells included in the first string include a first memory cell storing first data, a second memory cell storing complementary data of the first data, a third memory cell storing complementary data of the second data, and a fourth memory cell storing the second data; the plurality of memory cells included in the second string include a fifth memory cell storing complementary data of the first data, a sixth memory cell storing the first data, a seventh memory cell storing the second data, and an eighth memory cell storing complementary data of the second data; the third control circuit, in the exclusive OR operation, applies the first voltage to each selection transistor of the first string and the second string, applies the third voltage to each of the first memory cell, the third memory cell, the fifth memory cell, and the seventh memory cell, and applies the fourth voltage to each of the second memory cell, the fourth memory cell, the sixth memory cell, and the eighth memory cell; The semiconductor device according to claim 8 .

10. the third control circuit is configured to perform an exclusive NOR operation; the plurality of memory cells included in the first string include a first memory cell storing first data, a second memory cell storing complementary data of the first data, a third memory cell storing complementary data of the second data, and a fourth memory cell storing the second data; the plurality of memory cells included in the second string include a fifth memory cell storing complementary data of the first data, a sixth memory cell storing the first data, a seventh memory cell storing the second data, and an eighth memory cell storing complementary data of the second data; the third control circuit, in the exclusive NOR operation, applies the first voltage to each selection transistor of the first string and the second string, applies the third voltage to each of the first memory cell, the fourth memory cell, the fifth memory cell, and the eighth memory cell, and applies the fourth voltage to each of the second memory cell, the third memory cell, the sixth memory cell, and the seventh memory cell; The semiconductor device according to claim 8 .

11. A storage medium for storing a program for controlling a semiconductor device having a first bit line and a plurality of strings connected to the first bit line, each string including a selection transistor and a plurality of memory cells connected in series, the storage medium comprising: The program is configured to cause the semiconductor device to execute a read operation including applying a first voltage to select transistors of at least two strings among the plurality of strings, applying a second voltage lower than the first voltage to select transistors of strings other than the at least two strings, applying a third voltage to at least two memory cells among the plurality of memory cells of each of the plurality of strings, and applying a fourth voltage higher than the third voltage to memory cells other than the at least two memory cells. storage medium.

12. the semiconductor device further includes a plurality of bit lines including the first bit line and each connected to the plurality of strings, a plurality of sense amplifiers connected to the plurality of bit lines, and an output holding register that holds data output from each of the plurality of sense amplifiers; the program is further configured to, after executing the read operation, execute a read instruction based on the read result held in the output holding register. The storage medium of claim 11.

13. the semiconductor device further includes a plurality of bit lines including the first bit line and each connected to the plurality of strings, a plurality of sense amplifiers connected to the plurality of bit lines, and an output holding register that holds data output from each of the plurality of sense amplifiers; the program is further configured to execute a post-processing instruction including a logical operation based on the read result held in the output holding register after the read operation is executed. The storage medium of claim 11.

14. The semiconductor device further includes first and second memory cell arrays, each including the plurality of strings and configured to store data in page units; the program is further configured to write input data to a first page of the first memory cell array, and to write the input data read from the first page to a first string included in the plurality of strings of the second memory cell array. The storage medium of claim 11.

15. The program is further configured to, when a query is input from outside, execute a read operation of applying a voltage based on the query to each of the plurality of memory cells of the first string.

15. The storage medium of claim 14.

16. the semiconductor device further includes a third memory cell array connected to a plurality of sense amplifiers each having a latch circuit; The program further comprises: counting the number of first values ​​obtained as a result of executing a read operation based on a first query, and changing the values ​​held in the latch circuits of a number of sense amplifiers corresponding to the first count result based on the first query from a head of the plurality of sense amplifiers from the second value to a third value; counting the number of the first values ​​obtained as a result of executing a read operation based on a second query, and changing values ​​held in the latch circuits of sense amplifiers corresponding to a second count result based on the second query from the second value to the third value, starting from the sense amplifier next to the sense amplifier whose latch circuit holds the third value among the plurality of sense amplifiers; The latch circuit is configured to acquire the sum of the first count result and the second count result according to the binary number assigned to the last sense amplifier that holds the third value.

16. The storage medium of claim 15.

17. the program is further configured to, when writing the input data read from the first page to the first string of the second memory cell array, further write complementary data of the input data to the first string.

15. The storage medium of claim 14.

18. the plurality of strings of the second memory cell array further includes a second string connected to the same bit line as the first string; The program is further configured to write to the second string complementary data of the data stored in the first string.

18. The storage medium of claim 17.

19. the plurality of memory cells included in the first string include a first memory cell storing first data, a second memory cell storing complementary data of the first data, a third memory cell storing complementary data of the second data, and a fourth memory cell storing the second data; the plurality of memory cells included in the second string include a fifth memory cell storing complementary data of the first data, a sixth memory cell storing the first data, a seventh memory cell storing the second data, and an eighth memory cell storing complementary data of the second data; the program is further configured to execute an exclusive OR operation, and in the exclusive OR operation, apply the first voltage to each select transistor of the first string and the second string, apply the third voltage to each of the first memory cell, the third memory cell, the fifth memory cell, and the seventh memory cell, and apply the fourth voltage to each of the second memory cell, the fourth memory cell, the sixth memory cell, and the eighth memory cell.

20. The storage medium of claim 18.

20. the plurality of memory cells included in the first string include a first memory cell storing first data, a second memory cell storing complementary data of the first data, a third memory cell storing complementary data of the second data, and a fourth memory cell storing the second data; the plurality of memory cells included in the second string include a fifth memory cell storing complementary data of the first data, a sixth memory cell storing the first data, a seventh memory cell storing the second data, and an eighth memory cell storing complementary data of the second data; the program is further configured to execute an exclusive NOR operation, and in the exclusive NOR operation, apply the first voltage to each select transistor of the first string and the second string, apply the third voltage to each of the first memory cell, the fourth memory cell, the fifth memory cell, and the eighth memory cell, and apply the fourth voltage to each of the second memory cell, the third memory cell, the sixth memory cell, and the seventh memory cell.

20. The storage medium of claim 18.

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