Electronic device and monitoring method

Abstract

To enable analysis of malfunctions even after the malfunctions occur that cause some functions of a device to stop operating.SOLUTION: An electronic device includes at least three or more CPUs (Central Processing Units). The first CPU has a notification unit for notifying a third CPU, which is different from the first and second CPUs, of status information regarding processing instructions output from the first CPU to the second CPU, and the second CPU has a processing unit for executing processing instructions output from the first CPU, and the third CPU has a third storage unit and a writing unit for writing the acquired status information into the third storage unit when acquiring the status information notified from the first CPU.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an electronic device and a monitoring method. [Background technology]

[0002] 2. Description of the Related Art Some electronic devices equipped with multiple CPUs (Central Processing Units) have a function in which one CPU outputs a processing command to another CPU to cause the other CPU to execute the processing. The processing commands that are output are various, for example, a process for updating software or firmware. There is also a system for managing firmware updates in electronic devices (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 4929726 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when updating software or firmware for electronic devices, if the update fails, the CPU may not be able to start up, rendering the system itself inoperable. This inoperability can be caused by hardware malfunctions in the memory that stores the software or firmware, resulting in data corruption. When the onboard system itself becomes inoperable, it must be repaired as quickly as possible. If the cause of the malfunction is software, it may be possible to repair it by updating the software, and if the cause of the malfunction is hardware, it may be possible to repair it by replacing hardware-related parts such as the electrical board. For such repairs, it is preferable to take measures according to the cause of the malfunction. However, when a malfunction occurs and some of the equipment's functions are not working, it may be difficult to analyze the malfunction. Therefore, if the cause cannot be identified or it will take a long time to identify the cause, it may be possible to address the issue by replacing the electrical board itself.

[0005] The present invention has been made in consideration of the above circumstances, and its purpose is to provide an electronic device and a monitoring method that can analyze a malfunction even after a malfunction occurs and some of the functions of the device become inoperable. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems, one aspect of the present invention is an electronic device including a plurality of CPUs (central processing units), at least three or more, wherein a first CPU has a notification unit that notifies a third CPU, different from the first CPU and the second CPU, of status information regarding processing instructions output from the first CPU to a second CPU, the second CPU has a processing unit that executes the processing instructions output from the first CPU, and the third CPU has a third memory unit and a writing unit that, upon obtaining the status information notified from the first CPU, writes the obtained status information into the third memory unit.

[0007] Another aspect of the present invention is a monitoring method executed by an electronic device including a plurality of CPUs (central processing units), at least three or more, in which a first CPU notifies a third CPU different from the first and second CPUs of status information regarding a processing command output from the first CPU to a second CPU, the second CPU executes the processing command output from the first CPU, and when the third CPU acquires the status information notified from the first CPU, the acquired status information is written to a third memory unit connected to the third CPU. [Effects of the Invention]

[0008] As described above, according to this invention, status information regarding a processing command is output from the first CPU to a third CPU, which is different from the first CPU that outputs the processing command and the second CPU that receives the processing command, and the status information is stored in the nonvolatile memory of the third CPU. This allows the data stored in the nonvolatile memory of the third CPU to be referenced even if a malfunction occurs, making it possible to analyze the malfunction even after a malfunction has occurred and some of the device's functions have become inoperable. Furthermore, if the cause of the malfunction can be identified by analyzing the malfunction, a suitable countermeasure can be taken from among several options, such as a software update or replacing the electrical circuit board. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic block diagram showing the configuration of a monitoring system S according to an embodiment of the present invention. [Figure 2] 10 is a flowchart illustrating the operation of the electronic device when the processing command is an update process. [Figure 3] 10 is a flowchart illustrating the operation of the electronic device when a command is transmitted from a first CPU to a second CPU. [Figure 4] FIG. 10 is a schematic block diagram showing the configuration of a monitoring system Sa in a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] A monitoring system S according to an embodiment of the present invention will be described below with reference to the drawings. First Embodiment FIG. 1 is a schematic block diagram showing the configuration of a monitoring system S according to an embodiment of the present invention. The monitoring system S monitors an electronic device including at least three or more CPUs (Central Processing Units). The monitoring system S may be installed in the electronic device. The electronic device may be a monitoring system. The electronic device may be any device equipped with three or more CPUs, such as a display device or a projector. When the electronic device is a display device or a projector, the display device may have the function of the monitoring system S, or the projector may have the function of the monitoring system S. The display device may be any of a projector, liquid crystal display, LED (Light Emitting Diode) display, etc. One of the components that make up the electronic device is an electrical board K. On the electrical board K, a CPU 10, a nonvolatile memory 18, a CPU 20, a nonvolatile memory 28, a CPU 30, and a nonvolatile memory 38 are provided.

[0011] The CPU 10 is communicatively connected to the CPU 20 via a communication line CB12, and is communicatively connected to the CPU 30 via a communication line CB31. The CPU 10 is also communicatively connected to the nonvolatile memory 18 via a communication line CBa.

[0012] The CPU 20 is communicatively connected to the CPU 10 via a communication line CB12, and is communicatively connected to the CPU 30 via a communication line CB23. The CPU 20 is also communicatively connected to the nonvolatile memory 28 via a communication line CBb.

[0013] The CPU 30 is communicatively connected to the CPU 10 via a communication line CB31, and is communicatively connected to the CPU 20 via a communication line CB23. The CPU 30 is also communicatively connected to the nonvolatile memory 38 via a communication line CBc.

[0014] The CPU 10 also includes a communication unit 11, a processing unit 12, a notification unit 13, and a writing unit 14. The communication unit 11 has a function of communicating with the communication unit 21 of the CPU 20 via a communication line CB12, and a function of communicating with the communication unit 31 of the CPU 30 via a communication line CB31. The processing unit 12 executes various processes. For example, when the processing unit 12 receives a processing command output from another CPU (CPU 20, CPU 30), the processing unit 12 executes a process according to the received processing command. The notification unit 13 notifies a CPU 30, which is different from the CPUs 10 and 20, of status information relating to a processing command output from the CPU 10 to the CPU 20. Furthermore, the notification unit 13 notifies the CPU 20, which is different from the CPU 10 and the CPU 30, of status information relating to a processing command output from the CPU 10 to the CPU 30. The writing unit 14 has a function of writing the acquired status information into the non-volatile memory 18 when it acquires the status information notified from the CPU 20, and a function of writing the acquired status information into the non-volatile memory 18 when it acquires the status information notified from the CPU 30.

[0015] The CPU 20 also includes a communication unit 21, a processing unit 22, a notification unit 23, and a writing unit 24. The communication unit 21 has a function of communicating with the communication unit 11 of the CPU 10 via a communication line CB12, and a function of communicating with the communication unit 31 of the CPU 30 via a communication line CB23. The processing unit 22 executes various processes. For example, when the processing unit 22 receives a processing command output from another CPU (CPU 10, CPU 30), the processing unit 22 executes a process according to the received processing command. The notification unit 23 notifies the CPU 30, which is different from the CPU 10 and the CPU 20, of status information relating to a processing command output from the CPU 20 to the CPU 10. Furthermore, the notification unit 23 notifies the CPU 10, which is different from the CPU 20 and the CPU 30, of status information relating to a processing command output from the CPU 20 to the CPU 30. The writing unit 24 has a function of writing the acquired status information into the non-volatile memory 28 when it acquires the status information notified from the CPU 10, and a function of writing the acquired status information into the non-volatile memory 28 when it acquires the status information notified from the CPU 30.

[0016] The CPU 30 also includes a communication unit 31, a processing unit 32, a notification unit 33, and a writing unit . The communication unit 31 has a function of communicating with the communication unit 11 of the CPU 10 via a communication line CB31, and a function of communicating with the communication unit 21 of the CPU 20 via a communication line CB23. The processing unit 32 executes various processes. For example, when the processing unit 32 receives a processing command output from another CPU (CPU 10, CPU 20), the processing unit 32 executes a process according to the received processing command. The notification unit 33 notifies the CPU 20, which is different from the CPU 30 and the CPU 10, of status information relating to a processing command output from the CPU 30 to the CPU 10. Furthermore, the notification unit 33 notifies the CPU 10, which is different from the CPU 30 and the CPU 20, of status information relating to a processing command output from the CPU 30 to the CPU 20. The writing unit 34 has a function of writing the acquired status information into the non-volatile memory 38 when it acquires the status information notified from the CPU 10, and a function of writing the acquired status information into the non-volatile memory 38 when it acquires the status information notified from the CPU 20.

[0017] Next, the operation of the above-mentioned monitoring system S will be described. <<In the case of updates>> FIG. 2 is a flowchart illustrating the operation of the electronic device when the processing command is an update process. The update process is, for example, a process of causing each CPU to execute an update process. In this embodiment, an electronic device executes an update process that sequentially updates the programs of at least two of a plurality of CPUs, and executing this update process includes sequentially executing updates for multiple combinations of different combinations of a CPU that outputs an update instruction and a CPU that receives the update instruction. This will be described as an example of an update process in which, even if an update for a first combination of the multiple combinations does not end normally, updates for the remaining combinations continue to be executed sequentially.

[0018] When the electronic device receives an update command from the outside (step S10), based on this update command, the electronic device sequentially executes an update process, which is a series of processes, including a process in which CPU10 causes CPU20 to perform an update, a process in which CPU10 causes CPU30 to perform an update, and a process in which CPU30 causes CPU10 to perform an update. Here, there are three combinations of CPUs that perform updates. In the first combination, CPU 10 is the source that outputs the update instruction and CPU 20 is the destination that receives the instruction, and the first combination does not include CPU 30. In the second combination, CPU 10 is the source that outputs the update instruction and CPU 30 is the destination that receives the instruction, and CPU 20 is not included in the second combination. In the third combination, CPU30 is the source that outputs the update instruction and CPU10 is the destination that receives the instruction, and CPU20 is not included in the third combination. Other combinations of CPUs may be used instead of this combination. For example, CPU 20 may be the source of outputting an update instruction, CPU 10 may be the destination of the instruction, and CPU 30 may not be included in the combination.

[0019] The CPU 10 outputs a processing command to the CPU 20 to cause it to execute an update (step S11), and notifies the CPU 30 of status information related to the update (step S12), and stores the notified status information in the non-volatile memory 18. The notified status information includes, for example, that "at time t1, the CPU 10 output an instruction to start an update to the CPU 20." Here, the CPU 10 outputs a processing command to the CPU 20 to execute an update at a timing when it has not output a processing command to the CPU 30 for an update, and has not output a processing command to the CPU 30 for executing an update at a timing when it outputs the status information to the CPU 30.

[0020] When CPU 30 acquires the status information from CPU 10, writing unit 34 of CPU 30 writes the status information to nonvolatile memory 38 (step S13). Here, at the time when CPU 30 acquires the status information from CPU 10, CPU 30 has not received an update processing command from CPU 10. Therefore, CPU 30 is not currently executing update processing, and therefore, even if CPU 20 executes update processing based on a processing command from CPU 10, CPU 30 can execute the status information writing process regardless of whether the update was completed successfully or a malfunction occurred. This allows CPU 30 to leave in nonvolatile memory 38, as status information, the fact that CPU 10 has issued a processing command to CPU 20 to execute an update.

[0021] On the other hand, when the CPU 20 receives the update processing command from the CPU 10, it executes the update (step S14). This update processing may end normally, but may not end normally due to a malfunction. If a malfunction occurs, the CPU 20 may not operate normally after executing this update processing.

[0022] Here, if CPU 10 can acquire the processing status from CPU 20, regarding whether the update processing of CPU 20 ended normally or whether a problem occurred during the update, CPU 10 may store the processing status in nonvolatile memory 18 and output it as status information to CPU 30. This allows CPU 30 to write status information indicating whether the update of CPU 20 ended normally or not as a result of the update processing command output from CPU 10 to CPU 20 to nonvolatile memory 38. This allows CPU 30 to also leave status information indicating whether the update of CPU 20 ended normally or not in nonvolatile memory 38. CPU 10 can also leave status information indicating whether the update of CPU 20 ended normally or not in nonvolatile memory 18.

[0023] After the update process for the first combination is executed, CPU 10 proceeds to update process for the second combination, regardless of whether the update for the first combination has been completed normally or not. CPU 10 outputs a processing command to CPU 30 to execute the update (step S21), and notifies CPU 20 of status information related to the update (step S22), and stores the notified status information in non-volatile memory 18. The notified status information includes, for example, "CPU 10 output an instruction to start update to CPU 30 at time t2." Here, CPU 10 outputs a processing command to CPU 30 to execute the update at a timing when it has not output a processing command to CPU 20 for the update, and has not output a processing command to CPU 20 to execute the update at a timing when it outputs the status information to CPU 20.

[0024] When CPU 20 acquires the status information from CPU 10, writing unit 24 of CPU 20 writes the status information to nonvolatile memory 28 (step S23). Here, at the timing when CPU 20 acquires the status information from CPU 10, CPU 10 has not yet issued an update processing command to CPU 20. Therefore, CPU 30 is not currently executing an update process. Therefore, even if CPU 30 executes an update process based on a processing command from CPU 10, it can execute the status information write process regardless of whether the update was completed successfully or a malfunction occurred. Here, even if the update is executed in step S14, if CPU 20 can successfully execute the process of writing the status information to nonvolatile memory 28, it can leave the status information in nonvolatile memory 28. On the other hand, if the update in step S14 is executed but the update does not end normally, resulting in a state in which the process of writing the status information to non-volatile memory 28 cannot be executed normally, the status information cannot be left in non-volatile memory 28. However, status information indicating that a processing command to cause CPU 20 to execute the update process was output from CPU 10 to CPU 20 in step S13 remains in non-volatile memory 38, and this status information can be used as a clue to analyze the malfunction. For example, it can be determined that the malfunction may be related to the output of a processing command from CPU 10 to CPU 20 to execute the update process. Furthermore, if status information indicating whether or not the update from CPU 10 to CPU 20 ended normally remains in non-volatile memory 38, this status information can also be used as a clue to analyze the malfunction. In this way, the CPU 20 can leave in the nonvolatile memory 28, as status information, the fact that the CPU 10 has issued a processing command to the CPU 30 to execute the update.

[0025] On the other hand, when the CPU 30 receives the update processing command from the CPU 10, it executes the update (step S24). This update processing may end normally, but may not end normally due to a malfunction. If a malfunction occurs, the CPU 30 may not operate normally after executing this update processing.

[0026] Here, if CPU 10 can acquire the processing status from CPU 30, regarding whether the update processing of CPU 30 ended normally or whether a problem occurred during the update, CPU 10 may store the processing status in nonvolatile memory 18 and output it as status information to CPU 20. This allows CPU 20 to write status information indicating whether the update of CPU 30 ended normally or not as a result of the update processing command output from CPU 10 to CPU 30 to nonvolatile memory 28. This allows CPU 20 to leave status information indicating whether the update of CPU 10 ended normally or not in nonvolatile memory 28. CPU 10 can also leave status information indicating whether the update of CPU 30 ended normally or not in nonvolatile memory 18.

[0027] After the update process for the second combination is executed, CPU 30 proceeds to update process for the third combination, regardless of whether the update for the second combination has been completed normally or not. CPU 30 outputs a processing command to CPU 10 to execute the update (step S31), and notifies CPU 20 of status information related to the update (step S32), and stores the notified status information in non-volatile memory 38. The notified status information includes, for example, "CPU 30 output an instruction to start update to CPU 10 at time t3." Here, CPU 30 outputs a processing command to CPU 10 to execute the update at a timing when it has not output a processing command to CPU 20 for the update, and has not output a processing command to CPU 20 to execute the update at a timing when it outputs the status information to CPU 20.

[0028] When CPU 20 acquires the status information from CPU 30, writing unit 24 of CPU 20 writes the status information to nonvolatile memory 28 (step S33). Here, at the timing when CPU 20 acquires the status information from CPU 30, CPU 20 has not received an update processing command from CPU 30. Therefore, CPU 20 is not currently executing update processing. Therefore, even if CPU 20 executes update processing based on a processing command from CPU 30, it can execute the status information writing process regardless of whether the update was completed successfully or a malfunction occurred. Here, even if the update in step S14 is executed, if CPU 20 can successfully execute the process of writing the status information to nonvolatile memory 28, the status information can be left in nonvolatile memory 28. On the other hand, if the update in step S14 is executed but the update does not end normally, resulting in a state in which the process of writing the status information to non-volatile memory 28 cannot be executed normally, the status information cannot be left in non-volatile memory 28. However, status information indicating that a processing command to cause CPU 20 to execute the update process was output from CPU 10 to CPU 20 in step S13 remains in non-volatile memory 38, and this status information can be used as a clue to analyze the malfunction. For example, it can be determined that the malfunction may be related to the output of a processing command from CPU 10 to CPU 20 to execute the update process. Furthermore, if status information indicating whether or not the update from CPU 10 to CPU 20 ended normally remains in non-volatile memory 38, this status information can also be used as a clue to analyze the malfunction. In this way, the CPU 20 can leave in the nonvolatile memory 28 as status information that the CPU 30 has issued a processing command to the CPU 10 to execute the update.

[0029] On the other hand, when the CPU 10 receives the update processing command from the CPU 30, it executes the update (step S34). This update processing may end normally, but may not end normally due to a malfunction. If a malfunction occurs, the CPU 10 may not operate normally after executing this update processing.

[0030] Here, if the CPU 30 can acquire the processing status from the CPU 10, regarding whether the update processing of the CPU 10 ended normally or whether a problem occurred during the update, the CPU 30 may store the processing status in the nonvolatile memory 38 and output it as status information to the CPU 20. This allows the CPU 20 to write status information indicating whether the update of the CPU 10 ended normally or not, as a result of the update processing command output from the CPU 30 to the CPU 10, into the nonvolatile memory 28. This allows the CPU 20 to store in the nonvolatile memory 28 the status information indicating whether the update of the CPU 10 ended normally or not. The CPU 30 can also store in the nonvolatile memory 38 the status information indicating whether the update of the CPU 10 ended normally or not.

[0031] When the update process is complete, the electronic device executes a reboot. This causes CPU10, CPU20, and CPU30 to each restart. If a problem occurs during the updates in steps S14 and S34, CPU10 and CPU20 may not be able to restart. On the other hand, if the update in step S2 was completed normally, CPU30 can restart. As a result, even if the electronic device is not operating normally due to a malfunction occurring during the update, the CPU 30 can read out the status information remaining in the nonvolatile memory 38, thereby making it possible to refer to the log related to the update process (step S42). As a result, the cause of the malfunction in the electronic device can be analyzed based on the log (status information) obtained from the nonvolatile memory 38. Here, even if there is a malfunction in the update process between CPU 10 and CPU 20, and CPU 10 is unable to read out the log from nonvolatile memory 18, or CPU 20 is unable to read out the log from nonvolatile memory 28, because the log remains in nonvolatile memory 38 by CPU 30, the malfunction can be analyzed, and data that enables understanding that the update has failed can be left in nonvolatile memory 38.

[0032] <<In the case of commands>> In the above example, the case where the output processing command is an update processing command has been described, but the processing command may be one output from one CPU to another CPU. For example, the processing command may be a command that causes the second CPU to transmit to the first CPU the processing result corresponding to the processing command transmitted from the first CPU to the second CPU. FIG. 3 is a flowchart illustrating the operation of the electronic device when a command is transmitted from the first CPU to the second CPU. The CPU 10 outputs a processing command to the CPU 20 to cause the CPU 10 to transmit the processing result in response to the processing command from the CPU 10 (step S51), and the notification unit 13 of the CPU 10 outputs status information in response to the processing command to the CPU 30 (step S52). The CPU 30 acquires the status information output from the CPU 10 and stores it in the nonvolatile memory 38 .

[0033] Meanwhile, CPU 20 executes processing according to the command received from CPU 10 (step S54). The processing corresponding to the executed command may end normally, and the processing result may be output from CPU 20 to CPU 10. However, the processing may not end normally. An example of an abnormal end is when the command output in step S51 is invalid. If the command is invalid, a solution is not obtained as a processing result, and the command processing loops in CPU 20. As a result, CPU 10 may time out because it cannot obtain a solution from CPU 20. If the processing based on such a command does not end normally, CPU 10, which is the source of the command, and CPU 20, which is the destination of the command, may stop and not operate normally. Even in such a case, the cause of the malfunction can be analyzed by having CPU 30 read and refer to the status information remaining in nonvolatile memory 38.

[0034] Second Embodiment Next, a second embodiment will be described. 4 is a schematic block diagram showing the configuration of a monitoring system Sa in the second embodiment. The monitoring system Sa differs from the monitoring system S in the first embodiment in that an output control unit is provided for each CPU, but apart from the provision of the output control units, the monitoring system Sa has the same configuration as the monitoring system S. Therefore, the same components are denoted by the same reference numerals and their description is omitted, and the following description will mainly focus on the differences. The CPU 10a has an output control unit 15 in addition to the communication unit 11, processing unit 12, notification unit 13, and writing unit 14. The output control unit 15 causes an output device controllable by the CPU 10a to perform output based on the status information stored in the nonvolatile memory 18. The output device may be, for example, any of a liquid crystal panel, an LED lamp, a speaker, etc.

[0035] In this example, for example, a liquid crystal panel is assigned to CPU 10a as a controllable output device, and output control unit 15 has the function of controlling the liquid crystal panel. Output control unit 15 causes the liquid crystal panel to perform output based on status information stored in nonvolatile memory 18. For example, if a malfunction occurs in the electronic device, output control unit 15 causes the liquid crystal panel to display content based on the status information. As a result, even if a malfunction occurs, as long as CPU 30a is in an operable state, the status information remaining in nonvolatile memory 18 can be displayed on the liquid crystal panel. This allows maintenance personnel to analyze the cause of the malfunction based on the status information displayed on the liquid crystal panel.

[0036] Furthermore, an LED lamp is assigned to the CPU 20a as a controllable output device, and the output control unit 25 has the function of controlling the LED lamp. The output control unit 25 causes the LED lamp to perform output based on status information stored in the nonvolatile memory 28. For example, if a malfunction occurs in the electronic device, the output control unit 25 lights up the LED lamp according to a different lighting pattern depending on the status information. As a result, even if a malfunction occurs, as long as the CPU 20a is in an operable state, the LED lamp can be lighted up according to a lighting pattern corresponding to the status information remaining in the nonvolatile memory 28. For example, when the status information indicates a malfunction of CPU 10, output control unit 25 causes the LED lamp to blink according to a first lighting pattern, which is a blinking interval that can notify that CPU 10 is malfunctioning. Furthermore, when the status information indicates a malfunction of CPU 30, output control unit 25 causes the LED lamp to blink according to a second lighting pattern, which is a blinking interval that can notify that CPU 30 is malfunctioning and is different from the blinking interval of the first lighting pattern. This allows maintenance personnel to analyze the cause of the malfunction based on the flashing pattern of the LED lamp.

[0037] Furthermore, a speaker is assigned to the CPU 30a as a controllable output device, and the output control unit 35 has the function of controlling the speaker. The output control unit 35 causes the speaker to perform output based on the status information stored in the nonvolatile memory 38. For example, if a malfunction occurs in the electronic device, the output control unit 35 causes the speaker to output a different sound depending on the status information. As a result, even if a malfunction occurs, as long as the CPU 30a is in an operable state, the speaker can output a sound depending on the status information remaining in the nonvolatile memory 38. For example, when the status information indicates a malfunction of CPU 20, output control unit 25 outputs a first sound capable of notifying that CPU 20 is malfunctioning. When the status information indicates a malfunction of CPU 30, output control unit 25 outputs a second sound capable of notifying that CPU 30 is malfunctioning, which is different from the first sound. This allows the maintenance person to analyze the cause of the malfunction based on the sound being output. According to the second embodiment described above, when a malfunction occurs, the contents remaining in the non-volatile memory can be visualized using an LCD panel, LED, etc., and can be audibly grasped by outputting it from a speaker.

[0038] According to the first and second embodiments described above, in an electronic device including at least three CPUs (Central Processing Units), the CPUs can be mutually monitored. Furthermore, in the above-described embodiment, the case where data stored in non-volatile memory is read by a CPU has been described. However, if the CPU's function of reading data stored in non-volatile memory does not operate normally, the cause of the malfunction can be analyzed by reading the data stored in non-volatile memory using a jig, which is a device separate from the electronic device in which the CPU is installed.

[0039] Furthermore, according to the first and second embodiments described above, the cause of the malfunction can be identified and estimated by analyzing the log stored in the nonvolatile memory. Depending on the cause of the malfunction, it becomes easier to consider countermeasures such as replacing the electrical circuit board on which the CPU is mounted or updating the program. In this way, the cause of the malfunction can be analyzed even after a malfunction has occurred and some of the functions of the electronic device have become inoperable.

[0040] Furthermore, in the above-described first and second embodiments, the electronic device is described as having three CPUs, but the electronic device may also have four or more CPUs. When four or more CPUs are installed, the CPU that outputs the processing command may transmit status information to at least one of the CPU that outputs the processing command and a CPU other than the CPU that receives the processing command. In this case, the CPU to which the status information is transmitted may output the status information to all CPUs other than the CPU that outputs the processing command and the CPU that receives the processing command.

[0041] In this way, status information is output to a third CPU (a CPU different from the first and second CPUs) that is separate from the first CPU (the CPU that outputs the processing command) and the second CPU (the CPU that receives the processing command), and the status information is saved in the non-volatile memory of the third CPU, so that by referencing the data saved in the non-volatile memory of the third CPU, even if a malfunction occurs in the second CPU, it can be determined later that the cause was a processing command output from the first CPU to the second CPU. Since at least three CPUs installed in an electronic device perform this process of saving status information on each other, they can complement each other. In addition, because the status information can be stored in non-volatile memory connected to one of the CPUs, even if the first and second CPUs are not operating normally, the cause of the malfunction can be identified by referencing the data in the non-volatile memory of the third CPU. In this way, even if a malfunction occurs in an electronic device, data that identifies the cause of the malfunction can be stored in any of the three or more CPUs, allowing them to complement each other.

[0042] Furthermore, according to the first and second embodiments described above, even after some of the device's functions have stopped working, the malfunction can be easily analyzed, allowing countermeasures to be taken according to the cause of the malfunction. For example, if a software update is sufficient to address the malfunction, the software update can be performed to fix the malfunction, eliminating the need to replace the electrical circuit board. Furthermore, when a malfunction occurs, data can be recovered without replacing the circuit board by switching the device to a state (such as safe mode) that is minimally required for startup.

[0043] The above-mentioned communication lines CB12, CB23, and CB31 may be any communication lines. Furthermore, the communication lines CB12, CB23, and CB31 each use terminals that are fixed to a high or low logic level when a malfunction or startup failure occurs between the CPUs to be connected, and connect two signal lines, Tx and Rx, as status detection signals between the CPUs. The signal line Tx can be used to notify the status detection signal of the sending CPU to the other CPU, and the signal line Rx can be used to receive the status detection signal from the other CPU, which allows you to adopt the behavior of the other CPU. For example, when power is turned on, each CPU starts up by executing firmware and software stored in a nonvolatile memory connected to the CPU. When each CPU starts up normally, it outputs a normal logic value as a Status TX signal to the other CPU via the signal line Tx. The CPU that output the Status TX signal then detects whether a normal logic value is input to the Status Rx signal. When each CPU detects a normal logic value in the Status RX signal, it starts normal operations by firmware and software (for example, when the electronic device is a projector, it starts various operations to execute the projector function). On the other hand, if at least one of the CPUs detects an abnormal logical value in the Status RX signal, the detection of the abnormal logical value in the Status RX signal is written to non-volatile memory and kept as a log.

[0044] Furthermore, a mode setting (changing) signal may be added to each of the above-mentioned communication lines CB12, CB23, and CB31. Mode switching interconnects the start-up mode setting signals of the devices. If an abnormal logical value is detected in the Status RX signal output from the connected CPU, a mode setting (change) signal may be output to the connected CPU to switch modes. For example, the mode setting (change) signal may be a 2-bit setting, with Normal Mode being set when the two bits are High & High, and Safe Mode being set when the two bits are High / Low.

[0045] The processing units (11, 21, 31), notification units (13, 23, 33), and writing units (14, 24, 34) in the above-described embodiments may be implemented by a computer. In this case, a program for implementing these functions may be recorded on a computer-readable recording medium, and the program may be read and executed by a computer system. Note that the term "computer system" as used herein includes hardware such as an OS and peripheral devices. Furthermore, the term "computer-readable recording medium" refers to portable media such as flexible disks, optical magnetic disks, ROMs, and CD-ROMs, as well as storage devices such as hard disks built into a computer system. Furthermore, the term "computer-readable recording medium" may also include devices that dynamically store programs for a short period of time, such as communication lines used when transmitting programs via networks such as the Internet or communication lines such as telephone lines, or devices that store programs for a certain period of time, such as volatile memory within the computer systems that serve as the server or client in such cases. Furthermore, the above program may be one that realizes part of the above-mentioned functions, or may be one that can realize the above-mentioned functions in combination with a program already recorded in a computer system, or may be one that is realized using a programmable logic device such as an FPGA (Field Programmable Gate Array).

[0046] Although an embodiment of the present invention has been described above in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and includes designs within the scope of the gist of the present invention. [Explanation of symbols]

[0047] 10, 10a, 20, 20a, 30, 30a CPU 11, 21, 31 Communications Department 12, 22, 32 Processing section 13,23,33 Notification section 14, 24, 34 Writing section 15, 25, 35 Output control section 18,28,38 Non-volatile memory CB12,CB23,CB31,CBa,CBb,CBc Communication line K Electrical board S,Sa monitoring system

Claims

1. An electronic device including at least three or more CPUs (Central Processing Units), The first CPU is a notification unit that notifies a third CPU, which is different from the first CPU and the second CPU, of status information relating to a processing command output from the first CPU to the second CPU; The second CPU a processing unit that executes a processing command output from the first CPU; The third CPU A third storage unit; a writing unit that, upon receiving status information notified from the first CPU, writes the received status information into the third storage unit; An electronic device having:

2. The first CPU outputting a processing command to the second CPU for updating the program of the second CPU while not outputting a processing command to the third CPU; The notification unit of the first CPU notifying the third CPU of status information relating to the processing command for updating; The writing unit of the third CPU When the processing command is not received from the first CPU, status information regarding the processing command for updating is obtained and written to the third storage unit. The electronic device according to claim 1 .

3. The electronic device includes: executing an update process for sequentially updating the programs of at least two of the plurality of CPUs; Executing the update process includes: The method includes sequentially updating a plurality of combinations of a CPU that outputs an update instruction and a CPU that receives the update instruction, the combinations being different from one another; an update process in which, even if an update in a first combination among the plurality of combinations is not normally completed, updates in the remaining combinations are sequentially performed; The CPU that outputs the instruction for the combination for executing the update includes: outputting an instruction to perform an update to the CPU that receives the instruction, and notifying status information regarding the update to CPUs that are not included in the combination that executes the update; The CPU not included in the combination acquires the status information when it has not received the instruction to update from the CPU that outputs the instruction in the combination that executes the update, and writes the status information into a storage unit of the CPU not included in the combination. The electronic device according to claim 1 .

4. The first CPU outputting to the second CPU a processing command to cause the second CPU to transmit a processing result in response to the processing command from the first CPU to the first CPU, and outputting to the third CPU by the notification unit status information in response to the processing command; The third CPU acquires status information output from the first CPU and stores it in the third storage unit. The electronic device according to claim 1 .

5. The third CPU has an output control unit that causes an output device controllable by the third CPU to perform output based on the status information stored in the third storage unit. The electronic device according to any one of claims 1 to 4.

6. 1. A monitoring method executed by an electronic device including a plurality of CPUs (Central Processing Units), the plurality of CPUs being at least three or more, comprising: a first CPU notifies a third CPU different from the first CPU and the second CPU of status information relating to a processing command output from the first CPU to the second CPU; the second CPU executes a processing command output from the first CPU; When the third CPU acquires the status information notified from the first CPU, the acquired status information is written into a third storage unit connected to the third CPU. Monitoring method.

Images