Data access method, device and non-transitory computer-readable storage medium

Abstract

The present disclosure provides a data access method and device, and a non-transitory computer-readable storage medium. The method comprises: obtaining a plurality of to-be-processed instructions; wherein each to-be-processed instruction comprises a to-be-accessed address; determining to-be-merged instructions in the plurality of to-be-processed instructions, and performing merging processing on the to-be-merged instructions to obtain a merged instruction; and performing data access according to the to-be-accessed address corresponding to the merged instruction, thereby reducing the overhead of instructions, improving the efficiency of instruction processing, and effectively improving the performance of an electronic device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of electronic devices, and particularly relates to a data access method and device and a non-transitory computer-readable storage medium. BACKGROUND

[0002] With the development of technology, memories (for example, Nand flash) based on Joint Electron Device Engineering Council (JEDEC) protocols are widely applied to electronic devices such as mobile terminals.

[0003] At present, after a process on an electronic device generates a to-be-processed instruction, the to-be-processed instruction is sent to a memory based on a JEDEC protocol, and the memory processes the to-be-processed instruction, that is, accesses a to-be-accessed address of the to-be-processed instruction, that is, data read-write.

[0004] However, when the number of to-be-processed instructions is multiple, the to-be-processed instructions need to be sent to the memory one by one, which leads to an increase in instruction overhead, and the memory can only process the to-be-processed instructions one by one, which reduces the efficiency of instruction processing, thereby affecting the performance of the electronic device. SUMMARY

[0005] Therefore, the present disclosure provides a data access method and device and a non-transitory computer-readable storage medium, which can effectively improve the performance of an electronic device.

[0006] According to a first aspect of an embodiment of the present disclosure, a data access method is provided, applied to an electronic device, and the method comprises:

[0007] obtaining a plurality of to-be-processed instructions; wherein each to-be-processed instruction comprises a to-be-accessed address;

[0008] determining to-be-merged instructions in the plurality of to-be-processed instructions, and performing merging processing on the to-be-merged instructions to obtain a merged instruction;

[0009] performing data access according to a to-be-accessed address corresponding to the merged instruction.

[0010] Optionally, the determining to-be-merged instructions in the plurality of to-be-processed instructions comprises:

[0011] obtaining a first instruction; wherein the first instruction is any instruction in the to-be-processed instructions;

[0012] obtaining a second instruction from the instructions to be processed other than the first instruction; wherein the to-be-accessed address of the second instruction is indirectly continuous with the to-be-accessed address of the first instruction, and the to-be-accessed address of the second instruction is not continuous with the to-be-accessed address of the first instruction through the to-be-accessed address of another instruction to be processed;

[0013] determining the second instruction and the first instruction as the instructions to be merged in response to the second instruction and the first instruction satisfying a first preset merging condition.

[0014] Optionally, the determining the second instruction and the first instruction as the instructions to be merged in response to the second instruction and the first instruction satisfying a first preset merging condition comprises:

[0015] obtaining a storage interval and / or obtaining a current total data amount to be accessed; wherein the storage interval indicates a distance between the to-be-accessed address of the first instruction and the to-be-accessed address of the second instruction; and the current total data amount to be accessed indicates a sum of data amounts to be accessed corresponding to all the instructions to be merged.

[0016] determining the second instruction and the first instruction as the instructions to be merged in a case where the storage interval is less than a first preset threshold and / or the current total data amount to be accessed is less than a second preset threshold.

[0017] Optionally, the method further comprises:

[0018] stopping the traversing of the instructions to be processed other than the first instruction in a case where the current total data amount to be accessed is greater than or equal to the second preset threshold.

[0019] Optionally, the method further comprises:

[0020] obtaining a first time length and obtaining a first time threshold corresponding to the first instruction; wherein the first time length indicates a time length from the time when the first instruction is determined to be obtained to a current time.

[0021] continuing the traversing of the instructions to be processed other than the first instruction in response to the first time length being less than the first time threshold.

[0022] stopping the traversing of the instructions to be processed other than the first instruction in response to the first time length being greater than or equal to the first time threshold.

[0023] Optionally, the method further comprises:

[0024] obtaining a difference between the to-be-accessed address of the second instruction and the to-be-accessed address of the first instruction; wherein the to-be-accessed address is a logical address.

[0025] obtaining a preset storage unit size.

[0026] According to the difference and the preset storage unit size, the storage interval is obtained.

[0027] Optionally, the method further includes:

[0028] obtaining a first instruction; wherein the first instruction is any instruction in the to-be-processed instructions;

[0029] traversing the to-be-processed instructions other than the first instruction;

[0030] in response to the currently traversed to-be-processed instruction and the first instruction satisfying a second preset merging condition, determining the currently traversed to-be-processed instruction and the first instruction as the to-be-merged instructions.

[0031] Optionally, the method further includes:

[0032] saving the to-be-processed instructions into a preset instruction queue;

[0033] taking the to-be-processed instructions in the preset instruction queue that satisfy at least one of the following conditions as the first instruction:

[0034] a second time length corresponding to the to-be-processed instruction is greater than a second time threshold; wherein the second time length indicates a saving time length of the to-be-processed instruction in the preset instruction queue;

[0035] the to-be-processed instruction is in a set position in the preset instruction queue; wherein the set position is a head position or a tail position.

[0036] Optionally, the merging processing of the plurality of to-be-merged instructions to obtain a merged instruction includes:

[0037] generating a merging processing result according to the to-be-accessed addresses of the to-be-merged instructions, and encapsulating the merging processing result in a set instruction format to obtain the merged instruction.

[0038] Optionally, the method further includes:

[0039] obtaining a to-be-accessed data amount corresponding to each of the to-be-merged instructions respectively;

[0040] adding the to-be-accessed data amount corresponding to each of the to-be-merged instructions into a merging processing result respectively.

[0041] According to a second aspect of the embodiments of the present disclosure, a data access apparatus is provided, applied to an electronic device, and the apparatus includes:

[0042] an instruction obtaining module, configured to obtain a plurality of to-be-processed instructions; wherein each of the to-be-processed instructions includes a to-be-accessed address;

[0043] an instruction merging module, configured to determine to-be-merged instructions from the plurality of to-be-processed instructions, and perform merging processing on the to-be-merged instructions to obtain merged instructions;

[0044] an instruction sending module, configured to perform data access according to a to-be-accessed address corresponding to the merged instructions.

[0045] Optionally, the instruction merging module is specifically configured to:

[0046] obtain a first instruction; wherein the first instruction is any instruction from the to-be-processed instructions;

[0047] traverse to-be-processed instructions other than the first instruction to obtain a second instruction; wherein a to-be-accessed address of the second instruction is indirectly continuous with a to-be-accessed address of the first instruction, and the to-be-accessed address of the second instruction is not continuous with the to-be-accessed address of the first instruction through a to-be-accessed address of another to-be-processed instruction;

[0048] in response to the second instruction and the first instruction satisfying a first preset merging condition, determine the second instruction and the first instruction as the to-be-merged instructions.

[0049] Optionally, the instruction merging module is further configured to:

[0050] obtain a storage interval and / or obtain a current total data amount of access; wherein the storage interval indicates a distance between the to-be-accessed address of the first instruction and the to-be-accessed address of the second instruction; wherein the current total data amount of access indicates a sum of to-be-accessed data amounts corresponding to all to-be-merged instructions;

[0051] in a case where the storage interval is less than a first preset threshold and / or the current total data amount of access is less than a second preset threshold, determine the second instruction and the first instruction as the to-be-merged instructions.

[0052] Optionally, the instruction merging module is further configured to:

[0053] in a case where the current total data amount of access is greater than or equal to the second preset threshold, stop traversing to-be-processed instructions other than the first instruction.

[0054] Optionally, the instruction merging module is further configured to:

[0055] obtain a first time length and obtain a first time threshold corresponding to the first instruction; wherein the first time length indicates a time length from a time point of determining to obtain the first instruction to a current time point;

[0056] in response to the first time length being less than a first time threshold, continue to iterate through the pending instructions other than the first instruction;

[0057] in response to the first time length being greater than or equal to the first time threshold, stop iterating through the pending instructions other than the first instruction.

[0058] Optionally, the instruction merging module is further configured to:

[0059] obtain a difference between a to-be-accessed address of the second instruction and a to-be-accessed address of the first instruction; wherein the to-be-accessed address is a logical address;

[0060] obtain a preset storage unit size;

[0061] obtain the storage interval according to the difference and the preset storage unit size.

[0062] Optionally, the instruction merging module is specifically configured to:

[0063] obtain a first instruction; wherein the first instruction is any one of the pending instructions;

[0064] iterate through the pending instructions other than the first instruction;

[0065] in response to the currently iterated pending instruction and the first instruction satisfying a second preset merging condition, determine the currently iterated pending instruction and the first instruction as the to-be-merged instructions.

[0066] Optionally, the instruction merging module is further configured to:

[0067] save the pending instructions into a preset instruction queue;

[0068] take the pending instructions in the preset instruction queue that satisfy at least one of the following conditions as the first instruction:

[0069] a second time length corresponding to the pending instruction is greater than a second time threshold; wherein the second time length indicates a saving time length of the pending instruction in the preset instruction queue;

[0070] the pending instruction is in a preset position in the preset instruction queue; wherein the preset position is a head position or a tail position.

[0071] Optionally, the instruction merging module is specifically configured to:

[0072] generate a merging processing result according to the to-be-accessed addresses of the to-be-merged instructions, and encapsulate the merging processing result in a preset instruction format to obtain the merged instruction.

[0073] Optionally, the instruction merging module is further configured to:

[0074] respectively acquire the to-be-accessed data amount corresponding to each to-be-merged instruction;

[0075] respectively add the to-be-accessed data amount corresponding to each to-be-merged instruction into the merging processing result.

[0076] According to a third aspect of the embodiments of the present disclosure, a non-transitory computer-readable storage medium is provided, which stores a computer program. The program is executed by a processor to implement the steps of the data access method according to any one of the first aspect.

[0077] According to a fourth aspect of the embodiments of the present disclosure, a data access apparatus is provided, which comprises:

[0078] a processor;

[0079] a memory for storing processor-executable instructions;

[0080] The processor is configured to:

[0081] acquire a plurality of to-be-processed instructions; each to-be-processed instruction comprises a to-be-accessed address;

[0082] determine to-be-merged instructions from the plurality of to-be-processed instructions, and perform merging processing on the to-be-merged instructions to obtain a merged instruction;

[0083] perform data access according to the to-be-accessed address corresponding to the merged instruction.

[0084] According to a fifth aspect of the embodiments of the present disclosure, a computer program product is provided, which comprises a computer program. The computer program is executed by a processor to implement the steps of the data access method according to any one of the first aspect.

[0085] The technical solutions provided by the embodiments of the present disclosure can have the following beneficial effects: in the case of obtaining a plurality of to-be-processed instructions, to-be-merged instructions are determined from the plurality of to-be-processed instructions, that is, at least two to-be-processed instructions that can be merged are determined, and the determined to-be-merged instructions are merged to obtain a merged instruction, thereby reducing the number of instructions and the overhead of the instructions. Data access is performed according to the to-be-accessed address corresponding to the merged instruction, so that a plurality of to-be-accessed addresses can be accessed based on one instruction, that is, a plurality of to-be-processed instructions can be processed concurrently, thereby improving the efficiency of instruction processing and effectively improving the performance of the electronic device.

[0086] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0087] The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of the present disclosure.

[0088] Figure 1 is a schematic diagram of a file layout according to an example embodiment of the present disclosure;

[0089] Figure 2 is a flowchart of a data access method according to an example embodiment of the present disclosure;

[0090] Figure 3 is a schematic diagram of a sequential read-write process according to an example embodiment of the present disclosure;

[0091] Figure 4 is a flowchart of another data access method according to an example embodiment of the present disclosure;

[0092] Figure 5 is a schematic diagram of a random read-write process according to an example embodiment of the present disclosure;

[0093] Figure 6 is a schematic diagram of another random read-write process according to an example embodiment of the present disclosure;

[0094] Figure 7 is a block diagram of a data access device according to an example embodiment of the present disclosure;

[0095] Figure 8 is a schematic diagram of a structure for a data access device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0096] The detailed description set forth below represents the presently preferred example embodiments of the present disclosure. As these embodiments are described in relation to the various drawings, it should be appreciated that the embodiments can be implemented in any number of different system configurations, environments, and applications. It should also be appreciated that the terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting. The use of the terms "a" and "an" and "the" herein is intended to include the plural, unless the context clearly indicates otherwise. It should also be appreciated that the use of the singular is also not intended to exclude the plural and vice versa, unless the context clearly indicates otherwise.

[0097] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0098] It should be understood that, although the terms first, second, third, etc. can be employed in this disclosure to describe various information, the information should not be limited to these terms. These terms are only used to differentiate one piece of information from another piece of information of the same type. For example, without departing from the scope of this disclosure, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information. Depending on the context, the word "if' as used herein can be interpreted as "when" or "upon" or "in response to determining".

[0099] In the prior art, a to-be-processed instruction generated by a process on an electronic device is obtained, and the to-be-processed instruction is sent to a memory based on a JEDEC protocol, and the memory processes the to-be-processed instruction, that is, accesses a to-be-accessed address of the to-be-processed instruction.

[0100] The memory based on the JEDEC protocol, that is, the storage chip is accessed in units of blocks. As shown in Figure 1 The storage unit of data in the file system (for example, F2FS (Flash Friendly File System)) of the electronic device is 4 KB, the size of file 1 is 24 KB, and the data of file 1 can be placed at the positions of LBA1 to LBA6, that is, addresses 1 to 6.

[0101] Optionally, the Nand flash memory based on the JEDEC protocol includes an EMMC (Embedded Multi MediaCard) storage chip and a UFS (Universal Flash Storage) storage chip.

[0102] However, when the number of to-be-processed instructions is multiple, the to-be-processed instructions need to be sent to the memory based on the JEDEC protocol one by one, which leads to an increase in instruction overhead, that is, an increase in resources required for sending the related instructions to the memory, and the memory based on the JEDEC protocol can only process the to-be-processed instructions one by one, which reduces the efficiency of instruction processing, thereby affecting the performance of the electronic device.

[0103] Therefore, in view of the above problems, the embodiments of the present disclosure propose a data access method. After obtaining multiple to-be-processed instructions, the to-be-processed instructions are merged to obtain a merged instruction, the merged instruction including to-be-accessed addresses of the multiple to-be-processed instructions. The merged instruction is sent to a memory based on a JEDEC protocol, reducing the instruction overhead. The memory based on the JEDEC protocol accesses the multiple to-be-accessed addresses in the merged instruction, realizing concurrent processing of the to-be-processed instructions, improving the efficiency of instruction processing, and thereby improving the performance of the electronic device, that is, improving the overall IO (Input / Output) performance of the system.

[0104] AsFigure 2 As shown, Figure 2 FIG. 2 is a flow chart of a data access method according to an example embodiment of the present disclosure. The method is applied to an electronic device, and in particular, the method is applied to a processor of the electronic device. The method includes the following steps:

[0105] S201, obtaining a plurality of to-be-processed instructions. Each to-be-processed instruction includes a to-be-accessed address.

[0106] S202, determining to-be-merged instructions in the plurality of to-be-processed instructions, and performing merging processing on the to-be-merged instructions to obtain a merged instruction.

[0107] In the embodiment of the present disclosure, the electronic device supports multi-task parallel processing. During the running process, various data read-write operation requests, i.e., to-be-processed instructions, are generated by each process of the electronic device. After obtaining the to-be-processed instructions generated by the process, i.e., the plurality of to-be-processed instructions, to-be-processed instructions that can be merged are determined from the plurality of to-be-processed instructions, i.e., at least two to-be-processed instructions are taken as to-be-merged instructions, and merging processing is performed on the to-be-merged instructions, i.e., a plurality of instructions are merged into one instruction, and the instruction obtained by merging is taken as a merged instruction. The merged instruction includes a plurality of to-be-accessed addresses, and the plurality of to-be-accessed addresses include to-be-accessed addresses of each to-be-merged instruction.

[0108] Each to-be-processed instruction includes a to-be-accessed address, i.e., each to-be-processed instruction has a corresponding to-be-accessed address. The to-be-accessed address represents a data address to be accessed, i.e., an address to be subjected to data read-write.

[0109] Optionally, the to-be-accessed address is a logical address.

[0110] S203, performing data access according to the to-be-accessed address corresponding to the merged instruction.

[0111] In the embodiment, data access is performed based on the to-be-accessed addresses of each to-be-merged instruction in the merged instruction, i.e., the to-be-accessed addresses of each to-be-merged instruction in the merged instruction are accessed to perform corresponding data read-write operations. Thus, a single instruction can be used to access the to-be-accessed addresses of a plurality of to-be-processed instructions, and a plurality of instructions are not required to access a plurality of to-be-accessed addresses. Concurrent processing of instructions is achieved, and the efficiency of data access is improved.

[0112] Optionally, when data access is performed based on the merged instruction, the memory can be used to perform data access, i.e., the merged instruction is sent to a target memory, so that the target memory performs data access based on the to-be-accessed addresses of each to-be-merged instruction in the merged instruction.

[0113] ​​Specifically, after obtaining the merge instruction, the merge instruction is sent to the target memory. The target memory executes the merge instruction, i.e., parses the merge instruction to obtain a plurality of to-be-accessed addresses in the merge instruction, and accesses the plurality of to-be-accessed addresses in the merge instruction to perform corresponding data read / write operations, thereby improving the efficiency of instruction processing, fully utilizing the concurrent processing capability of the target memory, and improving the concurrency of the target memory.

[0114] The target memory includes a memory based on a JEDEC protocol, such as a Nand flash. Specifically, the target memory is an EMMC (Embedded Multi Media Card) memory chip, a UFS (Universal Flash Storage) memory chip, or the like.

[0115] Optionally, the electronic device includes a mobile terminal (e.g., a mobile phone, a tablet computer, or the like), a terminal device (e.g., a computer, a server), or the like, and a product including the target memory.

[0116] It can be understood that the access mode of the target memory includes random access (i.e., random read / write). Random read / write refers to discrete random address access to the memory. Taking the target memory as a Nand flash memory as an example, after obtaining the to-be-processed instruction generated by the process, the to-be-processed instruction is cached. In a case where the to-be-accessed address of the cached to-be-processed instruction is not an adjacent continuous address, it is indicated that the random access mode is used for access, and a multi-command mode is used, i.e., the to-be-processed instruction is sent to the Nand flash memory respectively, i.e., the Nand flash memory is accessed respectively, the overhead of the instruction is increased, and the Nand flash memory can only process one to-be-processed instruction at a time, which cannot fully utilize the concurrent processing capability of the Nand flash memory, and affects the throughput of system random access. For example, as shown in Figure 3 Process A generates instruction 1, and the to-be-accessed address in the instruction 1 is address 1 (i.e., address 1 in Figure 1 Process B generates instruction 2, and the to-be-accessed address in the instruction 2 is address 3 (i.e., address 3 in Figure 1 Process C generates instruction 3, and the to-be-accessed address in the instruction 3 is address 5 (i.e., address 5 in Figure 1 Processes A, B, and C access Figure 1data of the logical address 1, 3 and 5 of file 1 in the file system. Since the address 1, the address 3 and the address 5 are not continuous, the instruction 1, the instruction 2 and the instruction 3 cannot be combined, and can only be sent to the Nand flash memory respectively. The present disclosure combines the instructions to be processed which are not continuous in the address to be accessed, that is, combines a plurality of instructions to be processed to obtain one instruction, that is, obtains a combined instruction, so as to reduce the overhead of the instruction. The combined instruction is sent to the Nand flash memory, so that the Nand flash memory can access a plurality of addresses to be accessed at a time, and the efficiency of the instruction processing is improved.

[0117] As described above, in the case of obtaining a plurality of instructions to be processed, the instructions to be combined in the plurality of instructions to be processed are determined, that is, at least two instructions to be processed which can be combined are determined, and the determined instructions to be combined are combined to obtain a combined instruction, so as to reduce the number of instructions and the overhead of the instruction. According to the address to be accessed corresponding to the combined instruction, the data is accessed, so that a plurality of addresses to be accessed of the instructions to be processed can be accessed based on one instruction, the concurrent processing of the instruction is realized, the efficiency of the instruction processing is improved, and the performance of the electronic device is effectively improved.

[0118] As shown in Figure 4 , Figure 4 is another data access method flow chart according to an exemplary embodiment of the present disclosure. In Figure 2 the embodiment, in the case of random access, the instructions which are not continuous in the address to be accessed can be combined. The process will be described in combination with a specific embodiment as shown in Figure 4 .

[0119] S401, a plurality of instructions to be processed are obtained. Each instruction to be processed includes an address to be accessed.

[0120] S402, a first instruction is obtained. The first instruction is any instruction in the instructions to be processed.

[0121] In the embodiment of the present disclosure, one instruction to be processed is selected from the obtained instructions to be processed, and the selected instruction to be processed is taken as the first instruction.

[0122] Optionally, in order to improve the efficiency of data access, after obtaining the to-be-processed instruction, the to-be-processed instruction can be saved to a preset instruction queue for instruction caching, thereby facilitating the merging of the to-be-processed instruction. A to-be-processed instruction in the preset instruction queue is selected as the first instruction, that is, the first instruction is determined. The process of determining the first instruction is specifically as follows: the to-be-processed instruction is saved to the preset instruction queue. The to-be-processed instruction in the preset instruction queue that meets at least one of the following conditions is selected as the first instruction: the second time length corresponding to the to-be-processed instruction is greater than the second time threshold. The second time length indicates the storage time length of the to-be-processed instruction in the preset instruction queue. The to-be-processed instruction is located at a set position in the preset instruction queue. The set position is a head position or a tail position.

[0123] Optionally, the to-be-processed instructions in the preset instruction queue can be arranged based on a preset address sorting rule. The preset address sorting rule includes an address sorting rule from large to small (that is, the to-be-accessed addresses of the to-be-accessed instructions in the preset instruction queue are arranged from large to small), an address sorting rule from small to large (that is, the to-be-accessed addresses of the to-be-accessed instructions in the preset instruction queue are arranged from small to large), and the like.

[0124] Optionally, when the number of to-be-processed instructions meeting the condition is multiple, the to-be-processed instruction with the longest second time length can be selected as the first instruction. The second time length indicates the storage time length of the to-be-processed instruction in the preset instruction queue. The logical address is sequentially named, for example, 1000 storage blocks in a target memory are named as 1-1000, and correspondingly, the logical address is 1-1000. Since the to-be-accessed address is a logical address, the to-be-accessed address can be sorted according to the size of the to-be-accessed address, thereby sorting the to-be-processed instruction based on the order of the to-be-accessed address.

[0125] Optionally, the set position can also be other positions, which are not limited herein.

[0126] Optionally, the condition used to determine the first instruction from the preset instruction queue can also include other conditions, for example, the second time length corresponding to the to-be-processed instruction is the longest, that is, the to-be-processed instruction saved in the preset instruction queue for the longest time can be selected as the first instruction.

[0127] Optionally, after obtaining the to-be-processed instruction, the to-be-processed instruction can be processed first (for example, judging whether the instruction format is standard, whether the memory is idle, and the like), and the processed to-be-processed instruction is saved to the preset instruction queue.

[0128] S403, traverse the to-be-processed instruction other than the first instruction to obtain a second instruction. The to-be-accessed address of the second instruction is indirectly continuous with the to-be-accessed address of the first instruction, and the to-be-accessed address of the second instruction is not continuous with the to-be-accessed address of the first instruction through the to-be-accessed address of another to-be-processed instruction.

[0129] In the embodiments of the present disclosure, the to-be-processed instructions other than the first instruction in the preset instruction queue are traversed to determine whether the second instruction corresponding to the address discontinuity of the first instruction exists in the to-be-processed instructions other than the first instruction, so that when the second instruction is determined to exist, the to-be-merged instruction is determined based on the second instruction, that is, the first instruction and the second instruction are determined as the to-be-merged instruction. For example, the first instruction is an instruction at the head position in the preset instruction queue, and the instructions at other positions in the preset instruction queue are traversed to determine whether the second instruction exists in the instructions at the other positions in the preset instruction queue.

[0130] The to-be-accessed address of the second instruction is indirectly continuous with the to-be-accessed address of the first instruction, and the to-be-accessed address of the second instruction is not continuous with the to-be-accessed address of the first instruction through the to-be-accessed address of another to-be-processed instruction.

[0131] The indirectly continuous indicates that the to-be-accessed address of the second instruction is continuous with the to-be-accessed address of the first instruction through another logical address, that is, the to-be-accessed address of the second instruction is discontinuous with the to-be-accessed address of the first instruction. For example, the to-be-accessed address of the currently traversed to-be-processed instruction is 4, the to-be-accessed address of the first instruction is 1, and the to-be-accessed address of the currently traversed to-be-processed instruction needs to be continuous with the to-be-accessed address of the first instruction through another logical address (that is, logical addresses 2 and 3), so it is determined that the to-be-accessed address of the currently traversed to-be-processed instruction is indirectly continuous with the to-be-accessed address of the first instruction.

[0132] If the to-be-accessed address of the currently traversed to-be-processed instruction is 2 and the to-be-accessed address of the first instruction is 1, it is determined that the to-be-accessed address of the currently traversed to-be-processed instruction is continuous with the to-be-accessed address of the first instruction.

[0133] In the embodiments of the present disclosure, in the process of traversing the to-be-processed instructions other than the first instruction, it is determined whether the to-be-accessed address of the currently traversed to-be-processed instruction is indirectly continuous with the to-be-accessed address of the first instruction. If the to-be-accessed address of the currently traversed to-be-processed instruction is not indirectly continuous with the to-be-accessed address of the first instruction, it indicates that the to-be-accessed address of the currently traversed to-be-processed instruction is continuous with the to-be-accessed address of the first instruction, and it is determined that the currently traversed to-be-processed instruction is the sequentially accessed instruction corresponding to the first instruction, i.e., not the second instruction. If the to-be-accessed address of the currently traversed to-be-processed instruction is indirectly continuous with the to-be-accessed address of the first instruction, it is determined whether the to-be-accessed address of the currently traversed to-be-processed instruction is continuous with the to-be-accessed address of the first instruction through the to-be-accessed addresses of other to-be-processed instructions. If the to-be-accessed address of the currently traversed to-be-processed instruction is continuous with the to-be-accessed address of the first instruction through the to-be-accessed addresses of other to-be-processed instructions, it is determined that the currently traversed to-be-processed instruction is not the second instruction. If the to-be-accessed address of the currently traversed to-be-processed instruction is not continuous with the to-be-accessed address of the first instruction through the to-be-accessed addresses of other to-be-processed instructions, it is determined that the currently traversed to-be-processed instruction is the second instruction. For example, the to-be-processed instructions include instruction 1, instruction 2 and instruction 3. The to-be-accessed address of instruction 1 is 1, the to-be-accessed address of instruction 2 is 2, and the to-be-accessed address of instruction 3 is 3. Instruction 3 is the currently traversed to-be-processed instruction, and instruction 1 is the first instruction. It is determined that the to-be-accessed address of instruction 3 is not continuous with the to-be-accessed address of instruction 1, i.e., indirectly continuous, and it is further determined whether the to-be-accessed address of instruction 3 is continuous with the to-be-accessed address of instruction 1 through the to-be-accessed addresses of other to-be-processed instructions. Since the to-be-accessed address of instruction 3 is continuous with the to-be-accessed address of instruction 1 through the to-be-accessed address of instruction 2, it is determined that instruction 3 is not the second instruction.

[0134] Optionally, when the to-be-processed instructions are arranged based on the preset address ordering rule, in the process of traversing the to-be-processed instructions other than the first instruction, it is determined whether the to-be-accessed address of the currently traversed to-be-processed instruction is continuous with the to-be-accessed address of the first instruction. If the to-be-accessed address of the currently traversed to-be-processed instruction is continuous with the to-be-accessed address of the first instruction, it is determined that the currently traversed to-be-processed instruction is the sequentially accessed instruction corresponding to the first instruction, i.e., is not the second instruction. If the to-be-accessed address of the currently traversed to-be-processed instruction is not continuous with the to-be-accessed address of the first instruction, it is further determined whether the to-be-accessed address of the currently traversed to-be-processed instruction is continuous with the to-be-accessed address of the last traversed to-be-processed instruction. If the to-be-accessed address of the currently traversed to-be-processed instruction is continuous with the to-be-accessed address of the last traversed to-be-processed instruction, it is determined that the currently traversed to-be-processed instruction is the sequentially accessed instruction corresponding to the first instruction, i.e., is not the second instruction, in the case that the to-be-accessed address of the last traversed to-be-processed instruction is continuous with the to-be-accessed address of the first instruction or the to-be-accessed address of the traversed to-be-processed instruction is continuous with the to-be-accessed address of the first instruction. If the to-be-accessed address of the currently traversed to-be-processed instruction is not continuous with the to-be-accessed address of the last traversed to-be-processed instruction, it is determined that the currently traversed to-be-processed instruction is the second instruction.

[0135] Optionally, the access mode corresponding to the target memory further includes sequential access (i.e., sequential read and write). Sequential access refers to continuous address access to the memory, and random read and write refer to discrete random address access to the memory. When it is determined that the to-be-processed instructions other than the first instruction in the preset instruction queue are not the second instruction, it is indicated that the to-be-processed instructions other than the first instruction are sequentially accessed instructions of the first instruction, i.e., it is indicated that the to-be-accessed addresses of the to-be-processed instructions other than the first instruction can be sequentially accessed with the to-be-accessed address of the first instruction. Therefore, the first instruction and the to-be-processed instructions with to-be-accessed addresses continuous with the to-be-accessed address of the first instruction can be taken as to-be-merged instructions, and the to-be-merged instructions can be merged to obtain a merged instruction according to the sequential access rule. Data is accessed according to the to-be-accessed addresses of the to-be-merged instructions in the merged instruction.

[0136] The sequential access rule can be defined according to actual needs, for example, all or part of the to-be-processed instructions other than the first instruction are taken as to-be-merged instructions.

[0137] Specifically, in order to improve the efficiency of data read-write access, the to-be-processed instructions generated by each process can be cached. Taking a target memory as a Nand flash memory as an example, in the case that the to-be-accessed addresses of the cached to-be-processed instructions are adjacent continuous addresses, it is indicated that the sequential access mode can be used for access, and then the continuous adjacent addresses, i.e., the to-be-processed instructions, can be merged to enable the Nand flash memory to perform sequential access based on the merged to-be-processed instructions, i.e., the merged addresses, thereby maximizing the use of a small amount of instructions, ensuring that the addresses accessed by each instruction and the preceding and subsequent instructions are continuous, improving the concurrency of memory data processing, and reducing instruction overhead. For example, as shown in FIG. 8, process A generates instruction 1, the to-be-accessed address of the instruction 1 is address 1 (i.e., address 1 in FIG. 8), process B generates instruction 2, the to-be-accessed address of the instruction 2 is address 2 (i.e., address 2 in FIG. 8), and process C generates instruction 3, the to-be-accessed address of the instruction 3 is address 3 (i.e., address 3 in FIG. 8). Processes A, B, and C access the data of the logical addresses 1, 2, and 3 of the file 1 in FIG. 8. Since the address 1, the address 2, and the address 3 are adjacent and continuous, the instruction 1, the instruction 2, and the instruction 3 can be merged to obtain an instruction including the address 1, the address 2, and the address 3, i.e., a request A, and the request A is sent to the Nand flash memory to enable the Nand flash memory to perform sequential access based on the request A. Figure 5 Figure 1 Figure 1 Figure 1 Figure 1

[0138] S404, in response to the second instruction and the first instruction satisfying the first preset merging condition, determining the second instruction and the first instruction as to-be-merged instructions.

[0139] In the embodiment of the present disclosure, when it is determined that the currently traversed to-be-processed instruction is the second instruction, it is further judged whether the second instruction is a to-be-merged instruction, i.e., whether the second instruction and the first instruction satisfy the first preset merging condition. In the case that the second instruction and the first instruction satisfy the first preset merging condition, it is indicated that the second instruction, i.e., the currently traversed to-be-processed instruction, can be merged with the first instruction, i.e., concurrent access can be performed, and then the second instruction and the first instruction are taken as to-be-merged instructions, and the to-be-processed instructions other than the first instruction are further traversed, i.e., the to-be-processed instructions other than the next first instruction are further traversed, to determine whether the next to-be-processed instruction is the second instruction.

[0140] In response to the second instruction and the first instruction not satisfying the first preset merging condition, the to-be-processed instructions other than the first instruction are further traversed to determine whether the next to-be-processed instruction is the second instruction.

[0141] ​​​​​Optionally, before continuing to traverse the to-be-processed instructions other than the first instruction, it is needed to determine whether the time of caching the first instruction exceeds the time that the first instruction can wait for execution, that is, to obtain the first time length and obtain the first time threshold corresponding to the first instruction. The first time length indicates the time length from determining the first instruction to the current time. In response to the first time length being less than the first time threshold, it is indicated that the time that the instruction can wait for execution has not been exceeded, that is, the time that the instruction can be cached has not been exceeded, and thus the traversal of the to-be-processed instructions other than the first instruction is continued. In response to the first time length being greater than or equal to the first time threshold, it is indicated that the time of caching the instruction has been exceeded, that is, the time that the instruction can wait for execution has been exceeded, and thus the traversal of the to-be-processed instructions other than the first instruction is stopped, and the to-be-merged instructions determined in the traversal process are merged.

[0142] The first time threshold indicates an upper limit of the instruction execution waiting time. The first time threshold can be set based on the real-time requirement of the related application corresponding to the process, and indicates the upper limit of the instruction execution waiting time, that is, indicates the longest time that the instruction can be cached.

[0143] Specifically, because different processes have different real-time requirements, the first time threshold can be determined according to the process corresponding to the first instruction, that is, in the case of obtaining the first time threshold corresponding to the first instruction, the target process corresponding to the first instruction, that is, the process that generates the first instruction, is obtained, and the process type (for example, a video application type, a notepad application type) corresponding to the target process is determined. The time threshold corresponding to the process type is taken as the first time threshold corresponding to the first instruction.

[0144] Optionally, in response to the second instruction and the first instruction satisfying the first preset merging condition, the second instruction and the first instruction are determined as to-be-merged instructions, including:

[0145] The storage interval is obtained, and / or the current total access data amount is obtained. The storage interval indicates the distance between the to-be-accessed address of the first instruction and the to-be-accessed address of the second instruction. The current total access data amount indicates the sum of the to-be-accessed data amounts corresponding to all the to-be-merged instructions that have been determined.

[0146] In a case where the storage interval is less than a first preset threshold, and / or the current total access data amount is less than a second preset threshold, the second instruction and the first instruction are determined as to-be-merged instructions.

[0147] For example, the first preset merging condition includes that the storage interval is less than a first preset threshold. The storage interval is obtained. It is determined whether the storage interval is less than the first preset threshold. In response to the storage interval being less than the first preset threshold, it is indicated that the current traversed to-be-processed instruction can be accessed concurrently, and it is determined that the second instruction and the first instruction are to-be-merged instructions. In response to the storage interval being greater than or equal to the first preset threshold, it is indicated that the current traversed to-be-processed instruction cannot be accessed concurrently, and it is determined that the second instruction is not a to-be-merged instruction and cannot be merged with the first instruction.

[0148] For example, the first preset merging condition is that the current total access data amount is less than a second preset threshold. The current total access data amount is obtained. It is determined whether the current total access data amount is less than the second preset threshold. In response to the current total access data amount being less than the second preset threshold, it is indicated that the current traversed to-be-processed instruction can be accessed concurrently, and it is determined that the second instruction and the first instruction are to-be-merged instructions. In response to the current total access data amount being greater than or equal to the second preset threshold, it is indicated that the current traversed to-be-processed instruction cannot be accessed concurrently, and it is determined that the second instruction is not a to-be-merged instruction.

[0149] For example, the first preset merging condition includes that the storage interval is less than a first preset threshold and the current total access data amount is less than a second preset threshold. The storage interval and the current total access data amount are obtained. It is determined whether the storage interval is less than the first preset threshold and whether the current total access data amount is less than the second preset threshold. In response to the storage interval being less than the first preset threshold and the current total access data amount being less than the second preset threshold, it is indicated that the current traversed to-be-processed instruction can be accessed concurrently, and it is determined that the second instruction is obtained, and it is determined that the second instruction and the first instruction are to-be-merged instructions. In response to the storage interval being greater than or equal to the first preset threshold and / or the current total access data amount being greater than or equal to the second preset threshold, it is indicated that the current traversed to-be-processed instruction cannot be accessed concurrently, and it is determined that the second instruction is not a to-be-merged instruction.

[0150] The first preset threshold indicates an upper limit of a distance of a merging address, and the merging address represents a gap between two logical addresses that are merged. The first preset threshold is determined based on a cache size in the memory, so as to try to ensure that data accessed each time can be processed by the target memory at one time. Specifically, the first preset threshold can be provided by a supplier corresponding to the target memory, for example, the first preset threshold is 300M, indicating that the target memory can cache data of 300M at one time, so that the corresponding address can be accessed from the cached data.

[0151] The second preset threshold indicates an upper limit of a data amount of a single access, that is, indicates a maximum data amount of a single concurrent access. The second preset threshold needs to refer to hardware support of the target memory, and can be provided by a supplier corresponding to the target memory, for example, the second preset threshold is 128K.

[0152] Optionally, before obtaining the storage interval, the storage interval needs to be calculated, and the calculation process of the storage interval is as follows: obtaining the difference between the to-be-accessed address of the second instruction and the to-be-accessed address of the first instruction. The to-be-accessed address is a logical address. A preset storage unit size is obtained. The storage interval is obtained according to the difference and the preset storage unit size, that is, the product of the difference and the preset storage unit size. For example, the to-be-accessed address of the second instruction is 3, the to-be-accessed address of the first instruction is 1, and the preset storage unit size is 4 KB, and then the storage interval is (3-1)*4 KB = 8 KB.

[0153] In this embodiment, the target storage is accessed in units of blocks, that is, storage blocks, and the preset storage unit size is the size of a storage block, for example, 4 KB.

[0154] Optionally, before obtaining the total current access data amount, the total current access data amount needs to be calculated, and the calculation process of the total current access data amount is as follows: calculating the sum of the to-be-accessed data amounts corresponding to the determined to-be-merged instructions (that is, the first instruction and the second instruction), to obtain the total current access data amount.

[0155] In this embodiment, the to-be-accessed data amount represents the address length corresponding to the to-be-accessed address, which can represent the size of the data to be accessed. For example, 24 KB of data is written starting from the to-be-accessed address, and the 24 KB can be the to-be-accessed data amount. Of course, the to-be-accessed data amount can also represent an address offset, and the to-be-accessed data amount can be used to determine the amount of data to be accessed.

[0156] In this embodiment, the to-be-accessed data amount can be obtained from the to-be-processed instruction, that is, the to-be-processed instruction includes the to-be-accessed data amount, or the to-be-accessed data amount can be obtained independently, which is not limited herein.

[0157] For example, the first instruction is instruction 1, the to-be-processed instruction other than the first instruction includes instruction 2 and instruction 3, after determining that instruction 2 is a to-be-merged instruction, it is determined whether instruction 3 is a second instruction. In the case that instruction 3 is a second instruction, the storage interval is calculated, and the total current access data amount is calculated. In the calculation of the total current access data amount, the sum of the to-be-accessed data amounts corresponding to the determined to-be-merged instructions is calculated, that is, the sum of the to-be-accessed data amount corresponding to instruction 2 and the to-be-accessed data amount corresponding to instruction 1 is calculated, to obtain the total current access data amount.

[0158] Optionally, in the case of merging the first instruction and the second instruction that meet the first preset merging condition, the first instruction and the second instruction that meet the first preset merging condition can be merged, or the sequentially accessed instructions between the first instruction and the second instruction that meet the first preset merging condition can be merged. Correspondingly, the determined to-be-merged instructions also include the merged sequentially accessed instructions.

[0159] For example, the first instruction is instruction 1, the to-be-processed instructions other than the first instruction include instruction 2 and instruction 3, the to-be-accessed address in instruction 1 is address 1 in instruction 1, the to-be-accessed address in instruction 2 is address 2 in instruction 2, and the to-be-accessed address in instruction 3 is address 4 in instruction 3. Figure 1 For example, the first instruction is instruction 1, the to-be-processed instructions other than the first instruction include instruction 2 and instruction 3, the to-be-accessed address in instruction 1 is address 1 in instruction 1, the to-be-accessed address in instruction 2 is address 2 in instruction 2, and the to-be-accessed address in instruction 3 is address 4 in instruction 3. Figure 1 For example, the first instruction is instruction 1, the to-be-processed instructions other than the first instruction include instruction 2 and instruction 3, the to-be-accessed address in instruction 1 is address 1 in instruction 1, the to-be-accessed address in instruction 2 is address 2 in instruction 2, and the to-be-accessed address in instruction 3 is address 4 in instruction 3. Figure 1 For example, the first instruction is instruction 1, the to-be-processed instructions other than the first instruction include instruction 2 and instruction 3, the to-be-accessed address in instruction 1 is address 1 in instruction 1, the to-be-accessed address in instruction 2 is address 2 in instruction 2, and the to-be-accessed address in instruction 3 is address 4 in instruction 3.

[0160] Optionally, in a case where the current total data amount is greater than or equal to the second preset threshold, it is indicated that the data amount required to be accessed by the target memory based on the determined to-be-merged instructions in a single access has reached an upper limit, and therefore, there is no need to merge instructions, that is, there is no need to determine to-be-merged instructions, and therefore, the traversal of the to-be-processed instructions other than the first instruction is stopped.

[0161] Optionally, in the process of determining the to-be-merged instructions from the to-be-processed instructions, the first instruction can also be obtained. The first instruction is any instruction in the to-be-processed instructions. The to-be-processed instructions other than the first instruction are traversed. It is determined whether the currently traversed to-be-processed instruction and the first instruction satisfy a second preset merging condition. In response to the currently traversed to-be-processed instruction and the first instruction satisfying the second preset merging condition, the first instruction and the currently traversed to-be-processed instruction are determined as the to-be-merged instructions.

[0162] Optionally, in the process of determining the to-be-merged instructions from the to-be-processed instructions, the first instruction can also be obtained. The first instruction is any instruction in the to-be-processed instructions. The to-be-processed instructions other than the first instruction are traversed. It is determined whether the currently traversed to-be-processed instruction and the first instruction satisfy a second preset merging condition. In response to the currently traversed to-be-processed instruction and the first instruction satisfying the second preset merging condition, the first instruction and the currently traversed to-be-processed instruction are determined as the to-be-merged instructions.

[0163] S405, the to-be-merged instructions are merged to obtain merged instructions.

[0164] In the embodiments of the present disclosure, the merged processing result is generated according to the to-be-accessed addresses of the to-be-merged instructions, the merged processing result is packaged in a set instruction format to obtain the merged instructions.

[0165] In the embodiments of the present disclosure, after the instructions to be merged are determined, a merging processing result is generated according to the to-be-accessed addresses of the respective instructions to be merged, the merging processing result including the to-be-accessed addresses of the respective instructions to be merged. The merging processing result is encapsulated based on a set instruction format, and a merging instruction is obtained, so as to realize the merging of the instructions.

[0166] In the process of generating the merging processing result according to the to-be-accessed addresses of the respective instructions to be merged, the merging processing result including the to-be-accessed addresses of the respective instructions to be merged can be generated based on a preset structure type.

[0167] The preset structure type includes a linked list structure type, a tree structure type, an array structure type, and the like, and can be set according to actual requirements, which is not limited herein.

[0168] Optionally, the set instruction format is a format that can be recognized by the target memory, for example, a customized Write Buffer command format defined in JDECE.

[0169] Optionally, the to-be-accessed data amounts corresponding to the instructions to be merged can also be saved into the merging processing result, that is, the to-be-accessed data amounts corresponding to the respective instructions to be merged are respectively obtained. The to-be-accessed data amounts corresponding to the respective instructions to be merged are respectively added to the merging processing result, that is, the merging processing result includes the to-be-accessed data amounts and the to-be-accessed addresses of the instructions to be merged.

[0170] For example, as shown in FIG. 1, processes A, B and C need to access data in logical addresses 1, 3 and 5 of a file, and instructions 1, 2 and 3 are generated. Figure 6 The to-be-accessed address of the instruction 1 is address 1, and the to-be-accessed data amount corresponding to the instruction 1 is the length of the address 1. The to-be-accessed address of the instruction 2 is address 3, and the to-be-accessed data amount corresponding to the instruction 2 is the length of the address 3. The to-be-accessed address of the instruction 3 is address 5, and the to-be-accessed data amount corresponding to the instruction 3 is the length of the address 5. The instruction 1 is the first instruction, the instructions 2 and 3 are the second instructions, and it is determined that the instructions 2 and 3 are the instructions to be merged. Therefore, the address 1 and the length of the address 1 corresponding to the instruction 1, the address 3 and the length of the address 3 corresponding to the instruction 2, and the address 5 and the length of the address 5 corresponding to the instruction 3 are added to the list A, so as to realize the merging of the instructions.

[0171] S406, data is accessed according to the to-be-accessed address of the merging instruction.

[0172] In the embodiments of the present disclosure, after the merging instruction is obtained, the merging instruction is sent to the target memory, so that the target memory performs data access based on the to-be-accessed addresses of the respective instructions to be merged in the merging instruction.

[0173] In the embodiments of the present disclosure, in a random read-write scenario, that is, in a case where it is determined that a second instruction exists in addition to the first instruction, the first instruction is processed in combination with the second instruction involving discrete access to obtain a combined instruction, and the combined instruction is stored to a target storage device, thereby reducing the number of instructions sent to the target storage device, reducing the instruction overhead of random read-write, and the target storage device can access based on multiple access addresses in the combined instruction, improving the concurrency of the target storage device, and thereby improving the throughput of system random read-write, that is, improving the overall IO performance of the system.

[0174] In the embodiments of the present disclosure, in a case where it is determined that a second instruction does not exist in addition to the first instruction, that is, in a sequential read-write scenario, the instruction that can be sequentially read and written, that is, the to-be-processed instruction, is combined to obtain a combined instruction, and the combined instruction is sent to the target storage device, thereby reducing the number of instructions sent to the target storage device, reducing the instruction overhead of sequential read-write, and the target storage device can sequentially access based on multiple access addresses in the combined instruction, improving the concurrency of the storage device processing data, reducing the instruction overhead of the system, and effectively improving the overall IO performance of the system.

[0175] In the embodiments of the present disclosure, after obtaining the to-be-accessed instruction, the to-be-accessed instruction is saved to a preset instruction queue, a to-be-accessed instruction at a head position in the preset instruction queue is taken as a first instruction, and the remaining to-be-accessed instructions in the preset instruction queue are traversed backward. It is judged whether a second instruction with discontinuous to-be-accessed addresses exists in the remaining to-be-accessed instructions. If it exists, it indicates that random access is needed, and the second instruction and the first instruction are combined to obtain a corresponding combined instruction, thereby reducing the number of instructions and reducing the overhead of the instructions. The combined instruction is stored to the Nand flash memory, so that the Nand flash memory can access each to-be-accessed address in the combined instruction at a time, implement concurrent processing of the instructions, improve the efficiency of instruction processing, and thereby effectively improve the throughput of random access, that is, improve the overall IO performance of the system.

[0176] For each of the foregoing method embodiments, in order to simply describe, it is expressed as a combination of a series of actions, but those skilled in the art should know that the present disclosure is not limited by the order of the described actions, because according to the present disclosure, certain steps can be performed in other orders or at the same time.

[0177] Secondly, those skilled in the art should know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily necessary for the present disclosure.

[0178] Corresponding to the foregoing application function implementation method embodiments, the present disclosure also provides application function implementation device and corresponding terminal embodiments.

[0179] Referring to Figure 7 According to a data access device block diagram shown in an example embodiment, the device can include:

[0180] An instruction obtaining module 710 is configured to obtain a plurality of to-be-processed instructions. Each to-be-processed instruction includes a to-be-accessed address.

[0181] An instruction merging module 720 is configured to determine to-be-merged instructions from the plurality of to-be-processed instructions, and perform merging processing on the to-be-merged instructions to obtain a merged instruction.

[0182] An instruction sending module 730 is configured to perform data access according to a to-be-accessed address corresponding to the merged instruction.

[0183] Optionally, the instruction merging module 720 is specifically configured to:

[0184] Obtain a first instruction. The first instruction is any instruction from the to-be-processed instructions.

[0185] Iterate through the to-be-processed instructions other than the first instruction to obtain a second instruction. The to-be-accessed address of the second instruction is indirectly continuous with the to-be-accessed address of the first instruction, and the to-be-accessed address of the second instruction is not continuous with the to-be-accessed address of the first instruction through the to-be-accessed addresses of other to-be-processed instructions.

[0186] In response to the second instruction and the first instruction satisfying a first preset merging condition, the second instruction and the first instruction are determined as to-be-merged instructions.

[0187] Optionally, the instruction merging module 720 is further configured to:

[0188] Obtain a storage interval and / or obtain a current total data amount accessed. The storage interval indicates a distance between the to-be-accessed address of the first instruction and the to-be-accessed address of the second instruction. The current total data amount accessed indicates a sum of to-be-accessed data amounts corresponding to all to-be-merged instructions.

[0189] In a case where the storage interval is less than a first preset threshold and / or the current total data amount accessed is less than a second preset threshold, the second instruction and the first instruction are determined as to-be-merged instructions.

[0190] Optionally, the instruction merging module 720 is further configured to:

[0191] Obtain a first time length and obtain a first time threshold corresponding to the first instruction. The first time length indicates a time length from a time point of determining the first instruction to a current time point.

[0192] In response to the first time length being less than the first time threshold, the iteration through the to-be-processed instructions other than the first instruction is continued.

[0193] In response to the first time length being greater than or equal to the first time threshold, the iteration of the to-be-processed instructions other than the first instruction is stopped.

[0194] Optionally, the instruction merging module 720 is further configured to:

[0195] In a case where the current total data access amount is greater than or equal to the second preset threshold, the iteration of the to-be-processed instructions other than the first instruction is stopped.

[0196] Optionally, the instruction merging module 720 is further configured to:

[0197] The difference between the to-be-accessed address of the second instruction and the to-be-accessed address of the first instruction is obtained. The to-be-accessed address is a logical address.

[0198] The preset storage unit size is obtained.

[0199] The storage interval is obtained according to the difference and the preset storage unit size.

[0200] Optionally, the instruction merging module 720 is specifically configured to:

[0201] The first instruction is obtained. The first instruction is any one of the to-be-processed instructions.

[0202] The to-be-processed instructions other than the first instruction are iterated.

[0203] In response to the to-be-processed instruction currently iterated and the first instruction satisfying a second preset merging condition, the first instruction and the to-be-processed instruction currently iterated are determined as to-be-merged instructions.

[0204] Optionally, the instruction merging module 720 is further configured to:

[0205] The to-be-processed instructions are saved into a preset instruction queue.

[0206] The to-be-processed instructions in the preset instruction queue that satisfy at least one of the following conditions are taken as the first instruction:

[0207] The second time length of the to-be-processed instruction is greater than a second time threshold. The second time length indicates a saving time length of the to-be-processed instruction in the preset instruction queue.

[0208] The to-be-processed instruction is in a set position in the preset instruction queue. The set position is a head position or a tail position.

[0209] Optionally, the instruction merging module 720 is specifically configured to:

[0210] The merging processing result is generated according to the to-be-accessed addresses of the to-be-merged instructions, and the merging processing result is encapsulated in a set instruction format to obtain a merged instruction.

[0211] Optionally, the instruction merging module 720 is further configured to:

[0212] respectively acquire the to-be-accessed data amount corresponding to each to-be-merged instruction.

[0213] respectively add the to-be-accessed data amount corresponding to each to-be-merged instruction into the merging processing result.

[0214] For the device embodiment, since it basically corresponds to the method embodiment, the related parts can be referred to the part of the method embodiment. The device embodiment described above is only illustrative, wherein the units described above as separate components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed to multiple network units. According to actual needs, part or all of the modules can be selected to achieve the purpose of the present disclosure. Those skilled in the art can understand and implement it without creative labor.

[0215] Correspondingly, in one aspect, the present embodiment provides a data access device, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to:

[0216] acquire a plurality of to-be-processed instructions. Each to-be-processed instruction includes a to-be-accessed address.

[0217] determine to-be-merged instructions in the plurality of to-be-processed instructions, and perform merging processing on the to-be-merged instructions to obtain a merged instruction.

[0218] perform data access according to the to-be-accessed address corresponding to the merged instruction.

[0219] Figure 8 is a structural schematic diagram of a data access device 1500 according to an example embodiment. For example, the device 800 can be an electronic device, which can specifically be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, a wearable device such as a smart watch, smart glasses, a smart bracelet, smart running shoes, etc.

[0220] Referring to Figure 8 , the device 800 can include one or more of the following components: a processing component 802, a memory 804, a power supply component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0221] The processing component 802 generally controls the overall operations of the device 800, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 802 can include one or more processors 820 to execute instructions delivered from the memory 804 to complete all or part of the steps of the methods described above. In addition, the processing component 802 can include one or more modules to facilitate the interaction between the processing component 802 and other components. For example, the processing component 802 can include a multimedia module to facilitate the interaction between the multimedia component 808 and the processing component 802.

[0222] The memory 804 is configured to store various types of data to support the operations of the device 800. Examples of these data include instructions for any application or method operating on the device 800, contact data, phonebook data, messages, pictures, videos, and the like. The memory 804 can be implemented by any type of volatile or non-volatile storage devices or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read only memory (EEPROM), erasable programmable read only memory (EPROM), programmable read only memory (PROM), read only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0223] The power component 806 provides power to the various components of the device 800. The power component 806 can include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the device 800.

[0224] The multimedia component 808 includes a screen providing an output interface between the device 800 and a user. In some embodiments, the screen can include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes the touch panel, the screen can be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense a touch, a slide, and a gesture on the touch panel. The touch sensor can not only sense a boundary of a touching or sliding action, but also detect duration and pressure related to the touching or sliding action. In some embodiments, the multimedia component 808 includes a front camera and / or a back camera. The front camera and / or the back camera can receive external multimedia data when the device 800 is in an operating mode, such as a shooting mode or a video mode. Each of the front and back cameras can be a fixed optical lens system or have a focal length and optical zoom capability.

[0225] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC) that is configured to receive an external audio signal when the device 800 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

[0226] The I / O interface 812 provides an interface between the processing component 802 and peripheral interface modules, which can be a keypad, a click wheel, buttons, and the like. The buttons can include, but are not limited to, a home button, a volume button, a start button, and a lock button.

[0227] The sensor component 814 includes one or more sensors for providing status assessments for various aspects of the device 800. For example, the sensor component 814 can detect an open / closed position of the device 800, relative positioning of components, such as a display and a keypad of the device 800, a change of position of the device 800 or a component of the device 800, presence or absence of user contact with the device 800, a change in orientation or acceleration / deceleration of the device 800, and a temperature change of the device 800, among other possibilities. The sensor component 814 can include proximity sensor configured to detect presence of an object in proximity to the device 800 without any physical touch. The sensor component 814 can also include a light sensor (e.g., a CMOS or CCD image sensor) configured to work in an imaging application. In some embodiments, the sensor component 814 can also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0228] The communication component 816 is configured to facilitate wired or wireless communication between the device 800 and another device. The device 800 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, 4G LTE, 5G NR, or a combination thereof. In an example embodiment, the communication component 816 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In an example embodiment, the communication component 816 can further include a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) techniques, infrared data association (IrDA) techniques, ultra-wideband (UWB) techniques, Bluetooth (BT) techniques, and other techniques.

[0229] In exemplary embodiments, the apparatus 800 can be implemented with one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components, for performing the above methods.

[0230] In exemplary embodiments, a non-transitory computer-readable storage medium, such as the memory 804 including instructions, is also provided, which, when executed by the processor 820 of the apparatus 800, enables the apparatus 800 to perform a method of data access, comprising:

[0231] obtaining a plurality of to-be-processed instructions; wherein each to-be-processed instruction comprises a to-be-accessed address;

[0232] determining to-be-merged instructions in the plurality of to-be-processed instructions, and performing merging processing on the to-be-merged instructions to obtain a merged instruction;

[0233] performing data access according to the to-be-accessed address corresponding to the merged instruction.

[0234] The non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disc, and an optical data storage device, etc.

[0235] In exemplary embodiments, a computer program product is also provided, comprising a computer program which, when executed by a processor, implements the steps of the above method.

[0236] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure following, in general, the principles of the present disclosure and including such features to the extent that they are not disclosed in the prior art. The specification and examples are to be regarded as illustrative only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0237] It should be understood that the present disclosure is not limited to the precise structures herein described and illustrated, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the claims that follow.

Claims

1. A data access method, characterized in that, Applied to electronic devices, the method includes: Obtain multiple instructions to be processed; wherein each instruction to be processed includes an address to be accessed; The instructions to be merged among the plurality of instructions to be processed are identified, and the instructions to be merged are merged to obtain the merged instructions; Data access is performed based on the address to be accessed corresponding to the merge instruction; The method further includes: After receiving the instruction to be processed, the instruction to be processed is saved to a preset instruction queue; The step of determining the instruction to be merged among the plurality of instructions to be processed includes: Obtain a first instruction; wherein the first instruction is any one of the instructions to be processed; Traverse all pending instructions except the first instruction to obtain the second instruction; wherein the address to be accessed of the second instruction is indirectly continuous with the address to be accessed of the first instruction, and the address to be accessed of the second instruction is not continuous with the address to be accessed of the first instruction through the addresses to be accessed of other pending instructions. In response to the second instruction and the first instruction satisfying the first preset merging condition, the second instruction and the first instruction are determined as the instructions to be merged. The acquisition of the first instruction includes: Select one instruction to be processed from the preset instruction queue as the first instruction; The step of determining the second instruction and the first instruction as the instructions to be merged in response to the second instruction and the first instruction satisfying the first preset merging condition includes: Obtain the storage interval, wherein the storage interval indicates the distance between the address to be accessed by the first instruction and the address to be accessed by the second instruction; If the storage interval is less than a first preset threshold, the second instruction and the first instruction are determined to be the instructions to be merged. The method further includes: Obtain the difference between the address to be accessed in the second instruction and the address to be accessed in the first instruction; wherein the address to be accessed is a logical address; Get the preset storage unit size; The storage interval is obtained based on the difference and the preset storage unit size.

2. The method according to claim 1, characterized in that, The step of determining the second instruction and the first instruction as the instructions to be merged in response to the second instruction and the first instruction satisfying the first preset merging condition includes: Obtain the current total data volume; wherein, the current total data volume indicates the sum of the data volumes to be accessed corresponding to all instructions to be merged; If the total amount of data currently accessed is less than a second preset threshold, the second instruction and the first instruction are determined to be the instructions to be merged.

3. The method according to claim 2, characterized in that, The method further includes: If the total amount of data currently accessed is greater than or equal to the second preset threshold, stop traversing pending instructions other than the first instruction.

4. The method according to claim 1, characterized in that, The method further includes: Obtain a first duration and obtain a first time threshold corresponding to the first instruction; wherein, the first duration indicates the duration from the determination of obtaining the first instruction to the current time. In response to the first duration being less than the first time threshold, continue to traverse the pending instructions other than the first instruction; In response to the first duration being greater than or equal to the first time threshold, the process of traversing pending instructions other than the first instruction is stopped.

5. The method according to claim 1, characterized in that, The method further includes: Obtain a first instruction; wherein the first instruction is any one of the instructions to be processed; Iterate through all pending instructions except the first instruction; In response to the current traversal of the pending instruction and the first instruction satisfying the second preset merging condition, the current traversal of the pending instruction and the first instruction are determined as the instruction to be merged.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: The instruction to be processed in the preset instruction queue that meets at least one of the following conditions shall be used as the first instruction: The second duration corresponding to the instruction to be processed is greater than the second time threshold; wherein, the second duration indicates the storage duration of the instruction to be processed in the preset instruction queue; The instruction to be processed is located at a set position in a preset instruction queue; wherein, the set position is either the head position or the tail position.

7. The method according to claim 1, characterized in that, The process of merging the multiple instructions to be merged to obtain a merge instruction includes: Based on the access addresses of each instruction to be merged, a merging processing result is generated, and the merging processing result is encapsulated in a set instruction format to obtain the merging instruction.

8. The method according to claim 7, characterized in that, The method further includes: Obtain the amount of data to be accessed corresponding to each of the commands to be merged; The amount of data to be accessed corresponding to each of the commands to be merged is added to the merge processing result.

9. A data access device, characterized in that, Applied to electronic devices, the device includes: The instruction acquisition module is used to acquire multiple instructions to be processed; wherein each instruction to be processed includes an address to be accessed; The instruction merging module is used to determine the instructions to be merged among the multiple instructions to be processed, and to merge the instructions to be merged to obtain the merged instructions; The instruction sending module is used to access data according to the address to be accessed corresponding to the merging instruction; The device further includes an instruction queue storage module, used for: After receiving the instruction to be processed, the instruction to be processed is saved to a preset instruction queue; The instruction sending module is specifically used for: Obtain a first instruction; wherein the first instruction is any one of the instructions to be processed; Traverse all pending instructions except the first instruction to obtain the second instruction; wherein the address to be accessed of the second instruction is indirectly continuous with the address to be accessed of the first instruction, and the address to be accessed of the second instruction is not continuous with the address to be accessed of the first instruction through the addresses to be accessed of other pending instructions. In response to the second instruction and the first instruction satisfying the first preset merging condition, the second instruction and the first instruction are determined as the instructions to be merged. When the instruction sending module receives the first instruction, it is used for: The instruction sending module is also used for: Select one instruction to be processed from the preset instruction queue as the first instruction; Obtain the storage interval, wherein the storage interval indicates the distance between the address to be accessed by the first instruction and the address to be accessed by the second instruction; If the storage interval is less than a first preset threshold, the second instruction and the first instruction are determined to be the instructions to be merged. The instruction merging module is also used for: Obtain the difference between the address to be accessed in the second instruction and the address to be accessed in the first instruction; wherein the address to be accessed is a logical address; Get the preset storage unit size; The storage interval is obtained based on the difference and the preset storage unit size.

10. The apparatus according to claim 9, characterized in that, The instruction sending module is also used for: Obtain the current total data volume; wherein, the current total data volume indicates the sum of the data volumes to be accessed corresponding to all instructions to be merged; If the total amount of data currently accessed is less than a second preset threshold, the second instruction and the first instruction are determined to be the instructions to be merged.

11. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps of the data access method as described in any one of claims 1 to 8.

12. A data access device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured as follows: Obtain multiple instructions to be processed; wherein each instruction to be processed includes an address to be accessed; The instructions to be merged among the plurality of instructions to be processed are identified, and the instructions to be merged are merged to obtain the merged instructions; Data access is performed based on the address to be accessed corresponding to the merge instruction; The processor is also configured to: After receiving the instruction to be processed, the instruction to be processed is saved to a preset instruction queue; The step of determining the instruction to be merged among the plurality of instructions to be processed includes: Obtain a first instruction; wherein the first instruction is any one of the instructions to be processed; Traverse all pending instructions except the first instruction to obtain the second instruction; wherein the address to be accessed of the second instruction is indirectly continuous with the address to be accessed of the first instruction, and the address to be accessed of the second instruction is not continuous with the address to be accessed of the first instruction through the addresses to be accessed of other pending instructions. In response to the second instruction and the first instruction satisfying the first preset merging condition, the second instruction and the first instruction are determined as the instructions to be merged. The acquisition of the first instruction includes: Select one instruction to be processed from the preset instruction queue as the first instruction; The step of determining the second instruction and the first instruction as the instructions to be merged in response to the second instruction and the first instruction satisfying the first preset merging condition includes: Obtain the storage interval, wherein the storage interval indicates the distance between the address to be accessed by the first instruction and the address to be accessed by the second instruction; If the storage interval is less than a first preset threshold, the second instruction and the first instruction are determined to be the instructions to be merged. The processor is also configured to: Obtain the difference between the address to be accessed in the second instruction and the address to be accessed in the first instruction; wherein the address to be accessed is a logical address; Get the preset storage unit size; The storage interval is obtained based on the difference and the preset storage unit size.

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