Improved field plate

Abstract

To provide an integrated circuit.SOLUTION: An integrated circuit includes: a high voltage semiconductor device (such as a LDMOSFET) having a first doped region, a second doped region, and a drift region positioned between the first doped region and the second doped region; a plurality of stacked metal layers; a metal structure overlapping the drift region; and a field plate structure arranged between the metal structure and the drift region. The field plate structure 34 includes an array of floating field plates 35, and a pair of field plates including first and second field plates 40, 42. The pair of field plates overlaps the array of floating field plates. The first field plate and the second field plate are separated by a gap 48, and the gap is arranged diagonally over the drift region.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to an improved field plate, and more particularly to an improved field plate in an integrated circuit with high voltage semiconductor devices. [Background technology]

[0002] Lateral high-voltage (HV) semiconductor devices in integrated circuits are used in AC / DC converters and power switches. For example, lateral double-diffused MOS (LDMOS) transistors are used in high-voltage (HV) applications in integrated circuits. The reliability and breakdown characteristics of LDMOS depend on the drift region (a lightly doped region between the drain and source). Metal lines on the drift region can significantly alter the electric field distribution in that region, negatively impacting device performance, such as reducing the breakdown voltage. This limits the design flexibility of the integrated circuit and may require off-chip connections (e.g., wire bonding).

[0003] Koichi Endo (Toshiba), "Power Semiconductor Integrated Circuit Device Without Electric Field Concentration," U.S. Patent No. 5,315,139, June 1993, proposes a resistor placed between the HV drift region and the wiring layer passing over it. However, when using layers of existing CMOS processes, such as poly-Si layers, the resistor introduces unwanted leakage current into the HV device.

[0004] Akio Nakagawa et al. (Toshiba), "High-Voltage Planar Semiconductor Device," U.S. Patent No. 5,086,332, September 1989, describes a method by which low leakage can be achieved using special semi-insulating polysilicon (SIPOS). However, SIPOS requires additional manufacturing steps and still exhibits significant leakage, especially at high temperatures.

[0005] Tomohide Terashima (Mitsubishi Electric), "Structure for Preventing Electric Field Concentration in Semiconductor Devices," European Patent Application Publication No. 0 461 877, December 1991, describes multiple field plate strips arranged so that a uniform electric field is achieved by capacitive coupling between them. If the capacitive coupling between this metal line and the field plate is negligible compared to the coupling between the field plates, then a small metal line can be run over the field plate. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent No. 5,315,139 [Patent Document 2] U.S. Patent No. 5,086,332 [Patent Document 3] European Patent Application Publication No. 0461877 Summary of the Invention

[0007] Aspects of the present invention provide an integrated circuit as set out in the accompanying claims.

[0008] Alternatively, aspects of the invention may be defined by any of the following numbered paragraphs:

[0009] [Paragraph 1] 1. An integrated circuit comprising: a high voltage semiconductor device including a first doped region, a second doped region, and a drift region positioned between the first doped region and the second doped region; a plurality of laminated metal layers; a metal structure overlying the drift region; a field plate structure disposed between the metal structure and the drift region; Including, The field plate structure is an array of floating field plates; A pair of biased field plates Including, The pair of biased field plates overlap the array of floating field plates. [Paragraph 2] 10. The integrated circuit of paragraph 1, wherein the array of floating field plates is formed in a polysilicon layer or in a first metal layer of the plurality of stacked metal layers. [Paragraph 3] 3. The integrated circuit of paragraph 1 or 2, wherein the pair of biased field plates is formed in a second metal layer of the plurality of stacked metal layers. [Paragraph 4] 4. The integrated circuit of any one of paragraphs 1 to 3, wherein the floating field plate has an extension dimension that is arranged substantially perpendicular to the flow of current through the drift region in use. [Paragraph 5] 5. The integrated circuit of any of paragraphs 1 to 4, wherein the floating field plate has a rectangular shape. [Paragraph 6] 6. The integrated circuit of paragraph 5, wherein the rectangular shape has a short side with a dimension in the range of 1 μm to 5 μm and a long side with a dimension in the range of 1 μm to 10 mm. [Paragraph 7] 7. The integrated circuit of any one of paragraphs 1 to 6, wherein the pair of biased field plates includes a first field plate electrically connected to a low voltage point and a second field plate electrically connected to a high voltage point. [Paragraph 8] 8. The integrated circuit of any one of paragraphs 1 to 7, wherein the first field plate is electrically connected to the first doped region and the second field plate is electrically connected to the second doped region. [Paragraph 9] 9. The integrated circuit of any of paragraphs 1 to 8, wherein the first field plate and the second field plate are separated by a gap in the metal layer, the gap being positioned diagonally across the drift region. [Paragraph 10] 10. The integrated circuit of paragraph 9, wherein the gap has a width in the range of 0.5 μm to 5 μm. [Paragraph 11] 11. The integrated circuit of any of paragraphs 1 to 10, wherein the pair of biased field plates covers a substantially rectangular area, and the first and second field plates each have a triangular shape. [Paragraph 12] 12. The integrated circuit of any one of paragraphs 1 to 11, wherein the pair of biased field plates are positioned relative to the array of floating field plates such that the potential increases substantially linearly from a first floating field plate closest to the second doped region to a final floating field plate closest to the first doped region. [Paragraph 13] 13. The integrated circuit of any one of paragraphs 1 to 12, further comprising one or more additional pairs of biased field plates positioned above the drift region and overlapping the array of floating field plates. [Paragraph 14] 14. The integrated circuit of paragraph 13, wherein gaps between the field plates of the pair of biased field plates and gaps between the field plates of the one or more further pairs of biased field plates together form a zigzag pattern over the drift region. [Paragraph 15] 1. An integrated circuit comprising: a high voltage semiconductor device including a first doped region, a second doped region, and a drift region positioned between the first doped region and the second doped region; a plurality of laminated metal layers; a metal structure overlying the drift region; a field plate structure disposed between the metal structure and the drift region; Including, The field plate structure includes a metal layer that defines a slot. [Paragraph 16] 16. The integrated circuit described in paragraph 15, wherein the slot separates the metal layer into two portions, each portion providing a continuous metal cover over the drift region. [Paragraph 17] 17. The integrated circuit of paragraph 15 or 16, wherein the metal layer is formed in one of the plurality of stacked metal layers. [Paragraph 18] 18. The integrated circuit of paragraph 15, 16, or 17, wherein the metal layer is positioned as metal 4 or metal 5 of the plurality of stacked metal layers. [Paragraph 19] 19. The integrated circuit of any of paragraphs 15 to 18, wherein the slot has a width dimension in the range of 1 μm to 5 μm. [Paragraph 20] 20. The integrated circuit of any one of paragraphs 15 to 19, wherein the slot has a longitudinal axis that is substantially perpendicular to a direction from the first doped region to the second doped region. [Paragraph 21] 21. The integrated circuit of any of paragraphs 15 to 20, wherein the slot is located substantially midway between the first doped region and the second doped region. [Paragraph 22] 22. The integrated circuit of any of paragraphs 15 to 21, wherein the slot is positioned below the metal structure. [Paragraph 23] 23. The integrated circuit of paragraph 22, wherein the slot is the only slot formed in the metal layer and the only slot positioned below the metal structure. [Paragraph 24] 24. The integrated circuit of any of paragraphs 1 to 23, wherein the metal structure completely covers the drift region. [Paragraph 25] 25. The integrated circuit of any of paragraphs 1 to 24, wherein the metal structure completely covers the field plate structure. [Paragraph 26] 1. An integrated circuit device comprising: An integrated circuit according to any one of paragraphs 1 to 25; a high voltage region of the integrated circuit containing the high voltage semiconductor device; a low voltage region including a plurality of low voltage semiconductor devices; Including, an integrated circuit device, wherein the plurality of stacked metal layers includes metal lines configured to provide electrical connection with the high voltage semiconductor device and electrical connection with the plurality of low voltage semiconductor devices;

[0010] Specific embodiments will now be described with reference to the drawings. [Brief explanation of the drawings]

[0011] [Figure 1] 1 shows a schematic top view of an integrated circuit. [Figure 2A] 1 shows a schematic cross-sectional view of a HV semiconductor device. [Figure 2B] 10 shows the same HV device with metal lines in a fourth metal layer above the drift region. [Figure 3] FIG. 1 shows a schematic perspective view of a field plate structure. [Figure 4A] 1 shows a schematic top view of a field plate structure and a portion of a HV semiconductor device. [Figure 4B] 1 shows another schematic top view of a field plate structure. [Figure 4C] 1 shows a schematic cross-sectional view of a HV semiconductor device including a field plate structure. [Figure 5] FIG. 1 shows a schematic top view of an HV device including a field plate structure. [Figure 6] 1 shows a schematic top view of a large area HV semiconductor device. [Figure 7] 1 shows a schematic top view of another field plate structure. [Figure 8] 1 shows a schematic cross-sectional view of a HV semiconductor device including a field plate structure. [Figure 9] 1 shows a schematic cross-sectional view of a HV semiconductor device including a field plate structure. [Figure 10A]10A and 10B show graphs plotting the change in breakdown drain-source voltage. [Figure 10B] 10A and 10B show graphs plotting the change in breakdown drain-source voltage. DETAILED DESCRIPTION OF THE INVENTION

[0012] 1 shows a schematic top view of an integrated circuit 2 (e.g., an AC / DC converter) having an HV region 4 containing two LDMOS transistors 6. The LDMOS transistor 6 includes a source 8 and a drain 10, with a drift region 12 therebetween. The integrated circuit 2 further includes a low-voltage (LV) region 14 containing a plurality of LV devices 16. The HV region 4 and the LV region 14 are formed on the same semiconductor wafer. The LV devices 16 are typically CMOS devices formed in a conventional CMOS process. The LV devices typically include transistors, diodes, resistors, and capacitors.

[0013] To avoid high electric field densities in the drift region 12, there are no metal lines or connections overlapping the drift region 12. Therefore, an external connection to the drain pad 10 must be made. For example, this is often achieved by wire bonding to a metal connection pad. This introduces additional manufacturing steps, longer connections, and additional points of potential device failure.

[0014] FIG. 2A shows a schematic cross-sectional view of an HV semiconductor device 18 (e.g., an LDMOS). The HV semiconductor device 18 may be the LDMOS transistor 6 described in connection with FIG. 1 above. The device 18 includes a source region 20, a drain region 22, and a drift region 24 therebetween. The device 18 includes multiple metal layers 26a through 26d (only layers 26a through 26c are shown in FIGS. 2A and 2B, while layers 26a through 26d are shown in FIG. 4C). The multiple metal layers are Metal 1 (first metal) 26a (closest to the underlying semiconductor layer), Metal 2 (second metal) 26b, Metal 3 (third metal) 26c, and Metal 4 (fourth metal) 26d. The metal layers 26a through 26d are typically formed during a CMOS back-end-of-line (BEOL) process that forms the back-end stack. Metal layers 26a-26d are separated by interlevel dielectric layers (e.g., comprising silicon oxide) and connected by vias 28 that extend through the interlevel dielectric layers. Electric field lines 30 (dashed lines) are substantially uniformly distributed in and above drift region 24. An active silicon layer including source and drain regions 20 and 22 is disposed on substrate 25, which may be, for example, a silicon substrate or a silicon-on-insulator (SOI) substrate.

[0015] 2B shows the same HV device 18, but with a metal line 32 in the third metal layer 26c (Metal 3) above the drift region 24. The metal line 32 distorts the electric field lines 30, creating regions of high electric field density. Localized regions of high electric field density can reduce the breakdown voltage. In the illustrated example, the metal line 32 connects to the high terminal of the lateral HV device (corresponding to the drain region 22) and pushes the electric field toward the low terminal (corresponding to the source region 20), creating a region of high electric field density there.

[0016] To at least partially solve this problem, the present disclosure provides a field plate structure positioned between the drift region and any overlying metal lines, which can shield the drift region and provide a uniform electric field distribution under the metal lines.

[0017] FIG. 3 shows a schematic perspective view of a field plate structure 34 and a plot of voltage along the length (x) of the field plate structure 34. The field plate structure includes an array of floating field plates 35 in a first layer 36 (e.g., poly or metal 1) and a pair of biased field plates 38 overlapping the floating field plates 35 in a second layer 39 (e.g., metal 1, metal 2, or metal 3). The pair of biased field plates 38 includes a first field plate 40 connected to a low voltage point (e.g., source) and a second field plate 42 connected to a high voltage point (e.g., drain). For example, if the floating field plate 35 is positioned in the poly layer, the pair of biased field plates may be positioned in metal 1, with metal wiring positioned in metal 2 and above. If the floating field plate is positioned in metal 1, the pair of biased field plates 38 may be positioned in metal 2, with metal wiring positioned in metal 3 and above. The poly layer is the same layer in which the gate poly is positioned. Therefore, the floating field plate 35 may be deposited and patterned in the same process step as the gate poly of the device.

[0018] The first and second field plates 40 and 42 have a substantially triangular shape with a gap 48 between them. The triangular shapes have right-angled corners and together cover a substantially rectangular area. The gap 48 extends diagonally across an array of floating field plates 35. The angle of the gap 48 with respect to the length direction (x-axis) may range from 30° to 60°. The gap 48 may range from 2 μm to 4 μm. Due to tooling / manufacturing constraints, the substantially triangular shape may include a substantially flat or rounded tip.

[0019] An array of floating field plates 35 may include rectangular strips of metal or polysilicon. These strips are arranged in the length direction (x) with their long axis in the width direction (y). The extension dimension of these strips may range from 1 μm to 10 mm, typically covering the entire width of the underlying LDMOS. The gap / spacing between the strips may range from 0.5 μm to 5 μm.

[0020] As can be seen from the bottom plot of Figure 3, the voltage on the floating field plates 35 increases in the x-direction: the first floating field plate 35 (leftmost) is mostly covered by the first field plate 40 (connected to the low voltage point), while the last floating field plate 35 (rightmost) is mostly covered by the second field plate 42 (connected to the high voltage point).

[0021] FIG. 4A shows a schematic top view of a field plate structure 34 and a portion of an HV semiconductor device 18. The field plate structure 34 is shown as transparent (only outlined) so that the underlying semiconductor region is visible. The field plate structure 34 may be the field plate structure 34 described in connection with FIG. 3 above. The device 18 includes source regions 20, drain regions 22, and a drift region 24 therebetween. The field plate structure 34 covers the drift region 24. In particular, an array of floating field plates 35 is disposed along the X direction across the drift region 24 between the source regions 20 and the drain regions 22. The floating field plates 35 have a substantially rectangular shape with an elongated dimension along the Y direction (the width direction of the drift region 24). The floating field plates 35 have a width 46 (along x) and a spacing 44.

[0022] A pair of biased field plates 38 is disposed above the floating field plate 35. The pair 38 includes a first field plate 40 having a right-angled triangular shape and a second field plate 42 having a corresponding right-angled triangular shape. The first and second field plates are separated by a gap 48. A metal line 32 crosses the field plate structure 34.

[0023] Figure 4B is the same as Figure 4A, but shows a schematic top view with the opaque features of the field plate structure 34 indicated at their respective locations. For ease of understanding, Figures 4A and 4B show the triangular field plates 40, 42 as covering a larger area than the underlying floating field plate 35. However, in a preferred embodiment, the pair of biased field plates may have the same width as the array of floating field plates and may cover substantially the same area across the drift region 24.

[0024] FIG. 4C shows a schematic cross-sectional view of an HV semiconductor device 18 including the field plate structure 34 of FIGS. 3, 4A, and 4B. The HV device includes four stacked metal layers 26a through 26d (Metal 1 through Metal 4) separated by dielectric layers. The first metal layer 26a is directly connected to the source region 20 and the drain region 22. A floating field plate 35 is also positioned in the first metal layer 26a, and a pair of biased field plates 38 (including a first field plate 40 and a second field plate 42) are positioned in the second metal layer 26b. Metal lines 32 above the drift region 24 are positioned in the third metal layer 26c. The metal lines 32 may completely cover the drift region 24. This field plate structure allows for additional metal lines and wiring in the fourth metal layer 26d or even in higher metal levels depending on the given CMOS process. An advantage of this and related embodiments is that there can be complete metal coverage on top of the device. For example, metal line 32 and / or additional metal lines or wiring of fourth metal layer 26d, i.e., higher metal levels, can completely cover drift region 24 and / or floating metal plate 35 and / or pair of biased field plates 38. HV semiconductor device 18 includes or is positioned on substrate 25. Substrate 25 can be, for example, a silicon-on-insulator (SOI) substrate, silicon-on-sapphire, or GaN-on-Si.

[0025] The width (y-direction) of the pair of biased field plates 38 can be set to some extent by adjusting the angle of the gap between plates 40 and 42. However, for HV devices with dimensions on the order of millimeters, the pair of biased field plates 38 may be a unit cell that is repeated to cover a large area. In this case, the gap between the plates of multiple unit cells may form a zigzag pattern. The longitudinal dimension of the floating field plates 35 may be extended to cover the width (y-direction) of the drift region 24, and the number of floating field plates 35 may be increased to cover the length (x-direction) of the drift region 24.

[0026] 5 shows a schematic top view of a field plate structure 34 including two pairs of biased field plates 38a, 38b. The two pairs of biased field plates 38a, 38b include plates 40a, 42a and 40b, 42b, respectively. The biased field plates 38a, 38b overlap the floating field plate 35. Adjacent plates (e.g., 40a and 40b) connected to the same voltage may be formed from a single portion of a metal layer; that is, there may be no physical line or marker between them.

[0027] FIG. 6 shows a schematic top view of an HV semiconductor device 18 having a field plate structure 34. The device 18 has a multi-finger layout including six fingers (arranged as SDSDSDS), although the field plate structure may be configured for a single finger (SD) or for different devices with different numbers of fingers. The HV semiconductor device 18 may be one of the LDMOS transistors 6 described with reference to FIG. 1 above. A drift region 24 extends between a source region 20 and a drain region 22, connected to a source contact 8 and a drain contact 10, respectively. Multiple rows of pairs of biased field plates 38 are arranged to cover the drift region. An underlying floating field plate is not shown. Gaps 48 between the biased field plates 38 comprise a zigzag pattern. In some embodiments, the field plate structure 34 covers substantially the entire HV semiconductor device 18. In this case, free metal wiring is allowed above the device.

[0028] With slots in this arrangement, a substantially uniform electric field is obtained because the slots extend diagonally in a straight line, creating a stepped, quasi-linear potential distribution (see, for example, the graph in Figure 3 above). By changing the shape of the slot, the potential distribution can be made nonlinear. This allows for flexible design of the electric field. For example, the electric field can be pushed to the left or right.

[0029] This can be particularly advantageous for covering curved portions of the drift region, such as the region around drain 10 in Figure 1 above. Having a uniform electric field at these racetrack-shaped ends of the drift region (also called termination regions) can be difficult, but can be overcome by providing a field plate structure as described herein.

[0030] 7 shows a schematic top view of an HV semiconductor device 18 having a field plate structure 34. The field plate structure 34 includes an array of floating field plates 35 and a pair of biased field plates 38. The pair of biased field plates 38 includes a first field plate 40 connected to a low voltage point (e.g., a source) and a second field plate 42 connected to a high voltage point (e.g., a drain). The gap 48 between the field plates 40, 42 has a curved shape to provide a nonlinear variation in the x-direction of the potential at the floating field plate 35.

[0031] As an alternative solution, a field plate structure is provided that includes a metal layer above the drift region. This has a substantially straight slot, eliminating the need for an underlying floating field strip. The slot divides the metal layer into two parts (two field plates). One part is connected to the low-voltage terminal of the HV semiconductor device, and the other part is connected to the high-voltage terminal. Preferably, the length of the field plate is not substantially longer than the height of the metal layer above the drift region. Therefore, this solution can be effective for devices with short drift regions (corresponding to low voltages). This limitation depends on the given CMOS technology, i.e., the number of metal layers and the thickness of the interlayer dielectric.

[0032] FIG. 8 shows a schematic cross-sectional view of an HV device 52 including a field plate structure 54. The field plate structure 54 includes a metal layer 56 over the drift region 24 with a single slot 58 substantially in the middle. Except for the slot 58, the metal layer 56 covers the entire length of the drift region 24 (and may even cover the entire width of the drift region 24). The slot 58 is substantially perpendicular to the width direction (y) of the HV device 52. The field plate structure 54 is positioned in the third metal layer 26c (Metal 3), but depending on the length of the drift region, it may need to be located in a lower or higher metal layer (e.g., Metal 4 or Metal 5) or in another conductive layer such as poly-Si to provide a sufficiently uniform electric field distribution. The slot 58 may have a width ranging from 1 μm to 5 μm. The field plate structure 54 is typically connected to the drain and source regions by underlying metal layers 26a–26b and vias 28.

[0033] An advantage of this and related embodiments is that there can be complete metal coverage on top of the device. For example, metal line 32 and / or additional metal lines or wiring in fourth metal layer 26d, i.e., higher metal levels, can completely cover drift region 24 and / or field plate structures 54.

[0034] FIG. 9 shows a schematic cross-sectional view of an HV semiconductor device 18 (e.g., an LDMOS). A field plate structure 54 includes a metal layer 56 with a single slot 58. The HV semiconductor device 18 may be the LDMOS transistor 6 described in connection with FIG. 1 above. The device 18 includes a source region 20, a drain region 22, and a drift region 24 therebetween. The device 18 includes multiple metal layers 26a through 26d. The multiple metal layers 26a through 26d are Metal 1 (first metal) 26a (closest to the underlying semiconductor layer), Metal 2 (second metal) 26b, Metal 3 (third metal) 26c, and Metal 4 (fourth metal) 26d. The metal layers 26a through 26d are typically formed during a CMOS back-end-of-line (BEOL) process that forms the back-end stack. The metal layers 26a through 26d are separated by multiple interlayer dielectric layers (e.g., including silicon oxide) and connected by vias 28 that penetrate the interlayer dielectric layers. Field plate structure 54 causes electric field lines 30 (dashed lines) to be substantially uniformly distributed in and above drift region 24 .

[0035] 10A and 10B show graphs plotting the change in breakdown drain-source voltage (BVdss) compared to a bare NMOS device (without a field plate structure) for the two different embodiments described above.

[0036] 10A is a plot of ΔBVdss versus voltage applied to the metal plate of the fourth metal layer (Metal 4) above the drift region for a 155V NMOS device. As can be seen, both the array floating field plate and pair of biased triangular field plate embodiments, as well as the embodiment with a central slot, provide significant improvements over the bare NMOS device. This effect is particularly noticeable at higher voltages (155V and 400V in the graph).

[0037] 10B is a plot of ΔBVdss versus voltage applied to the metal plate of the fourth metal layer (Metal 4) above the drift region for a 290V NMOS device, where the triangular field plate embodiment provides better performance compared to the "center slot embodiment," but both embodiments are improved over no field plate.

[0038] The described embodiments allow for a full metal cover on top of the device, which improves the design of high power devices. The described embodiments allow for large metal structures, polygons, and / or full layer connections, as well as small "signal" connecting wires surrounded by large protective structures, allowing for low ohmic connections and / or low thermal resistance.

[0039] Generally, embodiments described herein provide an integrated circuit (IC) including a high-voltage region including a high-voltage semiconductor device (e.g., an LDMOSFET) including a first doped region, a second doped region, and a drift region positioned between the first and second doped regions, and a low-voltage region including a plurality of low-voltage semiconductor devices. The circuit further includes multiple stacked metal layers (e.g., six metal layers) including metal lines configured to provide electrical connection to the high-voltage semiconductor device and the plurality of low-voltage semiconductor devices. A metal structure overlies the drift region. The circuit further includes a field plate structure disposed between the metal structure and the drift region, the field plate structure including an array of floating field plates in a first layer and a pair of biased field plates in a second layer, the pair of biased field plates overlying the array of floating field plates.

[0040] The device may be a lateral PIN diode, where the first doped region is an n-type region that is the cathode region of the device, and the second doped region is a p-type region that is the anode region of the device. The device may be an LDMOS transistor, where the first doped region is a drain region and the second doped region is a source region. Alternatively, the device may be a junction field effect transistor (JFET) or an insulated gate bipolar transistor (IGBT), or other HV transistors such as lateral HV bipolar transistors. For a transistor, the first doped region may be a collector region or drain region, and the second doped region may be an emitter region or source region. For a diode, the first doped region may be a cathode region and the second doped region may be an anode region. The first doped region may be an n-type region connected to a high voltage (HV) point / terminal, and the second doped region may be a p-type region connected to a low voltage (LV) point / terminal. If the device is a bipolar device (e.g., an IGBT), the first doped region and the second doped region may have the same type of doping, for example, the first doped region and the second doped region may both be p-type regions.

[0041] The metal structure may be a metal line or a metal plate and may be indirectly connected to the first doped region or the second doped region. For example, the metal structure may be a wide (low-resistance) metal line that carries a high voltage to the first doped region (e.g., the drain of an LDMOS). To reduce resistance, the metal structure may cover a large portion of the drift region. Metal structures typically can distort and concentrate the electric field lines in the drift region, which can adversely affect the breakdown behavior of high-voltage semiconductor devices. A field plate structure between the metal line and the drift region can mitigate this and homogenize the electric field distribution in the drift region.

[0042] The plurality of stacked metal layers may include Metal 1, Metal 2, Metal 3, Metal 4, Metal 5, and Metal 6, with Metal 1 being closest to the underlying silicon and doped semiconductor regions. The device may include fewer or more metal layers depending on the particular technology used. For example, a 28 nm CMOS technology may have up to 12 metal layers. Metal 6 may be the top metal layer vertically farthest from the silicon. Metal 1 may be directly connected to the doped semiconductor regions (e.g., the first doped region and the second doped region) or may be connected to Metal 2 and other metal layers in the plurality by vias.

[0043] The first doped region and the second doped region may be formed in an active silicon layer (e.g., an epitaxial silicon layer) on a substrate. The substrate may be a silicon substrate or an SOI substrate including a buried oxide (BOX) layer. In other embodiments, the substrate may be silicon-on-sapphire or GaN-on-Si.

[0044] The floating field plate may have an extension dimension that is substantially perpendicular to the current flow through the drift region in use. For example, the floating field plate may be a strip that is perpendicular to the gap between the source and drain of the transistor. The drift region may include a substantially rectangular area, with one side at a first interface with the first doped region and a second, opposite side at a second interface with the second doped region. In this case, the floating field plate may be disposed parallel to the first and second sides. The floating field plate may have a substantially rectangular shape. Typically, all floating field plates in the array have the same dimensions. For example, each field plate may have the same width and length. The array may extend from above the second doped region to above the first doped region to cover substantially the entire length of the drift region. The array may also be present only on the drift region if the source and drain extend somewhat into the drift region to form short source and drain field plates. The extended dimension (along y) of the floating field plate is at least sufficient to cover the metal structures above the drift region. The extended dimension typically ranges from 1 μm to 10 mm, depending on the width of the drift region. The rectangular shape has a short dimension (along x) ranging from 1 μm to 5 μm. The gap between adjacent floating field plates may range from 1 μm to 5 μm.

[0045] The pair of biased field plates may include a first field plate electrically connected to a low voltage point and a second field plate electrically connected to a high voltage point. The pair of biased field plates may include a first field plate electrically connected to a first doped region and a second field plate electrically connected to a second doped region. The first and second field plates may be separated by a gap (e.g., a rectangular slot) in the second layer, and the gap may be disposed diagonally across the drift region. Diagonal in this sense means that the gap is at an angle relative to the width dimension of the drift region. The drift region may include a rectangular area, and the gap extends diagonally across the rectangular area in a piecewise manner in a serpentine or zigzag manner. For example, in one embodiment, the gap extends from above one corner of the drift region to the diagonally opposite corner of the drift region. The angle of the gap relative to the width direction of the drift region may range from 30 degrees to 60 degrees. The gap may have a width ranging from 1 μm to 5 μm.

[0046] A pair of biased field plates may cover a substantially rectangular area, for example, with the first and second field plates each having a substantially triangular shape (also referred to as a wedge shape). For example, the pair of field plates may each have a right-angled triangular shape. Their hypotenuses may face each other, forming a gap therebetween. Due to manufacturing constraints, the triangular shape may have flat or rounded ends. The edges of the triangular shape along the diagonal (e.g., the edges of the hypotenuse) may be jagged. For example, patterning may be constrained to linear motion along x and y, resulting in stepped diagonal lines. The rectangular area may completely cover the floating field plates of the underlying array (except where the gap is located). The pair of biased field plates may be positioned relative to the floating field plates of an array such that the potential increases substantially linearly from the first floating field plate closest to the second doped region to the last floating field plate closest to the first doped region.

[0047] The first layer (including the array of floating field plates) may be Poly-Si, or may be Metal 1 or Metal 2 of multiple stacked metal layers. For example, the array of floating field plates may be formed in a poly layer (e.g., the same poly layer used to form the gate poly of a transistor), in the metal layer closest to the underlying silicon, or in the metal layer second closest to the underlying silicon.

[0048] The second layer (including the pair of biased field plates) may be Metal 1, Metal 2, or Metal 3 of the stacked metal layers (depending on the layer in which the floating field plate is positioned). Preferably, the pair of biased field plates are positioned in the metal layer directly above the layer with the floating field plate, i.e., there may be no additional metal layer between the first and second layers.

[0049] Furthermore, embodiments described herein provide an integrated circuit (IC) including a high-voltage region including a high-voltage semiconductor device (e.g., an LDMOSFET) including a first doped region, a second doped region, and a drift region positioned between the first and second doped regions, and a low-voltage region including a plurality of low-voltage semiconductor devices. The circuit further includes multiple stacked metal layers (e.g., six metal layers) including metal lines configured to provide electrical connection to the high-voltage semiconductor device and the plurality of low-voltage semiconductor devices. A metal structure is connected to the high-voltage semiconductor device and overlaps the drift region. The circuit further includes a field plate structure disposed between the metal structure and the drift region, where the field plate structure includes a continuous metal layer having a slot positioned below the metal structure. The second doped region may be connected to the low-voltage region.

[0050] The slot separates the metal layer into two portions (two field plates). The first portion may be connected to the first doped region, and the second portion may be connected to the second doped region. The two portions of the metal layer are continuous over the drift region, although other portions of the metal layer may be used and may include other metal connections laterally spaced from the drift region. The slot is typically a single slot and may be positioned substantially in the center of the drift region (e.g., equidistant from the source and drain). In other embodiments, the slot may be within 40% to 60% of the center. The slot may have a width ranging from 1 μm to 5 μm, preferably between 2 μm and 4 μm.

[0051] The field plate structure may be positioned on metal 4 or metal 5 of the multiple stacked metal layers. For example, the multiple stacked metal layers may include six metal layers, and the field plate structure may be positioned on the second metal layer from the top, while the metal structure may be positioned on metal 6 (the top metal layer). The required height of the field plate structure depends on the length of the drift region. For short drift regions, a lower metal layer (e.g., metal 2 or metal 3) may be used. This allows for greater flexibility in metal routing, as there are more metal layers available on the field plate structure. For devices with longer drift regions, it may be necessary to use an upper metal layer. The height of the field plate structure may be equal to or greater than half the length of the drift region.

[0052] While specific embodiments of the present invention have been described above, it will be understood that the invention may be practiced otherwise than as described. The above description is intended to be illustrative and not limiting. It will be apparent to those skilled in the art that modifications may be made to the invention as described without departing from the scope of the claims set forth below.

[0053] Each feature disclosed or illustrated herein may be incorporated into the present invention either alone or in any suitable combination with any other feature disclosed or illustrated herein.

Claims

1. 1. An integrated circuit comprising: a high voltage semiconductor device including a first doped region, a second doped region, and a drift region positioned between the first doped region and the second doped region; a plurality of laminated metal layers; a metal structure overlying the drift region; a field plate structure disposed between the metal structure and the drift region; Including, The field plate structure is an array of floating field plates; a pair of field plates including first and second field plates; Including, the pair of field plates overlapping the array of floating field plates; the first field plate and the second field plate are separated by a gap; The gap is disposed diagonally across the drift region.

2. 10. The integrated circuit of claim 1, wherein the array of floating field plates is formed in a polysilicon layer or in a first metal layer of the plurality of stacked metal layers.

3. The integrated circuit of claim 1 , wherein the pair of field plates are formed in a second metal layer of the plurality of stacked metal layers.

4. 2. The integrated circuit of claim 1, wherein the floating field plate has an extension dimension that is arranged substantially perpendicular to the flow of current through the drift region in use.

5. The integrated circuit of claim 1 , wherein the floating field plate has a rectangular shape.

6. 6. The integrated circuit of claim 5, wherein the rectangular shape has a short side with a dimension in the range of 1 μm to 5 μm and a long side with a dimension in the range of 1 μm to 10 mm.

7. 2. The integrated circuit of claim 1, wherein the pair of field plates includes a first field plate electrically connected to a low voltage point and a second field plate electrically connected to a high voltage point.

8. 2. The integrated circuit of claim 1, wherein the first field plate is electrically connected to the first doped region and the second field plate is electrically connected to the second doped region.

9. 2. The integrated circuit of claim 1, wherein the first field plate and the second field plate are formed from one of the plurality of stacked metal layers.

10. 10. The integrated circuit of claim 9, wherein the gap has a width in the range of 0.5 μm to 5 μm.

11. 2. The integrated circuit of claim 1, wherein said pair of field plates covers a substantially rectangular area, and said first and second field plates each have a triangular shape.

12. 2. The integrated circuit of claim 1, wherein the pair of field plates are positioned relative to the array of floating field plates such that there is a substantially linear increase in potential from a first floating field plate closest to the second doped region to a last floating field plate closest to the first doped region.

13. 10. The integrated circuit of claim 1, further comprising one or more additional pairs of field plates disposed above the drift region and overlapping the array of floating field plates.

14. 14. The integrated circuit of claim 13, wherein gaps between the field plates of the pair of field plates and gaps between the field plates of the one or more additional pairs of field plates together form a zigzag pattern over the drift region.

15. 10. The integrated circuit of claim 1, wherein the pair of field plates are biased field plates.

16. 1. An integrated circuit comprising: a high voltage semiconductor device including a first doped region, a second doped region, and a drift region positioned between the first doped region and the second doped region; a plurality of laminated metal layers; a metal structure overlying the drift region; a field plate structure disposed between the metal structure and the drift region; Including, the field plate structure includes a metal layer connected to the first and second doped regions and defining a slot; the slot is positioned below the metal structure; The slot is the only slot formed in the metal layer and is the only slot positioned below the metal structure.

17. 17. The integrated circuit of claim 16, wherein the slot separates the metal layer into two portions, each portion providing a continuous metal cover over the drift region.

18. 17. The integrated circuit of claim 16, wherein the metal layer is formed in one of the plurality of stacked metal layers.

19. 17. The integrated circuit of claim 16, wherein the metal layer is positioned at metal 4 or metal 5 of the plurality of stacked metal layers.

20. 17. The integrated circuit of claim 16, wherein the slot has a width dimension in the range of 1 μm to 5 μm.

21. 17. The integrated circuit of claim 16, wherein the slot has a longitudinal axis substantially perpendicular to a direction from the first doped region to the second doped region.

22. 17. The integrated circuit of claim 16, wherein the slot is located substantially midway between the first doped region and the second doped region.

23. The integrated circuit of claim 1 or 16, wherein the metal structure completely covers the drift region.

24. The integrated circuit of claim 1 or 16, wherein the metal structure completely covers the field plate structure.

25. 1. An integrated circuit device comprising: an integrated circuit according to claim 1 or 16; a high voltage region of the integrated circuit containing the high voltage semiconductor device; a low voltage region including a plurality of low voltage semiconductor devices; Including, an integrated circuit device, wherein the plurality of stacked metal layers includes metal lines configured to provide electrical connection with the high voltage semiconductor device and electrical connection with the plurality of low voltage semiconductor devices;

Images