Power source control device, insulation DC / DC converter, and ac adaptor

Abstract

To provide a power source control device in which the efficiency of an insulation DC / DC converter can be improved.SOLUTION: A power source control device (1) includes an on-timing determination unit (80) configured to generate an output signal (ST) for determining a timing of turning on any one (3) of at least one switching element. The on-timing determination unit includes a bottom detection unit (80B) configured to detect a bottom of a resonance voltage (Vzt) generated when any one (3) of the at least one switching element is turned off. The on-timing determination unit outputs the output signal indicative of turning-on of the switching element at a timing when a timeout time, which is expressed by ((set number of target bottoms)-(number of detected bottoms))×(resonance time)=timeout time, elapses from cessation of the detection of the bottom.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to a power supply control device. [Background technology]

[0002] BACKGROUND ART Various isolated DC / DC converters have been proposed in the past (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2017-225248

[0004] [overview] There is a demand for improved efficiency in isolated DC / DC converters.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a power supply control device that can improve the efficiency of an isolated DC / DC converter.

[0006] A power supply control device according to one embodiment of the present disclosure is a power supply control device used in an isolated DC / DC converter configured to generate an output voltage by switching at least one switching element, the power supply control device comprising: an on-timing determination unit configured to generate an output signal for determining a timing to turn on any of the at least one switching element; the on-timing determination unit has a bottom detection unit configured to detect a bottom of a resonance voltage generated when any of the at least one switching element is turned off, The on-timing determination unit determines whether the bottom is detected or not. The output signal indicating the turning on of the switching element is output at the timing when the timeout time, which is expressed as ((set target bottom number) - (detected bottom number)) x (resonance time) = timeout time, has elapsed. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of an isolated DC / DC converter. [Figure 2] FIG. 2 is a diagram showing the internal configuration of a power supply control device according to a comparative example. [Figure 3] FIG. 3 is a table showing an example of the correspondence relationship between the number of bottoms and the threshold voltage of the feedback voltage. [Figure 4] FIG. 4 is an example of a timing chart for explaining the timeout control in the comparative example. [Figure 5] FIG. 5 is a graph showing an example of the characteristics of the correspondence relationship between output power and switching frequency. [Figure 6] FIG. 6 is a diagram illustrating a configuration of a set signal generation unit according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a timing chart showing an example of the operation of the set signal generating unit. [Figure 8] FIG. 8 is a diagram showing a modified example of an isolated DC / DC converter. [Figure 9] FIG. 9 is a diagram showing the internal configuration of a power supply control device according to a modified example. [Figure 10] FIG. 10 is a timing chart showing an example of light load operation in the isolated DC / DC converter according to the modified example. [Figure 11] FIG. 11 is a diagram illustrating an example of the configuration of an AC adapter.

[0008] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0009] <Flyback converter> Fig. 1 is a diagram showing an example of the configuration of a flyback converter. A flyback converter is a type of isolated DC / DC converter. Flyback converter 15 shown in Fig. 1 is configured as a QR (quasi-resonant) flyback converter.

[0010] A fuse F1, a diode bridge DB1, and a smoothing capacitor C1 are arranged in the upstream stage of the flyback converter 15. An AC voltage Vac is input to the diode bridge DB1 via the fuse F1, full-wave rectified, smoothed by the smoothing capacitor C1, and converted into an input voltage Vin as a DC voltage. The input voltage Vin is converted into an output voltage Vout as a DC voltage by the flyback converter 15.

[0011] The flyback converter 15 includes a power supply control device 1, a transformer Tr, a diode D1, a capacitor C2, voltage dividing resistors R1 and R2, and a feedback circuit .

[0012] The power supply control device 1 is a semiconductor device that controls a flyback converter 15. The power supply control device 1 has external terminals such as a DRAIN terminal, an FB terminal, and a ZT terminal for establishing electrical connection with the outside. The transformer Tr has a primary winding w1, a secondary winding w2, and an auxiliary winding w3.

[0013] One end of the primary winding w1 is connected to the input voltage Vin application terminal. The other end of the primary winding w1 is connected to the DRAIN terminal. One end of the secondary winding w2 is connected to the anode of the diode D1. A capacitor C2 is connected between the cathode of the diode D1 and the other end of the secondary winding w2. The output terminal Tout is connected to the cathode of the diode D1. An output voltage Vout is generated at the output terminal Tout.

[0014] The feedback circuit 10 has a photocoupler consisting of a light emitting diode PD and a phototransistor PT, and outputs a current from the phototransistor PT according to the error between a voltage based on the output voltage Vout and a target voltage. The phototransistor PT is connected to the FB terminal.

[0015] Voltage-dividing resistors R1 and R2 are connected in series between one end of the auxiliary winding w3 and the ground terminal (the terminal to which the ground potential is applied). The other end of the auxiliary winding w3 is connected to the ground terminal. The auxiliary winding voltage Vw generated in the auxiliary winding w3 is divided by the voltage-dividing resistors R1 and R2 to become the ZT voltage Vzt. The ZT voltage Vzt is applied to the ZT terminal.

[0016] <Comparative Example> Fig. 2 is a diagram showing the internal configuration of a power supply control device 1X according to a comparative example. The power supply control device 1X is an example of the power supply control device 1 shown in Fig. 1. The power supply control device 1X has an integrated drive control unit 2, a switching element 3, a current detection unit 4, a pull-up resistor 5, a gain addition unit 6, a comparator 7, and a set signal generation unit 8.

[0017] The switching element 3 is configured by an N-channel MOSFET (metal-oxide-semiconductor field-effect transistor). The drain of the switching element 3 is connected to the DRAIN terminal. The source of the switching element 3 is connected to the ground terminal via the current detection unit 4. The gate of the switching element 3 is driven by a gate signal G output from the drive control unit 2. When the gate signal G is at a high level, the switching element 3 is driven to an on state, and when the gate signal G is at a low level, the switching element 3 is driven to an off state.

[0018] The current detection unit 4 detects the current flowing through the switching element 3 in the ON state, and outputs a current detection signal Vcs as a voltage signal.

[0019] The FB terminal is connected to a terminal to which a reference voltage Vref is applied via a pull-up resistor 5. A current output from a feedback circuit 10 (FIG. 1) flows through the pull-up resistor 5, generating a feedback voltage Vfb at the FB terminal. That is, the feedback circuit 10 and the pull-up resistor 5 form a feedback voltage generating unit. A gain adding unit 6 amplifies the feedback voltage Vfb by a predetermined gain to generate a feedback voltage Vfb_g.

[0020] The current detection signal Vcs is applied to the non-inverting input terminal (+) of the comparator 7, and the feedback voltage Vfb_g is applied to the inverting input terminal (-). The comparator 7 compares the current detection signal Vcs with the feedback voltage Vfb_g and outputs a reset signal RS as the comparison result. When the current flowing through the switching element 3, which is in the ON state, increases and the current detection signal Vcs rises and exceeds the feedback voltage Vfb_g, the reset signal RS is asserted. This causes the drive control unit 2 to turn off the switching element 3. Note that turning off means switching from the ON state to the OFF state. In this way, the ON time of the switching element 3 is controlled by the feedback voltage Vfb_g and the current detection signal Vcs.

[0021] Next, the set signal generation unit 8 will be described. The set signal generation unit 8 has a bottom number setting unit 8A, a bottom detection unit 8B, and a timeout control unit 8C. The set signal generation unit 8 corresponds to an on-timing determination unit configured to generate an output signal (set signal ST) for determining the timing at which the switching element 3 is turned on.

[0022] When the switching element 3 is turned off, the ZT voltage Vzt generated at the ZT terminal resonates as a result of resonance occurring with the voltage at the DRAIN terminal. The set signal generator 8 performs bottom skip control. Bottom skip control is a control that skips the turn-on of the off-state switching element 3 by a predetermined number of bottoms that occur in the ZT voltage Vzt. Note that these bottoms are points where the resonating ZT voltage Vzt is minimal.

[0023] FIG. 3 is a table showing an example of the correspondence relationship between the number of bottoms and the threshold voltage of the feedback voltage Vfb. FIG. 3 shows the threshold voltage for switching the number of bottoms. For example, the threshold voltage for switching between 10 and 9 is Vfb109. If the feedback voltage Vfb is higher than the threshold voltage, it corresponds to the smaller number of bottoms. If the feedback voltage Vfb is equal to or lower than the threshold voltage, it corresponds to the larger number of bottoms. For example, if Vfb > Vfb109, the number of bottoms = 9, and if Vfb ≦ Vfb109, the number of bottoms = 10. The larger the number of bottoms, the smaller the threshold voltage. That is, Vfb21 > Vfb32 > ··· > Vfb98 > Vfb109.

[0024] The bottom number setting unit 8A determines the bottom number based on the correspondence relationship shown in FIG. 3, for example. In a light load state where the output power (= Vout × Iout) (FIG. 1) is small, the feedback voltage Vfb is small and the bottom number is large. This prevents the switching frequency from increasing in a light load state, thereby suppressing losses. In addition, in a heavy load state where the output power is large, the feedback voltage Vfb is large and the bottom number is set to 1. In other words, in a heavy load state, bottom skip control with the bottom number = 1 is performed.

[0025] When the bottom detector 8B detects the bottom of the ZT voltage Vzt, it generates a detection pulse Pdet. When the number of generated detection pulses Pdet reaches the set number of bottoms, the set signal ST is asserted. This causes the drive controller 2 to turn on the switching element 3. Note that turning on means switching from an off state to an on state. This bottom skip control controls the off time of the switching element 3.

[0026] If the detection pulses Pdet generated by the bottom detection unit 8B are not generated for a predetermined timeout time Tmout before the number of detection pulses Pdet reaches the set bottom number, the timeout control unit 8C forcibly asserts the set signal ST and turns on the switching element 3.

[0027] FIG. 4 is an example timing chart for explaining timeout control. FIG. 4 shows example waveforms of the ZT voltage Vzt, the detection pulse Pdet, and the set signal ST. The bottom of the resonating ZT voltage Vzt is detected and the detection pulse Pdet is generated. For example, if the number of bottoms is set to five or more, the example in FIG. 4 generates up to four detection pulses Pdet, but no pulses beyond the fourth are generated. Therefore, a predetermined timeout period Tmout elapses after the fourth detection pulse Pdet is generated, and the set signal ST is asserted. This timeout control allows the switching element 3 to be forcibly turned on when the auxiliary winding voltage Vw has attenuated and a bottom is not detected.

[0028] FIG. 5 is a graph showing an example of the relationship between output power and switching frequency. As shown by the solid line in FIG. 5, when no timeout occurs, the lower the output power, i.e., the lighter the load, the larger the bottom number that is set, and the more the switching frequency is suppressed. However, the timeout period Tmout is a fixed value. Therefore, when a timeout occurs, as shown by the dashed line in FIG. 5, bottom skipping is suppressed in the case of a light load with a large set bottom number, preventing the suppression of the switching frequency. This results in a problem of reduced efficiency under light load conditions.

[0029] <Embodiments of the present disclosure> In view of the above problems, an embodiment of the present disclosure is implemented. A flyback converter 15 according to the embodiment of the present disclosure has the same configuration as that shown in Fig. 1, but the set signal generating unit 8 (Fig. 2) in the power supply control device 1 is replaced with a set signal generating unit 80. Fig. 6 is a diagram showing the configuration of the set signal generating unit 80.

[0030] The set signal generation unit 80 includes a bottom number setting unit 80A, a bottom detection unit 80B, a resonance time detection unit 80C, a switch 80D, a capacitor 80E, a capacitor 80F, a switch 80G, a current mirror 80H, a switch 80I, a comparator 80J, an OR circuit 80K, a third bottom detection unit 80L, and a set signal output unit 80M. The resonance time detection unit 80C, the switch 80D, the capacitor 80E, the capacitor 80F, the switch 80G, the current mirror 80H, the switch 80I, the comparator 80J, the OR circuit 80K, and the third bottom detection unit 80L form a timeout signal generation unit 801.

[0031] The bottom number setting unit 80A sets the number of bottoms in accordance with the feedback voltage Vfb, similar to the previously described bottom number setting unit 8A.

[0032] The bottom detection unit 80B detects the bottom of the resonating ZT voltage Vzt and generates a detection pulse Pdet. The bottom detection unit 80B has a comparator CMP and a one-shot circuit SHT. The ZT voltage Vzt is applied to the inverting input terminal of the comparator CMP, and ground potential (0 V) is applied to the non-inverting input terminal. The comparison output Cpout output from the comparator CMP is input to the one-shot circuit SHT. When the one-shot circuit SHT detects the comparison output Cpout rising to a high level, it generates a detection pulse Pdet with a predetermined high-level width.

[0033] The resonance time detector 80C detects the time from the start of resonance of the ZT voltage Vzt between the first bottom and the second bottom as the resonance time. The resonance time corresponds to the resonance period.

[0034] A switch 80D is connected across a capacitor 80E. The on / off of the switch 80D is controlled by a resonance time detection unit 80C. The current mirror 80H has PMOS transistors PM1, PM2, and PM3 configured by P-channel MOSFETs. The sources of the PMOS transistors PM1, PM2, and PM3 are connected to the application terminal of the internal power supply voltage Vreg. The gate and drain of the PMOS transistor PM1 are shorted. The gates of the PMOS transistors PM1 and PM2 are connected to each other. The drain of the PMOS transistor PM2 is connected to one end of the capacitor 80E via a switch 80I. The other end of the capacitor 80E is connected to the ground terminal.

[0035] The gates of the PMOS transistors PM1 and PM3 are connected to each other. The drain of the PMOS transistor PM3 is connected to one end of a capacitor 80F. The other end of the capacitor 80F is connected to the ground terminal.

[0036] The current IREF flowing through the PMOS transistor PM1 is mirrored to become currents Ia and Ib flowing through the PMOS transistors PM2 and PM3, respectively. Since the sizes of the PMOS transistors PM2 and PM3 are 1:1, Ia=Ib. The currents Ia and Ib are used to charge the capacitors 80E and 80F, respectively.

[0037] The voltage Va of the capacitor 80E is applied to the inverting input terminal of the comparator 80J, and the voltage Vb of the capacitor 80F is applied to the non-inverting input terminal of the comparator 80J. The comparator 80J outputs a timeout signal TOUT.

[0038] The third bottom detection circuit 80L detects the third bottom from the start of resonance of the ZT voltage Vzt. The OR circuit 80K receives the timeout signal TOUT and the output Bdet of the third bottom detection circuit 80L. The switch 80G is connected across the capacitor 80F. The switch 80G is turned on and off according to the output of the OR circuit 80K.

[0039] The set signal output unit 80M monitors the detection pulse Pdet and the timeout signal TOUT, counts the number of times the detection pulse Pdet or the timeout signal TOUT goes high, and asserts the set signal ST when the count value reaches a set bottom number.

[0040] The operation of the set signal generation unit 80 configured as above will be described with reference to Fig. 7. Fig. 7 is a timing chart showing an example of the operation of the set signal generation unit 80. Fig. 7 shows example waveforms of the ZT voltage Vzt, the detection pulse Pdet, the voltages Va and Vb, the timeout signal TOUT, and the set signal ST.

[0041] First, at timing t0, resonance of the ZT voltage Vzt begins. Here, the switch 80D is turned on by the resonance time detection unit 80C, the capacitor 80E is discharged, and the voltage Va is 0V. The switch 80I is turned off. Furthermore, since the detection signal Bdet output from the third bottom detection unit 80L is at a high level, the output of the OR circuit 80K is at a high level. As a result, the switch 80G is turned on, the capacitor 80F is discharged, and the voltage Vb is 0V.

[0042] Then, at timing t1, a detection pulse Pdet corresponding to the first bottom is generated. Here, the resonance time detection unit 80C switches the switch 80D to the OFF state and switches the switch 80I to the ON state. This causes the current Ia to start charging the capacitor 80E, and the voltage Va starts to rise. Thereafter, at timing t2, a detection pulse Pdet corresponding to the second bottom is generated. Here, the resonance time detection unit 80C switches the switch 80I to the OFF state. This causes the rise in the voltage Va to stop, and thereafter the voltage Va is maintained at the voltage value Vrt at timing t2. That is, the resonance time is detected by determining the voltage value Vrt as the reference voltage of the comparator 80J.

[0043] Then, at timing t3, a detection pulse Pdet corresponding to the third bottom is generated. The third bottom detector 80L then detects the detection pulse Pdet and sets the detection signal Bdet to low level. This causes the output of the OR circuit 80K to go low, turning off the switch 80G. Therefore, charging of the capacitor 80F by the current Ib begins, and the voltage Vb starts to rise. Thereafter, the detection signal Bdet remains low.

[0044] Then, at timing t4, when voltage Vb exceeds voltage value Vrt, timeout signal TOUT goes high, and the output of OR circuit 80K goes high. This turns switch 80G on, discharges capacitor 80F, and voltage Vb drops sharply to 0 V. Then, timeout signal TOUT goes low, and the output of OR circuit 80K goes low. This turns switch 80G off, and capacitor 80F starts charging again.

[0045] Here, Ia=Ib, and the capacitances of capacitors 80E and 80F are 1:1, so the slopes of the increases in Va and Vb due to Ia and Ib are the same. Therefore, the period from timing t3 to t4 coincides with the resonance time Tr (the period from timing t1 to t2) detected by the resonance time detection unit 80C, and a pulse of the timeout signal TOUT is generated when the resonance time Tr has elapsed since the detection of the third bottom. In FIG. 7, the fourth bottom is detected at timing t4, and a detection pulse Pdet is generated. That is, at timing t4, both the detection pulse Pdet and the timeout signal TOUT are generated.

[0046] Thereafter, a timeout signal TOUT is generated at each of times t5 to t8, each time the resonance time Tr has elapsed since time t4. In Fig. 7, due to the decay of resonance, the fifth bottom and thereafter are not detected, and no detection pulse Pdet is generated, but as described above, a timeout signal TOUT corresponding to the fifth bottom and thereafter is generated.

[0047] The set signal output unit 80M monitors the detection pulse Pdet and the timeout signal TOUT from the start of resonance, and counts the number of times the detection pulse Pdet or the timeout signal TOUT goes high. As a result, the count value reaches 8 at timing t8. In this example, the set bottom number is 8, so the count value reaches the set bottom number and the set signal ST is asserted. This forcibly turns on the switching element 3.

[0048] That is, as in the above embodiment, ((set bottom number) - (detected bottom number)) x (resonance time) = timeout time, and the set signal ST is asserted when the timeout time has elapsed since the last detected bottom (the fourth bottom in FIG. 7). By doing this, the switching frequency does not increase even under light loads (when the set bottom number is large), and efficiency is improved compared to the above comparative example. For example, in FIG. 5, even when timeout operation is performed under light loads, the characteristics of the correspondence relationship between output power and switching frequency do not change from when timeout operation is not performed (i.e., the solid line).

[0049] The resonance time is determined by the inductance and parasitic capacitance of the transformer Tr, and it is more effective to detect it using a resonance time detector as in the above embodiment when dealing with various applications. However, the resonance time may be set by, for example, a resistor connected externally to the power supply control device 1 without providing a resonance time detector.

[0050] Furthermore, the resonance time does not necessarily have to be detected between the first and second bottoms as shown in Figure 7, but it is preferable to detect it between the first and second bottoms because this allows the voltage value Vr to be determined as quickly as possible.

[0051] Furthermore, the capacitance of the capacitors 80E, 80F does not necessarily have to be 1:1, but if it is 1:1, it is possible to set Ia=Ib, and the configuration of the current mirror 80H can be simplified.

[0052] <Modification> Next, an embodiment according to a modified example of the present disclosure will be described. Fig. 8 is a diagram showing an example configuration of an isolated DC / DC converter according to a modified example. The isolated DC / DC converter 100 shown in Fig. 8 includes a power supply control device 20, a primary side circuit 101, a secondary side circuit 102, and an auxiliary circuit 103, and is configured as an AHB (Asymmetric Half Bridge) flyback converter. The isolated DC / DC converter 100 converts an input voltage Vin, which is a DC voltage, into an output voltage Vout, which is also a DC voltage. The output voltage Vout is supplied to a load Z.

[0053] The primary circuit 101 includes a high-side switch QH, a low-side switch QL, a primary-side inductor Lp, a resonant inductor Lr, a resonant capacitor Cr, and a current detection resistor Rcs. The high-side switch QH and the low-side switch QL may be built into the power supply control device 1.

[0054] The high-side switch QH and the low-side switch QL are both configured with N-channel MOSFETs. However, the high-side switch QH is not limited to this and may be configured with, for example, a P-channel MOSFET. The high-side switch QH and the low-side switch QL form a half bridge.

[0055] The drain of the high-side switch QH is connected to the terminal to which the input voltage Vin is applied. The source of the high-side switch QH and the drain of the low-side switch QL are connected at node Nd. The source of the low-side switch QL is connected to one terminal of the current detection resistor Rcs. The other terminal of the current detection resistor Rcs is connected to the ground terminal.

[0056] The primary inductor Lp and the resonant inductor Lr are included in, for example, the primary winding of a transformer. In this case, the resonant inductor Lr corresponds to the leakage inductance in the primary winding. Note that the resonant inductor Lr may include an inductor provided separately from the transformer. One end of the resonant inductor Lr is connected to a node Nd. The other end of the resonant inductor Lr is connected to one end of the primary inductor Lp. The other end of the primary inductor Lp is connected to one end of the resonant capacitor Cr. The other end of the resonant capacitor Cr is connected to the source of the low-side switch QL.

[0057] The power supply control device 20 is a semiconductor device for controlling the isolated DC / DC converter 100, and has an HO terminal, an LO terminal, a CS terminal, a VCC terminal, a ZT terminal, a GND terminal, and an FB terminal as external terminals. The internal configuration of the power supply control device 20 will be described later.

[0058] A gate signal G1 output from the HO terminal is applied to the gate of the high-side switch QH. The high-side switch QH is in an on or off state depending on the level of the gate signal G1. A gate signal G2 output from the LO terminal is applied to the gate of the low-side switch QL. The low-side switch QL is in an on or off state depending on the level of the gate signal G2. The high-side switch QH and the low-side switch QL are switched complementarily, as will be described later. However, there is also a simultaneous off period (dead time) during which both the high-side switch QH and the low-side switch QL are in an off state.

[0059] One end of the current detection resistor Rcs is connected to the CS terminal. The current flowing through the current detection resistor Rcs is converted into a voltage by the current detection resistor Rcs and becomes a current detection signal Vcs. The current detection signal Vcs is generated at the CS terminal. As will be described later, the current detection signal Vcs is used to determine the turn-off timing (i.e., the on-time) of the high-side switch QH.

[0060] The secondary circuit 102 includes a secondary inductor Ls, a rectifier diode Ds, a smoothing capacitor Cs, and a feedback circuit 105.

[0061] The secondary-side inductor Ls is included in the transformer and is magnetically coupled to the primary-side inductor Lp. The rectifier diode Ds and smoothing capacitor Cs form a rectifying and smoothing circuit 104. The anode of the rectifier diode Ds is connected to one end of the secondary-side inductor Ls. The cathode of the rectifier diode Ds is connected to one end of the smoothing capacitor Cs. The other end of the secondary-side inductor Ls and the other end of the smoothing capacitor Cs are each connected to a ground terminal.

[0062] The feedback circuit 105 has a light-emitting diode PD and a phototransistor PT. The phototransistor PT is included in the primary side circuit 101. The light-emitting diode PD and the phototransistor PT form a photocoupler.

[0063] An output voltage Vout is generated at one end of the smoothing capacitor Cs. A current corresponding to the difference between the divided voltage of the output voltage Vout and the target voltage flows through the light-emitting diode PD. The light emitted by the light-emitting diode PD is received by the phototransistor PT. The phototransistor PT is connected to the FB terminal. Here, as shown in FIG. 9 (described later), the FB terminal is connected to the application terminal of the reference voltage Vref via a pull-up resistor 205. A voltage drop occurs in the pull-up resistor 205 due to the current flowing through the phototransistor PT, and a feedback voltage Vfb is generated at the FB terminal. In other words, the feedback circuit 105 and the pull-up resistor 205 constitute a feedback voltage generation unit.

[0064] The auxiliary circuit 103 includes an auxiliary inductor Ld, voltage-dividing resistors Rp1 and Rp2, a diode Dp, and a capacitor Cp. The auxiliary inductor Ld is included in the transformer and is magnetically coupled to the primary inductor Lp. One end of the auxiliary inductor Ld is connected to the anode of the diode Dp. The cathode of the diode Dp is connected to one end of the capacitor Cp. The other end of the auxiliary inductor Ld and the other end of the capacitor Cp are each connected to the ground terminal. One end of the capacitor Cp is connected to the VCC terminal. The auxiliary voltage Vd generated at one end of the auxiliary inductor Ld is rectified and smoothed by the diode Dp and the capacitor Cp to become the power supply voltage Vcc. The power supply voltage Vcc is applied to the VCC terminal.

[0065] The voltage dividing resistors Rp1 and Rp2 divide the auxiliary voltage Vd to generate the voltage Vzt that is applied to the ZT terminal. The voltage Vzt is used for bottom skip control, which will be described later.

[0066] 9 is a diagram showing the internal configuration of the power supply control device 20. The power supply control device 20 has a control logic unit 202, drivers 203 and 204, a pull-up resistor 205, a gain adding unit 206, a comparator 207, and a bottom skip control unit 208.

[0067] The control logic unit 202 controls the driving of the driver 203 by sending a driving signal Dr1 to the driver 203, and controls the driving of the driver 204 by sending a driving signal Dr2 to the driver 204. The driver 203 generates a gate signal G1 based on the driving signal Dr1 and outputs it from the HO terminal. The driver 204 generates a gate signal G2 based on the driving signal Dr2 and outputs it from the LO terminal.

[0068] As described above, the pull-up resistor 205 is used to generate the feedback voltage Vfb. The feedback voltage Vfb (FB terminal voltage) is amplified by the gain adding unit 206 based on a predetermined gain to generate an amplified voltage Vfb_g. The predetermined gain added by the gain adding unit 206 is a fixed value (e.g., 0.25). Vfb_g=Gain×Vfb.

[0069] A voltage Vfb_g is applied to the inverting input terminal (-) of the comparator 207. A current detection signal Vcs is applied to the non-inverting input terminal (+) of the comparator 207. The comparator 207 compares the voltage Vfb_g with the current detection signal Vcs, and outputs a comparison signal CP as the comparison result to the control logic unit 202. The comparison signal CP is used to determine the timing of turning off the high-side switch QH. In other words, the comparator 207 is configured as a turn-off control unit.

[0070] The bottom skip control unit 208 performs bottom skip control. Bottom skip control is a control for skipping the turn-on of the high-side switch QH by the number of bottoms of the half-bridge voltage Vhb generated at the node Nd (FIG. 8). The bottoms are the points where the half-bridge voltage Vhb becomes maximum. The bottom skip control unit 208 corresponds to an on-timing determination unit configured to generate an output signal (skip signal SK) for determining the timing to turn on the switching element (high-side switch QH).

[0071] The bottom skip control unit 208 includes a bottom number setting unit 208A and a bottom detection unit 208B. The bottom number setting unit 208A determines the number of bottoms to skip based on the feedback voltage Vfb. The method for setting the number of bottoms here is the same as in the embodiment described above. That is, in a light load state where the output power (=Vout×Iout) (FIG. 8) is small, the feedback voltage Vfb is small and the number of bottoms is large. This prevents the switching frequency from increasing in a light load state, thereby reducing losses. Furthermore, in a heavy load state where the output power is large, the feedback voltage Vfb is large and the number of bottoms is determined to be 1. That is, in a heavy load state, bottom skip control is performed with the number of bottoms set to 1.

[0072] The bottom detection unit 208B detects bottoms by detecting that the ZT voltage Vzt of the ZT terminal crosses a predetermined threshold Vzt_th in the negative direction. When the number of detected bottoms reaches a set number of bottoms, a skip signal SK indicating this is output from the bottom skip control unit 208 to the control logic unit 202. The skip signal SK is used to determine the timing at which the high-side switch QH is turned on.

[0073] Next, the operation of the isolated DC / DC converter 100 in a light load state will be described with reference to Fig. 10. Fig. 10 is a timing chart showing an example of operation in a light load state. Note that Fig. 10 shows example waveforms of the gate signals G1 and G2, the half-bridge voltage Vhb, the primary current Ir, and the ZT voltage Vzt.

[0074] First, when the primary current Ir reaches the peak current Ipeak, the gate signal G1 is switched to low level, and the high-side switch QH is turned off (timing t21). After that, when the dead time Tdead has elapsed, the gate signal G2 is switched to high level, and the low-side switch QL is turned on (timing t22).

[0075] In a light load state, when a predetermined on-time Ton_min has elapsed since the low-side switch QL was turned on (timing t22), the control logic unit 202 switches the gate signal G2 to low level to turn off the low-side switch QL (timing t23). The on-time Ton_min can be set by a setting resistor (not shown) connected to the outside of the power supply control device 20. The on-time Ton_min ensures that the on-time of the low-side switch QL is at least half the resonance period of Lr and Cr (π × √(Lr × Cr)) in order to efficiently send power to the secondary side.

[0076] At timing t23, when both the high-side switch QH and the low-side switch QL are turned off, the half-bridge voltage Vhb begins to resonate. At this time, the ZT voltage Vzt also begins to resonate. Here, when the ZT voltage Vzt crosses the threshold voltage Vzt_th in the negative direction, the bottom detection unit 208B detects a bottom. In a light load state, the feedback voltage Vfb is small, so the number of bottoms set by the bottom number setting unit 208A is large. In the example of FIG. 10, the set number of bottoms is 3. When the number of detected bottoms reaches the set number of bottoms, the bottom skip control unit 208 outputs a skip signal SK indicating this (timing t24).

[0077] At timing t25, which is a predetermined delay time Tdly after timing t24, the control logic unit 2 switches the gate signal G1 to high level and turns on the high-side switch QH, which increases the primary current Ir, and the same operation is repeated thereafter.

[0078] A configuration similar to the configuration for timeout operation in the previously described embodiment (FIG. 6) can be applied to the bottom skip control unit 208 of the power supply control device 20 according to this modification. That is, even if the resonance of the half-bridge voltage Vhb and the ZT voltage Vzt decay and a bottom cannot be detected midway through, a timeout signal TOUT can be generated for each resonance time, and when the number of bottoms reaches a set number, a skip signal SK indicating this can be output. Therefore, this modification also makes it possible to prevent a decrease in efficiency under light load due to the timeout operation.

[0079] As another modification, the timeout operation of the present disclosure can also be applied to, for example, a critical mode PFC (power factor correction circuit).

[0080] <Application example> FIG. 11 is a diagram showing an AC adapter 150 as an example of an application to which an isolated DC / DC converter including a power supply control device according to various embodiments of the present disclosure is applied.

[0081] The AC adapter 150 shown in FIG. 11 includes an adapter main body 151, a DC plug 152, and a cable 153. The adapter main body 151 is provided with an attachment plug 151A. The attachment plug 151A is connectable to an outlet. The adapter main body 151 has an AC / DC converter 110 built in. The AC / DC converter 110 has an isolated DC / DC converter and an input stage (not shown) provided before the isolated DC / DC converter. The input stage is a circuit that converts an AC voltage into an input voltage Vin, and includes an input filter, a diode bridge, a smoothing capacitor, etc.

[0082] The adapter main body 151 and the DC plug 152 are connected by a cable 153. An AC voltage input to the attachment plug 151A is converted into an output voltage Vout, which is a DC voltage, by the AC / DC converter 110 and output from the DC plug 152 via the cable 153. A device such as a smartphone or a tablet can be connected to the DC plug 152.

[0083] As described above, the present disclosure can improve the efficiency of the isolated DC / DC converter, thereby realizing an AC adapter 150 with excellent efficiency.

[0084] <Other> In addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0085] <Additional Notes> As described above, the power supply control device (1) according to one aspect of the present disclosure: A power supply control device used in an isolated DC / DC converter (15) configured to generate an output voltage (Vout) by switching at least one switching element (3), an on-timing determination unit (80) configured to generate an output signal (ST) for determining the timing to turn on any one of the at least one switching elements (3); the on-timing determination unit has a bottom detection unit (80B) configured to detect a bottom of a resonance voltage (Vzt) generated when any one of the at least one switching elements (3) is turned off, The on-timing determination unit determines whether the bottom is detected or not. The output signal indicating the turning on of the switching element is output at the timing when the timeout time, which is expressed as ((set target bottom number) - (detected bottom number)) x (resonance time) = timeout time, has elapsed (first configuration).

[0086] In the first configuration, the on-timing determination unit (80) may be configured to include a resonance time detection unit (80C) configured to detect the resonance time based on the detection result by the bottom detection unit (second configuration).

[0087] In the second configuration, the resonance time detection section may detect the time from the first bottom to the second bottom detected by the bottom detection section as the resonance time (third configuration).

[0088] In the first configuration, the resonance time may be set based on a setting element connected to the outside of the power supply control device (fourth configuration).

[0089] In any one of the first to fourth configurations, the on-timing determination unit (80) includes a timeout signal generation unit (801) configured to generate a pulsed timeout signal (TOUT) for each resonance time after the bottom is no longer detected by the bottom detection unit; The configuration may also include an output section (80M) that outputs the output signal indicating that the switching element is turned on when the sum of the number of bottoms detected by the bottom detection section and the number of timeout signals generated reaches the target bottom number (fifth configuration).

[0090] In the fifth configuration, the timeout signal generating unit (801) includes a first capacitor (80E), a second capacitor (80F), and a comparator (80J) configured to output the timeout signal; the comparator is configured to receive a first voltage (Va) of the first capacitor and a second voltage (Vb) of the second capacitor; When a predetermined first bottom is detected, charging of the first capacitor is started, and when a second bottom subsequent to the first bottom is detected, the charging is stopped, and the first voltage at that time is determined as a reference voltage (Vrt); charging of the second capacitor is started when a third bottom subsequent to the second bottom is detected, and when the second voltage exceeds the reference voltage, the second capacitor is discharged based on the output of the comparator, and thereafter, charging of the second capacitor is resumed based on the output of the comparator; The gradient of the increase in the second voltage due to charging of the second capacitor may be the same as the gradient of the increase in the first voltage due to charging of the first capacitor (sixth configuration).

[0091] In the sixth configuration, the timeout signal generating unit (801) includes a current mirror (80H) configured to generate currents (Ia, Ib) for charging the first capacitor and the second capacitor, respectively; The first capacitor and the second capacitor may have the same capacitance (seventh configuration).

[0092] An isolated DC / DC converter (15) according to an aspect of the present disclosure is an isolated DC / DC converter as a flyback converter including the power supply control device (1) of any one of the first to seventh configurations, and includes: a transformer (Tr) including a primary winding (w1) and a secondary winding (w2); and the switching element (3) including a first main electrode (e.g., a drain) connected to the primary winding, The resonant voltage (Vzt) is a voltage based on the resonance of the voltage of the first main electrode (eighth configuration).

[0093] An isolated DC / DC converter (100) according to an aspect of the present disclosure is an isolated DC / DC converter serving as a flyback converter including a power supply control device (20) having any one of the first to seventh configurations, a half bridge having a high-side switch (QH) and a low-side switch (QL) as the switching element; a resonant inductor (Lr), a primary inductor (Lp), and a resonant capacitor (Cr) connected to a connection node (Nd) at which the high-side switch and the low-side switch are connected; the resonant voltage (Vzt) is a voltage based on resonance that occurs in the voltage (Vhb) of the connection node when the low-side switch is turned off, The on-timing determination unit (208) is configured to generate the output signal (SK) for determining the timing to turn on the high-side switch (ninth configuration).

[0094] Moreover, an isolated DC / DC converter according to an embodiment of the present disclosure includes a power supply control device having any one of the first to seventh configurations (tenth configuration).

[0095] Moreover, an AC adapter (150) according to an aspect of the present disclosure includes an AD / DC converter (110) having the isolated DC / DC converter of the tenth configuration (eleventh configuration). [Industrial Applicability]

[0096] The present disclosure can be used in isolated DC / DC converters for various applications. [Explanation of symbols]

[0097] 1,1X Power Control Unit 2 Drive control unit 3 Switching elements 4 Current detection section 5 pull-up resistors 6 Gain adding section 7 Comparators 8 Set signal generator 8A Bottom number setting section 8B Bottom detection unit 8C Timeout control section 10 Feedback Circuit 15 Flyback Converter 20 Power supply control device 80 Set signal generator 80A Bottom number setting section 80B Bottom detection unit 80C Resonance time detector 80D Switch 80E, 80F capacitors 80G Switch 80H Current Mirror 80I Switch 80J Comparator 80K OR circuit 80L 3rd bottom detection unit 80M set signal output section 100 Isolated DC / DC Converter 101 Primary side circuit 102 Secondary circuit 103 Auxiliary circuit 104 Rectifier smoothing circuit 105 Feedback Circuit 110 AC / DC converter 150 AC adapter 151 Adapter body 151A plug 152 DC plug 153 Cable 202 Control Logic Section 203,204 Driver 205 pull-up resistor 206 Gain adding section 207 Comparator 208 Bottom skip control section 208A Bottom number setting section 208B Bottom detection unit C1 smoothing capacitor C2 capacitor CMP Comparator Cp capacitor Cr Resonant Capacitor Cs smoothing capacitor D1 Diode DB1 Diode Bridge Dp diode Ds rectifier diode F1 fuse Ld Auxiliary inductor Lp primary inductor Lr Resonant inductor Ls Secondary inductor Nd node PD Light Emitting Diode PM1, PM2, PM3 PMOS transistors PT phototransistor QH High-side switch QL Low-Side Switch R1, R2 voltage dividing resistors Rcs Current detection resistor Rp1, Rp2 voltage dividing resistors SHT One-shot circuit Tout output end Tr transformer Z load w1 Primary winding w2 Secondary winding w3 Auxiliary winding

Claims

1. 1. A power supply control device used in an isolated DC / DC converter configured to generate an output voltage by switching at least one switching element, an on-timing determination unit configured to generate an output signal for determining a timing to turn on any of the at least one switching element; the on-timing determination unit has a bottom detection unit configured to detect a bottom of a resonance voltage generated when any of the at least one switching element is turned off, The on-timing determination unit determines whether the bottom is detected or not. A power supply control device that outputs the output signal indicating the turning on of the switching element at a timing when the timeout time, which is expressed as ((set target bottom number) - (detected bottom number)) x (resonance time) = timeout time, has elapsed.

2. 2. The power supply control device according to claim 1, wherein the on-timing determination unit includes a resonance time detection unit configured to detect the resonance time based on a detection result by the bottom detection unit.

3. The power supply control device according to claim 2 , wherein the resonance time detection unit detects the time from a first bottom to a second bottom detected by the bottom detection unit as the resonance time.

4. 2. The power supply control device according to claim 1, wherein the resonance time is settable based on a setting element connected to an outside of the power supply control device.

5. The on-timing determination unit a timeout signal generating unit configured to generate a pulsed timeout signal for each resonance time after the bottom is no longer detected by the bottom detecting unit; an output unit that outputs the output signal indicating that the switching element is turned on when the sum of the number of bottoms detected by the bottom detection unit and the number of the generated timeout signals reaches the target number of bottoms; The power supply control device of claim 1 , further comprising:

6. the timeout signal generator includes a first capacitor, a second capacitor, and a comparator configured to output the timeout signal; the comparator is configured to receive a first voltage of the first capacitor and a second voltage of the second capacitor; Charging of the first capacitor is started when a predetermined first bottom is detected, and the charging is stopped when a second bottom subsequent to the first bottom is detected, and the first voltage at that time is determined as a reference voltage; charging of the second capacitor is started when a third bottom subsequent to the second bottom is detected, and when the second voltage exceeds the reference voltage, the second capacitor is discharged based on the output of the comparator, and thereafter, charging of the second capacitor is resumed based on the output of the comparator; 6. The power supply control device according to claim 5, wherein a gradient at which the second voltage increases due to charging of the second capacitor is the same as a gradient at which the first voltage increases due to charging of the first capacitor.

7. the timeout signal generator includes a current mirror configured to generate a current for charging the first capacitor and the second capacitor, The power supply control device according to claim 6 , wherein the first capacitor and the second capacitor have the same capacitance.

8. An isolated DC / DC converter as a flyback converter including the power supply control device according to any one of claims 1 to 7, a transformer including a primary winding and a secondary winding; and the switching element including a first main electrode connected to the primary winding, The resonant voltage is a voltage based on resonance of the voltage of the first main electrode.

9. An isolated DC / DC converter as a flyback converter including the power supply control device according to any one of claims 1 to 7, a half bridge having a high-side switch and a low-side switch as the switching element; a resonant inductor, a primary inductor, and a resonant capacitor connected to a connection node at which the high-side switch and the low-side switch are connected; Equipped with the resonant voltage is a voltage based on resonance that occurs in the voltage of the connection node when the low-side switch is turned off, The on-timing determination unit generates the output signal for determining the timing to turn on the high-side switch.

10. An isolated DC / DC converter comprising the power supply control device according to any one of claims 1 to 7.

11. An AC adapter comprising an AD / DC converter having the isolated DC / DC converter according to claim 10.

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