Semiconductor device

Abstract

To improve a breakdown voltage while maintaining an on-resistance of a semiconductor device.SOLUTION: A semiconductor device 10 includes: a semiconductor layer 12; a plurality of gate trenches 14; a plurality of source trenches 16; a plurality of gate electrodes 50 buried in the plurality of gate trenches 14, respectively; a plurality of source electrodes 52 buried in the plurality of source trenches 16, respectively; a source wiring 24 electrically connected to the plurality of source electrodes 52; and a plurality of contacts 26 connecting the source wiring 24 to the semiconductor layer 12. The semiconductor layer 12 includes a plurality of mesa parts 28. Each mesa part is defined between one of the plurality of gate trenches 14 and one of the plurality of source trenches 16 adjacent to the gate trench 14 in a first direction. In each mesa part 28, a distance between a contact 26 and each source trench 16 is smaller than a distance between the contact 26 and each gate trench 14.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a MISFET having a trench gate structure in which a gate electrode is buried in a gate trench. In the MISFET described in Patent Document 1, a plurality of source contact holes in which source plug electrodes are buried are formed alternately with a plurality of gate trenches. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-125649

[0004] [overview] In a semiconductor device having a trench gate structure, it is desired to improve the breakdown voltage while maintaining the on-resistance (or to reduce the on-resistance while maintaining the breakdown voltage).

[0005] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor layer having a first surface and a second surface opposite the first surface, the semiconductor layer including a drift region of a first conductivity type, a body region of a second conductivity type located on the drift region, and a source region of the first conductivity type located on the body region, a plurality of gate trenches having walls extending from the first surface into the semiconductor layer, a plurality of source trenches having walls extending from the first surface into the semiconductor layer, an insulating layer located on the first surface of the semiconductor layer and covering the walls of the gate trenches and the walls of the source trenches, a plurality of gate electrodes respectively embedded in the gate trenches, a plurality of source electrodes respectively embedded in the source trenches, a source wiring located on the insulating layer and electrically connected to the source electrodes, and a plurality of contacts connecting the source wiring to the semiconductor layer. The semiconductor layer includes a plurality of mesa portions, each mesa portion being defined between one of the gate trenches and one of the source trenches adjacent to the gate trench in a first direction. Each mesa includes a contact region of the second conductivity type in contact with one of the contacts, the contact region containing impurities of the second conductivity type at a higher concentration than the body region, and in each mesa, a distance between the contact and the source trench is smaller than a distance between the contact and the gate trench.

[0006] Other features and aspects will become apparent from the following detailed description, drawings, and claims. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is an enlarged view of a portion of FIG. [Figure 3] FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG. [Figure 4]FIG. 4 is a schematic cross-sectional view of the semiconductor device taken along line F4-F4 in FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line F5-F5 in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of the semiconductor device taken along line F6-F6 in FIG. [Figure 7] FIG. 7 is a graph showing breakdown voltages of semiconductor devices according to a number of experimental examples. [Figure 8] FIG. 8 is a graph showing threshold voltages of semiconductor devices according to a number of experimental examples. [Figure 9] FIG. 9 is a schematic plan view of an exemplary semiconductor device according to the second embodiment. [Figure 10] FIG. 10 is an enlarged view of a portion of FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view of the semiconductor device taken along line F11-F11 in FIG. [Figure 12] FIG. 12 is a schematic plan view of a semiconductor device according to a modified example. [Figure 13] FIG. 13 is a schematic cross-sectional view of the semiconductor device shown in FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view of a semiconductor device according to a modified example. [Figure 15] FIG. 15 is a schematic cross-sectional view of a semiconductor device according to a modified example.

[0008] [Detailed explanation] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. The same reference numerals refer to the same elements throughout the drawings and detailed description. The drawings may not be to scale, and the relative size, proportions, and depictions of elements in the drawings may be exaggerated for clarity, explanation, and convenience.

[0009] The following detailed description provides a comprehensive understanding of the described methods, devices, and / or systems. Modifications and equivalents of the described methods, devices, and / or systems will be apparent to those skilled in the art. Except for operations that necessarily occur in a particular order, the order of operations is illustrative and may be changed as would be apparent to one skilled in the art. Descriptions of functions and structures well known to those skilled in the art may be omitted. Example embodiments may have different forms and are not limited to the described examples.

[0010] First Embodiment An exemplary semiconductor device 10 according to a first embodiment will be described with reference to Figures 1 to 6. Figure 1 is a schematic plan view of the semiconductor device 10. Figure 2 is an enlarged view of a portion of Figure 1. Figures 3 to 6 are schematic cross-sectional views of the semiconductor device 10. As will be described below, the semiconductor device 10 may be configured as a trench-gate MISFET.

[0011] (Overall structure of semiconductor device) The semiconductor device 10 includes a semiconductor layer 12 having a first surface 12A and a second surface 12B opposite to the first surface 12A (see FIG. 3, etc.), a plurality of gate trenches 14 having walls 14A extending from the first surface 12A into the semiconductor layer 12, and a plurality of source trenches 16 having walls 16A extending from the first surface 12A into the semiconductor layer 12. The semiconductor layer 12 may be formed of, for example, silicon (Si).

[0012] In this disclosure, the term "gate trench" refers to a trench in which at least an electrode to which a gate voltage is applied (e.g., the gate electrode 50 described below) is disposed. The term "source trench" refers to a trench in which no electrode to which a gate voltage is applied is disposed, and in which at least an electrode to which a source voltage is applied (e.g., the source electrode 52 described below) is disposed. It should be noted that in addition to the electrode to which the gate voltage is applied, another electrode to which a voltage different from the gate voltage is applied (e.g., the first field plate electrode 54 described below) may also be disposed in the gate trench 14.

[0013] Additionally, multiple trenches may be interconnected in semiconductor device 10. In such cases, it should be understood that the terms "gate trench" and "source trench" may be used to refer to the trench portions having the electrode arrangements described above.

[0014] 1 and other drawings, the Z-axis direction of the mutually orthogonal X, Y, and Z axes is a direction that intersects (e.g., is perpendicular to) the first surface 12A of the semiconductor layer 12. As used herein, the term "plan view" refers to a view drawn from a perspective looking down on the object from above along the Z-axis direction, unless explicitly stated otherwise.

[0015] 1, the semiconductor layer 12 includes two side surfaces 12X1 and 12X2 extending along the X-axis direction in a plan view and two side surfaces 12Y1 and 12Y2 extending along the Y-axis direction in a plan view. The first surface 12A (and the second surface 12B) of the semiconductor layer 12 is surrounded by the side surfaces 12X1, 12Y1, 12X2, and 12Y2 and may have a rectangular shape in a plan view.

[0016] Each of the multiple gate trenches 14 extends in the X-axis direction in plan view. Each of the multiple gate trenches 14 has a width in the Y-axis direction. In the present disclosure, the width direction of the gate trench 14 may be referred to as the first direction, and the longitudinal direction may be referred to as the second direction. The first direction, which is the width direction, may be perpendicular to the second direction, which is the longitudinal direction. In the illustrated example, the longitudinal direction of the gate trench 14 is the X-axis direction, and the width direction is the Y-axis direction. Similarly, each of the multiple source trenches 16 extends in the X-axis direction in plan view. Each of the multiple source trenches 16 has a width in the Y-axis direction. In the illustrated example, the longitudinal direction of the source trench 16 is the X-axis direction, and the width direction is the Y-axis direction. In the present embodiment, the multiple gate trenches 14 and the multiple source trenches 16 may be arranged so that one gate trench 14 and one source trench 16 are alternately arranged in the first direction.

[0017] Optionally, the semiconductor device 10 may include connection trenches 18A and 18B communicating with the gate trench 14 and the source trench 16. In the example shown in FIG. 1 , the connection trench 18A may extend in the Y-axis direction so as to connect adjacent gate trenches 14 and source trenches 16. Furthermore, the connection trench 18B may extend so as to connect between the two ends of the outermost trench (the gate trench 14 in the example of FIG. 1 ) in a set of multiple gate trenches 14 and multiple source trenches 16 that are arranged alternately.

[0018] The semiconductor device 10 includes an insulating layer 20 located on the first surface 12A of the semiconductor layer 12. In one example, the insulating layer 20 may include at least one of a silicon oxide (SiO2) layer, a silicon nitride (SiN) layer, and a silicon oxynitride (SiON) layer.

[0019] The semiconductor device 10 may include a gate wiring 22 located on the insulating layer 20. The gate wiring 22 may include a gate pad portion 22P, a first gate wiring portion 22Y1 and a second gate wiring portion 22Y2 extending in the Y-axis direction, and a third gate wiring portion 22X extending in the X-axis direction. In the example shown in FIG. 1 , the gate pad portion 22P is located near a corner of the semiconductor device 10 (for example, a position where the side surface 12Y1 and the side surface 12X2 of the semiconductor layer 12 intersect). The first gate wiring portion 22Y1 is located near the side surface 12Y1 of the semiconductor layer 12. The second gate wiring portion 22Y2 is located near the side surface 12Y2 of the semiconductor layer 12. The third gate wiring portion 22X is located near the side surface 12X2 of the semiconductor layer 12. The first gate wiring portion 22Y1 is connected to the gate pad portion 22P. The second gate wiring portion 22Y2 is connected to the third gate wiring portion 22X. The third gate wiring portion 22X connects the gate pad portion 22P and the second gate wiring portion 22Y2.

[0020] The gate trenches 14 may intersect with the first gate wiring portion 22Y1 or the second gate wiring portion 22Y2 in a plan view. The source trenches 16 may intersect with the first gate wiring portion 22Y1 or the second gate wiring portion 22Y2 in a plan view.

[0021] The semiconductor device 10 includes a source wiring 24 located on the insulating layer 20. The source wiring 24 is spaced apart from the gate wiring 22. The source wiring 24 may include an inner source wiring portion 24A and a peripheral source wiring portion 24B. The inner source wiring portion 24A is electrically connected to the peripheral source wiring portion 24B. In the illustrated example, the inner source wiring portion 24A and the peripheral source wiring portion 24B are integrally formed. The inner source wiring portion 24A may be at least partially surrounded by the gate wiring 22 in a planar view. The peripheral source wiring portion 24B may surround the gate wiring 22 in a planar view.

[0022] Each of the plurality of gate trenches 14 may overlap both the inner source wiring portion 24A and the peripheral source wiring portion 24B in plan view. Each of the plurality of source trenches 16 may overlap both the inner source wiring portion 24A and the peripheral source wiring portion 24B in plan view.

[0023] The semiconductor device 10 includes a plurality of contacts 26 that connect the source wiring 24 to the semiconductor layer 12. The plurality of contacts 26 may be located below the inner source wiring portion 24A. Each contact 26 may be located between one of the plurality of gate trenches 14 and one of the plurality of source trenches 16 adjacent to the gate trench 14 in the first direction (the Y-axis direction in the illustrated example).

[0024] The semiconductor layer 12 includes a plurality of mesas 28. Each mesa 28 is defined between one of the plurality of gate trenches 14 and one of the plurality of source trenches 16 adjacent to the gate trench 14 in the first direction. Each mesa 28 is in contact with one of the plurality of contacts 26.

[0025] The semiconductor device 10 may further include a gate electrode contact 30, a source electrode contact 32, and a field plate electrode contact 34. The gate electrode contact 30 may be arranged in a region where the gate wiring 22 and the gate trench 14 overlap in a plan view. The gate electrode contact 30 is connected to the gate electrode 50, as described later with reference to FIG. 5. The source electrode contact 32 may be arranged in a region where the source wiring 24 and the source trench 16 overlap in a plan view. The source electrode contact 32 is connected to the source electrode 52, as described later with reference to FIGS. 4 and 6. The field plate electrode contact 34 may be arranged in a region where the source wiring 24 and the connection trench 18A overlap in a plan view. The field plate electrode contact 34 may be arranged in a region where the inner source wiring portion 24A or the outer periphery source wiring portion 24B overlaps with the connection trench 18A in a plan view. The field plate electrode contact 34 is connected to a first field plate electrode 54 and a second field plate electrode 56, as will be described later with reference to FIGS.

[0026] 1 is an example of the layout of the semiconductor device 10. For example, the number of gate trenches 14 and the number of source trenches 16 are not limited to those shown in the example, and can be determined arbitrarily according to the desired design of the semiconductor device 10.

[0027] (Details of trench gate structure) Fig. 2 is an enlarged view of the region indicated by the symbol F2 in Fig. 1. For ease of understanding, the source wiring 24 is omitted from Fig. 2. Fig. 3 is a schematic cross-sectional view of the semiconductor device 10 taken along the line F3-F3 in Fig. 2.

[0028] 3, the semiconductor layer 12 includes an n-type drain region 36. The drain region 36 may include at least a portion of the second surface 12B of the semiconductor layer 12. The n-type impurity concentration of the drain region 36 is 1×10 18 cm -3 More than 1×10 20 cm -3The drain region 36 may have a thickness of 40 μm or more and 450 μm or less.

[0029] The semiconductor layer 12 includes an n-type drift region 38. The drift region 38 may be located on the drain region 36. The drift region 38 may contain n-type impurities at a lower concentration than the drain region 36. The n-type impurity concentration of the drift region 38 is 1×10 15 cm -3 More than 1×10 18 cm -3 The drift region 38 may have a thickness of 1 μm or more and 25 μm or less.

[0030] The semiconductor layer 12 includes a p-type body region 40 located on the drift region 38. The p-type impurity concentration of the body region 40 is 1×10 16 cm -3 More than 1×10 18 cm -3 The body region 40 may have a thickness of not less than 0.5 μm and not more than 1.5 μm.

[0031] The semiconductor layer 12 includes an n-type source region 42 located on the body region 40. The source region 42 may include at least a portion of the first surface 12A of the semiconductor layer 12. The source region 42 may include a higher concentration of n-type impurities than the drift region 38. The n-type impurity concentration of the source region 42 is 1×10 19 cm -3 More than 1×10 21 cm -3 The source region 42 may have a thickness of 0.1 μm or more and 1 μm or less.

[0032] In one example, the drift region 38 may be formed from a Si substrate, and the drift region 38, the body region 40, and the source region 42 may be formed from a Si epitaxial layer.

[0033] In this disclosure, n-type may be referred to as the first conductivity type, and p-type may be referred to as the second conductivity type. The n-type impurities may include, for example, phosphorus (P), arsenic (As), and / or antimony (Sb). The p-type impurities may include, for example, boron (B), aluminum (Al), gallium (Ga), and / or indium (In).

[0034] The semiconductor device 10 may include a drain electrode 44 in contact with the second surface 12B of the semiconductor layer 12. The drain electrode 44 is electrically connected to the drain region 36. The drain electrode 44 may be formed from at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), Al, a Cu alloy, and an Al alloy.

[0035] As described above, the plurality of gate trenches 14 have walls 14A that extend from the first surface 12A into the semiconductor layer 12. More specifically, each of the plurality of gate trenches 14 may extend through the source region 42 and the body region 40 and may include a bottom 46 adjacent the drift region 38. For example, each of the plurality of gate trenches 14 may have a depth of not less than 1 μm and not more than 15 μm.

[0036] Similarly, the source trenches 16 have walls 16A extending from the first surface 12A into the semiconductor layer 12. More specifically, each of the source trenches 16 may extend through the source region 42 and the body region 40 and include a bottom 48 adjacent to the drift region 38. Each of the source trenches 16 may have a depth equal to that of each of the gate trenches 14. In this disclosure, the term "equal" in terms of two dimensions (including length, depth, distance, etc.) means that they are within a manufacturing variation range (e.g., ±20%). For example, each of the source trenches 16 may have a depth of 1 μm or more and 15 μm or less.

[0037] It should be understood that the walls 14A of the gate trench 14 and the walls 16A of the source trench 16 may extend in the Z-axis direction as shown, or may be angled relative to the Z-axis direction.

[0038] The semiconductor device 10 includes a plurality of gate electrodes 50 respectively embedded in a plurality of gate trenches 14. Each gate electrode 50 is separated from the semiconductor layer 12 by an insulating layer 20 covering a wall 14A of the gate trench 14 in which the gate electrode 50 is disposed. Each gate electrode 50 is disposed so as to face at least the body region 40 with the insulating layer 20 interposed therebetween.

[0039] The semiconductor device 10 includes a plurality of source electrodes 52 embedded in a plurality of source trenches 16, respectively. Each source electrode 52 is separated from the semiconductor layer 12 by an insulating layer 20 covering the wall 16A of the source trench 16 in which the source electrode 52 is disposed. Each source electrode 52 may be disposed at approximately the same position as each gate electrode 50 in the Z-axis direction. As will be described later with reference to FIG. 2, the source trench width W s is the gate trench width W g , the source electrode 52 disposed in the source trench 16 may have a width greater than that of the gate electrode 50 disposed in the gate trench 14.

[0040] The semiconductor device 10 may further include a first field plate electrode 54 embedded in the bottom 46 of each of the multiple gate trenches 14. The first field plate electrode 54 is separated from the gate electrode 50 (which is disposed in the same gate trench 14) by an insulating layer 20. The first field plate electrode 54 is separated from the semiconductor layer 12 by the insulating layer 20 covering the wall 14A of the gate trench 14 in which the first field plate electrode 54 is disposed. The first field plate electrode 54 may have a width smaller than that of the gate electrode 50.

[0041] The semiconductor device 10 may further include a second field plate electrode 56 embedded in the bottom 48 of each of the multiple source trenches 16. The second field plate electrode 56 is separated from the source electrode 52 (which is disposed in the same source trench 16) by an insulating layer 20. The second field plate electrode 56 is separated from the semiconductor layer 12 by the insulating layer 20 covering the wall 16A of the source trench 16 in which the second field plate electrode 56 is disposed. The second field plate electrode 56 may have a width smaller than that of the source electrode 52. Furthermore, the second field plate electrode 56 disposed in the source trench 16 may have a width larger than that of the first field plate electrode 54 disposed in the gate trench 14.

[0042] The gate electrode 50, the source electrode 52, the first field plate electrode 54, and the second field plate electrode 56 may be formed from conductive polysilicon. The multiple contacts 26 are partially embedded in the multiple mesa portions 28. Each of the multiple contacts 26 may at least partially face one of the multiple gate electrodes 50 in the first direction (the Y-axis direction in the illustrated example).

[0043] Each mesa 28 includes a p-type contact region 58 that contacts one of the contacts 26. The contact regions 58 contain impurities of the second conductivity type at a higher concentration than the body region 40. In one example, the p-type impurity concentration of the contact regions 58 is 1×10 19 cm -3 More than 1×10 21 cm -3 Each contact 26 can electrically connect the source wiring 24 located on the insulating layer 20 to a contact region 58 of the semiconductor layer 12.

[0044] Fig. 4 is a schematic cross-sectional view of the semiconductor device 10 taken along line F4-F4 in Fig. 2. As shown in Fig. 4, the source electrode contact 32 is connected to the source wiring 24 and the source electrode 52. As a result, the source wiring 24 is electrically connected to a plurality of source electrodes 52.

[0045] FIG. 5 is a schematic cross-sectional view of the semiconductor device 10 taken along line F5-F5 in FIG. 1. As shown in FIG. 5, a gate electrode contact 30 is connected to the gate wiring 22 and the gate electrode 50. This electrically connects the gate wiring 22 to the multiple gate electrodes 50. Two field plate electrode contacts 34 are connected to two ends 54A and 54B of a first field plate electrode 54, respectively. The ends 54A and 54B of the first field plate electrode 54 are located within the connection trench 18A. The first field plate electrode 54 extends in the X-axis direction from the end 54A to the end 54B. The end 54A is connected to the inner source wiring portion 24A of the source wiring 24 via one field plate electrode contact 34. The end 54B is connected to the outer source wiring portion 24B of the source wiring 24 via another field plate electrode contact 34.

[0046] FIG. 6 is a schematic cross-sectional view of the semiconductor device 10 taken along line F6-F6 in FIG. 1. As shown in FIG. 6, a source electrode contact 32 is connected to the source wiring 24 and the source electrode 52. Two field plate electrode contacts 34 are connected to two ends 56A and 56B of the second field plate electrode 56, respectively. The ends 56A and 56B of the second field plate electrode 56 are located within the connection trench 18A. The second field plate electrode 56 extends in the X-axis direction from the end 56A to the end 56B. The end 56A is connected to the inner source wiring portion 24A of the source wiring 24 via one field plate electrode contact 34 (which may be the same as the one connected to the end 54A of the first field plate electrode 54). The end 56B is connected to the outer source wiring portion 24B of the source wiring 24 via another field plate electrode contact 34 (which may be the same as the one connected to the end 54B of the first field plate electrode 54). Ends 56A and 56B of the second field plate electrode 56 may be connected to ends 54A and 54B of the first field plate electrode 54 shown in FIG. 5, respectively, within the connection trench 18A.

[0047] (contact placement) Next, the arrangement of the contacts 26 will be described in more detail with reference to Fig. 2. In this embodiment, the pitch P1 between two contacts 26 with one gate trench 14 disposed therebetween is the same as the pitch P2 between two contacts 26 with one source trench 16 disposed therebetween. That is, the multiple contacts 26 are arranged at a constant pitch in the first direction (the Y-axis direction in the illustrated example).

[0048] Each of the plurality of mesa portions 28 has a mesa width W m The mesa width W mcorresponds to the distance between one of the plurality of gate trenches 14 and one of the plurality of source trenches 16 adjacent to the gate trench 14 in the first direction. The plurality of mesa portions 28 have the same width in the first direction. Note that the semiconductor layer 12 may include other mesa portions (not shown) having different widths.

[0049] Each of the plurality of gate trenches 14 has a gate trench width W g Each of the plurality of source trenches 16 has a source trench width W s In this embodiment, the source trench width W s is the gate trench width W g is greater than.

[0050] In this way, the plurality of contacts 26 are arranged at a constant pitch in the first direction, and the source trench width W s is the gate trench width W g As a result, in each mesa portion 28, the contact 26 is positioned closer to the source trench 16 than to the gate trench 14. That is, in each mesa portion 28, the distance D1 between the contact 26 and the source trench 16 is smaller than the distance D2 between the contact 26 and the gate trench 14.

[0051] (Function of Semiconductor Device) The operation of the semiconductor device 10 will now be described. The gate electrode 50 embedded in the gate trench 14 faces the body region 40 of the semiconductor layer 12 via the insulating layer 20. When a predetermined voltage (gate voltage) is applied to the gate electrode 50, an inversion layer is formed in the p-type body region 40 along the wall 14A of the gate trench 14. The inversion layer in the body region 40 functions as a channel between the n-type source region 42 and the n-type drift region 38. In this way, the semiconductor device 10 can control the vertical flow of electrons between the source region 42 and the drift region 38.

[0052] In the semiconductor device 10, the mesa width W mHowever, by reducing the mesa width W m Reducing the distance D2 between the contact 26 and the gate trench 14 to reduce the on-resistance of the semiconductor device 10 also reduces the distance between the contact region 58 and the gate trench 14. The semiconductor layer 12 between the contact 26 and the gate trench 14 is the primary current path for the semiconductor device 10. However, as the distance D2 decreases, the voltage required to form an inversion layer along the wall 14A of the gate trench 14 increases due to the relatively high concentration of p-type impurities in the contact region 58. Therefore, reducing the distance D2 may increase the on-resistance of the semiconductor device 10.

[0053] On the other hand, the semiconductor layer 12 between the contact 26 and the source trench 16 is not a main current path in the semiconductor device 10. This is because in the body region 40, a channel is formed along the wall 14A of the gate trench 14 but not along the wall 16A of the source trench 16. Therefore, reducing the distance D1 between the contact 26 and the source trench 16 has only a limited effect on the on-resistance.

[0054] In this regard, in the semiconductor device 10 according to this embodiment, in each mesa portion 28, the distance D1 between the contact 26 and the source trench 16 is smaller than the distance D2 between the contact 26 and the gate trench 14. Therefore, it is possible to reduce the width of the mesa portion 28 while maintaining the distance between the gate trench 14 and the contact region 58 containing a relatively high concentration of p-type impurities. This makes it possible to improve the breakdown voltage of the semiconductor device 10 while maintaining the on-resistance. From another perspective, by making the distance D1 smaller than the distance D2, it is possible to increase the impurity concentration of the semiconductor layer 12 and reduce the on-resistance while maintaining the breakdown voltage of the semiconductor device 10.

[0055] FIG. 7 shows the breakdown voltage BV of semiconductor devices in several experimental examples. DSS 8 is a graph showing the threshold voltage V th7 and 8 are graphs showing the source trench width. The horizontal axis in Fig. 7 and Fig. 8 shows the source trench width in the same range.

[0056] The graphs in Figures 7 and 8 show the breakdown voltage BV when the source trench width is changed while the gate trench width and contact pitch are kept constant. DSS and threshold voltage V th 7 and 8 correspond to data obtained when the gate trench width is equal to the source trench width (an experimental example for comparison with this embodiment). The other points in the graphs correspond to data obtained when the source trench width is greater than the gate trench width (an experimental example equivalent to this embodiment).

[0057] As shown in FIG. 7, as the source trench width increases relative to the gate trench width, the breakdown voltage BV of the semiconductor device increases. DSS On the other hand, as shown in Figure 8, even if the source trench width is increased relative to the gate trench width, the threshold voltage V th is almost constant.

[0058] Increasing the source trench width while keeping the gate trench width and contact pitch constant corresponds to decreasing the distance between the contact and the source trench while maintaining the distance between the contact and the gate trench. Thus, the graphs of Figures 7 and 8 show that by making the distance D1 between the contact 26 and the source trench 16 smaller than the distance D2 between the contact 26 and the gate trench 14, the threshold voltage V th This shows that the breakdown voltage of the semiconductor device 10 can be improved while maintaining the above.

[0059] The semiconductor device 10 according to the first embodiment has the following advantages. (1) Each mesa portion 28 includes a contact region 58 of the second conductivity type that is in contact with one of the plurality of contacts 26, and the contact region 58 contains impurities of the second conductivity type at a higher concentration than the body region 40. In each mesa portion 28, a distance D1 between the contact 26 and the source trench 16 is smaller than a distance D2 between the contact 26 and the gate trench 14.

[0060] This configuration makes it possible to reduce the width of the mesa portion 28 while maintaining the distance between the contact region 58 containing a relatively high concentration of p-type impurities and the gate trench 14. Therefore, the breakdown voltage of the semiconductor device 10 can be improved while maintaining the on-resistance.

[0061] (2) Each of the plurality of gate trenches 14 has a gate trench width W g Each of the plurality of source trenches 16 has a source trench width W s and the source trench width W s is the gate trench width W g is greater than.

[0062] According to this configuration, in order to make the distance D1 smaller than the distance D2, the source trench width W s Since the distance is increased, the breakdown voltage of the semiconductor device 10 can be improved while maintaining the channel density (density of the gate trenches 14).

[0063] (3) The plurality of contacts 26 are partially embedded in the plurality of mesa portions 28, respectively, and each of the plurality of contacts 26 at least partially faces one of the plurality of gate electrodes in the first direction.

[0064] This configuration makes it possible to provide the contact 26 and contact region 58 that can be formed relatively easily even on the miniaturized mesa portion 28. (4) The semiconductor device 10 includes a first field plate electrode 54 embedded in the bottom 46 of each of the plurality of gate trenches 14, and a second field plate electrode 56 embedded in the bottom 48 of each of the plurality of source trenches 16. The first field plate electrode 54 is separated from the gate electrode 50 by the insulating layer 20, and the second field plate electrode 56 is separated from the source electrode 52 by the insulating layer 20.

[0065] According to this configuration, the first field plate electrode 54 is provided at the bottom 46 of each of the plurality of gate trenches 14, so that the breakdown voltage and switching speed of the semiconductor device 10 can be improved.

[0066] (5) The plurality of gate trenches 14 and the plurality of source trenches 16 are arranged such that one gate trench 14 and one source trench 16 are alternately arranged in the first direction.

[0067] This configuration reduces the channel density compared to when the source trench 16 is not provided, thereby reducing the total gate charge amount, thereby improving the switching speed of the semiconductor device 10.

[0068] Second Embodiment Next, an exemplary semiconductor device 100 according to a second embodiment will be described with reference to FIGS. 9 to 11. FIG. 9 is a schematic plan view of the semiconductor device 100. FIG. 10 is an enlarged view of a region designated by reference character F10 in FIG. 9. The source wiring 24 is omitted from FIG. 10 for ease of understanding. FIG. 11 is a schematic cross-sectional view of the semiconductor device 100 taken along line F11-F11 in FIG. 9 to 11. Components similar to those in the first embodiment are designated by the same reference characters. Detailed description of components similar to those in the first embodiment will be omitted.

[0069] As shown in FIGS. 9 to 11, in the second embodiment, the gate trench width W g is the source trench width W s10, the contacts 26 are arranged at a non-constant pitch in the first direction (the Y-axis direction in the illustrated example). Specifically, the pitch P1 between two contacts 26 between which one gate trench 14 is arranged is larger than the pitch P2 between two contacts 26 between which one source trench 16 is arranged.

[0070] As a result, in each mesa portion 28, the contact 26 is positioned closer to the source trench 16 than to the gate trench 14. That is, in each mesa portion 28, the distance D1 between the contact 26 and the source trench 16 is smaller than the distance D2 between the contact 26 and the gate trench 14.

[0071] As shown in Figure 11, the gate trench width W g is the source trench width W s Therefore, the source electrode 52 disposed in the source trench 16 may have a width equal to that of the gate electrode 50 disposed in the gate trench 14. Similarly, the second field plate electrode 56 disposed in the source trench 16 may have a width equal to that of the first field plate electrode 54 disposed in the gate trench 14.

[0072] In the semiconductor device 100 according to the second embodiment, in each mesa portion 28, the distance D1 between the contact 26 and the source trench 16 is smaller than the distance D2 between the contact 26 and the gate trench 14. This makes it possible to reduce the width of the mesa portion 28 while maintaining the distance between the gate trench 14 and the contact region 58 containing a relatively high concentration of p-type impurities. This makes it possible to improve the breakdown voltage of the semiconductor device 100 while maintaining the on-resistance. From another perspective, by making the distance D1 smaller than the distance D2, the impurity concentration of the semiconductor layer 12 can be increased to reduce the on-resistance while maintaining the breakdown voltage of the semiconductor device 10.

[0073] The semiconductor device 100 according to the second embodiment has the same advantages as the advantages (1) and (3) to (5) of the semiconductor device 10 according to the first embodiment. s Since the channel density can be increased compared to the semiconductor device 10 having the same dimensions except for the above, the on-resistance can be further reduced.

[0074] <Example of change> The above embodiment can be modified as follows. In the semiconductor device 10 according to the first embodiment, the multiple gate trenches 14 and the multiple source trenches 16 are arranged so that one gate trench 14 and one source trench 16 alternate in the first direction. Meanwhile, in another example, the multiple gate trenches 14 and the multiple source trenches 16 may be arranged so that one gate trench 14 and multiple source trenches 16 alternate in the first direction. Figures 12 and 13 show a semiconductor device 200 according to such a modified example.

[0075] Fig. 12 is a schematic plan view of the semiconductor device 200. Fig. 13 is a schematic cross-sectional view of the semiconductor device 200 taken along line F13-F13 in Fig. 12. As shown in Figs. 12 and 13, the gate trenches 14 and the source trenches 16 are arranged such that one gate trench 14 and multiple (two in the illustrated example) source trenches 16 are alternately arranged in a first direction (the Y-axis direction in the illustrated example). Therefore, each source trench 16 can be adjacent to another source trench 16 in the first direction without a gate trench 14 being disposed therebetween.

[0076] The semiconductor device 200 includes a plurality of inter-source contacts 202 that connect the source wiring 24 to the semiconductor layer 12. The plurality of inter-source contacts 202 may be located below the inner source wiring portion 24A. Each inter-source contact 202 is located between two source trenches 16 adjacent to each other in the first direction.

[0077] The semiconductor layer 12 includes a plurality of inter-source mesas 204. Each inter-source mesa 204 is defined between two of the plurality of source trenches 16 that are adjacent to each other in the first direction. Each inter-source mesa 204 is in contact with one of the plurality of inter-source contacts 202.

[0078] The plurality of inter-source contacts 202 are respectively partially embedded in the plurality of inter-source mesas 204. Each inter-source contact 202 may be at least partially located between two source electrodes 52.

[0079] Each inter-source mesa 204 includes a p-type contact region 206 that contacts one of the plurality of inter-source contacts 202. The contact region 206 contains impurities of the second conductivity type at a higher concentration than the body region 40. In one example, the p-type impurity concentration of the contact region 206 is 1×10 19 cm -3 More than 1×10 21 cm -3 Each inter-source contact 202 can electrically connect the source wiring 24 located on the insulating layer 20 to a contact region 206 of the semiconductor layer 12.

[0080] The inter-source contact 202 has a width greater than that of the contact 26. This is because, as shown in FIG. 12, the distance between the inter-source contact 202 and the source trench 16 is equal to the distance D1 between the contact 26 and the source trench 16, and the width of the inter-source mesa portion 204 is equal to the mesa width W of the mesa portion 28. m In each mesa portion 28, the contact 26 is disposed closer to the source trench 16 than to the gate trench 14, while the inter-source contact 202 is disposed at the center of the inter-source mesa portion 204 in the first direction.

[0081] The semiconductor device 200 according to the modified example has advantages similar to the advantages (1) to (4) of the semiconductor device 10 according to the first embodiment. In addition, the semiconductor device 200 can have a lower channel density than the semiconductor device 10, and therefore can further improve the switching speed.

[0082] Although not shown in the figures, in the semiconductor device 100 according to the second embodiment, multiple gate trenches 14 and multiple source trenches 16 can also be arranged so that one gate trench 14 and multiple source trenches 16 are alternately arranged in the first direction.

[0083] 3, the gate electrode 50 and the first field plate electrode 54 are disposed in the gate trench 14, and the source electrode 52 and the second field plate electrode 56 are disposed in the source trench 16, but in another example, the first field plate electrode 54 and the second field plate electrode 56 do not have to be disposed in the trenches 14, 16. FIG. 14 shows a semiconductor device 300 according to such a modified example.

[0084] 14, the semiconductor device 300 includes a plurality of gate electrodes 302 buried in a plurality of gate trenches 14, respectively. Each gate electrode 302 is separated from the semiconductor layer 12 by an insulating layer 20 that covers the wall 14A of the gate trench 14 in which the gate electrode 302 is disposed. Each gate electrode 302 is disposed so as to face at least the body region 40 via the insulating layer 20. In the illustrated example, one gate electrode 302 is buried in each gate trench 14. No other electrode is buried between the gate electrode 302 and the bottom 46 of the gate trench 14.

[0085] The semiconductor device 300 includes a plurality of source electrodes 304 buried in a plurality of source trenches 16, respectively. Each source electrode 304 is separated from the semiconductor layer 12 by an insulating layer 20 covering the wall 16A of the source trench 16 in which the source electrode 304 is located. In the illustrated example, one source electrode 304 is buried in each source trench 16. No other electrodes are buried between the source electrode 304 and the bottom 48 of the source trench 16.

[0086] Source trench width W s is the gate trench width W g , the source electrode 304 disposed in the source trench 16 may have a width greater than that of the gate electrode 302 disposed in the gate trench 14.

[0087] The semiconductor device 300 according to the modified example has the same advantages as the advantages (1) to (3) and (5) of the semiconductor device 10 according to the first embodiment. Although not shown, the first field plate electrode 54 and the second field plate electrode 56 may also be arranged not to be located inside the trenches 14, 16 in the semiconductor device 200 shown in FIGS.

[0088] 11, the gate electrode 50 and the first field plate electrode 54 are disposed in the gate trench 14, and the source electrode 52 and the second field plate electrode 56 are disposed in the source trench 16, but in another example, the first field plate electrode 54 and the second field plate electrode 56 do not have to be disposed in the trenches 14, 16. FIG. 15 shows a semiconductor device 400 according to such a modified example.

[0089] 15, a semiconductor device 400 includes a plurality of gate electrodes 402 buried in a plurality of gate trenches 14, respectively. Each gate electrode 402 is separated from the semiconductor layer 12 by an insulating layer 20 that covers the wall 14A of the gate trench 14 in which the gate electrode 402 is disposed. Each gate electrode 402 is disposed so as to face at least the body region 40 via the insulating layer 20. In the illustrated example, one gate electrode 402 is buried in each gate trench 14. No other electrode is buried between the gate electrode 402 and the bottom 46 of the gate trench 14.

[0090] The semiconductor device 400 includes a plurality of source electrodes 404 buried in a plurality of source trenches 16, respectively. Each source electrode 404 is separated from the semiconductor layer 12 by an insulating layer 20 covering the wall 16A of the source trench 16 in which the source electrode 404 is located. In the illustrated example, one source electrode 404 is buried in each source trench 16. No other electrodes are buried between the source electrode 404 and the bottom 48 of the source trench 16.

[0091] Gate trench width W g is the source trench width W s Therefore, the source electrode 404 disposed in the source trench 16 may have the same width as the gate electrode 402 disposed in the gate trench 14.

[0092] The semiconductor device 400 according to the modified example has advantages (1), (3), and (5) similar to those of the semiconductor device 10 according to the first embodiment. s Since the channel density can be increased compared to the semiconductor device 300 having the same dimensions except for the above, the on-resistance can be further reduced.

[0093] As shown in the example, the contacts 26 may be in the form of contact plugs partially embedded in each of the mesas 28, but in another example, the contacts 26 may be positioned to contact the top surfaces of the mesas 28.

[0094] 1, no trenches are provided that intersect with the third gate wiring portion 22X in a plan view, but in another example, multiple trenches that intersect with the third gate wiring portion 22X in a plan view may be provided. Such trenches may correspond to the gate trench 14 and the source trench 16 shown in FIG. 1 rotated 90 degrees in a plan view.

[0095] One or more of the various examples described herein may be combined to the extent that they are not technically inconsistent. In this specification, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B."

[0096] The term "on" as used in this disclosure can mean both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer can be placed directly on the second layer in contact with the second layer, while in other embodiments, the first layer can be placed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0097] Directional terms such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "front," "rear," "longitudinal," "lateral," "left," "right," "front," and "rear" used in this disclosure depend on the particular orientation of the device being described and illustrated. Various alternative orientations are contemplated in this disclosure, and therefore these directional terms should not be construed narrowly.

[0098] For example, the Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (e.g., the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0099] Terms such as "first," "second," and "third" in this disclosure are used merely to distinguish between objects and do not rank the objects. <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0100] (Appendix 1) a semiconductor layer (12) having a first surface (12A) and a second surface (12B) opposite the first surface (12A), the semiconductor layer (12) including a drift region (38) of a first conductivity type, a body region (40) of a second conductivity type located on the drift region (38), and a source region (42) of the first conductivity type located on the body region (40); a plurality of gate trenches (14) having walls (14A) extending from the first surface (12A) into the semiconductor layer (12); a plurality of source trenches (16) having walls (16A) extending from the first surface (12A) into the semiconductor layer (12); an insulating layer (20) located on the first surface (12A) of the semiconductor layer (12) and covering the walls (14A) of the plurality of gate trenches (14) and the walls (16A) of the plurality of source trenches (16); a plurality of gate electrodes (50) embedded in the plurality of gate trenches (14), respectively; a plurality of source electrodes (52) embedded in the plurality of source trenches (16), respectively; a source wiring (24) located on the insulating layer (20) and electrically connected to the plurality of source electrodes (52); a plurality of contacts (26) connecting the source wiring (24) to the semiconductor layer (12); Equipped with the semiconductor layer (12) includes a plurality of mesa portions (28), each of which is defined between one of the plurality of gate trenches (14) and one of the plurality of source trenches (16) adjacent to the gate trench (14) in a first direction, and each of the mesa portions (28) includes a contact region (58) of a second conductivity type in contact with one of the plurality of contacts (26), the contact region (58) including a second conductivity type impurity at a higher concentration than the body region (40); In each mesa portion (28), a distance (D1) between the contact (26) and the source trench (16) is smaller than a distance (D2) between the contact (26) and the gate trench (14).

[0101] (Appendix 2) Each of the plurality of gate trenches (14) has a gate trench width (W g ), and each of the plurality of source trenches (16) has a source trench width (W s ), and the source trench width (W s ) is larger than the gate trench width.

[0102] (Appendix 3) Each of the plurality of gate trenches (14) has a gate trench width (W g ), and each of the plurality of source trenches (16) has a source trench width (W s ), and the gate trench width (W g ) is the source trench width (W s 2. The semiconductor device of claim 1, wherein

[0103] (Appendix 4) 3. The semiconductor device according to claim 2, wherein the plurality of contacts (26) are arranged at a constant pitch in the first direction.

[0104] (Appendix 5) 4. The semiconductor device according to claim 3, wherein the plurality of contacts (26) are arranged at a non-constant pitch in the first direction.

[0105] (Appendix 6) 6. The semiconductor device according to any one of claims 1 to 5, wherein the plurality of mesas (28) have the same width in the first direction.

[0106] (Appendix 7) The semiconductor device according to any one of appendixes 1 to 6, wherein the plurality of contacts (26) are partially embedded in the plurality of mesa portions (28), and each of the plurality of contacts (26) at least partially faces one of the plurality of gate electrodes (50) in the first direction.

[0107] (Appendix 8) each of the plurality of gate trenches (14) extends through the source region (42) and the body region (40) and includes a bottom (46) adjacent to the drift region (38); 8. The semiconductor device according to claim 1, wherein each of the plurality of source trenches (16) extends through the source region (42) and the body region (40) and includes a bottom (48) adjacent to the drift region (38).

[0108] (Appendix 9) a first field plate electrode (54) embedded in the bottom (46) of each of the plurality of gate trenches (14); a second field plate electrode (56) embedded in the bottom (48) of each of the plurality of source trenches (16); Furthermore, 9. The semiconductor device of claim 8, wherein the first field plate electrode (54) is separated from the gate electrode (50) by the insulating layer (20), and the second field plate electrode (56) is separated from the source electrode (52) by the insulating layer (20).

[0109] (Appendix 10) 10. The semiconductor device according to claim 9, wherein the first field plate electrode (54) and the second field plate electrode (56) are electrically connected to the source wiring (24).

[0110] (Appendix 11) a drain electrode (44) in contact with the second surface (12B) of the semiconductor layer (12); a gate wiring (22) located on the insulating layer (20) and electrically connected to the gate electrode (50); 11. The semiconductor device according to any one of claims 1 to 10, further comprising:

[0111] (Appendix 12) The semiconductor device according to any one of appendices 1 to 11, wherein the plurality of gate trenches (14) and the plurality of source trenches (16) are arranged so that one gate trench (14) and one source trench (16) are alternately arranged in the first direction.

[0112] (Appendix 13) The semiconductor device according to any one of appendices 1 to 12, wherein the plurality of gate trenches (14) and the plurality of source trenches (16) are arranged such that one gate trench (14) and a plurality of source trenches (16) are alternately arranged in the first direction.

[0113] Various changes in form and detail may be made to the above-described examples without departing from the scope of the claims and their equivalents. The above-described examples are illustrative and not limiting. The description of a feature in each example should be considered applicable to similar features or aspects in other examples. Suitable results may be achieved if the sequential events are performed in a different order and / or if components within the described systems, architectures, devices, or circuits are combined in a different manner and / or replaced or supplemented by other components or their equivalents. The scope of the present disclosure is defined not by the detailed description, but by the claims and their equivalents. All variations within the scope of the claims and their equivalents are included herein. [Explanation of symbols]

[0114] 10, 100, 200, 300, 400...Semiconductor equipment 12...Semiconductor layer 12A…Side 1 12B…Second side 14...Gate trench 14A...wall 16...Source trench 16A...wall 18A, 18B...Connection trench 20...insulating layer 22...Gate wiring 22P...Gate pad 22Y1...First gate wiring section 22Y2...Second gate wiring section 22X...Third gate wiring section 24...Source wiring 24A...Inner source wiring section 24B...Outer source wiring section 26...Contact 28...Mesa section 30...Gate electrode contact 32...Source electrode contact 34...Field plate electrode contact 36...Drain region 38...Drift region 40...Body area 42...Source region 44...Drain electrode 46,48…Bottom 50, 302, 402...Gate electrodes 52,304,404...Source electrode 54...First field plate electrode 56...Second field plate electrode 58,206…contact area 202...Source contact 204...Mesa between sources D1,D2…distance P1, P2...Pitch W g …gate trench width W s …Source trench width W m …Mesa width

Claims

1. a semiconductor layer having a first surface and a second surface opposite to the first surface, the semiconductor layer including a drift region of a first conductivity type, a body region of a second conductivity type located on the drift region, and a source region of the first conductivity type located on the body region; a plurality of gate trenches having walls extending from the first surface into the semiconductor layer; a plurality of source trenches having walls extending from the first surface into the semiconductor layer; an insulating layer located on the first surface of the semiconductor layer and covering the walls of the gate trenches and the walls of the source trenches; a plurality of gate electrodes embedded in the plurality of gate trenches, respectively; a plurality of source electrodes embedded in the plurality of source trenches, respectively; a source wiring located on the insulating layer and electrically connected to the plurality of source electrodes; a plurality of contacts connecting the source wiring to the semiconductor layer; Equipped with the semiconductor layer includes a plurality of mesa portions, each mesa portion being defined between one of the plurality of gate trenches and one of the plurality of source trenches adjacent to the gate trench in a first direction, each mesa portion including a contact region of a second conductivity type in contact with one of the plurality of contacts, the contact region including an impurity of the second conductivity type at a concentration higher than that of the body region; In each mesa portion, the distance between the contact and the source trench is smaller than the distance between the contact and the gate trench.

2. 2. The semiconductor device according to claim 1, wherein each of the plurality of gate trenches has a gate trench width in the first direction, and each of the plurality of source trenches has a source trench width in the first direction, the source trench width being larger than the gate trench width.

3. 2. The semiconductor device according to claim 1, wherein each of the plurality of gate trenches has a gate trench width in the first direction, and each of the plurality of source trenches has a source trench width in the first direction, and the gate trench width is equal to the source trench width.

4. The semiconductor device according to claim 2 , wherein said plurality of contacts are arranged at a constant pitch in said first direction.

5. The semiconductor device according to claim 3 , wherein said plurality of contacts are arranged at a non-constant pitch in said first direction.

6. The semiconductor device according to any one of claims 1 to 5, wherein the plurality of contacts are partially embedded in the plurality of mesa portions, and each of the plurality of contacts is at least partially opposed to one of the plurality of gate electrodes in the first direction.

7. each of the plurality of gate trenches extends through the source region and the body region and includes a bottom adjacent to the drift region; 6. The semiconductor device according to claim 1, wherein each of the plurality of source trenches extends through the source region and the body region and includes a bottom portion adjacent to the drift region.

8. a first field plate electrode embedded in the bottom of each of the plurality of gate trenches; a second field plate electrode embedded in the bottom of each of the plurality of source trenches; Furthermore, 8. The semiconductor device according to claim 7, wherein the first field plate electrode is separated from the gate electrode by the insulating layer, and the second field plate electrode is separated from the source electrode by the insulating layer.

9. 9. The semiconductor device according to claim 8, wherein said first field plate electrode and said second field plate electrode are electrically connected to said source wiring.

10. a drain electrode in contact with the second surface of the semiconductor layer; a gate wiring located on the insulating layer and electrically connected to the gate electrode; The semiconductor device according to any one of claims 1 to 5, further comprising:

11. 6. The semiconductor device according to claim 1, wherein the plurality of gate trenches and the plurality of source trenches are arranged such that one gate trench and one source trench are alternately arranged in the first direction.

12. 6. The semiconductor device according to claim 1, wherein the plurality of gate trenches and the plurality of source trenches are arranged such that one gate trench and a plurality of source trenches are alternately arranged in the first direction.

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