Semiconductor device

Abstract

To provide a semiconductor device capable of improving output.SOLUTION: A semiconductor device has a channel layer, a barrier layer provided above the channel layer and containing InAlGaN, a first insulating layer provided on the barrier layer, and a second insulating layer provided on the first insulating layer, and the first insulating layer is a silicon nitride layer containing one or more of the Group III elements included in the barrier layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Many reports have been published on field-effect transistors, particularly high electron mobility transistors (HEMTs), which use nitride semiconductors as semiconductor devices. Known nitride semiconductor HEMTs use a GaN layer as the channel layer and an AlGaN or InAlGaN layer as the barrier layer. An InAlGaN layer is easier to lattice match with a GaN layer than an AlGaN layer, even when the Al composition is high, and is therefore preferred for achieving a high concentration of two-dimensional electron gas (2DEG). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-225426 [Patent Document 2] Patent Publication No. 2021-061298 [Patent Document 3] U.S. Patent No. 9,299,821 [Patent Document 4] U.S. Patent No. 9,761,438 [Patent Document 5] US Patent Application Publication No. 2013 / 0200389 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when an insulating layer such as a SiN layer is formed on the barrier layer by plasma-enhanced chemical vapor deposition (CVD), the InAlGaN layer is more susceptible to plasma damage than the AlGaN layer. If defects due to damage exist on the surface of the barrier layer, current collapse is likely to occur, making it difficult to improve output.

[0005] An object of the present disclosure is to provide a semiconductor device capable of improving output. [Means for solving the problem]

[0006] According to one embodiment of the present disclosure, there is provided a semiconductor device including: a channel layer; a barrier layer provided above the channel layer and containing InAlGaN; a first insulating layer provided on the barrier layer; and a second insulating layer provided on the first insulating layer, wherein the first insulating layer is a silicon nitride layer containing one or more of the Group III elements contained in the barrier layer. [Effects of the Invention]

[0007] According to the present disclosure, output can be improved. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a diagram showing an outline of the distribution of the proportions of elements contained in a channel layer, a spacer layer, a barrier layer, a first insulating layer, and a second insulating layer. [Figure 3] 1A to 1C are cross-sectional views (part 1) illustrating a method for manufacturing a semiconductor device according to a first embodiment. [Figure 4] 5A and 5B are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 5A to 5C are cross-sectional views (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 4A and 4B are cross-sectional views (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 5 is a cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] FIG. 3 is a diagram showing current collapse in the semiconductor device according to the first embodiment. [Figure 9] FIG. 10 is a diagram showing current collapse in a semiconductor device according to a reference example. [Figure 10] 10A to 10C are cross-sectional views showing another example of a method for forming the first insulating layer and the second insulating layer. [Figure 11] FIG. 10 is a diagram showing a discrete package according to a second embodiment. [Figure 12] FIG. 10 is a wiring diagram showing a PFC circuit according to a third embodiment. [Figure 13] FIG. 10 is a wiring diagram showing a power supply device according to a fourth embodiment. [Figure 14] FIG. 10 is a wiring diagram showing an amplifier according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description may be omitted.

[0010] (First embodiment) A first embodiment will be described. The first embodiment relates to a semiconductor device including a high electron mobility transistor (HEMT). Fig. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0011] As shown in FIG. 1, the semiconductor device 100 according to the first embodiment includes a substrate 101 and a nitride semiconductor layer structure 110 provided above the substrate 101. The nitride semiconductor layer structure 110 includes a nucleation layer 102, a channel layer 103, a spacer layer 104, and a barrier layer 105. The nucleation layer 102 is provided on the substrate 101. The channel layer 103 is provided on the nucleation layer 102. The spacer layer 104 is provided on the channel layer 103. The barrier layer 105 is provided on the spacer layer 104.

[0012] The substrate 101 is, for example, a semi-insulating SiC substrate. The nucleation layer 102 is, for example, an AlN layer with a thickness of 5 nm or more and 150 nm or less. The channel layer 103 is, for example, a GaN layer with a thickness of 1 μm or more and 5 μm or less. The spacer layer 104 is, for example, an Al[[ID=--5]] z Ga 1-z N layer (0.40 ≦ z ≦ 1.00). That is, the spacer layer 104 is, for example, an AlGaN layer with an Al composition z of 0.40 or more and 1.00 or less. The barrier layer 105 contains InAlGaN. The barrier layer 105 is, for example, an In x1 Al x2 Ga 1-x1-x2 N layer (0.00 < x1 ≦ 0.20, 0.10 ≦ x2 < 1.00). That is, the barrier layer 105 is, for example, an InAlGaN layer with an In composition x1 greater than 0.00 and less than or equal to 0.20 and an Al composition x2 of 0.10 or more and less than 1.00. 2DEG 150 exists near the upper surface of the channel layer 103.

[0013] The semiconductor device 100 has a first insulating layer 106 and a second insulating layer 107. The first insulating layer 106 is provided on the barrier layer 105, and the second insulating layer 107 is provided on the first insulating layer 106. The first insulating layer 106 is, for example, a SiN layer having a thickness of 1 nm or more and 5 nm or less and containing one or more of the Group III elements contained in the barrier layer 105. The second insulating layer 107 includes, for example, a layer of nitride, oxide, or oxynitride of Si, Al, Hf, Zr, Ti, Ta, or W, and is preferably a Si nitride (SiN) layer. The thickness of the second insulating layer 107 is, for example, 2 nm or more and 500 nm or less, and preferably about 100 nm.

[0014] FIG. 2 is a diagram showing an overview of the distribution of the proportions of elements contained in the channel layer 103, the spacer layer 104, the barrier layer 105, the first insulating layer 106, and the second insulating layer 107. FIG. 2 schematically shows the proportions of elements other than nitrogen (N) in each layer. The horizontal axis of FIG. 2 represents the distance from a point within the channel layer 103, and the vertical axis represents the proportions of elements. The actual proportions of elements in each layer can be obtained, for example, by transmission electron microscope (TEM)-energy dispersive X-ray spectroscopy (EDX).

[0015] An element isolation region that defines an element region is formed in the nitride semiconductor stack structure 110, and within the element region, a recess 109s for a source and a recess 109d for a drain are formed in a stack of the barrier layer 105, the first insulating layer 106, and the second insulating layer 107. The recesses 109s and 109d penetrate the first insulating layer 106 and the second insulating layer 107. The bottom surfaces of the recesses 109s and 109d are in the barrier layer 105.

[0016] An opening 109g for a gate is formed in the stack of the first insulating layer 106 and the second insulating layer 107. The opening 109g penetrates the first insulating layer 106 and the second insulating layer 107. The opening 109g is located between the source electrode 111 and the drain electrode 112 in a plan view.

[0017] The semiconductor device 100 has a source electrode 111, a drain electrode 112, and a gate electrode 113. The source electrode 111 is provided in a recess 109s, and the drain electrode 112 is provided in a recess 109d. The gate electrode 113 is provided on the second insulating layer 107 and contacts the barrier layer 105 through an opening 109g.

[0018] The source electrode 111 and the drain electrode 112 include, for example, a Ta film having a thickness of 10 nm to 50 nm and an Al film thereon having a thickness of 100 nm to 500 nm, and are in ohmic contact with the nitride semiconductor stacked structure 110. The gate electrode 113 includes, for example, a Ni film having a thickness of 10 nm to 50 nm and an Au film thereon having a thickness of 300 nm to 500 nm.

[0019] Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. Figures 3 to 7 are cross-sectional views showing the method for manufacturing the semiconductor device 100 according to the first embodiment.

[0020] First, as shown in FIG. 3, a nitride semiconductor stacked structure 110 is formed on a substrate 101. In forming the nitride semiconductor stacked structure 110, a nucleation layer 102, a channel layer 103, a spacer layer 104, and a barrier layer 105 are formed by, for example, metal organic vapor phase epitaxy (MOVPE). When growing the nitride semiconductor stacked structure 110, a mixed gas of trimethylgallium (TMGa) gas, which is a Ga source, and ammonia (NH) gas, which is an N source, is used as the source gas for growing the GaN layer. When growing the AlN layer, a mixed gas of trimethylaluminum (TMAl) gas, which is an Al source, and NH is used as the source gas for growing the AlGaN layer. When growing the InAlGaN layer, a mixed gas of TMAl gas, TMGa gas, and NH is used as the source gas for growing the InAlGaN layer. The supply and flow rates of TMAl gas, TMGa gas, and TMIn gas are appropriately set according to the composition of the nitride semiconductor layer to be grown. Hydrogen (H2) gas or nitrogen (N2) gas is used as the carrier gas. For example, the growth pressure is set to about 1 kPa to 100 kPa, and the growth temperature is set to about 700°C to 1200°C.

[0021] Next, a first insulating layer 106 is formed on the barrier layer 105. The first insulating layer 106 is formed in situ following the formation of the nitride semiconductor stacked structure 110. When forming the first insulating layer 106, a mixed gas of silane (SiH4) gas, which is a Si source, TMIn gas, TMAl gas, TMGa gas, and NH3 gas is used as a raw material gas. The supply and flow rates of TMIn gas, TMAl gas, and TMGa gas are appropriately set depending on the composition of the first insulating layer 106. H2 gas or N2 gas is used as a carrier gas.

[0022] Thereafter, the second insulating layer 107 is formed on the first insulating layer 106. The second insulating layer 107 is formed by, for example, a plasma CVD method. The second insulating layer 107 may be formed by an atomic layer deposition (ALD) method or a sputtering method. When the second insulating layer 107 is formed by the plasma CVD method, the film density of the second insulating layer 107 is set to, for example, 2.64 g / cm. 3 The above conditions are adopted.

[0023] Subsequently, an isolation region that defines an element region is formed in the nitride semiconductor stack structure 110. In forming the isolation region, for example, a photoresist pattern that exposes the region where the isolation region is to be formed is formed on the nitride semiconductor stack structure 110, and ions such as Ar are implanted using this pattern as a mask. Dry etching using a chlorine-based gas may be performed using this pattern as an etching mask.

[0024] Next, as shown in FIG. 4, a surface protection film 108 is formed on the second insulating layer 107. The surface protection film 108 includes a layer of an oxide, nitride, or oxynitride of, for example, Si, Al, Hf, Zr, Ti, Ta, or W, and is preferably a Si oxide (SiO2) layer. The surface protection film 108 can be formed by, for example, a plasma CVD method. The surface protection film 108 may also be formed by an ALD method or a sputtering method.

[0025] Thereafter, openings 108s and 108d are formed in the surface protective film 108, and recesses 109s and 109d are formed in the laminate of the barrier layer 105, the first insulating layer 106, and the second insulating layer 107. To form the openings 108s and 108d and the recesses 109s and 109d, for example, a photoresist pattern exposing the regions where the recesses 109s and 109d are to be formed is formed on the surface protective film 108 by photolithography. Then, using this pattern as an etching mask, dry etching is performed using a fluorine-based gas or a chlorine-based gas. The recesses 109s and 109d are formed so that their bottom surfaces are located in the barrier layer 105.

[0026] Next, as shown in FIG. 5, a source electrode 111 is formed in the recess 109s, and a drain electrode 112 is formed in the recess 109d. The source electrode 111 and the drain electrode 112 can be formed by, for example, a lift-off method. That is, a photoresist pattern exposing the regions where the source electrode 111 and the drain electrode 112 are to be formed is formed, and a metal film is formed by evaporation using this pattern as a growth mask, and this pattern is then removed together with the metal film thereon. To form the metal film, for example, a Ta film is formed, and then an Al film is formed thereon. Next, for example, a heat treatment is performed in a nitrogen atmosphere at 400°C to 1000°C (for example, 550°C) to establish ohmic characteristics. After the source electrode 111 and the drain electrode 112 are formed, the surface protective film 108 is removed.

[0027] 6, opening 109g is formed in the laminate of first insulating layer 106 and second insulating layer 107. In forming opening 109g, for example, a photoresist pattern exposing the region where opening 109g is to be formed is formed on second insulating layer 107 by photolithography, and dry etching using a fluorine-based gas is performed using this pattern as an etching mask. Instead of dry etching, wet etching using hydrofluoric acid or buffered hydrofluoric acid may be performed.

[0028] 7, a gate electrode 113 is formed on the second insulating layer 107, contacting the barrier layer 105 through the opening 109g. The gate electrode 113 can be formed by, for example, a lift-off method. That is, a photoresist pattern exposing the region where the gate electrode 113 is to be formed is formed, and a metal film is formed by evaporation using this pattern as a growth mask, and this pattern is then removed together with the metal film on top. To form the metal film, for example, a Ni film is formed, and then an Au film is formed on top of that.

[0029] In this manner, the semiconductor device 100 according to the first embodiment can be manufactured.

[0030] In the semiconductor device 100, a first insulating layer 106 is provided on a barrier layer 105, and a second insulating layer 107 is provided on the first insulating layer 106. The first insulating layer 106 can be formed in situ by MOVPE following the nitride semiconductor stack structure 110. Therefore, the barrier layer 105 is less likely to be damaged when the first insulating layer 106 is formed. In addition, the film density is 2.64 g / cm 3 Even if second insulating layer 107 is formed under the above conditions, barrier layer 105 is less likely to be damaged because first insulating layer 106 is formed. Therefore, according to semiconductor device 100, there are fewer defects on the surface of barrier layer 105, and current collapse is reduced, thereby improving output. It is also possible to keep on-resistance low.

[0031] Here, current collapse in the first embodiment and the reference example will be described. FIG. 8 is a diagram showing current collapse in the semiconductor device according to the first embodiment. FIG. 9 is a diagram showing current collapse in the semiconductor device according to the reference example. In the semiconductor device according to the reference example, the second insulating layer 107 is formed directly on the barrier layer 105 by plasma CVD without forming the first insulating layer 106. The other configuration of the reference example is the same as that of the first embodiment. As shown in FIGS. 8 and 9, current collapse is reduced in the first embodiment compared to the reference example. Therefore, the first embodiment can obtain a higher output than the reference example. This is because in the reference example, the barrier layer 105 is damaged during the formation of the second insulating layer 107, resulting in many defects on the surface of the barrier layer 105.

[0032] The first insulating layer 106 and the second insulating layer 107 may also be formed as follows: Figure 10 is a cross-sectional view showing another example of a method for forming the first insulating layer and the second insulating layer.

[0033] 10, a SiN layer is formed as an insulating layer 207 on the barrier layer 105 by plasma CVD. The thickness of the insulating layer 207 is equal to the thickness of the laminate of the first insulating layer 106 and the second insulating layer 107 to be formed. The insulating layer 207 has a film density of 2.50 g / cm. 3More than 2.56g / cm 3 The insulating layer 207 is formed under the following conditions. That is, the insulating layer 207 is formed under lower power conditions than the conditions for forming the second insulating layer 107 by the above manufacturing method. When the insulating layer 207 is formed under such conditions, the surface of the barrier layer 105 is less likely to be damaged. After the insulating layer 207 is formed, a heat treatment is performed at a temperature of about 600°C or higher and 800°C or lower. During this heat treatment, some of the group III elements contained in the barrier layer 105 diffuse into the insulating layer 207, and the film density of the insulating layer 207 increases. As a result, a laminate of the first insulating layer 106 and the second insulating layer 107 is obtained from the insulating layer 207. The film density of the second insulating layer 107 formed by this method is, for example, 2.64 g / cm 3 More than 2.70g / cm 3 The following is the result.

[0034] The thickness of the first insulating layer 106 is not limited, but is preferably 1 nm or more and 5 nm or less. If the thickness of the first insulating layer 106 is less than 1 nm, the effect of suppressing damage may be reduced. If the thickness of the first insulating layer 106 exceeds 5 nm, the cost may be high relative to the effect. The thickness of the first insulating layer 106 is more preferably 1 nm or more and 3 nm or less.

[0035] In the first insulating layer 106, the proportion of the Group III element relative to the total amount of silicon and Group III element is not limited, but is preferably 1 atomic % or more and 5 atomic % or less. If this proportion is less than 1 atomic %, the effect of suppressing damage may be reduced. If this proportion exceeds 5 atomic %, the insulating properties of the first insulating layer 106 may be reduced. This proportion is preferably 1 atomic % or more and 3 atomic % or less.

[0036] The composition of the spacer layer 104 is Al z Ga 1-z Although the Al composition z is expressed as AlN (0.40≦z≦1.00), the Al composition z may be 1.00 and the spacer layer 104 may be an AlN layer. The spacer layer 104 may not be provided, and the channel layer 103 and the barrier layer 105 may be in direct contact with each other.

[0037] (Second embodiment) Next, a second embodiment will be described. The second embodiment relates to a discrete package of a HEMT. Fig. 11 is a diagram showing the discrete package according to the second embodiment.

[0038] 11 , the back surface of a semiconductor device 1210 having a structure similar to that of the first embodiment is fixed to a land (die pad) 1233 using a die attach adhesive 1234 such as solder. A wire 1235d such as an Al wire is connected to a drain pad 1226d connected to a drain electrode 112, and the other end of the wire 1235d is connected to a drain lead 1232d integrated with the land 1233. A wire 1235s such as an Al wire is connected to a source pad 1226s connected to a source electrode 111, and the other end of the wire 1235s is connected to a source lead 1232s independent from the land 1233. A wire 1235g such as an Al wire is connected to a gate pad 1226g connected to a gate electrode 113, and the other end of the wire 1235g is connected to a gate lead 1232g independent from the land 1233. The land 1233, the semiconductor device 1210, and the like are packaged in a molding resin 1231 so that a part of the gate lead 1232g, a part of the drain lead 1232d, and a part of the source lead 1232s protrude.

[0039] Such a discrete package can be manufactured, for example, as follows. First, the semiconductor device 1210 is fixed to the land 1233 of the lead frame using a die attach adhesive 1234 such as solder. Next, by bonding using wires 1235g, 1235d, and 1235s, the gate pad 1226g is connected to the gate lead 1232g of the lead frame, the drain pad 1226d is connected to the drain lead 1232d of the lead frame, and the source pad 1226s is connected to the source lead 1232s of the lead frame. After that, sealing is performed using mold resin 1231 by a transfer molding method. Next, the lead frame is separated.

[0040] (Third embodiment) Next, a third embodiment will be described. The third embodiment relates to a PFC (Power Factor Correction) circuit equipped with a HEMT. Fig. 12 is a wiring diagram showing a PFC circuit according to the third embodiment.

[0041] The PFC circuit 1250 includes a switch element (transistor) 1251, a diode 1252, a choke coil 1253, capacitors 1254 and 1255, a diode bridge 1256, and an AC power supply (AC) 1257. The drain electrode of the switch element 1251 is connected to the anode terminal of the diode 1252 and one terminal of the choke coil 1253. The source electrode of the switch element 1251 is connected to one terminal of the capacitor 1254 and one terminal of the capacitor 1255. The other terminal of the capacitor 1254 is connected to the other terminal of the choke coil 1253. The other terminal of the capacitor 1255 is connected to the cathode terminal of the diode 1252. A gate driver is connected to the gate electrode of the switch element 1251. The AC 1257 is connected between both terminals of the capacitor 1254 via the diode bridge 1256. A DC power supply (DC) is connected between both terminals of the capacitor 1255. In this embodiment, a semiconductor device having the same structure as that of the first embodiment is used for the switch element 1251.

[0042] When manufacturing the PFC circuit 1250, the switch element 1251 is connected to the diode 1252 and the choke coil 1253, etc., using, for example, solder or the like.

[0043] (Fourth embodiment) Next, a fourth embodiment will be described. The fourth embodiment relates to a power supply device equipped with a HEMT, suitable for use as a server power supply. Fig. 13 is a wiring diagram showing the power supply device according to the fourth embodiment.

[0044] The power supply device is provided with a high-voltage primary circuit 1261 , a low-voltage secondary circuit 1262 , and a transformer 1263 disposed between the primary circuit 1261 and the secondary circuit 1262 .

[0045] The primary side circuit 1261 is provided with a PFC circuit 1250 according to the third embodiment and an inverter circuit, for example, a full-bridge inverter circuit 1260, connected between both terminals of a capacitor 1255 of the PFC circuit 1250. The full-bridge inverter circuit 1260 is provided with a plurality of (four in this case) switch elements 1264a, 1264b, 1264c, and 1264d.

[0046] The secondary side circuit 1262 is provided with a plurality of (three in this case) switch elements 1265a, 1265b, and 1265c.

[0047] In this embodiment, semiconductor devices having the same structure as in the first embodiment are used for the switch element 1251 of the PFC circuit 1250 and the switch elements 1264a, 1264b, 1264c, and 1264d of the full-bridge inverter circuit 1260 that constitute the primary side circuit 1261. On the other hand, ordinary MIS type FETs (field effect transistors) using silicon are used for the switch elements 1265a, 1265b, and 1265c of the secondary side circuit 1262.

[0048] (Fourth embodiment) Next, a fourth embodiment will be described. The fourth embodiment relates to an amplifier including a HEMT. Fig. 14 is a wiring diagram showing the amplifier according to the fourth embodiment.

[0049] The amplifier includes a digital predistortion circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273.

[0050] The digital predistortion circuit 1271 compensates for nonlinear distortion in the input signal. The mixer 1272a mixes the input signal, for which nonlinear distortion has been compensated, with an AC signal. The power amplifier 1273 includes a semiconductor device having a structure similar to that of the first embodiment, and amplifies the input signal mixed with the AC signal. Note that in this embodiment, for example, by switching a switch, the output signal can be mixed with the AC signal by the mixer 1272b and sent to the digital predistortion circuit 1271. This amplifier can be used as a high-frequency amplifier or a high-power amplifier. The high-frequency amplifier can be used, for example, in a transmitter / receiver for a mobile phone base station, a radar device, and a microwave generator.

[0051] The substrate may be a silicon carbide (SiC) substrate, a sapphire substrate, a silicon substrate, an AlN substrate, a GaN substrate, or a diamond substrate, and may be conductive, semi-insulating, or insulating.

[0052] The structures of the gate electrode, source electrode, and drain electrode are not limited to those in the above-described embodiments. For example, they may be composed of a single layer. Furthermore, the method for forming them is not limited to the lift-off method. Furthermore, if ohmic characteristics can be obtained, the heat treatment after forming the source electrode and drain electrode may be omitted. Heat treatment may also be performed after forming the gate electrode.

[0053] Furthermore, an n-type GaN region may be formed directly below the source and drain electrodes of the nitride semiconductor multilayer structure, which may be formed by, for example, ion implantation or regrowth.

[0054] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0055] Various aspects of the present disclosure are summarized below as appendices.

[0056] (Appendix 1) a channel layer; a barrier layer including InAlGaN provided above the channel layer; a first insulating layer provided on the barrier layer; a second insulating layer provided on the first insulating layer; and The semiconductor device, wherein the first insulating layer is a silicon nitride layer containing one or more of the group III elements contained in the barrier layer. (Appendix 2) 2. The semiconductor device according to claim 1, wherein the first insulating layer has a thickness of 1 nm or more and 5 nm or less. (Appendix 3) 3. The semiconductor device according to claim 1, wherein in the first insulating layer, the proportion of the Group III element with respect to the total amount of silicon and the Group III element is 1 atomic % or more and 5 atomic % or less. (Appendix 4) 4. The semiconductor device according to claim 1, wherein the second insulating layer contains silicon nitride. (Appendix 5) 5. The semiconductor device according to claim 1, further comprising a spacer layer between the channel layer and the barrier layer. (Appendix 6) 6. The semiconductor device according to claim 5, wherein the spacer layer comprises AlN or AlGaN. (Appendix 7) forming a barrier layer comprising InAlGaN above the channel layer; forming a first insulating layer on the barrier layer; forming a second insulating layer on the first insulating layer by plasma enhanced chemical vapor deposition; and A method for manufacturing a semiconductor device, wherein the first insulating layer is a silicon nitride layer containing one or more of the group III elements contained in the barrier layer. (Appendix 8) 8. The method for manufacturing a semiconductor device according to claim 7, wherein the first insulating layer is formed in situ with the barrier layer. (Appendix 9) An amplifier comprising the semiconductor device according to any one of claims 1 to 6. (Appendix 10) A power supply device comprising the semiconductor device according to any one of claims 1 to 6. [Explanation of symbols]

[0057] 100: Semiconductor device 101: Circuit board 102: Nucleation layer 103: Channel layer 104: Spacer layer 105: Barrier layer 106: First insulating layer 107: Second insulating layer 109d, 109s: recess 109g: opening 110: Nitride semiconductor stacked structure 111: Source electrode 112: Drain electrode 113: Gate electrode 207: Insulating layer

Claims

1. a channel layer; a barrier layer including InAlGaN provided above the channel layer; a first insulating layer provided on the barrier layer; a second insulating layer provided on the first insulating layer; and The semiconductor device, wherein the first insulating layer is a silicon nitride layer containing one or more of the group III elements contained in the barrier layer.

2. The semiconductor device according to claim 1 , wherein the first insulating layer has a thickness of 1 nm to 5 nm.

3. 3. The semiconductor device according to claim 1, wherein the ratio of the Group III element to the total amount of silicon and the Group III element in the first insulating layer is 1 atomic % or more and 5 atomic % or less.

4. 3. The semiconductor device according to claim 1, wherein the second insulating layer contains silicon nitride.

5. 3. The semiconductor device according to claim 1, further comprising a spacer layer between the channel layer and the barrier layer.

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