Signal generation device and signal generation method

Abstract

To provide a signal generation device and a signal generation method capable of significantly increasing a maximum phase difference that can be phase-matched between serial data output from a plurality of transceivers.SOLUTION: A signal generation device includes: a plurality of coarse adjustment parts 111 that roughly adjust phases of parallel data of a plurality of bits; a plurality of transceivers 20 that convert N bits of the parallel data roughly adjusted by each coarse adjustment part 111 into 1-bit serial data; and a phase synchronization control part that indirectly controls a phase of the serial data output from each transceiver 20 by roughly adjusting the phase of the parallel data by the plurality of coarse adjustment parts 111 in the coarse adjustment mode, and directly controls the phase of the serial data output from each transceiver 20 in a fine adjustment mode.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a signal generating device and a signal generating method, and more particularly to a signal generating device and a signal generating method that include a transceiver that converts parallel data into high-speed serial data and outputs the converted data. [Background technology]

[0002] As communication standards such as Ethernet® 800GbE (Gigabit Ethernet) and PCIe® (Peripheral Component Interconnect Express) Gen (Generation) 6 become faster, signal transmission methods are no longer simple binary digital signals such as NRZ (Non Return to Zero), but are now typified by PAM (Pulse Amplitude Modulation) 4. It is expected that transmission methods such as PAM8 and PAM16 will be standardized in the future. When developing or testing products that use these signals, a test signal source is required.

[0003] Such signal sources should naturally be able to generate signals such as PAM4 and PAM8, but it is also desirable that they be able to generate signals that have passed through a specific transmission path, or signals that have been subjected to emphasis or filtering. Therefore, there is a demand for an arbitrary waveform generator (AWG) that can generate arbitrary waveforms in an analog manner and has a high speed of over 100 Gsps (G Symbol / s).

[0004] An AWG must allow the user to freely set the analog waveform to be output. Naturally, since it is required to generate any desired signal, it must also be possible to set the waveform using numerical data. Therefore, an AWG must have a mechanism inside it to convert the digital data output from an FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit) into analog data. This conversion can be achieved using a Digital-to-Analog Converter (DAC).

[0005] However, when the required analog data output rate is high, not only does it become necessary to input signals multiplexed by a multiplexer (MUX) at higher speeds to the DAC, but the effects of phase differences between the multiple input signals input to the DAC and the MUX in the preceding stage cannot be ignored.For example, if the FPGA output rate is 32 Gbps and the DAC bit resolution is 8 bits, it is desirable that the maximum phase difference between all signals input to the MUX be less than 0.1 UI (Unit Interval) (3.125 ps).

[0006] Here, by using the technique described in Patent Document 1, it is possible to adjust the maximum phase difference between all signals input to the MUX to a value less than or close to 0.1 UI. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 6346212 Summary of the Invention [Problem to be solved by the invention]

[0008] However, the technology described in Patent Document 1 may adjust the phase between signals input to the MUX at a position that is shifted by one clock (1 UI), which occurs when there is a large phase shift between the signals before the adjustment.

[0009] Specifically, the technology described in Patent Document 1 cannot handle cases where a phase difference between pre-adjusted signals exceeds 1 UI. Furthermore, even if the phase difference between pre-adjusted signals is suppressed to within 1 UI by other means, there are technical and cost challenges, such as the need for an additional mechanism to adjust the clock phase provided to the FPGA transceiver, etc., and the need to measure the phase adjustment amount, which varies depending on the frequency. In the case of an FPGA, the phase difference between transceivers may change every time the FPGA is powered up or reset, requiring re-measurement of the phase adjustment amount. Furthermore, depending on the FPGA used, it may not be possible to suppress the phase difference between output signals to within 1 UI, even if the connection route within the FPGA is fixed.

[0010] In this case, when signals are multiplexed using a MUX, unintended data is generated. For example, if this data is used as a test signal for a Bit Error Rate Tester (BERT), the test signal itself will contain errors, making it impossible to measure the correct error rate.

[0011] The applicant attempted to solve these problems in Japanese Patent Application No. 2023-160154 (hereinafter referred to as the "prior application"), which makes it possible to align the phase difference of signals input to the DAC and the MUX in the preceding stage.

[0012] By using this technology, it is possible to align the phase difference between signals input to the DAC or the MUX in the previous stage. With this technology, an example has been shown in which the maximum phase difference tolerance between signals can be increased to, for example, 32UI. Although this is a significant increase compared to the phase tolerance of 1UI, it cannot be said that this tolerance is sufficient.

[0013] In Xilinx UltraScale+ GTY transceivers (FPGA transceivers), one channel of GTY Quad is made up of four lanes, each containing one transceiver. The phase error of UltraScale+ GTY transceivers is 500ps according to the datasheet, and 32UI is sufficient to converge this phase difference in one GTY Quad.

[0014] However, this is a value limited to one GTY Quad, and there is no guarantee of an upper limit to the phase error between GTY Quads, since it depends on the timing of the input clock and reset.

[0015] Furthermore, in addition to the effects of the FPGA itself, we must also consider the phase difference between lanes that occurs due to the connection path from the FPGA to the DAC and the MUX that precedes it, as well as the DAC and MUX themselves. When these factors of phase difference are taken into account, it is conceivable that the maximum phase difference between lanes may exceed 32 UI.

[0016] In addition, the maximum phase difference between lanes when using UltraScale+ is 32UI, but this value depends on the capacity of the FIFO (First-In First-Out) built into the FPGA transceiver. Therefore, depending on the FPGA, the maximum phase difference between lanes that can be tolerated may be smaller.

[0017] The present invention has been made to solve the above-mentioned problems in the prior art, and has as its object to provide a signal generating device and a signal generating method that can significantly increase the maximum phase difference that can be phase-matched between serial data output from multiple transceivers. [Means for solving the problem]

[0018] In order to achieve the above object, a signal generating device according to the present invention includes a parallel data output unit (11) that outputs parallel data of multiple bits, a plurality of coarse adjustment units (111) that roughly adjust the phase of the parallel data output from the parallel data output unit, a plurality of transceivers (20) that convert N bits of the parallel data roughly adjusted by each of the coarse adjustment units into 1-bit serial data, a phase synchronization control unit (31) that indirectly controls the phase of the serial data output from each of the transceivers in a coarse adjustment mode by coarsely adjusting the phase of the parallel data output from the parallel data output unit by the plurality of coarse adjustment units, and directly controls the phase of the serial data output from each of the transceivers in a fine adjustment mode, a frequency-divided clock output unit (14) that outputs a frequency-divided clock obtained by dividing the frequency of an external clock, a frequency-dividing ratio setting unit (33) that sets the frequency-dividing ratio of the frequency-divided clock in the frequency-divided clock output unit, a clock selection unit (17) that selects either the frequency-divided clock or the external clock, and a phase synchronization control unit (31) that converts the frequency-divided clock selected by the clock selection unit as the serial data. a rate control unit (34) that controls each of the transceivers to output a toggle pattern having a frequency half the frequency of the clock or the external clock; and a phase detection unit (40) that outputs a detection voltage corresponding to the phase difference between the divided clock or the external clock selected by the clock selection unit and the toggle pattern, wherein the phase synchronization control unit includes a phase acquisition processing unit (31b) that executes phase acquisition processing to acquire the detection voltage output from the phase detection unit while changing the phase of the toggle pattern from an initial value; a phase difference calculation processing unit (31d) that executes a phase difference calculation process that calculates an initial phase difference between the divided clock or the external clock selected by the clock selection unit and the initial value of the phase of the toggle pattern based on the detected voltage, and a phase shift processing unit (31e) that executes a phase shift process that shifts the phase of the toggle pattern from the initial value by the amount of the initial phase difference so that the phase difference between the divided clock or the external clock selected by the clock selection unit and the toggle pattern becomes a value within a predetermined range, and the phase synchronization control unitThe frequency division ratio setting unit repeatedly executes the phase acquisition process, the phase difference calculation process, and the phase shift process while gradually decreasing the frequency division ratio, and the clock selection unit selects the external clock instead of the frequency-divided clock after the phase shift process is executed when the frequency division ratio is equal to or less than a predetermined value, and the minimum value of the frequency division ratio set by the frequency division ratio setting unit in the coarse adjustment mode is equal to or greater than the maximum value of the frequency division ratio set by the frequency division ratio setting unit in the fine adjustment mode.

[0019] With this configuration, the signal generating device of the present invention can significantly increase the maximum phase difference that can be phase-matched between the serial data output from multiple transceivers, compared to the prior art technology in which the phase of the serial data was only directly controlled within each transceiver.

[0020] Furthermore, with this configuration, when the signal generating device according to the present invention is configured as an AWG, the degree of freedom in component placement is improved and the tolerance for differences in signal path length is increased, making it easier to configure a circuit that prevents crosstalk and noise from entering, and improving signal quality is expected.

[0021] Furthermore, in the signal generating device according to the present invention, each of the coarse adjustment units may include a plurality of coarse adjustment FIFOs (113) that change a difference between a write address to which L bits of the parallel data are sequentially written and a read address from which the written L bits of parallel data are sequentially read out in accordance with a coarse adjustment control signal output from the phase synchronization control unit, and a plurality of delay output units (114) that delay the L bits of parallel data read out from each of the coarse adjustment FIFOs by the N bits in accordance with the coarse adjustment control signal and output the delayed data to the plurality of transceivers, and the phase synchronization control unit may be configured to change the phase of the toggle pattern by changing the value of the coarse adjustment control signal in the coarse adjustment mode.

[0022] With this configuration, the signal generating device according to the present invention can expand the adjustable range of the phase of the toggle pattern from each transceiver.

[0023] Furthermore, the signal generating device according to the present invention may be configured such that four of the transceivers form one transceiver unit (12), each of the coarse adjustment units is provided corresponding to the transceiver unit, and the four transceivers in the transceiver unit convert the N bits of the parallel data coarsely adjusted by each of the coarse adjustment units into 1 bit of the serial data at the timing of a common clock signal.

[0024] With this configuration, the signal generating device of the present invention has one coarse adjustment unit provided for one transceiver unit having four transceivers, thereby enabling efficient phase matching between multiple transceiver units.

[0025] Furthermore, the signal generating device according to the present invention may be configured such that the clock selection unit selects the external clock instead of the divided clock after the phase shift process is executed when the division ratio is 4 or less.

[0026] Furthermore, a signal generating method according to the present invention uses a signal generating device (1) including: a parallel data output unit (11) that outputs parallel data of multiple bits; a plurality of coarse adjustment units (111) that coarsely adjust the phase of the parallel data output from the parallel data output unit; a plurality of transceivers (20) that convert N bits of the parallel data coarsely adjusted by each of the coarse adjustment units into 1-bit serial data; a frequency-divided clock output unit (14) that outputs a frequency-divided clock obtained by dividing the frequency of an external clock; a clock selection unit (17) that selects either the frequency-divided clock or the external clock; and a phase detection unit (40) that outputs a detection voltage corresponding to a phase difference between the frequency-divided clock or the external clock selected by the clock selection unit and the serial data, by coarsely adjusting the phase of the parallel data output from the parallel data output unit by the plurality of coarse adjustment units in a coarse adjustment mode. a frequency division ratio setting step (S23, S27, S35) of setting the frequency division ratio of the frequency division clock in the frequency division clock output unit; a rate control step (S41, S44, S47) of controlling each of the transceivers to output, as the serial data, a toggle pattern having a frequency that is half the frequency of the frequency division clock or the external clock selected by the clock selection unit; a phase acquisition step (S42, S45, S48) of executing a phase acquisition process of acquiring the detected voltage output from the phase detection unit while changing the phase of the toggle pattern from an initial value; and a phase difference calculation step (S43, S46, S47) of executing a phase difference calculation process of calculating an initial phase difference between the frequency division clock or the external clock selected by the clock selection unit and the initial value of the phase of the toggle pattern based on the detected voltage acquired by the phase acquisition step.S49), a phase shift processing step (S25, S33, S39) of executing a phase shift processing of shifting the phase of the toggle pattern from the initial value by the amount of the initial phase difference so that the phase difference between the divided clock or the external clock selected by the clock selection unit and the toggle pattern is within a predetermined range, steps (S25 to S28, S33 to S36) of repeatedly executing the phase acquisition processing, the phase difference calculation processing, and the phase shift processing while gradually decreasing the division ratio by the division ratio setting step, and an external clock selection step (S37) of selecting the external clock instead of the divided clock by the clock selection unit after the phase shift processing is executed when the division ratio is equal to or less than a predetermined value, wherein the minimum value of the division ratio set by the division ratio setting step in the coarse adjustment mode is equal to or greater than the maximum value of the division ratio set by the division ratio setting step in the fine adjustment mode. [Effects of the Invention]

[0027] The present invention provides a signal generating device and a signal generating method that can significantly increase the maximum phase difference that can be phase-matched between serial data output from a plurality of transceivers. [Brief explanation of the drawings]

[0028] [Figure 1] 1 is a block diagram showing a configuration of a signal generating device according to an embodiment of the present invention. [Figure 2] 2 is a block diagram showing a part of the configuration of a data output unit included in the signal generating device of FIG. 1. FIG. [Figure 3] 2 is a block diagram showing a detailed configuration of a coarse adjustment unit connected to a transceiver unit included in the signal generating device of FIG. 1. FIG. [Figure 4] 2 is a block diagram showing detailed configurations of a coarse adjustment FIFO, a delay output unit, and a controller included in the signal generating device of FIG. 1. FIG. [Figure 5]10 is a diagram showing the relationship between the LSB of the coarse adjustment control signal and the data output from each MUX in the delay output section. FIG. [Figure 6] 2 is a schematic diagram of a phase detection unit included in the signal generating device of FIG. 1. [Figure 7] FIG. 2 is a block diagram showing the configuration of one lane of the transceiver section. [Figure 8] 2 is a state transition diagram for explaining a usage amount control process performed by the signal generating device of FIG. 1. FIG. [Figure 9] 10 is a block diagram showing the configuration of an FPGA control unit included in the data output unit. FIG. [Figure 10] FIG. 10 is a diagram showing the relationship between a toggle pattern output from one lane of a data output unit and a clock. [Figure 11] 10 is a graph showing the relationship between a detection voltage according to a duty ratio of a phase detection signal output from a phase detection unit and the amount of change in the phase of a toggle pattern from an initial value. [Figure 12] This figure explains the phase shift processing of the toggle patterns of each lane by the phase synchronization control unit provided in the FPGA control unit, where (a) shows a case where the initial phase differences of the toggle patterns of all lanes are distributed in positive directions, (b) shows a case where the initial phase differences of the toggle patterns of each lane are distributed in either positive or negative directions, and (c) shows a case where the initial phase differences of the toggle patterns of each lane are distributed in either positive or negative directions, with the positive distribution and negative distribution separated by 0.5 UI or more. [Figure 13] 10 is a diagram showing the amount of phase shift of the toggle pattern by the phase synchronization control unit for each division ratio. FIG. [Figure 14] 2 is a flowchart showing the process of a signal generation method using the signal generation device of FIG. 1. [Figure 15] 15 is a flowchart showing details of the process in the coarse adjustment mode in the flowchart of FIG. 14. [Figure 16] 15 is a flowchart showing details of the process in the fine adjustment mode in the flowchart of FIG. 14. [Figure 17]15 and 16, (a) is a flowchart showing details of the global phase measurement process using a frequency-divided clock, (b) is a flowchart showing details of the global phase measurement process using an external clock, (c) is a flowchart showing details of the current phase measurement process, (b) is a flowchart showing details of the current phase measurement process, (c) is a flowchart showing details of the current phase measurement process, (c) is a flowchart showing details of the current phase measurement process, (b) is a flowchart showing details of the current phase measurement process using an external clock, (c) is a flowchart showing details of the current phase measurement process ... [Figure 18] FIG. 10 is a diagram showing the phase relationship of the toggle patterns of each lane after the usage control process. [Figure 19] 10A and 10B are diagrams showing the phase relationship of the toggle patterns of each lane when the division ratio of the divided clock is 64, in which (a) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the initial phase difference is calculated by the phase difference calculation process, and (b) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the phase is shifted by the phase shift process. [Figure 20] 10A and 10B are diagrams showing the phase relationship of the toggle patterns of each lane when the division ratio of the divided clock is 4, in which (a) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the initial phase difference is calculated by the phase difference calculation process, and (b) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the phase is shifted by the phase shift process. [Figure 21] 10A and 10B are diagrams showing the phase relationship of the toggle patterns of each lane when an external clock is selected by the clock selection unit, in which (a) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the initial phase difference is calculated by the phase difference calculation process, and (b) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the phase is shifted by the phase shift process. DETAILED DESCRIPTION OF THE INVENTION

[0029] DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a signal generating device and a signal generating method according to the present invention will be described with reference to the drawings.

[0030] 1 includes a data output unit 10, a clock selection unit 17, a phase detection unit 40, a MUX 50, an amplifier 52, an ADC 55, a DAC 60, an operation unit 65, and a control unit 70. The data output unit 10 is configured on, for example, an FPGA or an ASIC, but the following description will be given assuming that these are configured on an FPGA.

[0031] The data output unit 10 includes a parallel data output unit 11, a plurality of coarse adjustment units 111-1 to 111-8 (hereinafter also simply referred to as "coarse adjustment units 111"), a plurality of transceiver units 12-1 to 12-8 (hereinafter also simply referred to as "transceiver units 12"), a clock generation unit 13, a frequency-divided clock output unit 14, and an FPGA control unit 15.

[0032] The parallel data output section 11 has an internal memory (not shown) that stores a series of data strings of a predetermined pattern in advance, or an arithmetic circuit (not shown) that generates this data string.

[0033] The parallel data output unit 11 is configured to output, as multi-bit parallel data, a PAM signal pattern consisting of, for example, a multi-value K (K is an integer equal to or greater than 2) of two or more values, based on pattern information input from the operation unit 65. The parallel data output unit 11 generates a PAM signal pattern consisting of any multi-value K, such as an NRZ signal (K=2), a PAM3 signal (K=3), a PAM4 signal (K=4), a PAM5 signal (K=5), a PAM6 signal (K=6), a PAM7 signal (K=7), or a PAM8 signal (K=8). Here, the pattern information refers to information on the PAM signal pattern, such as the value of K and the type of pattern (for example, a Pseudo Random Binary Sequence (PRBS) pattern, a Short Stress Pattern Random Quaternary (SSPRQ) pattern, or any pattern).

[0034] Since each coarse adjustment unit 111 is provided corresponding to each transceiver unit 12, the number of coarse adjustment units 111 is equal to the number of transceiver units 12. Note that in the present invention, the number of coarse adjustment units 111 and transceiver units 12 is not limited to eight, and may be any number.

[0035] As shown in FIG. 2, the clock signal generated by the clock generating unit 13 is distributed to a QPLL (Quad Phase Locked Loop) 28 of each transceiver unit 12.

[0036] Each transceiver unit 12 includes, for example, four transceivers 20-0 to 20-3 arranged in four lanes, respectively, and a QPLL 28. That is, the four transceivers configure one transceiver unit 12.

[0037] The QPLL 28 converts, for example, a 500 MHz clock signal generated by the clock generating unit 13 into a 32 GHz clock signal.

[0038] Each transceiver 20 is an output unit of an FPGA and outputs a digital signal of 0 or 1. Each transceiver 20 converts N bits of the multi-bit parallel data output from the parallel data output unit 11, which has been roughly adjusted by a coarse adjustment unit 111 (described later), into 1-bit serial data, in synchronization with the timing of a common clock signal output from the QPLL 28. Here, N is an integer of 2 or greater.

[0039] That is, each transceiver unit 12 converts the multi-bit parallel data output from the parallel data output unit 11 into 4-bit parallel data and outputs it. That is, the data output unit 10 outputs 8 channels of 4-bit parallel data, in other words, 32 lanes of serial data.

[0040] The divided clock output unit 14 outputs a divided clock obtained by dividing the frequency of the external clock. The maximum frequency of the divided clock is half the frequency of the external clock. For example, the divided clock output unit 14 may be implemented by a transceiver having a similar configuration to each of the transceivers 20.

[0041] The clock selector 17 selects either the divided clock or the external clock in response to a clock selection signal output from a clock selection signal output unit 35 (described later). In this specification, the divided clock and the external clock are collectively referred to simply as "clock." The external clock is, for example, a 32 GHz pulse signal.

[0042] FIG. 3 is a diagram showing a specific configuration of the coarse adjustment unit 111 connected to one transceiver unit 12. As shown in FIG.

[0043] The coarse adjustment unit 111 has a speed adjustment FIFO 112, a coarse adjustment FIFO 113, a delay output unit 114, and a controller 115, and is configured to coarsely adjust the phase of the parallel data output from the parallel data output unit 11.

[0044] The speed adjustment FIFO 112 is an asymmetric FIFO that performs speed adjustment by converting multi-bit parallel data output from the parallel data output unit 11 into L-bit parallel data. In the example of FIG. 3, the speed adjustment FIFO 112 converts 512-bit parallel data into 256-bit parallel data, which is twice the speed. For example, the write clock frequency of the speed adjustment FIFO 112 is 250 MHz, and the read clock frequency is 500 MHz. Note that the speed adjustment FIFO 112 is not an essential component of the present invention.

[0045] The coarse adjustment FIFO 113 is configured to store L-bit parallel data output from the speed adjustment FIFO 112. That is, the coarse adjustment FIFO 113 stores L bits of the multi-bit parallel data output from the parallel data output unit 11. In the example of FIG. 3, L is 256.

[0046] The coarse adjustment FIFO 113 is configured to change the difference between the write addresses to which L bits of the parallel data output from the parallel data output unit 11 are sequentially written and the read addresses to which the written L bits of parallel data are sequentially read, in response to a coarse adjustment control signal output from a phase synchronization control unit 31, which will be described later. For example, the frequencies of the write clock and read clock of the coarse adjustment FIFO 113 are 500 MHz.

[0047] The delay output unit 114 delays the L-bit parallel data read from the coarse adjustment FIFO 113 by N bits in accordance with a coarse adjustment control signal output from a phase synchronization control unit 31 (described later), and outputs the delayed data to the transceivers 20-1 to 20-3. For example, the frequency of the read clock of the delay output unit 114 is 500 MHz.

[0048] The controller 115 controls the coarse adjustment FIFO 113 and the delay output unit 114 in response to a coarse adjustment control signal output from a phase synchronization control unit 31, which will be described later.

[0049] Fig. 4 is a block diagram showing detailed configurations of the coarse adjustment FIFO 113, the delay output unit 114, and the controller 115. Note that although clocks such as a read clock are not shown in Fig. 4, each unit operates on a common clock (for example, 500 MHz).

[0050] The controller 115 includes a counter 116 , an MSB extraction unit 117 , an LSB extraction unit 118 , and a subtraction unit 119 .

[0051] The counter 116 repeatedly outputs a value from the minimum address value of the subsequent coarse adjustment FIFO 113 to the maximum address value of the coarse adjustment FIFO 113, incrementing the value by one for each clock.

[0052] The MSB extraction unit 117 extracts the most significant bit (MSB), which is the upper 8 bits of the coarse adjustment control signal, and the LSB extraction unit 118 extracts the least significant bit (LSB), which is the lower 2 bits of the coarse adjustment control signal.

[0053] The number of bits of the MSB of the coarse adjustment control signal may be a value according to the capacity of the coarse adjustment FIFO 113. For example, if the capacity of the coarse adjustment FIFO 113 is 2048 bytes, that is, 16384 bits, the number of bits of the MSB of the coarse adjustment control signal may be 6 bits.

[0054] The subtraction unit 119 outputs a value obtained by subtracting the MSB extracted by the MSB extraction unit 117 from the value of the counter 116 .

[0055] The coarse adjustment FIFO 113 is a dual-port RAM (Random Access Memory), and its buffer configuration is classified as a ring buffer. As shown in Fig. 4, the coarse adjustment FIFO 113 has terminals addra, dina, wea, and addrb as input terminals, and terminals A and B as output terminals. Note that terminal A is unused in the configuration shown in Fig. 4.

[0056] Terminal dina receives as input the 256-bit parallel data output from the speed adjustment FIFO 112. Terminal addra receives as input a value from counter 116 that specifies the write address for the parallel data input to terminal dina. Terminal wea is set to the value "1" that enables the write operation for the parallel data input to terminal dina. Terminal addrb receives as input a value from subtraction unit 119 that specifies the read address for the parallel data input to terminal dina.

[0057] With this configuration, in the coarse adjustment FIFO 113, the data read from the read address and output from the terminal B is always delayed by the value of the MSB of the coarse adjustment control signal relative to the data written to the write address.

[0058] The delay output unit 114 has four data extraction units 120-0 to 120-3, three registers 121-1 to 121-3, four MUXes 122-0 to 122-3, and a data combining unit 123.

[0059] The data extraction unit 120-0 extracts 64 bits of data consisting of the 0th to 63rd bits (hereinafter also referred to as “data A”) from the 256-bit parallel data output from terminal B of the coarse adjustment FIFO 113.

[0060] The data extraction unit 120-1 extracts 64 bits of data (hereinafter also referred to as “data B”) consisting of the 64th to 127th bits from the 256-bit parallel data output from terminal B of the coarse adjustment FIFO 113.

[0061] The data extraction unit 120-2 extracts 64 bits of data consisting of the 128th to 191st bits (hereinafter also referred to as “data C”) from the 256-bit parallel data output from terminal B of the coarse adjustment FIFO 113.

[0062] The data extraction unit 120-3 extracts 64 bits of data consisting of the 192nd to 255th bits (hereinafter also referred to as “data D”) from the 256-bit parallel data output from terminal B of the coarse adjustment FIFO 113.

[0063] The register 121-1 is configured to hold the data B extracted by the data extracting section 120-1 for one clock.

[0064] The register 121-2 holds the data C extracted by the data extracting section 120-2 for one clock.

[0065] The register 121-3 holds the data D extracted by the data extracting section 120-3 for one clock.

[0066] Each of the MUXes 122-0 to 122-3 has terminals d0 to d3 and a terminal sel to which the LSB of the coarse adjustment control signal extracted by the LSB extraction unit 118 is input. The LSB of the coarse adjustment control signal serves as a selection signal for selecting one of the terminals d0 to d3.

[0067] When the LSB of the coarse adjustment control signal is 0, each MUX 122 outputs the data input to terminal d0. Specifically, MUX 122-0 outputs data B output from register 121-1 and one clock before. MUX 122-1 outputs data C output from register 121-2 and one clock before. MUX 122-2 outputs data D output from register 121-3 and one clock before. MUX 122-3 outputs the latest data A output from data extraction unit 120-0.

[0068] When the LSB of the coarse adjustment control signal is 1, each MUX 122 outputs the data input to terminal d1. Specifically, MUX 122-0 outputs data C from the previous clock output from register 121-2. MUX 122-1 outputs data D from the previous clock output from register 121-3. MUX 122-2 outputs the latest data A output from data extraction unit 120-0. MUX 122-3 outputs the latest data B output from data extraction unit 120-1.

[0069] When the LSB of the coarse adjustment control signal is 2, each MUX 122 outputs the data input to terminal d2. Specifically, MUX 122-0 outputs data D from the previous clock output from register 121-3. MUX 122-1 outputs the latest data A output from data extraction unit 120-0. MUX 122-2 outputs the latest data B output from data extraction unit 120-1. MUX 122-3 outputs the latest data C output from data extraction unit 120-2.

[0070] When the LSB of the coarse adjustment control signal is 3, each MUX 122 outputs the data input to terminal d3. Specifically, MUX 122-0 outputs the latest data A output from data extraction unit 120-0. MUX 122-1 outputs the latest data B output from data extraction unit 120-1. MUX 122-2 outputs the latest data C output from data extraction unit 120-2. MUX 122-3 outputs the latest data D output from data extraction unit 120-3.

[0071] Figure 5 is a diagram summarizing the relationship between the LSB of the coarse adjustment control signal and the data output from each MUX 122. Time t0 represents the time of the most recent clock. Time t1 represents the time of the clock immediately preceding the clock at time t0. The 0th to 3rd squares from the bottom correspond to MUX 122-0 to 122-3, respectively.

[0072] That is, the delay output unit 114 divides the 256-bit wide data output from the coarse adjustment FIFO 113 into 64-bit data A to D, holds up to 192 bits of data for one clock, and extracts any 64-bit data from the total 448 bits of data in chronological order, starting with the first 64-bit data.

[0073] The data combining unit 123 bundles the data A to D output from each MUX 122 to form 256-bit parallel data, and outputs it to the corresponding transceiver unit 12. Specifically, the transceiver 20-0 of lane 0 receives input of a multiple of 4 bit of the parallel data, the transceiver 20-1 of lane 1 receives input of a multiple of 4+1 bit of the parallel data, the transceiver 20-2 of lane 2 receives input of a multiple of 4+2 bit of the parallel data, and the transceiver 20-3 of lane 3 receives input of a multiple of 4+3 bit of the parallel data.

[0074] When the lowest 3 bits of the coarse adjustment control signal increase by 1, for example, from 000 to 001 to 010 to 011 to 100 to 101 to 110 to 111 to..., as can be seen from FIG. 5, the phase of the data output from delay output unit 114 advances by 64 bits with each change in LSB from 000 to 001 to 010 to 011.

[0075] In the next change from 011 to 100, according to FIG. 5, if we focus only on the LSB, it appears that the phase is delayed by 192 bits. However, at this time, the MSB increases by 1, so the read address of the coarse adjustment FIFO 113 decreases by 1 and the phase advances by 256 bits, and therefore the phase of the data output from the delay output unit 114 ultimately advances by 64 bits.

[0076] In other words, when the value of the coarse adjustment control signal increases by 1, the phase of the data output from the delay output unit 114 advances by 64 bits, and conversely, when the value of the coarse adjustment control signal decreases by 1, the phase of the data output from the delay output unit 114 lags behind by 64 bits.

[0077] 1 outputs a detection voltage corresponding to the phase difference between the divided clock or external clock selected by the clock selection unit 17 and the toggle pattern output from each transceiver 20. The toggle pattern is 1-bit serial data consisting of alternating repeats of "0" and "1", and is output from each transceiver 20 when a phase acquisition process or an initial voltage acquisition process, which will be described later, is executed. One phase detection unit 40 is disposed downstream of each transceiver 20. Since the phase detection unit 40 is used to check the phase of the toggle pattern output from each transceiver 20, it may be incorporated into the MUX 50 or may be disposed independently upstream of the MUX 50.

[0078] A schematic diagram of the phase detection unit 40 for one lane is shown in Fig. 6. As shown in the figure, the phase detection unit 40 includes, for example, a D flip-flop 41, an EXOR circuit 42, and an averaging circuit 43.

[0079] The D flip-flop 41 has two input terminals, a D terminal and a CLK terminal, and one output terminal, a Q terminal. A toggle pattern from the corresponding transceiver 20 is input to the D terminal, and a clock selected by the clock selection unit 17 is input to the CLK terminal.

[0080] The EXOR circuit 42 outputs a phase detection signal by taking the exclusive OR of the toggle pattern from the corresponding transceiver 20 and the output signal from the Q terminal of the D flip-flop 41. When a toggle pattern with a period twice that of the clock is input to the D terminal, the phase detection signal becomes a pulse-like signal with a duty ratio corresponding to the phase of the toggle pattern input to the D terminal.

[0081] The averaging circuit 43 is configured, for example, by a low-pass filter, and is configured to average the phase detection signal. When a toggle pattern with a period twice that of the clock is input to the D terminal, the averaging circuit 43 outputs a detection voltage signal according to the duty ratio of the phase detection signal. This makes it possible to obtain the phase of the toggle pattern from the corresponding transceiver 20 as a detection voltage.

[0082] The amplifier 52 amplifies the detected voltage signal from the phase detector 40 to a voltage level suitable for the ADC 55 at the subsequent stage, as required.

[0083] The ADC 55 samples the detection voltage signal amplified by the amplifier 52 at a predetermined sampling rate and converts it into digital data. That is, the ADC 55 outputs digital data of the detection voltage corresponding to the phase difference between the toggle pattern and the divided clock or external clock selected by the clock selection unit 17. Here, the predetermined sampling rate may be a value of several hundred ksps to several Msps, such as 500 ksps or 1 Msps. For this reason, an ADC with multiple input channels, such as a four-channel ADC, can also be used as the ADC 55.

[0084] The MUX 50 latches the m-bit parallel data output from each transceiver unit 12, selects n bits at a time in a predetermined order in synchronization with the external clock selected by the clock selection unit 17, and outputs n-bit data corresponding to the frequency of the external clock selected by the clock selection unit 17. Here, n is an integer greater than or equal to 1 and less than or equal to m-1. In the example shown in FIG. 1, n=1 and m=4. That is, the MUX 50 can multiplex the m-bit data from each transceiver unit 12 into n-bit data.

[0085] DAC 60 is an n×p-bit DAC that outputs an analog signal with n×p-bit resolution corresponding to the n×p-bit data output from all MUXes 50, i.e., a multi-level K PAM signal, where p is the number of transceiver units 12, and in the example shown in FIG. 1, n=1 and p=8.

[0086] The operation unit 65 is for accepting operation inputs by the user, and is configured, for example, as a touch panel equipped with a touch sensor for detecting a contact position by a touch operation on an input surface corresponding to a display screen of a display device (not shown). Alternatively, the operation unit 65 may be configured to include an input device such as a keyboard or a mouse. Operation inputs to the operation unit 65 are detected by the control unit 70.

[0087] The control unit 70 is composed of a control device such as a computer including, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an FPGA, a ROM (Read Only Memory), a RAM, and an HDD (Hard Disk Drive), and controls the operation of each of the above-mentioned components that make up the signal generating device 1.

[0088] 7 is a diagram showing the configuration of one lane of the transceiver unit 12. Each transceiver 20 includes a fine-tuning FIFO 21 that stores N bits of the L-bit parallel data output from the coarse-tuning unit 111, a parallel-in serial-out (PISO) 22 that converts the N-bit parallel data read from the fine-tuning FIFO 21 into 1-bit serial data in response to a read clock signal, a usage determination unit 23 that executes first and second usage determination processes to determine whether the usage of the fine-tuning FIFO 21 is equal to or greater than a usage threshold, a phase adjustment unit 24 that adjusts the phase of the read clock signal of the fine-tuning FIFO 21 so as to decrease or increase it, frequency dividers 25 and 26, and a subtractor 27.

[0089] That is, the transceiver 20 reads out the stored N-bit parallel data from the fine adjustment FIFO 21, performs parallel / serial conversion on the read parallel data in the PISO 22, and outputs the serial data.

[0090] In the signal generating device 1 of this embodiment, each transceiver unit 12 can be configured with a transceiver equipped with a function for adjusting the phase of a read clock signal, such as a TX Phase Interpolator PPM Controller (hereinafter referred to as "TXPI") provided by Xilinx, Inc. Furthermore, for example, an FPGA that configures the data output unit 10 can suitably be an UltraScale+ equipped with a GTY transceiver manufactured by Xilinx, Inc.

[0091] Generally, the timing at which multiple transceivers configured on an FPGA actually output data after they are started or reset does not necessarily match. Therefore, the usage amount of the fine-tuning FIFO 21 of each transceiver 20 is usually different when the data output starts. Furthermore, even when focusing on a single transceiver 20, the usage amount when the data output starts may differ each time the transceiver is started or reset.

[0092] The basic operation of TXPI in the fine adjustment mode will be described below with reference to FIG.

[0093] The fine adjustment FIFO 21 functions as a buffer for the parallel data output from the parallel data output unit 11 and is capable of storing up to M words of N-bit parallel data. The fine adjustment FIFO 21 writes or reads N-bit parallel data at the rising edge of an input write clock signal or read clock signal. The write clock signal and read clock signal are signals based on the clock signal output from the QPLL 28, for example.

[0094] The frequency divider 25 divides the read clock signal by the maximum number of words M of the fine-tuning FIFO 21 to obtain a read address for the fine-tuning FIFO 21. On the other hand, the frequency divider 26 divides the write clock signal by the maximum number of words M of the fine-tuning FIFO 21 to obtain a write address for the fine-tuning FIFO 21.

[0095] The subtractor 27 outputs the difference between the read address and the write address output from the frequency dividers 25 and 26. The difference output from the subtractor 27 reflects the usage amount of the fine adjustment FIFO 21.

[0096] The usage determination unit 23 executes first and second usage determination processes for determining, for each clock of the operation clock of the FPGA that constitutes the data output unit 10, whether the difference output from the subtractor 27 is equal to or greater than a usage threshold. The usage determination unit 23 constantly monitors the difference between the read address and write address of the fine-tuning FIFO 21 as the usage of the fine-tuning FIFO 21, and outputs 0 if this usage is less than the usage threshold, and 1 if it is equal to or greater than the usage threshold. For example, the usage threshold is M / 2, i.e., half the maximum number of words M of the fine-tuning FIFO 21. The usage of the fine-tuning FIFO 21 changes as the phase of the read clock signal changes.

[0097] The phase adjustment unit 24 executes a first phase adjustment process for decreasing the phase of the read clock signal by a predetermined amount and a second phase adjustment process for increasing the phase of the read clock signal by a predetermined amount in a usage control process in a fine adjustment mode, which will be described later. The first phase adjustment process is a process for decreasing the usage of the fine adjustment FIFO 21, and the second phase adjustment process is a process for increasing the usage of the fine adjustment FIFO 21.

[0098] The phase adjustment unit 24 can shift the read address value of the fine adjustment FIFO 21 by adjusting the phase of the read clock signal of the fine adjustment FIFO 21. This shifts the phase of the parallel data output from the fine adjustment FIFO 21. However, the phase adjustment unit 24 cannot adjust the phase of the parallel data output from the fine adjustment FIFO 21 to an arbitrary value, and the phase adjustment width and maximum adjustment amount that can be adjusted at one time are also limited. For example, when the output data rate of the transceiver 20 is 32 Gbps, the phase adjustment width that the phase adjustment unit 24 can adjust is 1 / 64 UI step width, and the maximum adjustment amount that the phase adjustment unit 24 can adjust is 64 UI.

[0099] The following describes the usage control process executed by the usage control processor 31a of the phase synchronization controller 31 (see FIG. 9) included in the FPGA controller 15, with reference to the state transition diagram in FIG. 8. The usage control process of the usage control processor 31a controls the usage of the fine-tuning FIFO 21 of each transceiver 20 in the fine-tuning mode, and is executed independently for each lane, i.e., for each transceiver 20.

[0100] 8, the usage control processor 31a includes eight states S1 to S7, namely, an initial state, a PRESET state, a BUFCHK1 state, a TXPI_DEC state, a TXPI_INC state, a BUFCHK2 state, and a PHASEADJ state. Arrows between states indicate transitions and their directions.

[0101] First, the usage control processor 31a transitions from the initial state S1 to the PRESET state S2. The PRESET state S2 is a standby state until each transceiver 20 starts outputting serial data. Here, each transceiver 20 starts generating a clock in a clock generation circuit (not shown) when it is ready to start outputting serial data after startup or reset. The usage control processor 31a can detect the rising edge of this clock to determine when each transceiver 20 starts outputting serial data.

[0102] When the usage control processing unit 31a detects that each transceiver 20 has started outputting serial data, it transitions from the PRESET state S2 to the BUFCHK1 state S3. The BUFCHK1 state S3 is a state in which the usage control processing unit 31a causes the usage determination unit 23 to execute the first usage determination process.

[0103] The usage control processing unit 31a transitions from the BUFCHK1 state S3 to the TXPI_DEC state S4 on the condition that the first usage determination process determines that the usage of the fine-tuning FIFO 21 of each transceiver 20 is equal to or greater than the usage threshold. The TXPI_DEC state S4 is a state in which the usage control processing unit 31a causes the phase adjustment unit 24 to execute the first phase adjustment process.

[0104] The usage control processor 31a transitions from the TXPI_DEC state S4 back to the BUFCHK1 state S3 on the condition that the phase of the read clock signal of the fine adjustment FIFO 21 of each transceiver 20 has been decreased by a predetermined amount by the first phase adjustment process.

[0105] The usage control processor 31a transitions from the BUFCHK1 state S3 to the TXPI_INC state S5 on the condition that the number of consecutive times that the usage of the fine-tuning FIFO 21 of each transceiver 20 is determined to be less than the usage threshold value by the first usage determination process reaches the first determination count. The TXPI_INC state S5 is a state in which the usage control processor 31a causes the phase adjuster 24 to execute the second phase adjustment process.

[0106] The usage control processor 31a transitions from the TXPI_INC state S5 to the BUFCHK2 state S6 on the condition that the phase of the read clock signal of the fine adjustment FIFO 21 of each transceiver 20 has been increased by a predetermined amount by the second phase adjustment process. The BUFCHK2 state S6 is a state in which the usage control processor 31a causes the usage determiner 23 to execute the second usage determination process.

[0107] The usage control processing unit 31a transitions from the BUFCHK2 state S6 back to the TXPI_INC state S5 on the condition that the usage of the fine-tuning FIFO 21 of each transceiver 20 is determined to be less than the usage threshold by the second usage determination process.

[0108] The usage control processor 31a transitions from the BUFCHK2 state S6 to the PHASEADJ state S7 on the condition that the number of consecutive times that the usage of the fine-tuning FIFO 21 of each transceiver 20 is determined to be equal to or greater than the usage threshold value in the second usage determination process reaches the second determination count. The PHASEADJ state S7 is a state in which the usage control processor 31a causes the phase adjuster 24 to finish adjusting the phase of the read clock signal and waits until a reset signal is input to each transceiver 20.

[0109] 8 for all transceivers 20, the usage control processing unit 31a can halve the usage of the fine adjustment FIFO 21 for all lanes, thereby aligning the data latency of all lanes. Since the phase of the multi-bit parallel data output from the parallel data output unit 11 is the same for all lanes, the phase of the serial data output from all transceivers 20 will also be approximately the same.

[0110] 8, when the phase adjustment width by phase adjustment unit 24 is 1 / 64 UI, the phase of the serial data output from transceiver 20 can be adjusted with a calculated accuracy of ±0.008 UI (theoretical limit value). Note that the first and second determination counts may be equal or different from each other.

[0111] 8, if the transitions from BUFCHK1 state S3 to TXPI_DEC state S4, from BUFCHK2 state S6 to TXPI_INC state S5, from BUFCHK1 state S3 to TXPI_INC state S5, and from BUFCHK2 state S6 to PHASEADJ state S7 are executed if the respective conditions for their transitions are satisfied once, the maximum phase difference between the serial data output from all transceivers 20 after phase adjustment is complete will be greater than the theoretical limit value. This is thought to be because the usage of the fine-adjustment FIFO 21 constantly fluctuates due to jitter components in the write clock signal and read clock signal, which causes fluctuations in the results of the first and second usage determination processes performed by the usage determiner 23.

[0112] Therefore, in the processing of the usage control processing unit 31a shown in Figure 8, the signal generating device 1 of this embodiment specifies the first and second number of judgments that must be made consecutively to satisfy the transition conditions for the transition from the BUFCHK1 state S3 to the TXPI_INC state S5 and the transition from the BUFCHK2 state S6 to the PHASEADJ state S7, and executes the transition only if the transition conditions are met that number of times in a row.

[0113] As shown in FIG. 9, the FPGA control unit 15 includes a phase synchronization control unit 31, a frequency division ratio setting unit 33, a rate control unit , and a clock selection signal output unit .

[0114] The rate control unit 34 controls each transceiver 20 to output, as 1-bit serial data from each transceiver 20, a toggle pattern having a frequency that is half the frequency of the divided clock or external clock selected by the clock selection unit 17. For example, the rate control unit 34 controls the parallel data output unit 11 to output N-bit parallel data such that the frequency of the toggle pattern output from each transceiver 20 is half the frequency of the divided clock or external clock.

[0115] The clock selection signal output unit 35 outputs a clock selection signal for selecting either the external clock or the divided clock to the clock selection unit 17. Specifically, when the division ratio set by the division ratio setting unit 33 is equal to or less than a predetermined value, the clock selection signal output unit 35 outputs a clock selection signal for causing the clock selection unit 17 to select the external clock instead of the divided clock after the first phase shift process or the second phase shift process is executed. The minimum value of the division ratio is, for example, an integer equal to or less than 4.

[0116] In the coarse adjustment mode, the phase synchronization control unit 31 causes the multiple coarse adjustment units 111 to coarsely adjust the phase of the parallel data output from the parallel data output unit 11, thereby indirectly controlling the phase of the toggle pattern, which is serial data output from each transceiver 20. In the fine adjustment mode, the phase synchronization control unit 31 directly controls the phase of the toggle pattern, which is serial data output from each transceiver 20.

[0117] Here, the toggle pattern and the frequency division ratio in the coarse adjustment mode will be explained.

[0118] For example, when the divided clock output section 14 outputs a divided clock with a division ratio of 128 and a frequency of 250 MHz based on a 32 GHz external clock, the frequency of the toggle pattern output from each transceiver 20 is half that, 125 MHz.

[0119] In this case, when the value of the coarse adjustment control signal changes by 1 (a change of 64 bits), the phase of the toggle pattern changes by 0.25 UI, assuming one cycle of the divided clock is 1 UI. In other words, when using a divided-by-128 clock, for example, if the value of the coarse adjustment control signal changes by ±2, the phase of the toggle pattern will change by ±0.5 UI relative to the divided clock.

[0120] Similarly, when the divided clock output section 14 outputs a divided clock with a division ratio of 256 and a frequency of 125 MHz based on a 32 GHz external clock, the frequency of the toggle pattern output from each transceiver 20 is half that, 62.5 MHz.

[0121] In this case, when the value of the coarse adjustment control signal changes by 1 (a change of 64 bits), the phase of the toggle pattern changes by 0.125 UI, assuming one cycle of the divided clock is 1 UI. In other words, when using a divided clock with a frequency division of 256, for example, if the value of the coarse adjustment control signal changes by ±4, the phase of the toggle pattern will change by ±0.5 UI relative to the divided clock.

[0122] The phase synchronization control unit 31 includes a usage control processing unit 31a, a phase acquisition processing unit 31b, an initial voltage acquisition processing unit 31c, a phase difference calculation processing unit 31d, and a phase movement processing unit 31e.

[0123] As already described, the usage control processing of the usage control processing unit 31a includes processing for causing the usage determination unit 23 to execute a first usage determination processing, processing for causing the phase adjustment unit 24 to execute a first phase adjustment processing, processing for causing the usage determination unit 23 to execute a second usage determination processing, processing for causing the phase adjustment unit 24 to execute a second phase adjustment processing, and processing for causing the phase adjustment unit 24 to end adjustment of the phase of the read clock signal. The usage control processing unit 31a executes the above-described usage control processing before the phase acquisition processing, which will be described later, is executed by the phase acquisition processing unit 31b.

[0124] The phase acquisition processing unit 31b changes the phase of the toggle pattern output from each transceiver 20 from its initial value, and obtains the initial value V0 and maximum value V1 of the detected voltage output from the phase detection unit 40. H , and the minimum value V L Here, the digital data of the detected voltage is input from the ADC 55 to the phase acquisition processing unit 31b.

[0125] In the coarse adjustment mode, the phase acquisition processing unit 31b controls each coarse adjustment unit 111 by changing the value of the coarse adjustment control signal, thereby changing the phase of the toggle pattern output from each transceiver 20 from its initial value. In the fine adjustment mode, the phase acquisition processing unit 31b controls the phase adjustment unit 24 of each transceiver 20, thereby changing the phase of the toggle pattern output from each transceiver 20 from its initial value.

[0126] A specific example of the phase acquisition process by the phase acquisition processor 31b will be described below. The phase acquisition processor 31b performs the phase acquisition process on all toggle patterns for 32 lanes simultaneously or sequentially. Figure 10 shows the relationship between the toggle pattern and the clock output from the transceiver 20 of one lane of the data output unit 10.

[0127] First, the phase acquisition processing unit 31b acquires the detected voltage output from the phase detection unit 40 at the start of the phase acquisition process. Here, the phase of the toggle pattern at the start is set to 0 UI. Furthermore, the phase synchronization control unit 31 acquires the detected voltage output from the phase detection unit 40 while moving the phase of the toggle pattern within a range of -0.75 UI to +0.75 UI, with one clock cycle at that time being set to 1 UI. For example, as shown by the arrows in FIG. 10, the phase synchronization control unit 31 moves the phase of the toggle pattern from 0 UI, which is the initial value at the start of the phase acquisition process, to -0.75 UI, then from -0.75 UI to +0.75 UI, and finally from +0.75 UI to 0 UI at the start.

[0128] For example, in fine adjustment mode, this means that the operation of measuring the detected voltage output from phase detection unit 40 is repeated every time the phase of the toggle pattern is moved by approximately 0.1 UI. This allows the results shown in Figure 11 to be obtained. In the graph of Figure 11, the horizontal axis represents the amount of change [UI] in the phase of the toggle pattern from its initial value, and the vertical axis represents the detected voltage [V] output from phase detection unit 40.

[0129] On the other hand, in the coarse adjustment mode, for example, when the division ratio of the divided clock is 128, the minimum phase shift of the toggle pattern is 0.25 UI, so although the number of data points is reduced, it is still possible to obtain detection voltage data such as that shown in Figure 11.

[0130] In the coarse adjustment mode, the phase acquisition process, the initial voltage acquisition process (described later), and the phase difference calculation process (described later) may be performed using one transceiver 20 included in each transceiver unit 12. For example, Fig. 3 shows a configuration for performing the process in the coarse adjustment mode using the transceiver 20-1 of lane 1.

[0131] In the phase acquisition process, for example, eight ADC55s with four-channel input and 500 ksps are used, and digital data of the detected voltage is acquired 10 times per channel per measurement point for averaging. In this case, a measurement time of about 80 μs is required per measurement point. If the toggle pattern phase is shifted and measured at 32 measurement points, the measurement time required is approximately 3 ms.

[0132] In fine adjustment mode, TXPI adjusts the phase of the serial data from each transceiver 20 based on the usage of the fine adjustment FIFO 21, so if the usage is uneven in the initial state, it may not be possible to ensure an adjustment range of ±0.75 UI. For this reason, the phase synchronization control unit 31 performs the usage control process described above, so that the phase of the toggle pattern can be moved within a range of ±0.75 UI.

[0133] In the above description, the range of phase change of the toggle pattern is -0.75 UI to +0.75 UI, but the present invention is not limited to this. The range of phase change of the toggle pattern needs to be at least 1 UI, and the phase of the toggle pattern may be changed within the range of -0.5 UI to +0.5 UI, for example.

[0134] Furthermore, the phase acquisition processing unit 31b calculates an initial value V0, which is the detected voltage at the start of the phase acquisition process, and a maximum value VH , the minimum value of the detection voltage V L Get.

[0135] 11, the relationship between the detected voltage and the phase of the toggle pattern exhibits linearity in units of 1 UI. Therefore, the phase acquisition processing unit 31b uses the linear least squares method to find an approximation line of the relationship between the detected voltage and the phase of the toggle pattern, rather than the output value itself from the phase detection unit 40, and obtains the initial value V0 and the maximum value V H , minimum value V L Calculate.

[0136] This reduces the influence of disturbances such as noise on the measurement result of the phase difference between the clock and the toggle pattern by the phase detection unit 40, and the initial value V0 and the maximum value V H , minimum value V L The accuracy of each value of can be improved.

[0137] The initial voltage acquisition processing unit 31c is configured to perform an initial voltage acquisition process to acquire the detected voltage output from the phase detection unit 40 as an initial voltage V0' after the phase of the toggle pattern output from each transceiver 20 is shifted by the phase shift processing unit 31e described later.

[0138] That is, the initial voltage acquisition process by the initial voltage acquisition processor 31c is premised on the fact that the phase acquisition process by the phase acquisition processor 31b has already been performed. The initial voltage acquisition process does not move the phase of the toggle pattern, but only acquires the initial voltage V0', which is the detected voltage at the time the initial voltage acquisition process is performed. For this reason, the initial voltage acquisition process can also be considered a part of the phase acquisition process. The initial voltage acquisition processor 31c is configured to perform the initial voltage acquisition process simultaneously or sequentially for all toggle patterns for 32 lanes.

[0139] The phase difference calculation processing unit 31d calculates the initial value V0 and the maximum value V1 of the detected voltage acquired by the phase acquisition processing unit 31b. H , and the minimum value V LBased on this, a first initial phase difference P between the divided clock or the external clock selected by the clock selection unit 17 and the initial value of the phase of the toggle pattern is calculated. C1 The first phase difference calculation process is executed to calculate the following.

[0140] Furthermore, the phase difference calculation processing unit 31d calculates the maximum value V of the detected voltage acquired by the phase acquisition processing of the phase acquisition processing unit 31b. H and minimum value V L and the initial voltage V0′ acquired by the initial voltage acquisition processing of the initial voltage acquisition processing unit 31c, a second initial phase difference P between the frequency-divided clock selected by the clock selection unit 17 and the phase of the toggle pattern shifted by the phase shift processing unit 31e described later is calculated. C2 In this specification, the first phase difference calculation process and the second phase difference calculation process are collectively referred to simply as "phase difference calculation process."

[0141] The phase difference calculation processing unit 31d calculates the initial value V0 and maximum value V of the detected voltage acquired by the phase acquisition processing. H , and the minimum value V L By substituting into the following equation (1), the first initial phase difference P of the toggle pattern at the start of the phase acquisition process is obtained. C1 Furthermore, the phase difference calculation processing unit 31d calculates the maximum value V of the detected voltage obtained by the phase acquisition processing. H and minimum value V L and the initial voltage V0′ acquired by the initial voltage acquisition process into the following equation (2), the second initial phase difference P C2 In this specification, the first initial phase difference P C1 and the second initial phase difference P C2 are summed up and simply referred to as "initial phase difference P C " is also called.

[0142]

number

[0143]

number

[0144] That is, the second phase difference calculation process is performed by calculating the maximum value V of the detected voltage acquired by the phase acquisition process. H and minimum value V L Since the initial phase difference P C For example, if the measurement conditions are the same as those exemplified for the phase acquisition process, the measurement time required for the initial voltage acquisition process is about 80 μs.

[0145] The phase synchronization control unit 31 performs the same phase difference calculation process for all toggle patterns for 32 lanes simultaneously or sequentially. As a result, for example, the lane numbers and initial phase differences P C The correspondence is obtained.

[0146] 12(a) to 12(c), lane numbers 0 to 3 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-1, respectively. Lane numbers 4 to 7 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-2, respectively. Lane numbers 8 to 11 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-3, respectively. Lane numbers 12 to 15 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-4, respectively. Lane numbers 16 to 19 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-5, respectively. Lane numbers 20 to 23 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-6, respectively. Lane numbers 24 to 27 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-7, respectively. Lane numbers 28 to 31 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-8, respectively.

[0147] The phase shift processing unit 31e shifts the phase of the toggle pattern output from each transceiver 20 so that the phase difference between the divided clock or external clock selected by the clock selection unit 17 and the toggle pattern is a value (phase difference) within a predetermined range.

[0148] In the coarse adjustment mode, the phase shift processing unit 31e controls each coarse adjustment unit 111 by changing the value of the coarse adjustment control signal to shift the phase of the toggle pattern output from each transceiver 20. In this case, the value within the predetermined range is the value closest to 0 within the precision of the phase adjustment width that each coarse adjustment unit 111 can adjust.

[0149] Furthermore, in the fine adjustment mode, the phase shift processing unit 31e controls the phase adjustment unit 24 of each transceiver 20 to shift the phase of the toggle pattern output from each transceiver 20. In this case, the value within the predetermined range is the value closest to 0 within the precision of the phase adjustment width that the phase adjustment unit 24 can adjust.

[0150] The phase shift processing unit 31e shifts the phase of the toggle pattern output from each transceiver 20 from the initial value at the start of the phase acquisition process by a first initial phase difference P C1 The first phase shift process shifts the toggle pattern phase by the second initial phase difference P C2 In this specification, the first phase shift process and the second phase shift process are collectively referred to simply as "phase shift process."

[0151] Hereinafter, the phase shift processing of the toggle pattern of each lane performed by the phase shift processing unit 31e will be described with reference to FIGS. 12(a) to 12(c).

[0152] FIG. 12(a) shows the initial phase difference P CIn this case, the phase shift processing unit 31e shifts the phase of the toggle pattern of all lanes toward 0 by -P C The initial phase difference P C The same is true if is negatively distributed.

[0153] FIG. 12(b) shows the initial phase difference P C is distributed either positively or negatively, and the distribution width is less than 0.5 UI. In this case, the phase shift processing unit 31e shifts the phase of the toggle pattern that is distributed positively toward 0 by -P C The phase of the toggle pattern shifts negatively towards 0. C Move only.

[0154] FIG. 12(c) shows the initial phase difference P C is distributed in either positive or negative directions, and the positive distribution and the negative distribution are separated by 0.5 UI or more. In this case, the initial phase difference P C It is considered that a part of the distribution of 1+P appears to be shifted by 1 UI. For this reason, the phase shift processing unit 31e shifts the phase of the toggle pattern that is positively distributed in the positive direction toward 0 by, for example, 1+P C and shifts the phase of the negatively distributed toggle pattern towards 0 in the positive direction -P C Move only.

[0155] As can be seen from FIGS. 12(a) to 12(c), the four transceivers 20 included in the same transceiver unit 12 have the same initial phase difference P C For this reason, the phase synchronization control unit 31 performs the phase acquisition process, the initial voltage acquisition process, and the phase difference calculation process for only one transceiver 20 included in each transceiver unit 12, and calculates the obtained initial phase difference P C may be regarded as an initial phase difference common to the four transceivers 20 included in each transceiver unit 12.

[0156] The division ratio setting unit 33 is configured to set the division ratio of the divided clock based on the external clock to the divided clock output unit 14. The phase synchronization control unit 31 repeatedly executes an initial voltage acquisition process, a second phase difference calculation process, and a second phase movement process, which are parts of the phase acquisition process, while the division ratio setting unit 33 gradually decreases the division ratio.

[0157] The minimum division ratio set by the division ratio setting unit 33 in the coarse adjustment mode is equal to or greater than the maximum division ratio set by the division ratio setting unit 33 in the fine adjustment mode. For example, in this embodiment, the minimum division ratio in the coarse adjustment mode is 128, and the maximum division ratio in the fine adjustment mode is 64.

[0158] In the prior art, the frequency division ratio is an integer that is a power of 2, and is repeatedly halved to change, for example, 64, 32, 16, 8, 4, and 2 in that order.

[0159] In the signal generating device 1 of this embodiment, the division ratio is, for example, an integer that is a power of 2 or 4, and the minimum value is 4 or less. The division ratio setting unit 33 repeatedly reduces the division ratio to 1 / 4. For example, if the maximum division ratio is 256, the division ratio setting unit 33 changes the division ratio in the order of 256, 64, 16, and 4. Furthermore, if the maximum division ratio is 128, for example, the division ratio setting unit 33 changes the division ratio in the order of 128, 32, 8, and 2.

[0160] Compared to the prior art technology in which the division ratio is reduced by 1 / 2, the signal generating device 1 of this embodiment reduces the division ratio by 1 / 4, thereby speeding up the process of matching the maximum phase difference between the toggle patterns of each lane with an accuracy of 0.1 UI or less based on the divided clock, and reducing the time required for phase matching between lanes.

[0161] Furthermore, if the maximum phase difference between the toggle patterns of each lane can be adjusted to an accuracy of 0.1 UI or less based on the divided clock, the division ratio is not limited to 1 / 4 and may be the reciprocal of an integer that is a power of 2, such as 1 / 8 or 1 / 16.

[0162] 13 is a diagram showing, for each division ratio in fine adjustment mode, when the toggle pattern phase is shifted within a range of −0.75 UI to +0.75 UI relative to 1 UI of the divided clock, the amount of shift in the toggle pattern phase due to the phase acquisition process as a percentage of the capacity of the fine adjustment FIFO 21. For example, the capacity of the fine adjustment FIFO 21 is equivalent to 128 UI when 1 clock of the external clock is taken as 1 UI, and is equivalent to 2 UI (±1 UI) for a divided clock obtained by dividing the external clock by a maximum of 64.

[0163] When the division ratio is 64, 75% of the capacity of the fine adjustment FIFO 21 is used to shift the phase of the toggle pattern. Thereafter, the amount of shift becomes 1 / 4 every time the division ratio becomes 1 / 4, and when the division ratio is 1, the amount of shift becomes 1.17% of the capacity of the fine adjustment FIFO 21.

[0164] An example of the signal generation method using the signal generating device 1 of this embodiment will be described below with reference to the flowcharts in Figures 14, 15, 16, 17(a), (b), and (c). Note that descriptions that overlap with the description of the configuration of the signal generating device 1 described above will be omitted as appropriate. The processing shown in this flowchart is performed for each of the 32 lanes of output.

[0165] First, when each transceiver unit 12 is started or reset (step S11: YES), the phase synchronization control unit 31 executes processing in the coarse adjustment mode (step S12). For example, when the bit rate of the PAM signal output from the signal generating device 1 is changed by a user's operation input to the operation unit 65, each transceiver unit 12 is reset.

[0166] The process in the coarse adjustment mode is performed using one transceiver 20-1 in each transceiver unit 12. As shown in Fig. 15, the process in step S12 includes the processes in steps S21 to S28.

[0167] [Coarse mode processing] In step S21, the phase synchronization control unit 31 sets an initial value of the coarse adjustment control signal (step S21). For example, if the coarse adjustment control signal is a signal consisting of a 10-bit value, it is conceivable to set the initial value to 512, which is approximately half the maximum value.

[0168] Next, the clock selection unit 17 selects a divided clock (divided clock selection step S22).

[0169] Next, the frequency division ratio setting unit 33 sets the value of the frequency division ratio of the frequency-divided clock in the frequency-divided clock output unit 14 to 1024 (frequency division ratio setting step S23). At this time, there is a phase difference between the frequency-divided clock and the external clock, but this does not need to be taken into consideration at this point.

[0170] Next, the FPGA control unit 15 executes a full-range phase measurement process using the frequency-divided clock (step S24). As shown in Fig. 17(a), the process of step S24 includes the processes of steps S41 to S43.

[0171] In step S41, the rate control unit 34 causes each transceiver 20 to output a toggle pattern having a frequency half the frequency of the frequency-divided clock whose division ratio has been set to 1024 in the frequency-division ratio setting step S23 (rate control step S41).

[0172] Next, the phase acquisition processing unit 31b calculates the initial value V0 and maximum value V1 of the detected voltage output from the phase detection unit 40 while changing the phase of the toggle pattern output from the transceiver 20-1 from the initial value in the range of −0.75 UI to +0.75 UI, with one cycle of the frequency-divided clock having a frequency division ratio of 1024 being 1 UI. H , and the minimum value V L(phase acquisition processing step S42).

[0173] Next, the phase difference calculation processing unit 31d calculates the initial value V0 and maximum value V of the detected voltage acquired in the phase acquisition processing step S42. H , and the minimum value V L Based on this, a first initial phase difference P between the divided clock having a division ratio of 1024 and the initial value of the phase of the toggle pattern output from the transceiver 20-1 is calculated. C1 A first phase difference calculation process is executed to calculate the phase difference (phase difference calculation process step S43).

[0174] Next, the phase shift processing unit 31e shifts the phase of the toggle pattern from the initial value to the first initial phase difference P so that the phase difference between the frequency-divided clock, whose frequency division ratio is set to 1024 in the frequency division ratio setting step S23, and the toggle pattern output from the transceiver 20-1 falls within a predetermined range. C1 Then, a first phase shift process is executed to shift the phase by the amount of (phase shift process step S25).

[0175] If the current division ratio is greater than 64 (step S26: NO), the division ratio setting unit 33 sets the division ratio of the divided clock in the divided clock output unit 14 to 1 / 4 of the current value (division ratio setting step S27).

[0176] Next, the FPGA control unit 15 executes a current phase measurement process (step S28). As shown in FIG. 17(c), the process of step S28 includes the processes of steps S47 to S49.

[0177] In step S47, the rate control unit 34 causes each transceiver 20 to output a toggle pattern having a frequency that is half the frequency of the divided clock having the division ratio set in the division ratio setting step S27 (rate control step S47).

[0178] Next, the initial voltage acquisition processing unit 31c executes an initial voltage acquisition process to acquire the detected voltage output from the phase detection unit 40 as an initial voltage V0' (initial voltage acquisition process step S48).

[0179] Next, the phase difference calculation processing unit 31d calculates the maximum value V of the detected voltage acquired in the phase acquisition processing step S42. H and minimum value V L and a second initial phase difference P between the phase of the toggle pattern output from the transceiver 20-1 and the frequency-divided clock selected by the clock selector 17 based on the initial voltage V0′ acquired in the initial voltage acquisition process step S48. C2 Then, a second phase difference calculation process is executed to calculate the phase difference (phase difference calculation process step S49).

[0180] Next, in step S25, the phase shift processing unit 31e shifts the phase of the toggle pattern from the current value to the second initial phase difference P so that the phase difference between the divided clock having the division ratio set in the division ratio setting step S27 and the toggle pattern output from the transceiver 20-1 falls within a predetermined range. C2 Then, the second phase shift process is executed to shift the phase by the amount of (phase shift process step S25). Then, the process from step S26 onwards is executed again.

[0181] That is, steps S25 to S28 are steps for repeatedly executing the initial voltage acquisition process, the second phase difference calculation process, and the second phase movement process while gradually decreasing the frequency division ratio in the frequency division ratio setting step S27.

[0182] On the other hand, if the current division ratio is 64 or less (step S26: YES), the process of step S13 is executed.

[0183] [Fine-tuning mode processing] 16, the process of step S13 includes the processes of steps S31 to S39. In step S13, the phase synchronization control section 31 executes the process of the fine adjustment mode (step S13).

[0184] First, the phase synchronization control unit 31 executes a usage control process (step S31). By the usage control process, the usage of the fine adjustment FIFO 21 of each transceiver 20 is halved.

[0185] FIG. 18 is a simplified diagram illustrating an example of the phase relationship of the toggle patterns output from the transceiver 20 of each lane after the usage control process in fine adjustment mode. The vertical dashed lines in the diagram indicate the rising edges of the external clock. Each transceiver unit 12 has four lanes, Lane 0 to Lane 3. "Ch1 Lane 0," "Ch1 Lane 2," "Ch4 Lane 0," and "Ch7 Lane 3" in the diagram represent Lane 0 of the transceiver unit 12-1, Lane 2 of the transceiver unit 12-1, Lane 0 of the transceiver unit 12-4, and Lane 3 of the transceiver unit 12-7, respectively. Data indicated by "0" in the toggle pattern of each lane is data that should be in phase across all lanes. This notation is used in subsequent figures. After the usage control process, the phases of the toggle patterns of each lane are usually shifted by more than one clock of the external clock.

[0186] Next, the FPGA control unit 15 executes a full-area phase measurement process using a divided clock with a division ratio of 64 or less that is currently set (step S32). The process of step S32 is the same as the processes of steps S41 to S43 in the coarse adjustment mode, except that it is executed for the transceivers 20 of all lanes and the value of the division ratio is different.

[0187] FIG. 19(a) shows the first initial phase difference P C1 1 is a simplified diagram showing the timing of the toggle patterns of each lane immediately after the calculation of . At this time, if the maximum phase difference between the toggle patterns of each lane is 32 UI or less based on the external clock, the subsequent phase shift process can be executed without error.

[0188] Next, the phase shift processing unit 31e shifts the phase of the toggle pattern from the initial value to the first initial phase difference P so that the phase difference between the frequency-divided clock whose frequency division ratio is set to 64 or less in the frequency division ratio setting step S27 and the toggle pattern output from each transceiver 20 falls within a predetermined range.C1 Then, a first phase shift process is executed to shift the phase by the amount of (phase shift process step S33).

[0189] 19(b) is a simplified diagram showing the timing of the toggle patterns of each lane immediately after the phase is shifted by the first phase shift process when the division ratio of the divided clock is 64. At this time, the maximum phase difference between the toggle patterns of all lanes is adjusted to 0.1 UI or less based on the divided clock, that is, 6.4 UI or less (0.1 UI × 64 division) based on the external clock.

[0190] If the current division ratio is greater than 4 (step S34: NO), the division ratio setting unit 33 sets the division ratio of the divided clock in the divided clock output unit 14 to 1 / 4 of the current value (division ratio setting step S35).

[0191] Next, the FPGA control unit 15 executes a current phase measurement process (step S36). The process of step S36 is similar to the processes of steps S47 to S49 in the coarse adjustment mode, except that it is executed for the transceivers 20 of all lanes and the value of the frequency division ratio is different.

[0192] Next, in step S33, the phase shift processing unit 31e shifts the phase of the toggle pattern from the current value to the second initial phase difference P so that the phase difference between the divided clock having the division ratio set in the division ratio setting step S35 and the toggle pattern output from each transceiver 20 falls within a predetermined range. C2 Then, the second phase shift process is executed to shift the phase by the amount of (phase shift process step S33). Then, the process from step S34 onwards is executed again.

[0193] That is, steps S33 to S36 are steps for repeatedly executing the initial voltage acquisition process, the second phase difference calculation process, and the second phase movement process while gradually decreasing the frequency division ratio in the frequency division ratio setting step S35.

[0194] 20(a) shows that when the division ratio of the divided clock is decreased by 1 / 4 from 64 by the division ratio setting unit 33 and reaches 4, the second initial phase difference P C2 FIG. 10 is a simplified diagram showing the timing of the toggle pattern of each lane immediately after the calculation of

[0195] 20(b) is a simplified diagram showing the timing of the toggle patterns of each lane immediately after the phase is shifted by the second phase shift process when the division ratio of the divided clock is 4. At this time, the maximum phase difference between the toggle patterns of all lanes is adjusted to 0.1 UI or less based on the divided clock, that is, 0.4 UI or less (0.1 UI × 4 division) based on the external clock.

[0196] On the other hand, if the current division ratio is 4 or less (step S34: YES), the clock selection unit 17 selects the external clock instead of the divided clock (external clock selection step S37). The external clock corresponds to a divided clock with a division ratio of 1, but its phase does not match that of the normal divided clock.

[0197] Next, the FPGA control unit 15 executes a full-range phase measurement process using the external clock (step S38). As shown in FIG. 17(b), the process of step S38 includes the processes of steps S44 to S46.

[0198] In step S44, the rate control unit 34 causes each transceiver 20 to output a toggle pattern having a frequency that is half the frequency of the external clock (rate control step S44).

[0199] Next, the phase acquisition processing unit 31b calculates the initial value V0 and maximum value V1 of the detected voltage output from the phase detection unit 40 while changing the phase of the toggle pattern output from each transceiver 20 from the initial value within the range of −0.75 UI to +0.75 UI, with one cycle of the external clock being 1 UI. H , and the minimum value V L (phase acquisition process step S45).

[0200] Next, the phase difference calculation processing unit 31d calculates the initial value V0 and the maximum value V of the detected voltage acquired in the phase acquisition processing step S45. H , and the minimum value V L Based on this, a first initial phase difference P between the external clock and the initial value of the phase of the toggle pattern output from each transceiver 20 is calculated. C1 Then, a first phase difference calculation process is executed to calculate the phase difference (phase difference calculation process step S46).

[0201] FIG. 21(a) shows the first initial phase difference P C1 FIG. 10 is a simplified diagram showing the timing of the toggle pattern of each lane immediately after the calculation of

[0202] Next, the phase shift processing unit 31e shifts the phase of the toggle pattern from the initial value to the first initial phase difference P so that the phase difference between the external clock selected in the external clock selection step S37 and the toggle pattern output from each transceiver 20 falls within a predetermined range. C1 Then, a first phase shift process is executed to shift the phase by the amount of (phase shift process step S39).

[0203] 21(b) is a simplified diagram showing the timing of the toggle patterns of each lane immediately after the phase is shifted by the first phase shift process when the external clock is selected by the clock selection unit 17. At this time, the maximum phase difference between the toggle patterns of all lanes is adjusted to 0.1 UI (0.1 UI × 1 division) or less based on the external clock.

[0204] Then, the phase synchronization control unit 31 goes into a standby state until each transceiver unit 12 is activated or reset again (step S11).

[0205] In step S11, the transceiver units 12 are started or reset, so that the processes from step S12 onward are automatically executed, but the present invention is not limited to this. For example, in step S11, the user may press an execute button provided on an operation screen (not shown) of the signal generating device 1 via the operation unit 65, so that the user can execute the processes from step S12 onward at any timing.

[0206] When the phase adjustment of the toggle pattern output from each transceiver 20 is completed in step S39, the FPGA control unit 15 automatically transitions to a mode for generating a PAM signal during normal operation, and causes the parallel data output unit 11 to output N-bit parallel data for normal operation according to the frequency of the external clock.

[0207] As described above, the signal generation method using the signal generator 1 of this embodiment starts in a coarse adjustment mode by gradually using a divided clock, for example, divided by 1024 to divided by 64, to roughly adjust the phase of 256-bit data input from the parallel data output unit 11 to each transceiver unit 12 in 64-bit units.Then, the signal generation method using the signal generator 1 of this embodiment then gradually uses a divided clock of 64 or less and an external clock in a fine adjustment mode to finely adjust the phase of the toggle pattern of each lane.

[0208] In steps S33 to S36, in which the initial voltage acquisition process, the second phase difference calculation process, and the second phase shift process are repeatedly performed while gradually decreasing the division ratio of the divided clock, the maximum value V of the detected voltage increases as the frequencies of the clock and the toggle pattern increase. H and minimum value V L Therefore, in the signal generation method using the signal generator 1 of this embodiment, the relationship between the phase of the detection voltage and the toggle pattern is measured again by the full-range phase measurement process using the external clock in step S38, and the maximum value V of the detection voltage that matches the frequency of the external clock is calculated. H and minimum value V L It is designed to obtain the following.

[0209] As described above, the signal generating device 1 of this embodiment indirectly controls the phase of the serial data output from each transceiver 20 by coarsely adjusting the phase of the parallel data output from the parallel data output unit 11 using multiple coarse adjustment units 111, and then directly controls the phase of the serial data output from each transceiver 20 using the phase adjustment units 24 within each transceiver 20.

[0210] With this configuration, the signal generating device 1 of this embodiment can significantly increase the maximum phase difference that can be phase-matched between the serial data output from each of the multiple transceivers 20, compared to the prior art technology in which the phase of the serial data from each transceiver 20 was only directly controlled by the phase adjustment unit 24.

[0211] Furthermore, due to this configuration, when the signal generating device 1 of this embodiment is configured as an AWG, the degree of freedom in component placement is improved and the tolerance for differences in signal path length is increased, making it easier to configure a circuit that prevents crosstalk and noise from entering, and improving signal quality is expected.

[0212] Furthermore, the signal generating device 1 according to this embodiment is configured to change the phase of the toggle pattern from each transceiver 20 by changing the value of the coarse adjustment control signal input to the coarse adjustment unit 111 in the coarse adjustment mode.

[0213] Specifically, the coarse adjustment FIFO 113 can adjust the data phase in 256-bit increments. In contrast, the practical adjustable width of the phase adjustment unit 24 of each transceiver 20 is less than 128 bits. Therefore, a means is needed to bridge the gap between the adjustable width of 256 bits and the adjustable width of less than 128 bits. The signal generating device 1 of this embodiment realizes this means using the delay output unit 114 and the coarse adjustment control signal.

[0214] With this configuration, the signal generating device 1 according to this embodiment can expand the adjustable range of the phase of the toggle pattern from each transceiver 20. The upper limit of the adjustable range is the same as the capacity of the coarse adjustment FIFO 113. For example, if the capacity of the coarse adjustment FIFO 113 is 2048 bytes, the adjustable phase range is ±8192 UI.

[0215] Furthermore, after completing the phase adjustment of all lanes, the signal generating device 1 according to this embodiment can also change the phase of the final output signal from the DAC 60 by, for example, having the FPGA control unit 15 add or subtract the same value to the coarse adjustment control signals of all coarse adjustment units 111. For example, it is possible to adjust the phase of the output signal from the DAC 60 by dividing the number of bits corresponding to the amount of phase change desired by 64, adding or subtracting this value to or from the coarse adjustment control signal, and then adjusting the remainder using the phase adjustment unit 24 of each transceiver 20. This is a function that is certainly required when configuring an AWG with multiple output channels.

[0216] Furthermore, the signal generating device 1 of this embodiment is provided with one coarse adjustment unit 111 for one transceiver unit 12 having four transceivers 20, and therefore, phase matching can be performed efficiently between multiple transceiver units 12. [Explanation of symbols]

[0217] 1. Signal Generator 10 Data output section 11 Parallel data output section 12, 12-1 to 12-8 Transceiver section 14-divided clock output section 15 FPGA control unit 17 Clock selection section 20,20-0~20-3 Transceiver 21 FIFO for fine adjustment 28 QPLL 31 Phase synchronization control section 31a Usage control processing unit 31b Phase acquisition processing unit 31c Initial voltage acquisition processing section 31d Phase difference calculation processing unit 31e Phase shift processing unit 33 Division ratio setting section 34 Rate control section 40 Phase detection section 111,111-1~111-8 Coarse adjustment section 112 FIFO for speed adjustment 113 FIFO for rough adjustment 114 Delay output section 115 Controller 116 Counter 117 MSB extraction part 118 LSB extraction part 119 Subtraction Section 120-0~120-3 Data extraction section 121-1 to 121-3 registers 122,122-0~122-4 MUX 123 Data Joint

Claims

1. a parallel data output unit (11) that outputs parallel data of multiple bits; a plurality of coarse adjustment units (111) for coarsely adjusting the phase of the parallel data output from the parallel data output unit; a plurality of transceivers (20) for converting N bits of the parallel data roughly adjusted by each of the coarse adjustment units into 1-bit serial data; a phase synchronization control unit (31) that indirectly controls the phase of the serial data output from each of the transceivers by roughly adjusting the phase of the parallel data output from the parallel data output unit using the plurality of coarse adjustment units in a coarse adjustment mode, and directly controls the phase of the serial data output from each of the transceivers in a fine adjustment mode; a divided clock output unit (14) that outputs a divided clock obtained by dividing the frequency of an external clock; a division ratio setting unit (33) that sets the division ratio of the divided clock to the divided clock output unit; a clock selection unit (17) that selects either the divided clock or the external clock; a rate control unit (34) that controls each of the transceivers to output, as the serial data, a toggle pattern having a frequency that is half the frequency of the divided clock or the external clock selected by the clock selection unit; a phase detection unit (40) that outputs a detection voltage corresponding to a phase difference between the divided clock or the external clock selected by the clock selection unit and the toggle pattern, The phase synchronization control unit a phase acquisition processing unit (31b) that executes a phase acquisition process to acquire the detected voltage output from the phase detection unit while changing the phase of the toggle pattern from an initial value; a phase difference calculation processing unit (31d) that executes a phase difference calculation process to calculate an initial phase difference between the divided clock or the external clock selected by the clock selection unit and the initial value of the phase of the toggle pattern, based on the detection voltage acquired by the phase acquisition processing unit; a phase shift processing unit (31e) that executes a phase shift process to shift the phase of the toggle pattern from the initial value by the amount of the initial phase difference so that the phase difference between the frequency-divided clock or the external clock selected by the clock selection unit and the toggle pattern falls within a predetermined range; the phase synchronization control unit repeatedly executes the phase acquisition process, the phase difference calculation process, and the phase shift process while the division ratio setting unit gradually decreases the division ratio; the clock selection unit selects the external clock instead of the divided clock after the phase shift process is executed when the frequency division ratio is equal to or less than a predetermined value; a minimum value of the division ratio set by the division ratio setting unit in the coarse adjustment mode being equal to or greater than a maximum value of the division ratio set by the division ratio setting unit in the fine adjustment mode.

2. Each of the coarse adjustment units is a plurality of coarse adjustment FIFOs (113) for varying a difference between a write address to which L bits of the parallel data are sequentially written and a read address from which the written L bits of the parallel data are sequentially read in response to a coarse adjustment control signal output from the phase synchronization control unit; a plurality of delay output units (114) that delay the L-bit parallel data read from each of the coarse adjustment FIFOs by the N-bit unit in response to the coarse adjustment control signal and output the delayed data to the plurality of transceivers, 2. The signal generating device according to claim 1, wherein the phase synchronization control section changes the phase of the toggle pattern by changing the value of the coarse adjustment control signal in the coarse adjustment mode.

3. The four transceivers constitute one transceiver unit (12), each of the coarse adjustment units is provided corresponding to each of the transceiver units, 3. The signal generating device according to claim 1, wherein the four transceivers in the transceiver unit convert the N bits of the parallel data coarsely adjusted by each of the coarse adjustment units into 1 bit of the serial data at the timing of a common clock signal.

4. 3. The signal generating device according to claim 1, wherein the clock selection unit selects the external clock instead of the divided clock after the phase shift process is performed when the division ratio is 4 or less.

5. a parallel data output unit (11) that outputs parallel data of multiple bits; a plurality of coarse adjustment units (111) for coarsely adjusting the phase of the parallel data output from the parallel data output unit; a plurality of transceivers (20) for converting N bits of the parallel data roughly adjusted by each of the coarse adjustment units into 1-bit serial data; a divided clock output unit (14) that outputs a divided clock obtained by dividing the frequency of an external clock; a clock selection unit (17) that selects either the divided clock or the external clock; a phase detection unit (40) that outputs a detection voltage corresponding to the phase difference between the divided clock or the external clock selected by the clock selection unit and the serial data, a signal generation method in which the phase of the serial data output from each of the transceivers is indirectly controlled by coarsely adjusting the phase of the parallel data output from the parallel data output unit by the plurality of coarse adjustment units in a coarse adjustment mode, and the phase of the serial data output from each of the transceivers is directly controlled in a fine adjustment mode, a division ratio setting step (S23, S27, S35) of setting the division ratio of the divided clock to the divided clock output unit; a rate control step (S41, S44, S47) of controlling each of the transceivers to output, as the serial data, a toggle pattern having a frequency that is half the frequency of the divided clock or the external clock selected by the clock selection unit; a phase acquisition processing step (S42, S45, S48) of executing a phase acquisition process to acquire the detected voltage output from the phase detection unit while changing the phase of the toggle pattern from an initial value; a phase difference calculation processing step (S43, S46, S49) of executing a phase difference calculation processing to calculate an initial phase difference between the divided clock or the external clock selected by the clock selection unit and the initial value of the phase of the toggle pattern based on the detection voltage acquired by the phase acquisition processing step; a phase shift processing step (S25, S33, S39) of executing a phase shift processing to shift the phase of the toggle pattern from the initial value by the initial phase difference so that the phase difference between the frequency-divided clock or the external clock selected by the clock selection unit and the toggle pattern falls within a predetermined range; a step of repeatedly executing the phase acquisition process, the phase difference calculation process, and the phase shift process while gradually decreasing the frequency division ratio in the frequency division ratio setting step (S25 to S28, S33 to S36); an external clock selection step (S37) of selecting the external clock instead of the frequency-divided clock by the clock selection unit after the phase shift process is executed when the frequency division ratio is equal to or less than a predetermined value, a minimum value of the division ratio set by the division ratio setting step in the coarse adjustment mode being equal to or greater than a maximum value of the division ratio set by the division ratio setting step in the fine adjustment mode.

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