Mounting device and positioning method

Abstract

To provide a mounting device and a positioning method capable of arranging a chip part while suppressing an occurrence of misalignment at a predetermined position of a substrate when the chip part is mounted on the substrate using a stamp that holds a plurality of chip parts.SOLUTION: The present invention provides a mounting device including: a substrate stage for holding a substrate; a stamp for holding a plurality of chip components; a stamp base for holding the stamp; and imaging means for observing the stamp base and the substrate from the same direction. The stamp and the stamp base have transparency, and the imaging means is capable of simultaneously acquiring position information on at least one of the stamp and the stamp base and position information on the substrate. The present invention provides a positioning method using the device.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a mounting apparatus and alignment method for mounting chip components on a substrate, and more particularly to a mounting apparatus and alignment method using a stamp that holds a plurality of chip components. [Background technology]

[0002] There are applications where many chip components are mounted on a substrate, such as a micro LED display where many micro LEDs are mounted on a TFT substrate. In such applications, it is necessary to align and mount the chip components on each of the many mounting positions PC on substrate B shown in Figure 9.

[0003] For example, in a micro LED display, at least hundreds of thousands of LED chips need to be mounted on a single TFT substrate, and mounting the LED chips one by one would take an enormous amount of time. Therefore, efforts are being made to improve productivity by using a so-called stamp method (e.g., Patent Document 1), which allows multiple chip components C to be mounted at once in accordance with the pitch of the mounting locations PC on the substrate B.

[0004] FIG. 10 illustrates a stamp used when mounting multiple chip components C on a substrate B at one time, with FIG. 10(a) being a side view and FIG. 10(b) being a view from the side holding the chip components C. In FIG. 10, the stamp 6 has protrusions 61 arranged on a stamp body 60. The protrusions 61 hold the chip components C and are arranged to match the pitch of the mounting positions PC. The stamp 6 is held by a stamp base 5 from the side opposite the protrusions 61. The first stamp recognition mark 6A1 and the second stamp recognition mark 6A2 are provided at fixed positions relative to the arrangement of the protrusions 61. Position information about the stamp 6 can be obtained from the positions of the first stamp recognition mark 6A1 and the second stamp recognition mark 6A2, and the arrangement of the protrusions 61 arranged on the stamp 6 can also be determined.

[0005] FIG. 11 shows the state in which chip components C are mounted on a portion of substrate B using stamp 6 shown in FIG. 10, and multiple chip components C held by stamp 6 are mounted on substrate B at one time. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2023-145354 Summary of the Invention [Problem to be solved by the invention]

[0007] In order to mount a plurality of chip components C on the mounting points PC of the substrate B using the stamp 6, Each of the plurality of chip components C held by the stamp 6 must be aligned with the mounting position PC on the substrate B before being mounted.

[0008] For this reason, alignment is performed using stamp recognition marks 6A (first stamp recognition mark 6A1 and second stamp recognition mark 6A2), which serve as a guide for determining the position information of the stamp and the arrangement of the chip components C held on the stamp, and board recognition marks BA, which serve as a guide for the arrangement of the mounting locations PC within the board B. FIG. 12(a) shows a state in which the stamp recognition marks 6A and board recognition marks BA are observed using a dual-viewpoint camera 70 with an upper and lower field of view. The amount of positional misalignment is calculated from the relative positions of the stamp 6 and board 2 obtained here, and the position of at least one of the board B and stamp 6 is adjusted to correct the amount of positional misalignment. FIG. 12(b) shows a state in which the stamp 6 is lowered to bring the chip components C into close contact with the board B.

[0009] After this, the chip component C is heated to bond the electrodes of the chip component C to the electrodes of the substrate B, thereby bonding the chip component C to the substrate B. Recently, a method using a laser to heat the chip component C has been gaining attention, and an example of this is shown in Figure 13. Figure 13 shows a method of heating individual chip components C with laser light L. Due to the high energy density of the laser light, the chip components C can be heated instantaneously. Therefore, even when heating each chip component C sequentially, as shown in Figures 13(a) to 13(c), the time required to heat all of the chip components C held by the stamp 6 is short. In order to heat the chip components C with laser light L, the method shown in Figure 13 requires the stamp base 5 and stamp 6 to transmit light linearly. In other words, the stamp base 5 and stamp 6 are transparent.

[0010] After all of the chip components C held by the stamp 6 are heated and mounted on the substrate B, the stamp 6 is raised as shown in Fig. 14(b). After this, the stamp 6 holding the chip components C is placed over a predetermined area where the next chip component C will be mounted as shown in Fig. 14(b), and the stamp 6 and substrate B are aligned before mounting.

[0011] 12(a) and 14(b), conventionally, a two-view imaging means 70, known as a two-view camera, has been used to obtain position information of the stamp recognition mark 6A and the board recognition mark BA. Here, the two-view imaging means 70 has an upper camera that images the stamp 6 and a lower camera that images the board B, so the two-view imaging means 70 needs to be placed between the stamp 6 and the board B. In other words, a space large enough to place the two-view imaging means 70 is required between the stamp 6 and the board B.

[0012] However, if there is a slight tilt in the axis of the lifting means used to raise and lower the stamp 6, even if there is no positional misalignment when observed with the two-view imaging means, this is undesirable as it will cause a positional misalignment when the chip component C is brought into close contact with the substrate B.

[0013] The present invention has been made in consideration of the above-mentioned problems, and provides a mounting device and alignment method that can position chip components on a substrate while minimizing misalignment when mounting chip components on the substrate using a stamp that holds multiple chip components. [Means for solving the problem]

[0014] In order to solve the above problem, the invention described in claim 1 is as follows: A mounting device that mounts multiple chip components at predetermined positions on a substrate at once, a substrate stage for holding the substrate; and a stamp for holding the plurality of chip components; a stamp base for holding the stamp; and an imaging means for observing the stamp base and the substrate from the same direction; The stamp and the stamp base are transparent, and the imaging means is capable of simultaneously acquiring positional information of at least one of the stamp and the stamp base and positional information of the substrate.

[0015] The invention described in claim 2 is the mounting device described in claim 1, The mounting apparatus further comprises a chip surface imaging means for observing the stamp direction from the substrate stage side.

[0016] The invention described in claim 3 is a method for arranging a plurality of chip components held on a stamp at predetermined positions on a substrate, comprising: This is an alignment method including: a position information collecting step of acquiring position information of the substrate and position information of the stamp from images captured from the same direction; a relative position calculating step of calculating the relative position of the stamp and the substrate based on the result obtained in the position information collecting step; a correction amount calculating step of calculating a correction amount if the result obtained in the relative position calculating step is outside an allowable range; and an adjustment step of adjusting the position of at least one of the stamp and the substrate based on the correction amount.

[0017] The invention described in claim 4 is the alignment method described in claim 3, In the position information collecting step, when acquiring the position information of the stamp, the positioning method involves capturing an image of a stamp recognition mark provided on the stamp.

[0018] The invention described in claim 5 is the alignment method described in claim 4, This is an alignment method in which, prior to the position information collection step, a chip information collection step is performed to obtain the positional relationship between the arrangement of chip components held by the stamp and the stamp recognition mark using an image captured from the side holding the chip components.

[0019] The invention described in claim 6 is a method for arranging a plurality of chip components held on a stamp at predetermined positions on a substrate, comprising: a position information collecting step of acquiring position information of the substrate and position information of a stamp base holding the stamp from images captured from the same direction; a relative position calculating step of calculating a relative position between the stamp base and the substrate based on the results obtained in the position information collecting step; and a correction amount calculating step of calculating a correction amount if the results obtained in the relative position calculating step are outside an allowable range. The alignment method includes an adjustment step of adjusting the position of at least one of the stamp base and the substrate based on the correction amount.

[0020] The invention described in claim 7 is the alignment method described in claim 6, In the position information collecting step, when acquiring the position information of the stamp base, an image of a stamp base recognition mark provided on the stamp base is captured.

[0021] The invention described in claim 8 is the alignment method described in claim 7, This is an alignment method in which, prior to the position information collection step, a chip information collection step is performed to obtain the positional relationship between the arrangement of chip components held by the stamp and the stamp base recognition mark using an image captured from the side holding the chip components.

[0022] The invention described in claim 9 is the alignment method described in any one of claims 3 to 8, In the position information collecting step, when acquiring the position information of the substrate, an image of a substrate recognition mark provided on the substrate is captured.

[0023] The invention described in claim 10 is the alignment method described in claim 9, This is an alignment method in which the substrate recognition mark is imaged through the stamp base.

[0024] The invention described in claim 11 is the alignment method described in any one of claims 3 to 8, In the position information collecting step, when acquiring the position information of the board, an image of a chip component already mounted on the board is taken.

[0025] The invention described in claim 12 is The alignment method according to claim 11, This is an alignment method in which the chip component is imaged through the stamp base. [Effects of the Invention]

[0026] According to the present invention, when chip components are mounted on a substrate using a stamp that holds a plurality of chip components, it is possible to position the chip components in predetermined positions on the substrate while suppressing misalignment. [Brief explanation of the drawings]

[0027] [Figure 1] 1 is a schematic diagram of a mounting apparatus according to an embodiment of the present invention. [Figure 2]This explains the alignment method of embodiment 1 of the present invention, and shows (a) a state in which position information of the stamp and the substrate is being acquired, and (b) a state in which the positional relationship between the stamp recognition mark used to acquire the position information of the stamp and the arrangement of the chip components held by the stamp is being acquired. [Figure 3] FIG. 10 is a diagram showing a state in which position information of a board is acquired using a chip component already mounted on the board in alignment according to the first embodiment of the present invention. [Figure 4] This figure explains an example of using stamp-corresponding substrate recognition marks arranged according to stamps for alignment in embodiment 1 of the present invention, and shows (a) the arrangement of stamp-corresponding substrate recognition marks arranged on a substrate, and (b) the state in which position information of the substrate is obtained using the stamp-corresponding substrate recognition marks. [Figure 5] This figure explains a case where it is difficult to simultaneously capture images of both the stamp recognition mark and the stamp-compatible substrate recognition mark in an example where a stamp-compatible substrate recognition mark is used for alignment in embodiment 1 of the present invention, and shows (a) a state in which position information of the stamp recognition mark is being acquired, and (b) a state in which position information of the stamp-compatible substrate recognition mark is being acquired. [Figure 6] 10A and 10B are diagrams illustrating the arrangement of stamp base recognition marks used in the alignment method according to the second embodiment of the present invention, in which (a) is a side view and (b) is a view from the surface that holds the chip component. [Figure 7] Regarding the alignment of embodiment 2 of the present invention, (a) shows the state in which the positional relationship between the stamp base recognition mark used to acquire position information of the stamp base and the arrangement of chip components held by the stamp is being acquired, and (b) shows the state in which relative position information of the stamp recognition mark and the substrate is being acquired. [Figure 8]In an example in which a stamp-compatible substrate recognition mark is used for alignment in embodiment 2 of the present invention, (a) shows a state in which the stamp-compatible substrate recognition mark and the stamp-based recognition mark are imaged simultaneously, and (b) shows a state in which position information of only the stamp-compatible substrate recognition mark is obtained when it is difficult to image both the stamp-based recognition mark and the stamp-compatible substrate recognition mark simultaneously. [Figure 9] 1A and 1B are diagrams showing an example of a substrate on which a large number of chip components are mounted. [Figure 10] This explains a stamp that can mount multiple chip components at once and a stamp base that holds the stamp, where (a) is a side view and (b) is a view from the surface that holds the chip components. [Figure 11] FIG. 10 is a diagram showing an example in which a plurality of chip components are mounted on a substrate at one time using a stamp. [Figure 12] 1A and 1B are diagrams illustrating the process of mounting multiple chip components on a substrate using a stamp, in which (a) shows the state of alignment and (b) shows the state of the chip components being tightly attached to the substrate. [Figure 13] This explains the process of mounting multiple chip components on a substrate using a stamp, and shows (a) the state in which the chip components are heated and mounted with a laser, (b) the state in which different chip components are successively heated and mounted with a laser, and (c) the stage at which mounting of the chip components held by the stamp is completed. [Figure 14] This explains the process of mounting multiple chip components on a substrate using a stamp, and shows (a) the stamp with multiple chip components mounted on it being raised at once, and (b) the stamp holding the multiple chip components being aligned in an area of ​​the substrate where no chip components are mounted. DETAILED DESCRIPTION OF THE INVENTION

[0028] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following describes embodiments of the present invention with reference to the accompanying drawings. Fig. 1 shows a mounting apparatus 1 used in the first and second embodiments of the present invention.

[0029] The mounting device 1 in Figure 1 uses a stamp 6 to mount multiple chip components C on a substrate B at once, and is equipped with a substrate stage 2, a lifting means 3, a head unit 4, a stamp base 5, the stamp 6, and an imaging means 7.

[0030] Here, the substrate stage 2 holds the substrate B on a flat surface by suction or the like, and may have a function to move the substrate B in the in-plane direction (XY direction).

[0031] The lifting means 3 is fixed to a frame (not shown), has a drive shaft connected to the head unit 4, and has the function of moving the head 4 up and down and the function of applying a predetermined pressure to the head 4. It may also have the function of adjusting the rotation angle of the head 4, with the drive shaft movement direction (Z direction) as the rotation axis.

[0032] The head 4 has a stamp base 5 fixed to the bottom, and is moved up and down (and the rotation angle around the vertical axis) by the lifting means 3, and has a cavity through which the imaging means 7 can enter and exit.

[0033] The stamp base 5 is a transparent plate-like object that forms the underside of the head 4, and has the function of holding the stamp 6 on its underside. Here, it is preferable to make the stamp 6 replaceable, as the stamp 6 is held by suction or the like, but care must be taken when attempting to heat the chip component C with a laser, because the laser light will be scattered if there is a reduced pressure flow path in the optical path of the laser light leading to the part that holds the chip component C (the protrusion 61 in Figure 10(a)).

[0034] As shown in Fig. 10, the stamp 6 has protrusions 61 provided at locations on the stamp body 60, which is a transparent plate-like object, where the chip component C is to be held, and the side opposite to the side with the protrusions 61 is held by the chip base 5. The protrusions 61 are provided at a pitch that matches the chip mounting locations PC of the board on which the chip component C is to be mounted. The surface of the protrusions 61 that comes into close contact with the chip component C may be adhesive, and the protrusions 61 themselves may be made of an adhesive material. Alternatively, there may be no protrusions 61, and the flat surface of the stamp body 60 may directly hold the chip component C.

[0035] The imaging means 7 has a field of view from above the stamp base 5 toward the substrate, and is configured so as to be able to move in and out of the cavity of the head part 4 by a driving means (not shown).

[0036] The mounting apparatus 1 in Fig. 1 mainly shows the components related to alignment, but also includes a heating means for heating the chip components C. In the embodiment of the present invention, it is assumed that the chip components C will be heated with laser light, and is provided with a laser irradiation means 9 (not shown), which is composed of a laser light source and a scanning mechanism. Note that the laser irradiation by the laser irradiation means 9 may be a method in which the laser light L is scanned to sequentially heat the chip components C, as shown in Fig. 13, but the takt time can be shortened by configuring the laser light emitted from a high-output laser light source to branch and heat multiple chip components C simultaneously.

[0037] The mounting apparatus 1 also includes a control unit 10 (not shown), which is connected to the substrate stage 2, the lifting means 3, the imaging means 7, and the laser irradiation means 9 (not shown).

[0038] The control unit 10 is connected to the substrate stage 2 and has the function of controlling whether or not the substrate B is adsorbed and the position of the substrate within the XY plane.

[0039] The control unit 10 is connected to the lifting means 3 and has the function of controlling the lifting and pressure of the head unit 4, as well as the rotation angle around the lifting direction (Z direction) as the rotation axis.

[0040] The control unit 10 is connected to the imaging means 7 (and a driving means for moving the imaging means 7), and has the function of controlling the position of the imaging means 7, and capturing and processing images acquired by the imaging means 7.

[0041] The control unit 10 is connected to the laser irradiation means 9 (not shown) and has the function of controlling the output and irradiation position of the laser light.

[0042] A method for aligning the substrate B and the stamp 6 using the mounting device 1 of FIG. 1 will be described below.

[0043] First, Fig. 2(a) is a diagram illustrating the alignment method according to embodiment 1. In Fig. 2(a), the imaging means 7 is placed on the stamp base 5 and faces the substrate B. Here, since this embodiment is premised on heating the chip component C with laser light, the stamp base 5 and stamp 6 are transparent, and it is possible to image the stamp recognition mark 6A from the same direction as the substrate recognition mark BA on the substrate B, and obtain the position information of the stamp 6 and the substrate B (position information collection step). Therefore, the relative position of the stamp 6 with respect to the board B can be calculated, and the positional relationship between the arrangement of the chip components C held on the stamp 6 and the arrangement of the mounting positions PC on the board B is also calculated (relative position calculation step), and if the result is within the allowable range, no position correction is required. On the other hand, if it is outside the allowable range, the amount of correction to correct the positional deviation is calculated (correction amount calculation step).

[0044] Therefore, once the correction amount is calculated, the position of at least one of the stamp 6 and the substrate B is adjusted (adjustment step) according to the correction amount to perform alignment. Here, in the configuration of the mounting device 1 shown in Fig. 1, the stamp 6 undergoes angle adjustment (with the Z direction as the axis of rotation) using the lifting means 3, and the substrate B undergoes position adjustment within the XY plane using the substrate stage 2. However, the configuration of the mounting device 1 is one of the embodiments, and the substrate stage 2 may have a function for adjusting the angle, or the head unit 4 may have a function for adjusting the position of the stamp base 5 in the XY directions.

[0045] As shown in Fig. 2(a), the stamp recognition mark 6A (related to the positional information of the stamp 6) and the board recognition mark BA (related to the positional information of the board B) can be observed from the same direction, so alignment can be performed with the stamp 6 close to the board B within a range where the chip component C does not come into contact with the board B. Therefore, the descending distance from alignment to bringing the chip component C into close contact with the board B can be made extremely short compared to the case where the two-view imaging means 70 shown in Fig. 12(a) is used. In other words, it is possible to suppress positional deviation of the chip component C with respect to the mounting location on the board after alignment, and it becomes possible to place the chip component C at the predetermined position on the board B while suppressing deviation.

[0046] Incidentally, when the stamp 6 picks up the chip components C in the previous process, the arrangement of the protrusions 61 must be aligned with the arrangement of the chip components C to be picked up, but the chip components C may be picked up with a positional deviation. In such a case, even if the relative position calculation step and subsequent steps are performed using the positional relationship between the stamp recognition mark 6A and the protrusions 61, the amount of positional deviation at the time of picking up remains.

[0047] Therefore, the chip information collecting step shown in Fig. 2(b) is performed to mount the chip component C at a predetermined position on the substrate B even when the chip component C is held in a misaligned state with respect to the protrusion 61. The chip information collecting step is performed prior to the position information collecting step, and uses the chip surface imaging means 8 shown in Fig. 2(b) to obtain the positional relationship of the stamp recognition marks 6A with respect to the arrangement of the chip components C from the side of the stamp 6 that holds the chip components C, and this positional relationship can be used in the relative position calculating step. The chip surface imaging means 8 is also connected to the control unit 10, and the control unit 10 has the function of importing and processing the images obtained by the chip surface imaging means 8.

[0048] In the example shown in Figure 2(a), the position information of board B is obtained using board recognition marks BA, but in many cases there is only one set of board recognition marks BA per board B. For this reason, there is a concern that the positional accuracy of the board may decrease when aligning a large board B using only the board recognition marks BA as a reference. For this reason, it is also possible to use mounted chip components C as a reference for obtaining position information of board B. Figure 3 shows the state in which board position information is obtained using mounted chip components C, and the position information collection step is performed using chip components C at the corners, etc., of the chip component array that has already been mounted using stamp 6, and stamp recognition marks 6A.

[0049] Note that in the method of using chip components C at corners of the chip component array, if there is any misalignment in the mounted chip components C, there is a concern that the amount of misalignment will accumulate with each mounting, so care must be taken. Also, in mounting using the stamp 6, chip components C may be missing from the specified position on the board, and it is necessary to incorporate measures to deal with the case where chip components C are missing from a specific location (for example, a corner of the array).

[0050] For the reasons described above, in order to mount chip components C on a large substrate B with high precision, it is preferable to provide stamp-corresponding board recognition marks BPA on the substrate B in accordance with the stamp 6 (the arrangement of chip components C held by the stamp 6). FIG. 4(a) shows the stamp-corresponding board recognition marks BPA provided on the substrate B, and FIG. 4(b) shows the imaging means 7 imaging the stamp-corresponding board recognition marks BPA to obtain substrate position information. Specifically, the relative positional relationship between the substrate B and the stamp 6 is determined from positional information between the stamp recognition first mark 6A1 and the stamp-corresponding board recognition mark BPAm (n and m are natural numbers) and between the stamp recognition mark 6A2 and the stamp-corresponding board recognition mark BPAn+1m+1. Note that even when the stamp-corresponding board recognition marks BPA are used, the chip position information step as shown in FIG. 2(b) may also be performed.

[0051] When the stamp-corresponding recognition mark BPA is used, as shown in FIG. 4(b), the stamp recognition mark 6A (of the stamp 6) and the stamp-corresponding substrate recognition mark BPA are imaged for each alignment. Depending on the positional relationship between the stamp-corresponding substrate recognition mark BPA and the stamp 6 (for example, when the outer periphery of the stamp 6 is positioned directly above the stamp-corresponding substrate recognition mark BPA), the stamp recognition mark 6A and the stamp-corresponding substrate recognition mark BPA may not be imaged simultaneously. Taking such a situation into consideration, the observation may be divided into two observations, one for the stamp recognition mark 6A only and the other for the stamp-corresponding substrate recognition mark BPA only, as shown in FIG. 5(a). When observing only the stamp-corresponding substrate recognition mark BPA, the relative position of the substrate B (and the imaging means 7) and the stamp 6 is changed by a predetermined amount, and then returned to its original position after observing only the stamp-corresponding substrate recognition mark BPA.

[0052] In the explanation up to this point, it has been assumed that the stamp recognition mark 6A is provided on the stamp 6, but the guide for arranging the chip components C held on the stamp 6 may be provided on the stamp base 5 instead of the stamp 6.

[0053] 6 shows a stamp base 5 according to a second embodiment of the present invention, in which the stamp base 5 holds a stamp 6 (holding a chip component C), with FIG. 6(a) being a side view and FIG. 6(b) being a view seen from the surface holding the chip component C. The stamp base 5 of the second embodiment shown in FIG. 6 is provided with stamp base recognition marks 5A (stamp base first recognition mark 5A1, stamp base second recognition mark 5A2). The alignment method of embodiment 2 uses a stamp base recognition mark 5A instead of the stamp recognition mark 6A of embodiment 1, and the arrangement status of the chip components C held by the stamp 6 can be determined from the position information of the stamp base recognition mark 5A.

[0054] However, since the stamp recognition mark 6A is arranged at a fixed position relative to the arrangement of the protrusions 61, it is possible to know the arrangement of the protrusions 61 only from the position information of the stamp recognition mark 6A, but it is not possible to know the arrangement of the protrusions 61 accurately only from the stamp base recognition mark 5A provided on the stamp base 5 to which the stamp 6 can be detached. For this reason, when performing alignment using the stamp base recognition mark 5A, it is necessary to grasp the positional relationship of the stamp base recognition mark 5A relative to the arrangement of the chip components C as a chip information collection step using chip surface imaging means 8, as shown in Figure 7(a).

[0055] When the stamp-based recognition mark 5A is used, as in the case of using the stamp recognition mark 6A in embodiment 1, the position information of the substrate B can be obtained using the substrate recognition mark BA shown in Figure 7(a), the mounted chip component C shown in Figure 8(a), or the stamp-compatible substrate recognition mark BPA shown in Figure 8(b).

[0056] In other words, by replacing the stamp recognition mark 6A in embodiment 1 with the stamp base recognition mark 5A, alignment can be performed through a position information collection step, a relative position calculation step, a correction amount calculation step, and an adjustment step, assuming that a chip information collection step is performed.

[0057] 7(b), 8(a), and 8(b), the stamp base recognition mark 5A and the mark related to the position information of the substrate B can be observed from the same direction, so alignment can be performed with the stamp 6 close to the substrate B within a range where the chip component C does not come into contact with the substrate B. This makes it possible to extremely shorten the distance that the stamp 6 descends from alignment to the time when the chip component C is tightly attached to the substrate B. In other words, it is possible to suppress misalignment of the chip component C with respect to the mounting location on the substrate that occurs after alignment. [Explanation of symbols]

[0058] 1 Mounting equipment 2. Substrate stage 3 Lifting means 4 Head 5 Stamp Base 6 Stamps 7. Imaging means (camera) 8. Chip surface imaging means 9 Laser irradiation means 10 Control Unit 60 Stamp body 61 Protrusion 70 2-view imaging means (2-view camera) 5A (5A1, 5A2) stamp-based recognition mark 6A (6A1, 6A2) stamp recognition mark B board BA (BA1, BA2) board recognition mark BPA stamp compatible PCB identification mark C Chip parts L laser light PC chip component mounting location

Claims

1. A mounting device that mounts multiple chip components at predetermined positions on a substrate at once, a substrate stage for holding the substrate; a stamp for holding the plurality of chip components; a stamp base for holding the stamp; an imaging means for observing the stamp base and the substrate from the same direction; the stamp and the stamp base are transparent; A mounting apparatus in which the imaging means is capable of simultaneously acquiring position information of at least one of the stamp and the stamp base, and position information of the substrate.

2. The mounting device according to claim 1, The mounting apparatus further comprises a chip surface imaging means for observing the stamp direction from the substrate stage side.

3. 1. A method for aligning a plurality of chip components held on a stamp at predetermined positions on a substrate, comprising: a position information collecting step of acquiring position information of the substrate and position information of the stamp from images captured from the same direction; a relative position calculation step of calculating a relative position between the stamp and the substrate based on the results obtained in the position information collection step; a correction amount calculation step of calculating a correction amount if the result obtained in the relative position calculation step is outside an allowable range; an alignment method including an adjusting step of adjusting the position of at least one of the stamp and the substrate based on the amount of correction;

4. The alignment method according to claim 3, The positioning method includes capturing an image of a stamp recognition mark provided on the stamp when acquiring the position information of the stamp in the position information collecting step.

5. The alignment method according to claim 4, An alignment method in which, prior to the position information collection step, a chip information collection step is performed to obtain the positional relationship between the arrangement of chip components held by the stamp and the stamp recognition mark using an image captured from the side holding the chip components.

6. 1. A method for aligning a plurality of chip components held on a stamp at predetermined positions on a substrate, comprising: a position information collecting step of acquiring position information of the substrate and position information of the stamp base holding the stamp from images captured from the same direction; a relative position calculation step of calculating a relative position between the stamp base and the substrate based on the results obtained in the position information collection step; a correction amount calculation step of calculating a correction amount if the result obtained in the relative position calculation step is outside an allowable range; an alignment method including an adjusting step of adjusting the position of at least one of the stamp base and the substrate based on the correction amount;

7. The alignment method according to claim 6, In the position information collecting step, when acquiring the position information of the stamp base, an image of a stamp base recognition mark provided on the stamp base is captured.

8. The alignment method according to claim 7, An alignment method in which, prior to the position information collection step, a chip information collection step is performed to obtain the positional relationship between the arrangement of chip components held by the stamp and the stamp base recognition mark using an image captured from the side holding the chip components.

9. The alignment method according to any one of claims 3 to 8, The positioning method includes capturing an image of a board recognition mark provided on the board when acquiring the position information of the board in the position information collecting step.

10. The alignment method according to claim 9, An alignment method in which the substrate recognition mark is imaged through the stamp base.

11. The alignment method according to any one of claims 3 to 8, The positioning method includes capturing an image of a chip component already mounted on the substrate when acquiring the position information of the substrate in the position information collecting step.

12. The alignment method according to claim 11, An alignment method in which the chip component is imaged through the stamp base.

Images