Test circuit

Abstract

To provide a test circuit capable of suppressing an increase in circuit scale as compared with a case where a new circuit is separately provided for testing an ECC circuit.SOLUTION: The test circuit includes: a generation unit configured to generate a selection signal on the basis of a test signal for enabling any one of a plurality of tests including at least a bit-shift test and an ECC test, and a command signal defining operations of a memory core; a selection unit configured to select one of a first test pattern and a second test pattern as test data according to the selection signal and output the selected test data; and a comparison unit configured to compare read data read from the memory core with the test data when the bit-shift test is enabled, and to compare correction data, which is data obtained by error correction of the read data by an ECC circuit, with the test data when the ECC test is enabled.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The disclosed technology relates to a test circuit. [Background technology]

[0002] Patent document 1 states, "According to this embodiment, a semiconductor integrated circuit is provided that can perform both SRAM core testing and ECC circuit testing separately in an SRAM macro that incorporates an SRAM core and an ECC circuit with a simple configuration."

[0003] Patent Document 2 states that "a semiconductor device is provided that can determine whether an error can be corrected by an ECC circuit using a BIST circuit."

[0004] Patent Document 3 states that "We provide a test circuit and a test method that enable testing of ECC circuits and inspects ECC functions with a small additional circuit scale even when data length is long." [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2019-168316 [Patent Document 2] Japanese Patent Application Publication No. 2018-156712 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-176828 Summary of the Invention [Problem to be solved by the invention]

[0006] In recent years, as LCD TVs and LCD monitors have become larger and higher resolution, the buffer memory used for image processing has also become larger in capacity. Testing large-capacity devices such as DDR SDRAM takes longer, resulting in increased costs. Therefore, it is desirable to minimize the scale of test circuits in order to reduce chip costs.

[0007] Therefore, an object of the present disclosure is to provide a test circuit that can suppress an increase in circuit size compared to when a new circuit is provided separately for testing an ECC circuit. [Means for solving the problem]

[0008] The test circuit of the present disclosure includes: a generation unit that generates a selection signal based on a test signal that enables one of a plurality of tests, including at least a bit shift test that tests input / output paths of a plurality of bits in a memory core by inverting each bit one by one, and an ECC test that tests an ECC circuit that detects and corrects bit errors that occur in the memory core, and a command signal that defines the operation of the memory core; a selection unit that selects, in accordance with the selection signal, either a first test pattern in which the plurality of bits are set to a predetermined logic level or a second test pattern in which a specific bit of the plurality of bits is set to a logic level different from the predetermined logic level, and outputs the selected test data; and a comparison unit that, when the bit shift test is enabled, compares the test data with read data read from the memory core, and, when the ECC test is enabled, compares the test data with corrected data obtained by error correction of the read data by the ECC circuit. [Effects of the Invention]

[0009] The present disclosure provides an advantageous effect of providing a test circuit that can suppress an increase in circuit size compared to when a new circuit is provided separately for testing an ECC circuit. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing an example of a system configuration of a memory system 10′ according to a conventional example. [Figure 2] FIG. 1 is a diagram showing an example of a circuit configuration of a BIST circuit 100′ according to a conventional example, together with a test target. [Figure 3] 1 is a diagram illustrating an example of a system configuration of a memory system 10 according to the present embodiment. [Figure 4] 1 is a diagram illustrating an example of a functional configuration of a BIST circuit 100 according to the present embodiment. [Figure 5] 1 is a diagram showing an example of a circuit configuration of a BIST circuit 100 according to the present embodiment together with a test target. DETAILED DESCRIPTION OF THE INVENTION

[0011] An example of an embodiment of the technology of the present disclosure will be described below with reference to the drawings. Note that the same reference numerals are used to designate identical or equivalent components and parts in each drawing. Furthermore, the dimensional proportions of the drawings may be exaggerated for the sake of explanation and may differ from the actual proportions.

[0012] 1 is a diagram showing an example of the system configuration of a memory system 10' according to a conventional example. This diagram shows the configuration of a DDR SDRAM (Double-Data-Rate Synchronous Dynamic Random Access Memory) as an example. The conventional memory system 10' includes a memory core 20, a serial-parallel conversion circuit 30, a command controller 40, an RW controller 50, and a BIST (Built In Self Test) circuit 100'.

[0013] In this memory system 10', we will first explain the normal mode, i.e., non-test mode, in which an LSI (not shown) accesses the memory core 20. In the normal mode, during a write operation, the serial-parallel conversion circuit 30 converts data supplied from the LSI terminal EXTDQ, which is a data input / output terminal, from serial to parallel. This figure shows an example in which the serial-parallel conversion circuit 30 converts data from 16 bits to 128 bits. Data is then written from the serial-parallel conversion circuit 30 to the memory core 20 via the data bus MDB.

[0014] In addition, in a read operation, the serial-parallel conversion circuit 30 converts the data read from the memory core 20 via MDB from parallel to serial, and the data is then supplied from the serial-parallel conversion circuit 30 to EXTDQ.

[0015] Next, a test mode (referred to as "BIST mode") in which the BIST circuit 100' tests the test target will be described. In the BIST mode, the serial-parallel conversion circuit 30 is not used. In the BIST mode, in a write operation, data is written from the BIST circuit 100' to the memory core 20 via the MDB.

[0016] In addition, in a read operation, data is read from the memory core 20 to the BIST circuit 100' via the MDB. Then, the BIST circuit 100' verifies the read data and outputs the result to a terminal of the LSI.

[0017] WRITE and WRITE_BIST shown in this diagram are write command signals that define the write operation to the memory core 20. WRITE and WRITE_BIST define READ, i.e., a read operation from the memory core 20, when they are "0", and WRITE, i.e., a write operation to the memory core 20, when they are "1". In the BIST mode, the address, READ / WRITE, etc. are controlled from the BIST circuit 100', but for simplicity, only the write command signal is shown in this diagram.

[0018] 2 is a diagram showing an example of the circuit configuration of a conventional BIST circuit 100' together with the test target. In the conventional BIST circuit 100', the test target is only a memory core 20. This diagram shows the circuit configuration of the BIST circuit 100' when the test target memory core 20 is tested in two test modes: a simultaneous test and a bit shift test.

[0019] The simultaneous test is a test mode in which multiple bits in the memory core 20 are tested simultaneously at a single test timing. In the simultaneous test, the BIST circuit 100′ selects a first test pattern in which multiple bits are set to a predetermined logic level (for example, all bits 0) as test data and writes it to the memory core 20 in a write operation.

[0020] Next, in a read operation, the BIST circuit 100' reads the data written in the memory core 20. Then, the BIST circuit 100' compares the read data read from the memory core 20 with the test data, i.e., the first test pattern. If the two match, the BIST circuit 100' outputs PASS as the test result, and if the two do not match, the BIST circuit 100' outputs FAIL as the test result.

[0021] That is, for example, when the first test pattern is set to all bits 0, the BIST circuit 100' outputs PASS if all bits of the read data are 0, and outputs FAIL otherwise.

[0022] In the bit shift test, physical shorts and interference between bits in paths related to the write / read bus MDB in the memory core 20 are detected by inverting only one bit of the bus. Then, this detection is repeatedly performed while shifting the inverted bit one bit at a time. In this way, the bit shift test is a test mode in which the input / output paths of multiple bits in the memory core 20 are tested while being inverted one bit at a time.

[0023] In the bit shift test, the BIST circuit 100' detects whether a specific bit among the multiple bits input from the address decoder 130 is at a logic level different from a predetermined logic level (for example, MDB<127:1> is all 0, MDB <0> 1) selects the second test pattern set in 1) as test data and writes it to the memory core 20.

[0024] Next, in a read operation, the BIST circuit 100' reads the data written in the memory core 20. Then, the BIST circuit 100' compares the read data read from the memory core 20 with the test data, i.e., the second test pattern. If the two match, the BIST circuit 100' outputs PASS as the test result, and if the two do not match, the BIST circuit 100' outputs FAIL as the test result.

[0025] For example, if the second test pattern is MDB <0> If only MDB<127:1> is set to 1 and MDB<127:1> is set to all 0, the BIST circuit 100' <0> If only 1 and MDB<127:1> are all 0, it outputs PASS. <0> Adjacent MDB <1> If the bit shift test is executed, the test is repeated by shifting a specific bit one bit at a time.

[0026] The BIST circuit 100′ may be configured to be able to test the memory core 20 to be tested in two test modes, such as the simultaneous test and the bit shift test. The BIST circuit 100′ includes a BIST controller 110, a multiplexer 120, an address decoder 130, a flip-flop 140, and a compare 150.

[0027] The BIST controller 110 outputs a test signal that enables one of multiple tests (two tests in this example). "BITSHIFTEN" shown in this figure is a first test signal that enables the bit shift test. Note that BITSHIFTEN is defined as "0" to disable the bit shift test and "1" to enable the bit shift test.

[0028] The multiplexer 120 selects either the first test pattern or the second test pattern in accordance with the selection signal and outputs it as test data. In the conventional BIST circuit 100', BITSHIFTEN itself may be the selection signal.

[0029] When BITSHIFTEN is 0, the multiplexer 120 selects BG_DATA, which is 1-bit data set to a predetermined logic level (for example, 0) in the BIST circuit 100′. On the other hand, when BITSHIFTEN is 1, the multiplexer 120 selects the address decoder 130.

[0030] Here, the BIST circuit 100' is provided with the same number of multiplexers 120 as the number of bits (128 in this figure). Therefore, when BITSHIFTEN is 0, the multiplexer 120 selects and outputs the first test pattern, in which all 128 bits are set to 0, as test data.

[0031] On the other hand, when BISTSHIFTEN is 1, the multiplexer 120 selects and outputs as test data a second test pattern in which only a specific bit of the 128 bits designated by the address decoder 130 is set to 1 and the other 127 bits are set to 0. That is, the multiplexer 120 selects and outputs as test data a second test pattern in which a specific bit is shifted by one bit in response to the increment operation of the memory address.

[0032] The flip-flops 140 hold the test data output by the multiplexer 120. Like the multiplexers 120, the flip-flops 140 are also provided in the BIST circuit 100′ in the same number as the number of bits. As a result, in a write operation, the test data held in the flip-flops 140 is written to the memory core 20. In addition, in a read operation, the test data held in the flip-flops 140 is supplied to the compare 150 as a comparison target.

[0033] In a read operation, the compare 150 compares the read data read from the memory core 20 with the test data supplied from the flip-flop 140, and outputs PASS if the two match, and outputs FAIL if the two do not match.

[0034] That is, when BITSHIFTEN is 0, the compare 150 determines whether the read data matches the first test pattern, and when BITSHIFTEN is 1, the compare 150 determines whether the read data matches the second test pattern.

[0035] Such a memory system 10' may be implemented with a function for detecting and correcting bit errors that occur in the memory core 20. Such a function is called ECC (Error Checking and Correction). The technology of the present disclosure is applicable to a system equipped with such an ECC function.

[0036] 3 is a diagram showing an example of the system configuration of a memory system 10 according to this embodiment. In this figure, the same or equivalent components and parts as those in FIG. 1 are denoted by the same reference numerals, and descriptions thereof will be omitted hereinafter except for differences.

[0037] The memory system 10 according to this embodiment further includes an ECC circuit 60 between the BIST circuit 100 and the memory core 20 in addition to the components of the memory system 10′ according to the conventional example. The ECC circuit is a circuit that detects and corrects bit errors that occur in the memory core 20.

[0038] In this memory system 10, first, a normal mode, i.e., a non-test mode, in which the LSI accesses the memory core 20 will be described. In the normal mode, during a write operation, the serial-to-parallel conversion circuit 30 converts data supplied from the LSI's data input / output terminal EXTDQ from serial to parallel. This diagram illustrates an example in which the serial-to-parallel conversion circuit 30 converts data from 16 bits to 128 bits. Next, the ECC circuit 60 adds a parity bit as an error detection code to the data transmitted from the serial-to-parallel conversion circuit 30 via MDB. This diagram illustrates an example in which the ECC circuit 60 adds an 8-bit parity bit to 128-bit data. Then, data is written from the ECC circuit 60 to the memory core 20 via the data bus DB.

[0039] Furthermore, in a read operation, the ECC circuit 60 detects and, if necessary, corrects errors in the data read from the memory core 20 via DB. Next, the serial-to-parallel conversion circuit 30 converts the data from the ECC circuit 60 via MDB from parallel to serial. The data is then supplied from the serial-to-parallel conversion circuit 30 to EXTDQ.

[0040] When such an ECC circuit 60 is added, the ECC circuit 60 becomes a test target in addition to the memory core 20. The test mode for testing the ECC circuit 60 is called an ECC test. "ECCTEST" shown in this figure is a second test signal that enables the ECC test. Note that ECCTEST is defined as disabling the ECC test when it is "0" and enabling the ECC test when it is "1."

[0041] In the ECC test, in a write operation, the BIST circuit 100 selects as test data a second test pattern in which a specific bit among a plurality of bits is set to a logic level different from a predetermined logic level, and writes the second test pattern to the memory core 20. That is, the BIST circuit 100 generates error data that is shifted by one bit in response to the increment operation of the memory address.

[0042] In the memory system 10 according to this embodiment, the number of bits of the MDB is 128 bits in normal mode, excluding the parity bit, but becomes 136 bits including the parity bit in BIST mode. In this case, the BIST circuit generates test data based on the logic that, for example, when all bits are 0, the parity bits are also all 0. Also, when all bits are 1, the parity bits are all 1.

[0043] Furthermore, in a read operation, the BIST circuit 100 selects as test data a first test pattern in which multiple bits are set to a predetermined logic level. The read data read from the memory core 20 via the DB undergoes error detection and error correction in the ECC circuit 60. If the ECC circuit 60 correctly corrects a bit error, a specific bit is corrected from a different logic level (e.g., 1) to a predetermined logic level (e.g., 0). Therefore, even if a second test pattern is written to the memory core 20, the corrected data from the ECC circuit 60 via the MDB should match the first test pattern. Therefore, the BIST circuit 100 compares the error-corrected data corrected by the ECC circuit 60 with the first test pattern. If the two match, the BIST circuit 100 outputs PASS as a test result, and if the two do not match, it outputs FAIL as a test result.

[0044] The test circuit according to this embodiment reduces the circuit size by sharing some circuits when performing a plurality of tests including at least such a bit shift test and an ECC test.

[0045] The background to this is that in recent years, as LCD TVs and LCD monitors have become larger and higher resolution, the buffer memory used for image processing has also become larger in capacity. The test time for large-capacity DDR SDRAMs and other devices has become longer, resulting in increased costs. Therefore, as one cost-effective measure, it is desirable to reduce pin counts in the test process by using parallel measurement to shorten test time. Therefore, it is desirable to incorporate the BIST circuit 100 into the memory LSI to reduce pin counts and to minimize the size of the test circuit to reduce chip costs.

[0046] FIG. 4 is a diagram illustrating an example of the functional configuration of a BIST circuit 100 according to this embodiment. This diagram focuses on only the functional configuration necessary for explaining the technology of the present disclosure. However, the BIST circuit 100 may further include other functional configurations not shown. Furthermore, this diagram illustrates functionally separated functional blocks, which may not necessarily correspond to the actual device configuration. Therefore, even if one block is shown in this diagram, it does not necessarily mean that it is configured by one device. Furthermore, even if different blocks are shown in this diagram, it does not necessarily mean that they are configured by separate devices.

[0047] The BIST circuit 100 is an example of a test circuit in the present disclosure and includes a generating section 210, a selecting section 220, a comparing section 230, and a switching section 240.

[0048] The generation unit 210 generates a selection signal based on a test signal that enables one of a plurality of tests including at least a bit shift test that tests a plurality of bits in the memory core 20 bit by bit, and an ECC test that tests an ECC circuit that detects and corrects bit errors that occur in the memory core 20, and a command signal that defines the operation of the memory core 20.

[0049] In accordance with the selection signal, the selection unit 220 selects either a first test pattern in which multiple bits are set to a predetermined logic level, or a second test pattern in which a specific bit among the multiple bits is set to a logic level different from the predetermined logic level, and outputs the selected test pattern as test data.

[0050] When the bit shift test is enabled, the comparison unit 230 compares the read data read from the memory core 20 with the test data, and when the ECC test is enabled, it compares the test data with the corrected data obtained by error correction of the read data by the ECC circuit 60. Then, when the comparison result shows that the two match, the comparison unit 230 outputs PASS as the test result, and when the two do not match, it outputs FAIL as the test result.

[0051] The switching unit 240 switches the connection with the memory core 20 so that the ECC circuit 60 can be bypassed.

[0052] 5 is a diagram showing an example of the circuit configuration of the BIST circuit 100 according to this embodiment together with the test target. In this figure, the same reference numerals are used for the same or equivalent components and parts as those in FIG. 2, and explanations thereof will be omitted hereinafter except for the differences.

[0053] The BIST circuit 100 according to this embodiment includes an AND circuit 160, an OR circuit 170, and a switch 180 in addition to the circuits included in the conventional BIST circuit 100'.

[0054] The logical product circuit 160 is a circuit that calculates the logical product of a second test signal that enables the ECC test and a write command signal that defines a write operation to the memory core 20. More specifically, the logical product circuit 160 may be a two-input AND circuit. WRITE may be input to one of the two inputs, and ECCTEST may be input to the other of the two inputs.

[0055] The OR circuit 170 is a circuit that calculates the logical sum of the output of the AND circuit 160 and a first test signal that enables the bit shift test. More specifically, the OR circuit 170 may be a two-input OR circuit. The output of the AND circuit 160 may be input to one of the two inputs, and BITSHIFTEN may be input to the other of the two inputs.

[0056] In the BIST circuit 100 according to this embodiment, the output of the OR circuit 170 may be supplied as a selection signal to the multiplexer 120. A logic circuit including the AND circuit 160 and the OR circuit 170 is an example of the generation unit 210 in the present disclosure. In this manner, the generation unit 210 may be configured by a logic circuit that outputs a selection signal by logically operating the test signal and the command signal.

[0057] The multiplexer 120 selects either the first test pattern or the second test pattern according to the output of such a logic circuit. The multiplexer 120 is an example of the selection unit 220 in the present disclosure. Therefore, when the ECC test is enabled, the selection unit 220 may select the second test pattern in a write operation to the memory core 20 and may select the first test pattern in a read operation from the memory core 20. Furthermore, when the bit shift test is enabled, the selection unit 220 may select the first test pattern in both the write operation and the read operation.

[0058] The switch 180 switches the connection between the BIST circuit 100 and the memory core 20 so as to be able to bypass the ECC circuit 60 provided between the BIST circuit 100 and the memory core 20. When the ECC test is enabled, the switch 180 may connect the terminal a to the terminal b and the terminal d to the terminal e. When the bit shift test is enabled, the switch 180 may connect the terminal a to the terminal b and the terminal d to the terminal f.

[0059] The switch 180 is an example of the switching unit 240 in the present disclosure. Therefore, when an ECC test is enabled, the switching unit 240 may switch the connection with the memory core 20 so as to bypass the ECC circuit 60 in a write operation. Furthermore, when a bit shift test is enabled, the switching unit 240 may switch the connection with the memory core 20 so as to bypass the ECC circuit 60 in both a write operation and a read operation.

[0060] Therefore, when the ECC test is enabled, in a read operation, the compare 150 is supplied with corrected data obtained by the ECC circuit 60 performing error correction on the read data read from the memory core 20. In addition, the first test pattern selected by the multiplexer 120 is supplied from the flip-flop 140 to the compare 150.

[0061] On the other hand, when the bit shift test is enabled, in a read operation, the read data read from the memory core 20 is supplied to the compare 150, bypassing the ECC circuit 60. In addition, the second test pattern selected by the multiplexer 120 is supplied from the flip-flop 140 to the compare 150.

[0062] The compare unit 150 is an example of the comparison unit 230 in the present disclosure. Therefore, when the ECC test is enabled, the comparison unit 230 compares the read data read from the memory core 20 with the first test pattern, which is error-corrected by the ECC circuit 60. On the other hand, when the bit shift test is enabled, the comparison unit 230 compares the read data read from the memory core 20 with the second test pattern.

[0063] With this configuration, the BIST circuit 100 according to this embodiment can use a single 1-bit shift test circuit to execute both the 1-bit shift test on the memory core 20 and the test on the 1-bit correction ECC circuit 60. Therefore, the BIST circuit 100 according to this embodiment can share part of an existing test circuit for different tests, thereby suppressing an increase in circuit size compared to when a new circuit is provided separately for testing the ECC circuit 60.

[0064] In particular, in the BIST circuit 100 according to this embodiment, the generation unit 210 is configured by a logic circuit including a logical product circuit that calculates the logical product of ECCTEST and WRITE, and a logical sum circuit that calculates the logical sum of the output of the logical product circuit and BITSHIFTEN. Therefore, according to the BIST circuit 100 according to this embodiment, by simply adding a general-purpose logic circuit, a circuit for a bit shift test (for example, an address decoder) can also be used in common for an ECC test.

[0065] This disclosure also includes the following:

[0066] (Appendix 1) a generator that generates a selection signal based on a test signal that enables one of a plurality of tests including at least a bit shift test that tests input / output paths of a plurality of bits in a memory core while inverting each bit, and an ECC test that tests an ECC circuit that detects and corrects bit errors that occur in the memory core, and a command signal that defines the operation of the memory core; a selection unit that selects, in accordance with the selection signal, either a first test pattern in which the plurality of bits are set to a predetermined logic level or a second test pattern in which a specific bit of the plurality of bits is set to a logic level different from the predetermined logic level, and outputs the selected test data; a comparison unit that compares the read data read from the memory core with the test data when the bit shift test is enabled, and compares the test data with corrected data obtained by error correction of the read data by the ECC circuit when the ECC test is enabled; A test circuit comprising: (Appendix 2) the selection unit selects the second test pattern in a write operation to the memory core and selects the first test pattern in a read operation from the memory core when the ECC test is enabled. Test circuit described in Appendix 1. (Appendix 3) the selection unit selects the first test pattern in both a write operation to the memory core and a read operation from the memory core when the bit shift test is enabled. 1. A test circuit as described in Appendix 1 or 2. (Appendix 4) the generation unit is configured by a logic circuit that outputs the selection signal by logically operating the test signal and the command signal. 4. The test circuit of any one of claims 1 to 3. (Appendix 5) The logic circuit comprises: a logical product circuit that calculates a logical product of a second test signal that enables the ECC test and a write command signal that defines a write operation to the memory core; an OR circuit that calculates a logical OR of an output of the AND circuit and a first test signal that enables the bit shift test; 5. The test circuit of any one of claims 1 to 4. (Appendix 6) a switching unit that switches a connection between the ECC circuit and the memory core so that the ECC circuit can be bypassed; 6. The test circuit of any one of claims 1 to 5. (Appendix 7) the switching unit switches a connection with the memory core so as to bypass the ECC circuit in a write operation to the memory core when the ECC test is enabled; 7. The test circuit of any one of claims 1 to 6. (Appendix 8) the switching unit switches the connection with the memory core so as to bypass the ECC circuit in both a write operation to the memory core and a read operation from the memory core when the bit shift test is enabled. 8. The test circuit of any one of claims 1 to 7. [Explanation of symbols]

[0067] 10 Memory System 20 memory cores 30 Serial-parallel conversion circuit 40 Command Controller 50RW controller 60 ECC circuit 100 BIST circuits 110 BIST Controller 120 Multiplexer 130 Address Decoder 140 Flip-Flop 150 Compare 160 Logical AND Circuit 170 OR circuit 180 Switch 210 Generation part 220 Selection Section 230 Comparison Section 240 Switching section

Claims

1. a generator that generates a selection signal based on a test signal that enables one of a plurality of tests including at least a bit shift test that tests input / output paths of a plurality of bits in a memory core while inverting each bit, and an ECC test that tests an ECC circuit that detects and corrects bit errors that occur in the memory core, and a command signal that defines the operation of the memory core; a selection unit that selects, in accordance with the selection signal, either a first test pattern in which the plurality of bits are set to a predetermined logic level or a second test pattern in which a specific bit of the plurality of bits is set to a logic level different from the predetermined logic level, and outputs the selected test data; a comparison unit that compares the read data read from the memory core with the test data when the bit shift test is enabled, and compares the test data with corrected data obtained by error correction of the read data by the ECC circuit when the ECC test is enabled; A test circuit comprising:

2. the selection unit, when the ECC test is enabled, selects the second test pattern in a write operation to the memory core and selects the first test pattern in a read operation from the memory core.

2. The test circuit of claim 1.

3. the selection unit selects the first test pattern in both a write operation to the memory core and a read operation from the memory core when the bit shift test is enabled.

3. The test circuit of claim 2.

4. the generation unit is configured by a logic circuit that outputs the selection signal by logically operating the test signal and the command signal.

4. The test circuit of claim 3.

5. The logic circuit comprises: a logical product circuit that calculates a logical product of a second test signal that enables the ECC test and a write command signal that defines a write operation to the memory core; a logical OR circuit that calculates a logical OR of an output of the logical AND circuit and a first test signal that enables the bit shift test, 5. The test circuit of claim 4.

6. a switching unit that switches a connection between the memory core and the ECC circuit so that the ECC circuit can be bypassed; 6. A test circuit according to any one of claims 1 to 5.

7. the switching unit switches the connection with the memory core so as to bypass the ECC circuit in a write operation to the memory core when the ECC test is enabled.

7. The test circuit of claim 6.

8. the switching unit switches the connection with the memory core so as to bypass the ECC circuit in both a write operation to the memory core and a read operation from the memory core when the bit shift test is enabled.

8. The test circuit of claim 7.

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