Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing variations in a result of calibration between a plurality of VCOs and reducing variations in characteristics of the VCOs.SOLUTION: This semiconductor device includes: a voltage controlled oscillator that includes an N-channel MOS transistor and outputs an oscillation signal having a frequency corresponding to an input voltage input to a gate of the N-channel MOS transistor; an input voltage supply circuit that supplies the input voltage; and a calibration voltage generation circuit that generates a calibration voltage for calibration by operating instead of the input voltage supply circuit when calibration of the voltage controlled oscillator is performed. The calibration voltage generation circuit is configured to generate a voltage obtained by combining a first voltage reflecting a threshold voltage of the N-channel MOS transistor and a second voltage which is an arbitrary fixed voltage.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device that includes a voltage-controlled oscillator and has a function of calibrating the voltage-controlled oscillator. [Background technology]

[0002] Phase-locked loop (PLL) circuits and clock data recovery (CDR) circuits are equipped with voltage-controlled oscillators (VCOs), which vary the output frequency according to the input voltage. A VCO can set the output frequency to a desired value by fixing the input voltage at a certain value. However, due to variations in the transistors and other components that make up a VCO, there is a problem in that the output frequency varies between multiple VCOs even when the same input voltage is applied. For this reason, technologies are being developed to incorporate calibration functions into VCOs and reduce such variations. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 3254427 Summary of the Invention [Problem to be solved by the invention]

[0004] When VCO calibration is performed, variations in the threshold voltages of the transistors contained in the VCOs can cause variations in the calibration results among multiple VCOs, which can also cause variations in the VCO characteristics. It is desirable to reduce such variations.

[0005] In view of the above problems, the present invention provides a semiconductor device that can suppress variations in calibration results among a plurality of VCOs and reduce variations in VCO characteristics. [Means for solving the problem]

[0006] A semiconductor device according to the present invention comprises: a voltage-controlled oscillator including an N-channel MOS transistor and outputting an oscillation signal having a frequency corresponding to an input voltage input to a gate of the N-channel MOS transistor; an input voltage supply circuit for supplying the input voltage; and a calibration voltage generation circuit for operating in place of the input voltage supply circuit during calibration of the voltage-controlled oscillator to generate a calibration voltage for calibration. The calibration voltage generation circuit is configured to generate a voltage obtained by combining a first voltage reflecting the threshold voltage of the N-channel MOS transistor and a second voltage which is an arbitrary fixed voltage. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a semiconductor device that can suppress variations in calibration results among a plurality of VCOs and reduce variations in VCO characteristics. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a circuit diagram illustrating a semiconductor device 1 according to a first embodiment. [Figure 2A] 3 is a schematic diagram illustrating a calibration operation in the semiconductor device 1 according to the first embodiment. FIG. [Figure 2B] 4 is a graph showing a calibration operation in the semiconductor device 1 according to the first embodiment. [Figure 2C] 3 is a schematic diagram illustrating a calibration operation in the semiconductor device 1 according to the first embodiment. FIG. [Figure 3] 2 is a circuit diagram illustrating an example of the configuration of a calibration voltage generating circuit 40 of the semiconductor device 1 according to the first embodiment. FIG. [Figure 4] 4 is a graph illustrating an example of the operation of the calibration voltage generating circuit 40 of the semiconductor device 1 according to the first embodiment. [Figure 5] 1 is a schematic diagram illustrating a calibration voltage generating circuit 40 of a semiconductor device 1 according to a first embodiment. [Figure 6] 4 is a graph illustrating the operation of the calibration voltage generating circuit 40 of the semiconductor device 1 according to the first embodiment. [Figure 7] 4 is a graph illustrating the operation of the calibration voltage generating circuit 40 of the semiconductor device 1 according to the first embodiment. [Figure 8] 10 is a circuit diagram illustrating an example of the configuration of a calibration voltage generating circuit 40 of a semiconductor device 1 according to a second embodiment. FIG. [Figure 9] An application example of each embodiment will be shown. [Figure 10] An application example of each embodiment will be shown. [Figure 11] 10 is a circuit diagram illustrating an example of the configuration of a calibration voltage generating circuit 40C of a semiconductor device according to a comparative example. FIG. [Figure 12] 10 is a graph illustrating the operation of the comparative example. [Figure 13] 10 is a graph illustrating the operation of the comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. In the accompanying drawings, functionally identical elements may be designated by the same numerals. Note that the accompanying drawings show embodiments and implementation examples according to the principles of the present disclosure, but these are for understanding the present disclosure and are not to be used to interpret the present disclosure in a limiting manner. The descriptions in this specification are merely typical examples and are not intended to limit the scope or application of the present disclosure in any way.

[0010] Although the present embodiment has been described in sufficient detail to enable those skilled in the art to implement the present disclosure, it should be understood that other implementations and forms are possible, and that changes in configuration and structure and substitutions of various elements are possible without departing from the scope and spirit of the technical ideas of the present disclosure. Therefore, the following description should not be interpreted as being limited thereto.

[0011] [First embodiment] A semiconductor device 1 according to a first embodiment will be described with reference to Fig. 1. The semiconductor device 1 includes a voltage-controlled oscillator 10, a charge pump circuit (input voltage supply circuit) 20 (CP), a loop filter (low-pass filter) 30 (LPF), and a calibration voltage generation circuit 40.

[0012] As an example, the VCO 10 includes a ring oscillator 11 formed by connecting multiple inverters in a ring shape, a driver 12 for driving the ring oscillator 11, and a switch circuit SW2. The driver 12 includes multiple NMOS transistors connected in parallel. The number of NMOS transistors to be driven by the switch circuit SW2 is set according to the calibration result. In other words, at least one of the multiple NMOS transistors is set to a conductive state according to the calibration result. The switch circuit Sw2 controls the number of NMOS transistors to be driven among the multiple NMOS transistors, thereby changing the driving capability of the driver 12.

[0013] The charge pump circuit 20 converts the input voltage V CTRL The charge pump circuit 20 supplies an output current to the loop filter 30 during normal operation of the VCO 10 to charge the loop filter 30. The loop filter 30 generates and supplies an input voltage V CTRLto the gate of the NMOS transistor of the driver 12. During normal operation, a control signal CALIB="L" is supplied to the charge pump circuit 20, causing the charge pump circuit 20 to start a voltage adjustment operation (voltage step-up or voltage step-down operation). In addition, the control signal CALIB="L" turns off the switch circuit SW1 connecting the calibration voltage generation circuit 40 and the VCO 10.

[0014] When performing calibration of the VCO 10, the calibration voltage generation circuit 40 generates a calibration voltage V CALIB While the calibration voltage generation circuit 40 is operating, the adjustment operation by the charge pump circuit 20 is stopped, and conversely, while the charge pump circuit 20 is operating, the operation of the calibration voltage generation circuit 40 is stopped. When calibration is performed, the control signal CALIB is set to "H", which turns on the switch circuit SW1 and causes the calibration voltage generation circuit 40 to start operating, while the charge pump circuit 20 stops operating.

[0015] 2A to 2C, the calibration operation of the VCO 10 in the semiconductor device 1 will be described. When the calibration operation is started, first, the control signal CALIB is set to "H", which causes the charge pump circuit 20 to stop operating, and conversely, the calibration voltage generation circuit 40 to start operating, which causes the input voltage V CTRL Instead of the calibration voltage V CALIB is supplied to the gate of the NMOS transistor in the driver 12 (step S11). At the start of the calibration operation, the driving capability of the driver 12 is set to the minimum (for example, as shown in (1) of FIG. 2B, only one NMOS transistor is driven).

[0016] In this state, the frequency F of the signal output by the VCO 10 is measured (step S12), and it is determined whether or not this frequency F is greater than a reference value F1 (step S13). If the determination in step S13 is affirmative (Yes), an appropriate margin is added to the setting of the VCO 10 (step S14), and the setting of the VCO 10 is finalized (step S15). If the determination in step S13 is negative (No), the setting of the VCO 16 is increased by one step (for example, as shown in (2) of FIG. 2B, the number of NMOS transistors driven by the driver 12 is increased by one), and steps S12 to S13 are executed again. Thereafter, the above procedure is repeated until the frequency F becomes greater than the reference value F1 ((3) to (4) of FIG. 2B). For example, as shown in FIG. 2C, the calibration voltage V CALIB When the frequency F exceeds the reference value F1 under the given condition (symbol c in FIG. 2C), the calibration is completed.

[0017] Here, the operation when a calibration voltage generating circuit 40C according to a comparative example is used will be described with reference to Figs. 11 to 13. As shown in Fig. 11, the calibration voltage generating circuit 40C according to the comparative example applies a power supply voltage V to both ends of a voltage dividing resistor made up of resistor elements 47 and 48. DD and ground voltage V SS The calibration voltage V of the connection node N4 is given. CALIB That is, the calibration voltage V outputted by the calibration voltage generating circuit 40C is CALIB is the power supply voltage V DD In this case, the problem arises that the frequency F of the signal output from the VCO 10 varies among the multiple VCOs.

[0018] The variation in output frequency among multiple VCOs is caused by variations in the threshold voltage of the NMOS transistors that make up the driver of VCO 10. This point will be explained using Figure 12.

[0019] The three graphs in Figure 12 show the cases where the threshold voltage of the NMOS transistor in the driver 12 of the VCO 10 is typical, fast, and slow, respectively. TH If the voltage VOUT is less than the threshold voltage VOUT, the NMOS transistor is in a non-conductive state (OFF), and only an off-leak current flows through the NMOS transistor. The off-leak current is small enough that it can be approximated as no current flowing. Since the VCO 10 is driven by the current supplied from the NMOS transistor, the gate voltage of the NMOS transistor is equal to or greater than the threshold voltage VOUT. TH Below this, VCO10 will not oscillate.

[0020] As in the circuit of Figure 11, the calibration voltage V CALIB is a fixed value, the threshold voltage V TH and the calibration voltage V CALIB The difference between the threshold voltage V TH This fluctuates due to variations in the threshold voltage V, which affects the calibration results. Figure 13 shows the relationship between the input voltage and output frequency F of the VCO 10 when the threshold voltage of the NMOS transistor is different. As shown in Figure 13, TH If the frequency and voltage characteristics of VCO12 are different, the input / output characteristics (FV characteristics) of VCO12 will also change (the slope of the graph will be different), and the calibration results will vary.

[0021] 3, an example of the configuration of the calibration voltage generation circuit 40 according to the first embodiment will be described. The calibration voltage generation circuit 40 adjusts the threshold voltage V TH The calibration voltage V CALIB is configured to vary.

[0022] As shown in FIG. 3, the calibration voltage generating circuit 40 includes a PMOS transistor 41, a resistor element 42, and a diode-connected NMOS transistor 43 (first voltage generating N-channel MOS transistor) that constitute a constant voltage circuit, and is connected to a power supply voltage terminal (V DD ) and the ground potential terminal (V SS The PMOS transistor 41 is connected in series between the first and second terminals. The PMOS transistor 41 has a gate connected to a reference voltage V REF Given a constant current I REF This NMOS transistor 43 can be substantially the same element as the NMOS transistor included in the driver 12 of the VCO 10.

[0023] As a result, the calibration voltage V generated by the calibration voltage generating circuit 40 in FIG. CALIB is expressed as follows [Equation 1].

[0024]

number

[0025] where V TH is the threshold voltage of the NMOS transistor 43, β is the current amplification factor of the NMOS transistor 43, and Rc is the resistance value of the resistance element 42. The calibration voltage generating circuit 40 supplies a constant current I REF By applying the calibration voltage V CALIB Generate.

[0026] In this [Equation 1], the first and second terms on the right side are the gate-source voltage V of the NMOS transistor 43. GS However, as shown in Figure 4, the constant current I REF (Drain current I D ) variation ΔI REF is the gate-source voltage V GS The influence of variations in the NMOS transistor on the calibration voltage V CALIB The effect on V THThe voltage across the resistor element 42 is constant current I REF However, the constant current I REF By reducing the variation in the temperature, the influence can be made negligible.

[0027] In this way, the calibration voltage V generated by the calibration voltage generating circuit 40 in FIG. CALIB is the threshold voltage V of the NMOS transistor 43 TH This makes it possible to suppress variations in the calibration results of the VCO 10 among multiple VCOs.

[0028] The effects of the semiconductor device of the first embodiment will be described with reference to Figures 5 to 7. Figure 5 is an equivalent circuit diagram of the calibration voltage generation circuit 40 (Figure 3) of the first embodiment, and Figures 6 and 7 are graphs explaining the operation of the first embodiment (the solid line graph in Figure 6 shows the state in which the frequency F exceeds the reference value F1). As shown in Figure 5, the calibration voltage generation circuit 40 of Figure 3 can be equivalently represented as a constant voltage generation unit 49 realized by a diode-connected NMOS transistor 43, a constant current circuit (PMOS transistor 41), and a resistor element 42.

[0029] As shown in FIG. 6, the calibration voltage generating circuit 40 generates a voltage V TH Even if the threshold voltage V TH Vc+V is the sum of Vc and V TH to the calibration voltage V CALIB As a result, the input / output characteristics of the VCO 10 are as shown in FIG. TH It can be made substantially the same regardless of fluctuations in the temperature.

[0030] As described above, according to the semiconductor device 1 of the first embodiment, variations in the characteristics of the VCO after calibration can be suppressed regardless of fluctuations in the threshold voltage of the NMOS transistor.

[0031] [Second embodiment] A semiconductor device 1 according to a second embodiment will be described with reference to Fig. 8. The semiconductor device 1 according to the second embodiment has the same overall configuration as the first embodiment (Fig. 1). However, the configuration of the calibration voltage generation circuit 40 differs from that of the first embodiment.

[0032] As shown in FIG. 8, the calibration voltage generation circuit 40 of the second embodiment includes a differential amplifier 44, a PMOS transistor 45, and a resistor element 46 in addition to the PMOS transistor 41, resistor element 42, and diode-connected NMOS transistor 43 of the first embodiment (FIG. 3).

[0033] The differential amplifier 44 receives a reference voltage V supplied from a reference voltage generating circuit (not shown). REF is supplied to the non-inverting input terminal, and the voltage of the connection node N3 between the resistor element 46 and the PMOS transistor 45 is supplied to the inverting input terminal, and a differentially amplified signal is output to the gate of the PMOS transistor 45. The PMOS transistor 45 and the resistor element 46 are connected to a power supply voltage terminal (V DD ) and the ground potential terminal (V SS ) and the PMOS transistor 45 is connected in a current mirror with the PMOS transistor 41.

[0034] According to the circuit of FIG. 8, feedback control of differential amplifier 44 generates a constant current with less fluctuation in PMOS transistor 45, which is mirrored to PMOS transistor 41, thereby generating a calibration voltage V CALIB The fluctuation factor of the NMOS transistor threshold voltage V TH The third term on the right side of the above [Equation 1], I REF R C=(V REF / R REF )·R C If the resistor elements 42 and 46 have the same element structure, the variations will be the same, and the third term will be a constant. Similarly, the second term on the right side can be ignored, so the calibration voltage V CALIB is essentially the threshold voltage V of the NMOS transistor. TH and the constant voltage Vc.

[0035] The semiconductor device 1 of the second embodiment can achieve the same effects as the semiconductor device 1 of the first embodiment. Since the calibration voltage generation circuit 40 shown in FIG. 8 is used, the calibration voltage V CALIB (variations in the PMOS transistor 41 can be ignored), and the specific variations in the VCO can be further suppressed.

[0036] [Application example 1] 9 shows an example in which the semiconductor device 1 of the above embodiment is applied to a phase locked loop (PLL circuit). This phase locked loop includes a VCO 10, a charge pump circuit 20, a low-pass filter 30, and a calibration voltage generating circuit 40, similar to those of the above embodiment, as well as a frequency divider circuit 50 and a phase frequency comparator 60. The phase frequency comparator 60 converts the clock signal CLK output by the VCO 10 into a signal having a frequency divider circuit 50 and a phase frequency comparator 60. OUT The charge pump circuit 20 detects the phase and frequency error between the feedback signal obtained by dividing the frequency of the input clock signal CLKREF by 1 / N, and outputs a control signal UP or DOWN according to this error. The charge pump circuit 20 adjusts the output voltage according to this control signal UP or DOWN. As a result, the output clock signal CLK OUT The phase of the input signal CLK REF The phase of the signal can be synchronized with that of the signal.

[0037] [Application example 2] 10 shows an example in which the semiconductor device 1 of the above embodiment is applied to a clock data recovery circuit (CDR). This CDR circuit includes a phase comparator 70 in addition to the VCO 10, charge pump circuit 20, low-pass filter 30, and calibration voltage generation circuit 40 similar to those of the above embodiment. The phase comparator 70 receives a signal DATA IN The input clock is CLK. OUT and data OUT The phase comparator 70 separates the input signal DATA IN and the output signal CLKOUT of the VCO 10, and outputs a control signal UP or DOWN. OUT The input signal DATA IN can be synchronized to.

[0038] [others] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0039] 1...Semiconductor device 10...Voltage-controlled oscillator 11...Ring oscillator 12...Driver SW1, SW2...Switch circuit 20...Charge pump circuit (input voltage supply circuit) 30...Loop filter (low-pass filter) 40...Calibration voltage generation circuit 41, 45...PMOS transistor 42, 46...Resistance elements 43...NMOS transistor 44...Differential amplifier 49...Constant voltage circuit

Claims

1. a voltage-controlled oscillator including an N-channel MOS transistor and outputting an oscillation signal having a frequency corresponding to an input voltage input to a gate of the N-channel MOS transistor; an input voltage supply circuit that supplies the input voltage; a calibration voltage generating circuit that operates in place of the input voltage supply circuit when performing calibration of the voltage-controlled oscillator and generates a calibration voltage for calibration; Equipped with The calibration voltage generating circuit a first voltage reflecting a threshold voltage of the N-channel MOS transistor; a second voltage which is an arbitrary fixed voltage; 10. A semiconductor device comprising: a first input terminal for supplying a first voltage to a first output terminal of a semiconductor device;

2. The calibration voltage generating circuit 2. The semiconductor device according to claim 1, further comprising a diode-connected N-channel MOS transistor for generating a first voltage, wherein said first voltage is generated in said N-channel MOS transistor for generating a first voltage.

3. The calibration voltage generating circuit 3. The semiconductor device according to claim 2, further comprising a resistor element and the first voltage generating N-channel MOS transistor connected in series, wherein the calibration voltage is generated by passing a constant current generated by a constant current circuit through the resistor element.

4. The constant current circuit is a current mirror circuit configured by connecting a first P-channel MOS transistor and a second P-channel MOS transistor in a current mirror configuration; a reference resistance element connected between the first P-channel MOS transistor and a ground potential; a differential amplifier that differentially amplifies the potential of one terminal of the reference resistance element and a reference voltage and outputs an output signal to the first P-channel MOS transistor; The semiconductor device according to claim 3 , comprising:

5. 5. A phase locked loop circuit comprising: the semiconductor device according to claim 1; and a phase frequency comparator that compares an output signal and an input signal of the voltage controlled oscillator to control the input voltage supply circuit.

6. 5. A clock data recovery circuit comprising: the semiconductor device according to claim 1; and a phase comparator that compares an output signal of the voltage controlled oscillator with an input signal to control the input voltage supply circuit.

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