MOS variable capacitance element

Abstract

To provide a MOS variable capacitance element having improved capacitance change characteristics in response to changes in gate voltage.SOLUTION: A MOS variable capacitance element includes a substrate of a first conductivity type or a second conductivity type, a P-type first diffusion region and a P-type second diffusion region provided in the substrate and to which a reference voltage higher than the voltage of the substrate is applied, a P-type third diffusion region provided between the first diffusion region and the second diffusion region and having a lower impurity concentration than the first diffusion region and the second diffusion region, and a P-type gate electrode provided on the third diffusion region via an insulating film and to which a gate voltage applied is variable.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a MOS variable capacitance element. [Background technology]

[0002] Known MOS-type capacitance elements include MOS-type variable capacitance elements whose capacitance varies depending on the voltage applied to a gate electrode and the voltage applied to a diffusion region facing the gate electrode via an insulating film (see, for example, Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-252480 [Patent Document 2] Japanese Patent Application Laid-Open No. 2009-059891 Summary of the Invention [Problem to be solved by the invention]

[0004] A known MOS variable capacitance element is one in which the voltage applied to the diffusion region is used as a reference voltage and the capacitance is variable in response to changes in the gate voltage applied to the gate electrode. In conventional MOS variable capacitance elements of this type, there is room for improvement in the change in capacitance in response to changes in the gate voltage applied to the gate electrode. Therefore, a MOS variable capacitance element with improved capacitance change characteristics is desired.

[0005] An object of the present disclosure is to provide a MOS variable capacitance element with improved characteristics of capacitance change in response to changes in gate voltage. [Means for solving the problem]

[0006] In order to achieve the above object, a MOS-type variable capacitance element according to a first aspect of the present disclosure comprises: a substrate of a first conductivity type or a second conductivity type; first and second P-type diffusion regions provided within the substrate and to which a reference voltage higher than the voltage of the substrate is applied; a third P-type diffusion region provided between the first and second diffusion regions and having a lower impurity concentration than the first and second diffusion regions; and a P-type gate electrode provided on the third diffusion region via an insulating film and having a variable gate voltage applied thereto.

[0007] The MOS variable capacitance element of the second aspect is the MOS variable capacitance element of the first aspect, wherein when the first conductivity type is P type, the MOS variable capacitance element further comprises an N type well region provided in the substrate, in which the first diffusion region, the second diffusion region, and the third diffusion region are provided.

[0008] In order to achieve the above object, a MOS-type variable capacitance element according to a third aspect of the present disclosure includes a substrate of a first conductivity type or a second conductivity type, first and second N-type diffusion regions provided within the substrate and to which a reference voltage lower than a power supply voltage is applied, a third N-type diffusion region provided between the first and second diffusion regions and having a lower impurity concentration than the first and second diffusion regions, and an N-type gate electrode provided on the third diffusion region via an insulating film and having a variable gate voltage applied thereto.

[0009] A fourth aspect of the MOS variable capacitance element is the MOS variable capacitance element of the third aspect, wherein when the first conductivity type is N type, the MOS variable capacitance element further comprises a P type well region provided in the substrate, in which the first diffusion region, the second diffusion region, and the third diffusion region are provided. [Effects of the Invention]

[0010] According to the present disclosure, it is possible to provide a MOS variable capacitance element with improved characteristics of capacitance change in response to changes in gate voltage. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view of an example of a MOS variable capacitance element according to a first embodiment. [Figure 2] FIG. 3 is a diagram for explaining an example of a CV characteristic according to the first embodiment. [Figure 3] FIG. 1 is a cross-sectional view of an example of a conventional MOS variable capacitance element. [Figure 4] FIG. 10 is a cross-sectional view of an example of a MOS variable capacitance element according to a second embodiment. [Figure 5] FIG. 10 is a diagram for explaining an example of a CV characteristic according to the second embodiment. [Figure 6] FIG. 1 is a cross-sectional view of an example of a conventional MOS variable capacitance element. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the following embodiments do not limit the technology of the present disclosure.

[0013] [First embodiment] The configuration of the MOS (Metal Oxide Semiconductor) variable capacitance element of this embodiment will be described. 1 shows a cross-sectional view of an example of a MOS-type variable capacitance element 10 of this embodiment. As shown in Fig. 1, the MOS-type variable capacitance element 10 of this embodiment includes a substrate 20, a well region 22, diffusion regions 24, 26, 28, and 30, an insulating film 32, a sidewall 34, and a gate electrode 36.

[0014] The substrate 20 is a P-type substrate made of a semiconductor such as silicon.

[0015] A diffusion region 24 in which a high concentration of P-type impurities is diffused is provided in the substrate 20. The diffusion region 24 is connected to the ground voltage GND via a terminal 40.

[0016] The well region 22 is provided in the substrate 20 and has N-type impurities diffused therein.

[0017] A diffusion region 26 in which a high concentration of N-type impurities is diffused is provided in the well region 22. The diffusion region 26 is connected to a power supply voltage VDD via a terminal 46.

[0018] Diffusion region 28 and diffusion region 30 are diffusion regions in which a high concentration of P-type impurities is diffused, and are provided in well region 22. Diffusion region 28 of the present embodiment is an example of a first diffusion region of the present disclosure, and diffusion region 30 is an example of a second diffusion region of the present disclosure.

[0019] A reference voltage VS is applied to the diffusion region 28 and the diffusion region 30 from an external voltage supply unit (not shown) via the terminal 44. Therefore, the diffusion region 28 and the diffusion region 30 are set to the same potential. The reference voltage VS is a voltage higher than the substrate 20. As described above, in this embodiment, the ground voltage GND is applied to the substrate 20 via the terminal 40 and the diffusion region 24, so the reference voltage VS is a voltage higher than the ground voltage GND. In other words, in the MOS-type variable capacitance element 10 of this embodiment, the potentials of the diffusion region 28 and the diffusion region 30 are higher than the potential of the substrate 20. In the MOS-type variable capacitance element 10 of this embodiment, the reference voltage VS is set to 1 V, as an example.

[0020] The diffusion region 29 is a diffusion region in which a low concentration of P-type impurities is diffused, and is provided between the diffusion region 28 and the diffusion region 30 in the well region 22. The impurity concentration of at least the diffusion region 29 is lower than the impurity concentrations of the diffusion region 28 and the diffusion region 30. The diffusion region 29 of this embodiment is an example of a third diffusion region of the present disclosure.

[0021] Gate electrode 36 is a gate electrode in which a high concentration of P-type impurities is diffused, and is provided on diffusion region 29 via insulating film 32 such as an oxide film. A gate voltage VG applied to gate electrode 36 from an external voltage supply unit (not shown) via terminal 42 is variable. In MOS-type variable capacitance element 10 of this embodiment, for example, gate voltage VG can be changed within a range of 0 V to power supply voltage VDD.

[0022] In addition, sidewalls 34 are provided on the sides of the gate electrode 36 .

[0023] In the MOS-type variable capacitance element 10, the capacitance changes depending on the potential difference between the gate electrode 36 and the diffusion region 29. The potential of the diffusion region 29 corresponds to the reference voltage VS applied to the diffusion region 28 and the diffusion region 30. Therefore, the capacitance of the MOS-type variable capacitance element 10 corresponds to the difference between the gate voltage VG applied to the gate electrode 36 and the reference voltage VS applied to the diffusion region 28 and the diffusion region 30.

[0024] Fig. 2 shows an example of CV characteristics indicating changes in capacitance C with respect to gate voltage V, as a comparative example with the conventional MOS variable capacitance element 100 shown in Fig. 3. In Fig. 2, the CV characteristics of the MOS variable capacitance element 10 of this embodiment are shown by a solid line, and the CV characteristics of the conventional MOS variable capacitance element 100 are shown by a dotted line.

[0025] The conventional MOS-type variable capacitance element 100 shown in FIG. 3 includes a P-type substrate 120, heavily doped P-type diffusion regions 128 and 130, an insulating film 132, a sidewall 134, and a gate electrode 136. The substrate 120 is a P-type substrate, and the substrate 120 includes the diffusion region 128 and the diffusion region 130, in which a heavily doped P-type impurity is diffused. A reference voltage VS is applied to the diffusion region 128 and the diffusion region 130 from an external voltage supply unit (not shown) via a terminal 144. In the conventional MOS-type variable capacitance element 100, the reference voltage VS is set to 0 V, for example. The diffusion region 129 is a diffusion region in which a lightly doped P-type impurity is diffused, and is provided between the diffusion region 128 and the diffusion region 130 in the substrate 120. The gate electrode 136 is a gate electrode in which a heavily doped P-type impurity is diffused, and is provided on the diffusion region 129 via the insulating film 132. A gate voltage VG applied to the gate electrode 136 from an external voltage supply unit (not shown) via a terminal 142 can be changed. Side walls 134 are provided on the sides of the gate electrode 136.

[0026] 2, in the conventional MOS variable capacitance element 100, the capacitance C changes significantly when the gate voltage VG is near 0 V, and the change in capacitance C becomes more gradual as the gate voltage VG increases. Thus, in the conventional MOS variable capacitance element 100, the change in capacitance C becomes more limited as the gate voltage VG increases. It is preferable for a MOS variable capacitance element to have a constant rate of change in capacitance C relative to a change in gate voltage VG, and a large amount of change.

[0027] As described above, in the conventional MOS variable capacitance element 100, in order to include a range in which the change in capacitance C is large relative to the change in gate voltage VG, it is preferable that the gate voltage VG be near 0 V, i.e., include a range in which the gate voltage VG is negative (-). For example, in the example shown in FIG. 2, it is preferable that the range of the gate voltage VG be from -1 V to the power supply voltage VDD-1 V.

[0028] To make the gate voltage VG a negative voltage, a voltage supply unit capable of supplying negative voltages is required. However, many general-purpose voltage supply units, i.e., power supply devices, are unable to supply negative voltages. Furthermore, power supply devices that supply negative voltages generally have problems such as a complicated configuration and are expensive.

[0029] Therefore, in the MOS variable capacitance element 10 of this embodiment, as described above, the reference voltage VS applied to the diffusion region 28 and the diffusion region 30 is set to a voltage (1 V) higher than the voltage of the substrate 20. The capacitance C of the MOS variable capacitance element 10 corresponds to the difference between the gate voltage VG applied to the gate electrode 36 and the reference voltage VS applied to the diffusion region 28 and the diffusion region 30. Therefore, by setting the reference voltage VS applied to the diffusion region 28 and the diffusion region 30 to a voltage higher than the voltage of the substrate 20, this can be considered to be the same as when a negative gate voltage VG is applied to the gate electrode 136 in the conventional MOS variable capacitance element 100.

[0030] Specifically, in the MOS-type variable capacitance element 10 of this embodiment, the reference voltage Vs is 1 V, and therefore the CV curve is similar to that of the conventional MOS-type variable capacitance element 100, shifted 1 V toward a higher potential, as shown in Fig. 2. Therefore, in the MOS-type variable capacitance element 10 of this embodiment, the CV characteristics can sufficiently include a range in which the change in capacitance C is large. Furthermore, by setting the amount of shift, i.e., the reference voltage Vs, to an appropriate value, it is possible to prevent imbalance in the capacitance change ratio when viewed from the midpoint with respect to the range of change in the gate voltage Vg, as shown in Fig. 2, and to improve the balance of the capacitance change ratio.

[0031] In the conventional MOS variable capacitance element 100, even if a voltage higher than that applied to the substrate 120 is applied to the diffusion region 128 and the diffusion region 130, a leakage current occurs because the substrate 120 and the diffusion region 128 and the diffusion region 130 are all of the same conductivity type (P type). Therefore, it is difficult to achieve a state similar to that in which a negative gate voltage VG is applied to the gate electrode 136.

[0032] In contrast, in the MOS variable capacitance element 10 of this embodiment, a P-type diffusion region 28, a diffusion region 29, and a diffusion region 30 are provided in an N-type well region 22 provided in a substrate 20. This makes it possible to suppress the occurrence of leakage current, and to create a state similar to that in which a negative gate voltage VG is applied.

[0033] As described above, the MOS variable capacitance element 10 of this embodiment comprises a P-type substrate 20, P-type diffusion regions 28 and 30 provided within the substrate 20 and to which a reference voltage VS higher than that of the substrate 20 is applied, a P-type diffusion region 29 provided between the diffusion regions 28 and 30 and having a lower impurity concentration than the diffusion regions 28 and 30, and a P-type gate electrode 36 provided on the diffusion region 29 via an insulating film 32 and having a variable gate voltage VG applied thereto.

[0034] In the MOS variable capacitance element 10 of this embodiment, a reference voltage Vs higher than the voltage of the substrate 20 is applied to the diffusion region 28 and the diffusion region 30, and therefore the CV characteristics (CV curve) can be shifted in the positive direction in accordance with the reference voltage Vs. Therefore, the MOS variable capacitance element 10 of this embodiment improves the CV characteristics, which are the change characteristics of the capacitance C in accordance with changes in the gate voltage Vg.

[0035] Furthermore, although the MOS variable capacitance element 10 of this embodiment is provided with an N-type well region 22, a well region constituting another MOS transistor provided in the chip on which the MOS variable capacitance element 10 is formed may be used instead. In this case, the implantation process for forming the well region 22 for the MOS variable capacitance element 10 can be made unnecessary.

[0036] The extent to which the reference voltage VS should be higher than the voltage of the substrate 20 can be determined based on the amount of shift corresponding to the desired CV characteristics, i.e., the change in capacitance C that is desired when the gate voltage VG is applied.

[0037] Furthermore, in this embodiment, the case where the conductivity type of the substrate 20 is P-type has been described, but the conductivity type of the substrate 20 may also be N-type. In this case, the conductivity type of the substrate 20 differs from the conductivity types of the diffusion region 28 and the diffusion region 30, and therefore the occurrence of leakage current can be suppressed, so that the N-type well region 22 does not need to be provided.

[0038] [Second embodiment] 4 shows a cross-sectional view of an example of a MOS-type variable capacitance element 50 of this embodiment. As shown in Fig. 4, the MOS-type variable capacitance element 50 of this embodiment includes a substrate 60, diffusion regions 64, 68, and 70, an insulating film 72, a sidewall 74, and a gate electrode 76.

[0039] The substrate 60 is a P-type substrate made of a semiconductor such as silicon.

[0040] A diffusion region 64 in which a high concentration of P-type impurities is diffused is provided in the substrate 60. The diffusion region 64 is connected to the ground voltage GND via a terminal 80.

[0041] Diffusion region 68 and diffusion region 70 are diffusion regions in which a high concentration of N-type impurities is diffused, and are provided in substrate 60. Diffusion region 68 of the present embodiment is an example of a first diffusion region of the present disclosure, and diffusion region 70 is an example of a second diffusion region of the present disclosure.

[0042] A reference voltage VS is applied to the diffusion region 68 and the diffusion region 70 from an external voltage supply unit (not shown) via a terminal 84. Therefore, the diffusion region 68 and the diffusion region 70 are set to the same potential. The reference voltage VS is a voltage lower than the power supply voltage VDD. In the MOS-type variable capacitance element 50 of this embodiment, the reference voltage VS is set to VDD-1V, as an example.

[0043] The diffusion region 69 is a diffusion region in which a low concentration of N-type impurities is diffused, and is provided between the diffusion region 68 and the diffusion region 70 in the substrate 60. The impurity concentration of at least the diffusion region 69 is lower than the impurity concentrations of the diffusion region 68 and the diffusion region 70. The diffusion region 69 of this embodiment is an example of a third diffusion region of the present disclosure.

[0044] The gate electrode 76 is a gate electrode in which a high concentration of N-type impurities is diffused, and is provided on the diffusion region 69 via an insulating film 72 such as an oxide film. The gate voltage VG applied to the gate electrode 76 from an external voltage supply unit (not shown) via a terminal 82 is variable. In the MOS variable capacitance element 50 of this embodiment, for example, the gate voltage VG can be changed within a range of 0 V to the power supply voltage VDD.

[0045] In addition, sidewalls 74 are provided on the sides of the gate electrode 76 .

[0046] In the MOS-type variable capacitance element 50, the capacitance changes depending on the potential difference between the gate electrode 76 and the diffusion region 69. The potential of the diffusion region 69 depends on the reference voltage VS applied to the diffusion region 68 and the diffusion region 70. Therefore, the capacitance of the MOS-type variable capacitance element 50 depends on the difference between the gate voltage VG applied to the gate electrode 76 and the reference voltage VS applied to the diffusion region 68 and the diffusion region 70.

[0047] Fig. 5 shows an example of CV characteristics indicating changes in capacitance C with respect to gate voltage V, as a comparative example with the conventional MOS variable capacitance element 150 shown in Fig. 6. In Fig. 5, the CV characteristics of the MOS variable capacitance element 50 of this embodiment are shown by a solid line, and the CV characteristics of the conventional MOS variable capacitance element 150 are shown by a dotted line.

[0048] The conventional MOS variable capacitance element 150 shown in FIG. 6 includes a P-type substrate 160, a heavily doped P-type diffusion region 164, heavily doped N-type diffusion regions 168 and 170, an insulating film 172, a sidewall 174, and a gate electrode 176.

[0049] The conventional MOS variable capacitance element 150 differs from the MOS variable capacitance element 100 of this embodiment in the reference voltage Vs applied thereto. Specifically, in the conventional MOS variable capacitance element 150, the reference voltage Vs applied to the diffusion region 168 and the diffusion region 170 from an external voltage supply unit (not shown) via a terminal 184 is different. In the conventional MOS variable capacitance element 150, as an example, the reference voltage Vs is the power supply voltage Vdd. However, the two elements are the same in that a ground voltage GND is applied to the diffusion region 164 via a terminal 180 and a gate voltage Vg in the range of 0 V to the power supply voltage Vdd is applied to the gate electrode 176 via a terminal 182.

[0050] As shown in FIG. 5, in the CV characteristics of the conventional MOS variable capacitance element 150, when viewed from the midpoint of the range of change in the gate voltage VG, the balance of the capacitance change ratio is unbalanced, resulting in poor balance of the capacitance change ratio.

[0051] In contrast, in the MOS variable capacitance element 50 of this embodiment, a reference voltage VS lower than the power supply voltage VDD is applied to the diffusion region 68 and the diffusion region 70, and therefore the CV characteristics (CV curve) can be shifted in the negative direction in accordance with the reference voltage VS, as shown in Fig. 5. Therefore, with the MOS variable capacitance element 50 of this embodiment, the CV characteristics, which are the change characteristics of the capacitance C in accordance with changes in the gate voltage VG, are improved.

[0052] Specifically, in the MOS variable capacitance element 50 of this embodiment, the reference voltage VS is the power supply voltage VDD-1 V, and therefore the CV curve is similar to that of the conventional MOS variable capacitance element 150, shifted toward the lower potential side by about 1 V, as shown in Fig. 5. Therefore, in the MOS variable capacitance element 50 of this embodiment, it is possible to prevent bias in the balance of the capacitance change ratio when viewed from the midpoint within the range of change in the gate voltage VG, and to improve the balance of the capacitance change ratio.

[0053] In the MOS variable capacitance element 50 of this embodiment, even if a voltage lower than the power supply voltage VDD is applied to the diffusion region 68 and the diffusion region 70, no leakage current occurs because the substrate 60 is P-type and the diffusion region 68 and the diffusion region 70 are N-type, resulting in a reverse bias PN connection. Therefore, the gate electrode 36 can be brought into a state similar to that in which a gate voltage VG higher by 1 V is applied.

[0054] As described above, the MOS variable capacitance element 50 of this embodiment includes a P-type substrate 60, N-type diffusion regions 68 and 70 provided within the substrate 60 and to which a reference voltage VS lower than the power supply voltage VDD is applied, an N-type diffusion region 69 provided between the diffusion regions 68 and 70 and having a lower impurity concentration than the diffusion regions 68 and 70, and an N-type gate electrode 76 provided on the diffusion region 69 via an insulating film 72 and to which a gate voltage VG applied is variable.

[0055] In the MOS variable capacitance element 50 of this embodiment, a reference voltage VS lower than the power supply voltage VDD is applied to the diffusion region 68 and the diffusion region 70, and therefore the CV characteristics (CV curve) can be shifted in the negative direction in accordance with the reference voltage VS. Therefore, the MOS variable capacitance element 50 of this embodiment improves the CV characteristics, which are the change characteristics of the capacitance C in accordance with changes in the gate voltage VG.

[0056] The extent to which the reference voltage VS should be lower than the power supply voltage VDD can be determined based on the amount of change in capacitance C that is desired when a gate voltage VG is applied, i.e., the amount of shift corresponding to the desired CV characteristics.

[0057] Furthermore, in this embodiment, the case where the conductivity type of the substrate 60 is P-type has been described, but the conductivity type of the substrate 60 may also be N-type. In this case, the conductivity type of the substrate 60 is the same as the conductivity types of the diffusion region 68 and the diffusion region 70, which may cause a concern of leakage current. Therefore, it is preferable to provide a P-type well region in the substrate 60, and to provide the N-type diffusion region 68 and the diffusion region 70 in the P-type well region.

[0058] As described above, the MOS variable capacitance element 10 of the first embodiment and the MOS variable capacitance element 50 of the second embodiment can improve the change characteristics of the capacitance C in response to changes in the gate voltage VG.

[0059] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention. [Explanation of symbols]

[0060] 10, 50 MOS variable capacitance element 20, 60 board 22 well area 28, 29, 30, 68, 69, 70 Diffusion area 32, 72 insulating film 36, 76 Gate electrode

Claims

1. a substrate of a first conductivity type or a second conductivity type; a P-type first diffusion region and a P-type second diffusion region provided in the substrate and to which a reference voltage higher than the voltage of the substrate is applied; a P-type third diffusion region provided between the first diffusion region and the second diffusion region and having a lower impurity concentration than the first diffusion region and the second diffusion region; a P-type gate electrode provided on the third diffusion region via an insulating film, the gate voltage of which is variable; A MOS variable capacitance element comprising:

2. When the first conductivity type is P type, The semiconductor device further includes an N-type well region provided in the substrate, in which the first diffusion region, the second diffusion region, and the third diffusion region are provided.

2. The MOS variable capacitance element according to claim 1.

3. a substrate of a first conductivity type or a second conductivity type; an N-type first diffusion region and a second diffusion region provided in the substrate and to which a reference voltage lower than a power supply voltage is applied; an N-type third diffusion region provided between the first diffusion region and the second diffusion region and having a lower impurity concentration than the first diffusion region and the second diffusion region; an N-type gate electrode provided on the third diffusion region via an insulating film, the gate voltage applied to which is variable; A MOS variable capacitance element comprising:

4. When the first conductivity type is N-type, The semiconductor device further includes a P-type well region provided in the substrate, in which the first diffusion region, the second diffusion region, and the third diffusion region are provided.

2. The MOS variable capacitance element according to claim 1.

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