Driver, display system, electro-optical device, and electronic apparatus

Abstract

To provide a driver, etc. with which it is possible to correct data voltage errors arising from excess or shortage of charges due to pixel capacitance in capacitor drive.SOLUTION: A driver 100 drives an electro-optical panel 200 to reverse polarity, the electro-optical panel including a plurality of data lines and a plurality of pixels provided to each data line. The driver 100 includes a first to n-th capacitors provided between an output terminal TQj and nodes for the first to n-th capacitor drive; a capacitor drive circuit 20 for outputting first to n-th capacitor drive voltages corresponding to capacitance drive data DTH [n-1: 0] to the nodes for the first to n-th capacitor drive; and a control circuit 40 for supplying the capacitance drive data DTH [n-1: 0] to the capacitor drive circuit 20. The capacitance drive data is generated by addition processing of correction data corresponding to reference grayscale data, which is the grayscale data of the preceding frame or the current frame, and grayscale data GD [9:0] of the current frame.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a driver, a display system, an electro-optical device, an electronic device, and the like. [Background technology]

[0002] Patent Document 1 discloses a driver that capacitively drives an electro-optical panel. The driver in Patent Document 1 includes a capacitor circuit connected to a data voltage output terminal, a capacitor drive circuit that drives the capacitor circuit, and a variable capacitance circuit connected to the data voltage output terminal. The capacitance of the variable capacitance circuit is set so that the capacitance obtained by adding the capacitance of the variable capacitance circuit and the capacitance of the electro-optical panel has a given capacitance ratio relationship with the capacitance of the capacitor circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-80805 Summary of the Invention [Problem to be solved by the invention]

[0004] In polarity inversion driving, positive and negative polarity driving alternate every frame. Focusing on a single pixel, in a frame in which positive polarity driving is performed, the pixel maintains the negative polarity voltage of the previous frame, resulting in a negative charge being supplied to the data line when the pixel is connected to the data line. In a frame in which negative polarity driving is performed, the pixel maintains the positive polarity voltage of the previous frame, resulting in a positive charge being supplied to the data line when the pixel is connected to the data line. Such excess or deficiency of charge results in an error in charge storage in capacitive driving, resulting in a problem of an error between the pixel's write voltage and the target voltage. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a driver for polarity inversion driving an electro-optical panel including a plurality of data lines and a plurality of pixels provided on each data line, the driver including: first to nth capacitors provided between an output terminal and first to nth capacitor driving nodes (n is an integer of 2 or greater); a capacitor driving circuit that outputs first to nth capacitor driving voltages corresponding to capacitive driving data to the first to nth capacitor driving nodes; and a control circuit that supplies the capacitive driving data to the capacitor driving circuit, the capacitive driving data being generated by adding correction data corresponding to reference grayscale data, which is grayscale data of the previous frame or the current frame, to the grayscale data of the current frame.

[0006] Another aspect of the present disclosure relates to a display system including a driver and a processing device that transmits grayscale data to the driver.

[0007] Furthermore, yet another aspect of the present disclosure relates to a display system including a driver and a processing device that determines the correction data based on the reference gradation data, generates the capacitive driving data by adding the correction data and the gradation data of the current frame, and transmits the capacitive driving data to the driver.

[0008] Yet another aspect of the present disclosure relates to an electro-optical device including a driver and the electro-optical panel.

[0009] Yet another aspect of the present disclosure relates to an electronic device including a driver and the electro-optical panel. [Brief explanation of the drawings]

[0010] [Figure 1] 1 shows an example of the configuration of an electro-optical device. [Figure 2] 1 shows a first example of a configuration of a display system and a first example of a detailed configuration of a driver. [Figure 3] A detailed example of the output circuit configuration. [Figure 4] 5A and 5B are diagrams for explaining the operation of a switch and a switch and a variable capacitance circuit. [Figure 5] A detailed example of the configuration of an electro-optical panel. [Figure 6] FIG. 10 is a diagram illustrating a charge error due to pixel capacitance. [Figure 7] 10 shows an example of a signal waveform in the current frame with positive polarity drive. [Figure 8] 10 shows a first detailed configuration of a processing circuit when a driver performs correction processing. [Figure 9] FIG. 4 is a diagram illustrating conversion performed by a conversion unit. [Figure 10] 10 shows a second detailed configuration example of the processing circuit when the driver performs correction processing. [Figure 11] 10A and 10B show a second example of a configuration of a display system and a second example of a detailed configuration of a driver. [Figure 12] Example of calculation of correction factor. [Figure 13] An example of the gradation values ​​of the gradation data in the previous frame. [Figure 14] First calculation example of correction value for the current frame. [Figure 15] 10 shows an example of gradation values ​​after correction using correction data in the current frame. [Figure 16] Second calculation example of correction value for current frame. [Figure 17] Third calculation example of correction value for current frame. [Figure 18] Example of electronic device configuration DETAILED DESCRIPTION OF THE INVENTION

[0011] Preferred embodiments of the present disclosure will be described in detail below. Note that the embodiments described below do not unduly limit the scope of the claims, and not all of the configurations described in the embodiments are necessarily essential components.

[0012] 1. Electro-optical devices 1 shows an example of the configuration of an electro-optical device 400. The electro-optical device 400 includes a driver 100 and an electro-optical panel 200. In the following, an electro-optical device 400 using a demultiplex driving method will be described as an example, but the present invention is not limited to this. For example, the electro-optical device 400 may use a phase expansion driving method. In addition, in the following, an example in which the number of demultiplexes is 8 will be described, but the number of demultiplexes may be p, where p is an integer of 2 or more.

[0013] The driver 100 includes a control circuit 40, output circuits DD1 to DDk, output terminals TQ1 to TQk, and control signal output terminals SQ1 to SQ8, where k is an integer equal to or greater than 2. The driver 100 is, for example, an integrated circuit device in which multiple circuit elements are integrated on a semiconductor substrate. The output terminals TQ1 to TQk are, for example, pads provided on the semiconductor substrate, or lead terminals or bump terminals provided on the package of the integrated circuit device.

[0014] The electro-optical panel 200 includes input terminals TI1 to TIk, signal supply lines SL1 to SLk, demultiplexers DM1 to DMk, data lines DL11 to DL18, DL21 to DL28, ..., DLk1 to DLk8, and control signal input terminals SI1 to SI8. The electro-optical panel 200 is an active matrix liquid crystal display panel, an EL display panel using self-luminous elements, or the like. EL is an abbreviation for Electro-Luminescence.

[0015] The control circuit 40 outputs corresponding grayscale data to the output circuit DD1. The output circuit DD1 converts the grayscale data into a data voltage and outputs the data voltage to the output terminal TQ1. The output terminal TQ1 is connected to the input terminal TI1, which is connected to a signal supply line SL1. The output circuits DD2 to DDk, output terminals TQ2 to TQk, input terminals TI2 to TIk, and signal supply lines SL2 to SLk are configured in the same manner.

[0016] The demultiplexer DM1 includes switches SW11 to SW18. Each switch is, for example, a TFT. TFT stands for Thin Film Transistor. One end of the switch SW11 is connected to a signal supply line SL1, and the other end is connected to a data line DL11. The switch SW11 is controlled to be turned on or off by a control signal S1. Similarly, one end of the switches SW12 to SW18 is connected to the signal supply line SL1, and the other end is connected to data lines DL12 to DL18. The switches SW12 to SW18 are controlled to be turned on or off by control signals S2 to S8. The demultiplexers DM2 to DMk, switches SW21 to SW28, ..., SWk1 to SWk8, and data lines DL21 to DL28, ..., DLk1 to DLk8 are similarly configured. The number of switches and the number of data lines in each demultiplexer may be p, which is the same as the number of demultiplexers.

[0017] Although not shown in FIG. 1, the electro-optical panel 200 has a plurality of pixels arranged in a matrix. Each pixel is connected to one data line and one scanning line. The scanning lines are selected by a scanning line driving circuit (not shown). The scanning line driving circuit may be included in the driver 100 or may be provided externally to the driver 100.

[0018] Demultiplex driving will be explained using output circuit DD1 as an example. During one horizontal scanning period, switches SW11, SW12, ..., SW18 are sequentially turned on. When switch SW11 is on, output circuit DD1 writes data voltages to pixels connected to data line DL11. Similarly, when switches SW12, ..., SW18 are on, output circuit DD1 writes data voltages to pixels connected to data lines DL12, ..., DL1k. Note that rotation may be performed in demultiplex driving, and the order in which switches SW11, SW12, ..., SW18 are turned on may be arbitrary. A data voltage is a voltage written to one pixel at a time. Eight pixels are driven in a time-series manner by demultiplex driving, and the data voltages for each pixel are output to a signal supply line as a time-series signal. This signal is referred to as a data signal. In addition to pixel driving, precharging, postcharging, or both may be performed during the horizontal scanning period.

[0019] 2. Detailed driver configuration example FIG. 2 shows a first configuration example of a display system 600 and a first detailed configuration example of a driver 100. The output circuit DDj shown in FIG. 2 is any one of the output circuits DD1 to DDk, where j is an integer between 1 and k. The display system 600 includes a display controller 300 and a driver 100. The driver 100 includes an output circuit DDj and a control circuit 40. The output circuit DDj includes a capacitor circuit 10, a capacitor driving circuit 20, and a variable capacitance circuit 30. The control circuit 40 includes a processing circuit 42, an interface circuit 44, and a register circuit 48.

[0020] The interface circuit 44 performs interface processing between the driver 100 and the display controller 300 that controls the driver 100. The interface circuit 44 outputs the grayscale data GD[9:0] received from the display controller 300 to the processing circuit 42. The number of bits of the received grayscale data may be arbitrary. The interface circuit 44 is, for example, an image interface circuit of the LVDS system, parallel RGB system, or display port system. LVDS is an abbreviation for Low Voltage Differential Signaling.

[0021] The processing circuit 42 outputs capacitive driving data DTH[11:0] to the capacitor driving circuit 20 based on the gradation data GD[9:0]. The capacitor driving circuit 20 drives the capacitor circuit 10 based on the capacitive driving data DTH[11:0]. The capacitor circuit 10 and the variable capacitance circuit 30 are connected to an output node NVQ, which is connected to the output terminal TQj. When the capacitor circuit 10 is driven, charge is injected from the capacitor circuit 10 to the output node NVQ, or charge is discharged from the output node NVQ to the capacitor circuit 10. This charge transfer is redistributed to the variable capacitance circuit 30 and the internal capacitance of the electro-optical panel 200, and the output voltage VQ of the output node NVQ becomes a data voltage corresponding to the capacitive driving data DTH[11:0]. The relationship between the gradation data GD[9:0], the capacitive driving data DTH[11:0], and the data voltage will be described later.

[0022] Driving using the capacitor circuit 10 and the capacitor driving circuit 20 is referred to as capacitive driving. As will be described later, in capacitive driving, a charge error occurs due to pixel capacitance. In this embodiment, the processing circuit 42 corrects the capacitive driving data DTH[11:0] so as to correct the charge error. This reduces the error between the target voltage and the data voltage corresponding to the grayscale data GD[9:0].

[0023] The register circuit 48 stores various data that configure the operation of the driver 100. For example, the register circuit 48 stores a correction coefficient used for the above-described correction. Alternatively, the register circuit 48 stores the setting data CSW[4:0] that configures the capacitance value of the variable capacitance circuit 30. For example, the display controller 300 writes the correction coefficient and the setting data CSW[4:0] to the register circuit 48 via the interface circuit 44. Alternatively, the driver 100 may include a nonvolatile memory (not shown) that pre-stores the correction coefficient and the setting data CSW[4:0], and the correction coefficient and the setting data CSW[4:0] may be loaded from the nonvolatile memory to the register circuit 48. The processing circuit 42 performs the above-described correction using the correction coefficient read from the register circuit 48. Furthermore, the processing circuit 42 sets the capacitance value of the variable capacitance circuit 30 by outputting the setting data CSW[4:0] read from the register circuit 48 to the variable capacitance circuit 30.

[0024] 3 shows a detailed configuration example of the output circuit DDj. The output circuit DDj includes a capacitor circuit 10, a capacitor drive circuit 20, a variable capacitance circuit 30, a switch SWDR, a switch SWVC, a switch SWQ, an output terminal TQj, and a common voltage input terminal TVC.

[0025] One end of the switch SWDR is connected to the node NA1, and the other end is connected to the node NA2. One end of the switch SWVC is connected to the common voltage input terminal TVC, and the other end is connected to the node NA2. The common voltage input terminal TVC is, for example, a pad provided on the semiconductor substrate of the integrated circuit device constituting the driver 100, or a lead terminal or bump terminal provided on the package of the integrated circuit device. One end of the switch SWQ is connected to the node NA2, and the other end is connected to the output node NVQ that is connected to the output terminal TQj. Each of the switches SWDR, SWVC, and SWQ is an analog switch, and is, for example, a P-type MOS transistor, an N-type MOS transistor, or a transfer gate.

[0026] The capacitor circuit 10 includes capacitors CD1 to CD12. The capacitor driving circuit 20 includes driving circuits DR1 to DR12. However, the number of capacitors and driving circuits may be n, where n is an integer equal to or greater than 2. Similarly, the number of bits of the capacitive driving data DTH[11:0] may be n.

[0027] One end of the capacitor CDi is connected to the node NA1, and the other end is connected to the capacitor driving node NDRi. i is an integer between 1 and 12. The capacitors CD1 to CD12 have binary-weighted capacitance values. Specifically, the capacitance value of the capacitor CDi is 2 (i-1) ×CD1.

[0028] The processing circuit 42 outputs the ith bit DTH[i-1] of the capacitive drive data DTH[11:0] to the input node of the drive circuit DRi. The drive circuit DRi outputs a capacitor drive voltage corresponding to the logic level of the ith bit DTH[i-1] to the capacitor drive node NDRi. That is, when the bit DTH[i-1] is at a first logic level, the drive circuit DRi outputs a first voltage level to the capacitor drive node NDRi, and when the bit DTH[i-1] is at a second logic level, the drive circuit DRi outputs a second voltage level to the capacitor drive node NDRi. For example, the first logic level is "0" and the second logic level is "1," the first voltage level is a low-potential power supply voltage, and the second voltage level is a high-potential power supply voltage. The drive circuit DRi is composed of, for example, a level shifter that shifts the input logic level to the output voltage level of the drive circuit DRi and a buffer circuit that buffers the output of the level shifter.

[0029] When the switches SWDR and SWQ are on, the drive circuits DR1 to DR12 drive the capacitors CD1 to CD12, causing charge redistribution between the capacitors CD1 to CD12, the variable capacitance circuit 30, and the capacitance on the electro-optical panel side, resulting in a data voltage being written to the pixel.

[0030] The variable capacitance circuit 30 includes adjustment switches SWA1 to SWA5 and adjustment capacitors CA1 to CA5, where the number of switches and adjustment capacitors is m, where m is an integer of 2 or greater.

[0031] One end of the adjustment switches SWAs is connected to the node NA2, and the other end is connected to one end of the adjustment capacitor CAs. The other end of the adjustment capacitor CAs is connected to the low-potential side power supply. s is an integer between 1 and 5. The adjustment switches SWA1 to SWA5 are, for example, P-type MOS transistors, N-type MOS transistors, or transfer gates. The adjustment capacitors CA1 to CA5 have binary-weighted capacitance values. Specifically, the capacitance value of the adjustment capacitor CAs is 2 (s-1) ×CA1.

[0032] The adjustment switches SWAs are controlled to be on or off by the s-th bit CSW[s-1] of CSW[4:0]. When the adjustment switches SWAs are on, the adjustment capacitor CAs is connected to the node NA2, and the capacitance value of the adjustment capacitor CAs is added to the capacitance value of the variable capacitance circuit 30. That is, the capacitance value of the variable capacitance circuit 30 is set according to the on / off states of the adjustment switches SWA1 to SWA5.

[0033] The output circuit DDj may further include a gradation voltage generation circuit and an amplifier circuit. The gradation voltage generation circuit performs D / A conversion on the capacitive drive data DTH[11:0] and outputs a gradation voltage corresponding to the capacitive drive data DTH[11:0]. The gradation voltage generation circuit includes, for example, ladder resistors that generate voltages corresponding to each gradation value, and a selection circuit that selects from those voltages a voltage corresponding to the capacitive drive data DTH[11:0]. The amplifier circuit amplifies or buffers the gradation voltage output by the gradation voltage generation circuit and outputs it to the output node NVQ. The amplifier circuit is, for example, a voltage follower circuit. The voltage output by the amplifier circuit and the voltage output by capacitive drive are basically the same.

[0034] Alternatively, the output circuit DDj may include a gradation voltage generation circuit but not an amplifier circuit. The gradation voltage generation circuit performs D / A conversion on the capacitive drive data DTH[11:0] and outputs a gradation voltage corresponding to the capacitive drive data DTH[11:0] to the output node NVQ.

[0035] 4 is a diagram illustrating the operation of the switches SWDR and SWQ and the variable capacitance circuit 30. During a precharge period before pixel driving in a horizontal scanning period, precharge is performed by a common voltage VC. The precharge period includes a first period and a second period; for example, the first period is the first half of the precharge period, and the second period is the second half of the precharge period.

[0036] In the first period, the switches SWVC and SWQ are on, and the switch SWDR and the switches SWA1 to SWA5 of the variable capacitance circuit 30 are off. Also, all the switches of the demultiplexers DM1 to DMk in the electro-optical panel 200 are on. This causes the data lines to be precharged by the common voltage VC.

[0037] In the second period, the switches SWVC and SWDR are on, and the switch SWQ is off. Of the switches SWA1 to SWA5 of the variable capacitance circuit 30, only the switch selected by the setting data CSW[4:0] may be on, or all may be on. The capacitance drive data DTH[11:0] is 800h, which corresponds to the common voltage VC. "h" indicates a hexadecimal number. As a result, the capacitor circuit 10 and the capacitors of the variable capacitance circuit 30 are precharged by the common voltage VC.

[0038] During the pixel driving period, the switch SWVC is off, and the switches SWDR and SWQ are on. Of the switches SWA1 to SWA5 of the variable capacitance circuit 30, only the switch selected by the setting data CSW[4:0] is on. This causes the output voltage VQ to be output according to the capacitance driving data DTH[11:0].

[0039] The output voltage VQ during the pixel drive period will be described. The power supply voltage of the drive circuits DR1 to DR12 of the capacitor drive circuit 20 is set to 15V. The total capacitance of the capacitors CD1 to CD12 of the capacitor circuit 10 is set to CD, and the capacitance of the variable capacitance circuit 30 is set to CA. The capacitance on the electro-optical panel side as seen from the output terminal TQj is set to CLCD. The capacitance value CLCD includes the parasitic capacitance of the wiring connecting the output terminal TQj and the input terminal TI1, the parasitic capacitance of the signal supply line SLj, and the parasitic capacitance of one data line. The maximum amplitude of the capacitive drive is expressed as CD / (CD+CA+CLCD)×15V. Here, the maximum amplitude of the capacitive drive refers to the amplitude of the capacitive drive when the capacitive drive data DTH[11:0] changes from 000h to FFFh.

[0040] To set the maximum amplitude of capacitive driving to VAM, the capacitance value CA of the variable capacitance circuit 30 is set so that VAM = CD / (CD + CA + CLCD) × 15V. Because the capacitance values ​​of the capacitors CD1 to CD12 of the capacitor circuit 10 are binary-weighted, the output voltage VQ changes linearly with the voltage amplitude VAM as the capacitive driving data DTH[11:0] changes from 000h to FFFh. For example, if VAM = 10V and the common voltage VC is 7.5V, the output voltage VQ will change from 2.5V to 12.5V. The voltage range for positive driving is 7.5V to 12.5V, and the voltage range for negative driving is 7.5V to 2.5V. To allow for correction, as described later in FIG. 9, the maximum amplitude of capacitive driving is virtually set greater than 10V. For example, in the example of FIG. 9, the virtually doubled maximum amplitude VAM = 20V. The power supply voltage of the drive circuits DR1 to DR12 of the capacitor drive circuit 20 must be greater than VAM, and is set to, for example, 25V. In this case, the capacitance value CA of the variable capacitance circuit 30 may be set so that 20V = CD / (CD + CA + CLCD) × 25V. Note that in FIG. 9, GD[9:0] may be multiplied by a gain of approximately 2 to 1.34 to convert it to DT[11:0] so that the maximum amplitude VAM is greater than 10V and less than 15V. In this case, the power supply voltage of the drive circuits DR1 to DR12 can be set to 15V.

[0041] The capacitance value CA of the variable capacitance circuit 30 is determined, for example, as follows. When certain capacitance drive data DTH[11:0] is input to the capacitor drive circuit 20, the target voltage of the output voltage VQ is known. Therefore, predetermined capacitance drive data DTH[11:0] is input to the capacitor drive circuit 20, and the capacitance value CA of the variable capacitance circuit 30 is determined so that the output voltage VQ at that time becomes the target voltage. For example, the driver 100 may include a monitor circuit that monitors the output voltage VQ, and the processing circuit 42 may determine the capacitance value CA of the variable capacitance circuit 30 based on the monitoring results. Alternatively, an inspection device may monitor the voltage of the output terminal TQj during an inspection process or the like when manufacturing the electro-optical device 400, and the capacitance value CA of the variable capacitance circuit 30 may be determined based on the monitoring results. Alternatively, the capacitance value CA of the variable capacitance circuit 30 may be determined using circuit simulation.

[0042] 3. Charge error due to pixel capacitance 5 shows an example of the detailed configuration of the electro-optical panel 200. The following description will be given taking the demultiplexer DMj as an example. The electro-optical panel 200 includes an input terminal TIj, switches SWj1 to SWj8 of the demultiplexer DMj, data lines DLj1 to DLj8, scanning lines GL1 to GLm, and a plurality of pixels PX arranged in a matrix. Note that capacitances CPV and CPD are parasitic capacitances and do not exist as circuit elements.

[0043] Each pixel PX includes a pixel transistor and a pixel capacitance. When the electro-optical panel 200 is a liquid crystal display panel, the pixel capacitance includes liquid crystal and two electrodes arranged opposite each other with the liquid crystal sandwiched between them. The source of the pixel transistor is connected to a data line, the gate is connected to a scanning line, and the drain is connected to one end of the pixel capacitance. The other end of the pixel capacitance is connected to ground. The parasitic capacitance CPV is the parasitic capacitance when the electro-optical panel 200 is viewed from the output terminal TQj of the driver 100, and includes the parasitic capacitance of the wiring connecting the output terminal TQj of the driver 100 and the input terminal TIj of the electro-optical panel 200, and the parasitic capacitance of the signal supply line SLj within the electro-optical panel 200. The parasitic capacitance CPD is the parasitic capacitance of one data line.

[0044] 6 is a diagram for explaining the charge error due to pixel capacitance, taking the scanning line GL1 as an example, and explaining a case where the previous frame is driven by negative polarity and the current frame is driven by positive polarity.

[0045] As shown in the left diagram of Figure 6, when negative polarity drive ends in the previous frame, all pixels PX connected to scan line GL1 hold a negative data voltage. A negative data voltage is a voltage equal to or lower than the common voltage VC. As shown in the center and right diagrams of Figure 6, during the horizontal scanning period of the current frame, which is positive polarity drive, a positive data voltage is written to the first pixel, then to the second pixel, and so on up to the eighth pixel. A positive data voltage is a voltage equal to or higher than the common voltage VC.

[0046] Figure 7 shows an example of signal waveforms in the current frame with positive polarity drive. Here, an example of waveforms up to the fourth pixel driven by demultiplex drive during the horizontal scanning period is shown. Waveforms of S1 to S4 for the control signals of the demultiplexer DMj are also shown. When the control signal is at a high level, the switch is on. The target voltage is 10V for all pixels.

[0047] During the precharge period, the switches SWj1 to SWj8 of the demultiplexer are all on, and the data lines DLj1 to DLj8 are precharged by a common voltage VC=7.5V supplied from the outside.

[0048] During the pixel drive period, the control signal S1 turns on the switch SWj1, and a data voltage of 10V is written to the pixel on the data line DLj1. The first diagram from the top of Figure 7 shows an example of the waveform of the ideal output voltage VQ when there is no charge error. When there is no charge error, the output voltage VQ becomes the target voltage of 10V, and 10V is also written to the pixel.

[0049] However, as explained in the left diagram of Figure 6, a negative data voltage was held in the pixel capacitor in the previous frame. Therefore, when writing to the pixel, as shown in the center diagram of Figure 6, the pixel transistor turns on, connecting the pixel capacitor to the data line, and the negative charge accumulated in the pixel capacitor is supplied to the data line DLj1. In capacitive driving, when charge conservation is established at the output node NVQ of the output circuit DDj, a target voltage corresponding to the capacitive driving data DTH[11:0] is output. Therefore, the negative charge from the pixel capacitor as described above becomes an error, and the output voltage VQ becomes lower than the target voltage of 10V, as shown in the second diagram of Figure 7. As a result, the charge error is supplied from the pixel capacitor across frames, resulting in an error in the data voltage relative to the target voltage. The voltage error, converted into a grayscale value, is a maximum of several to 10 grayscales. As shown in the second diagram of Figure 7, as demultiplexing driving progresses to the second pixel, the third pixel, the fourth pixel, and so on, the error accumulates, and the output voltage VQ becomes lower than the target voltage of 10V. In addition, in a frame of negative polarity drive, a positive charge is supplied from the pixel capacitance, so an error occurs in the direction in which the output voltage VQ becomes higher than the target voltage.

[0050] The above-mentioned grayscale errors affect display quality, or there is a need to add an amplifier circuit to the output circuit DDj or increase the amplifier circuit's charge supply capacity to absorb the charge error. Adding an amplifier circuit increases power consumption or circuit area. Even if an amplifier circuit is included, a small charge error is desirable from the perspective of reducing power consumption or circuit area. Furthermore, since there is a possibility that the amount of charge supply may be limited depending on the amplifier circuit configuration, such as when the amplifier circuit is constructed using a low-voltage process, a small charge error is desirable from the perspective of design freedom for the amplifier circuit.

[0051] The polarity inversion driving may be any of frame inversion driving, line inversion driving, and dot inversion driving. In any polarity inversion driving, if a pixel is focused on, the polarity is inverted every frame, and the above-mentioned problem occurs in the same way.

[0052] 4. Method for correcting data voltage errors Fig. 8 shows a first detailed configuration example of the processing circuit 42 when the driver 100 performs correction processing. The processing circuit 42 includes a correction value calculation section 410, a conversion section 420, an addition section 430, and a frame memory 450. Note that the configuration example of Fig. 8 is just one example, and various configurations that can realize the calculations described later with reference to Figs. 11 to 17 may be adopted.

[0053] The charge error due to pixel capacitance is determined by the data voltage written to the pixel in the previous frame. Therefore, the processing circuit 42 calculates correction data CC for correcting the data voltage error due to the charge error using the grayscale data GD[9:0] of the previous frame.

[0054] Specifically, the frame memory 450 stores the grayscale data GD[9:0] for one frame. The frame memory 450 is a semiconductor memory such as a DRAM or an SRAM. The correction value calculation unit 410 reads the grayscale data of the previous frame from the frame memory 450 for the pixel for which correction data CC is to be calculated. This grayscale data is designated as GDM[9:0]. The correction value calculation unit 410 calculates correction data CC for correcting the data voltage error due to the charge error described above using the grayscale data GD[9:0] for the target pixel and the grayscale data GDM[9:0] of the previous frame. The number of bits of the correction data CC may be any number, as long as it is set appropriately according to the maximum correction value. The conversion unit 420 converts the grayscale data GD[9:0] into grayscale data DT[11:0] for capacitive drive based on a polarity signal POL. The polarity signal POL indicates whether positive drive or negative drive is to be performed. The adder 430 adds the correction data CC to the grayscale data DT[11:0] and outputs the result of the addition as the capacitive driving data DTH[11:0].

[0055] According to this embodiment, a data voltage error occurs in the current frame due to the charge accumulated in the pixel in the previous frame. However, by correcting the data voltage error using the correction data CC, the error between the target voltage and the data voltage can be reduced. When ideally corrected, the data voltage matches the target voltage, as shown in the first diagram of FIG. 7 . Alternatively, even if the data voltage does not perfectly match the target voltage, the error between the target voltage and the data voltage, as shown in the second diagram of FIG. 7 , can be reduced by correction. Reducing the data voltage error in this way makes it possible to omit an amplifier circuit from the output circuit DDj. Alternatively, even if an amplifier circuit is provided in the output circuit DDj, it is possible to reduce the power consumption or circuit area of ​​the amplifier circuit, or to increase design freedom, such as by fabricating the amplifier circuit using a low-voltage process.

[0056] 9 is a diagram illustrating the conversion performed by the conversion unit 420. When the polarity signal POL indicates positive polarity drive, the conversion unit 420 converts the grayscale data GD[9:0] to grayscale data DT[11:0] using DT[11:0]=GD[9:0]+800h. When the polarity signal POL indicates negative polarity drive, the conversion unit 420 converts the grayscale data GD[9:0] to grayscale data DT[11:0] using DT[11:0]=7FFh-GD[9:0]. When no data voltage error occurs due to capacitance error, DT[11:0]=BFFh, 800h, and 400h correspond to output voltages VQ of 12.5V, 7.5V, and 2.5V due to capacitive drive, respectively. The range of the gradation data DT[11:0] output by the conversion unit 420 is 400h to BFFh, but the gradation data DT[11:0] includes 000h to FFFh. 000h to 3FFh and C00h to FFFh are provided so that the capacitive driving data DTH[11:0] does not overflow even when correction etc. is performed. For example, in this embodiment, the capacitive driving data DTH[11:0] does not overflow even when correction data CC is added.

[0057] The charge error due to the pixel capacitance described above is negative in positive drive and positive in negative drive. Therefore, correction is performed to increase the gradation value in positive drive and to decrease the gradation value in negative drive. This correction is equivalent to adding positive correction data CC to the converted gradation data DT[11:0]. That is, referring to FIG. 9, adding positive correction data CC to the gradation data DT[11:0] is equivalent to increasing the gradation value of the gradation data GD[9:0] in positive drive and is equivalent to decreasing the gradation value of the gradation data GD[9:0] in negative drive. For this reason, in the configuration example of FIG. 8, the correction data CC is a positive value, and correction is achieved by adding the correction data CC to the converted gradation data DT[11:0].

[0058] 10 shows a second detailed configuration example of the processing circuit 42 when the driver 100 performs correction processing. The processing circuit 42 includes a correction value calculation section 410, a conversion section 420, and an addition section 430.

[0059] In this configuration example, the correction value calculation unit 410 calculates the correction data CC using the grayscale data GD[9:0] of the current frame as the grayscale data of the previous frame. For example, if the grayscale data GD[9:0] is grayscale data for a still image, the grayscale data of the previous frame and the grayscale data of the current frame are the same, so this configuration example can be used. Alternatively, if the grayscale data GD[9:0] is grayscale data for a moving image, the grayscale data of the previous frame and the grayscale data of the current frame are different. However, since the maximum error in the data voltage caused by capacitance error is several to 10 grayscales, it does not significantly affect the image quality when viewed as a moving image. Therefore, the configuration example of Figure 10 may be used for moving images. Since the driver 100 may not have a built-in frame memory, omitting the frame memory makes it easier to incorporate a correction function into the driver 100.

[0060] 11 shows a second configuration example of a display system 600 and a second detailed configuration example of the driver 100. In this configuration example, the display controller 300 has a built-in correction function. The display controller 300 corrects the grayscale data GD[9:0] to generate capacitive driving data DTH[11:0] and transmits the capacitive driving data DTH[11:0] to the interface circuit 44 of the driver 100. The processing circuit 42 outputs the capacitive driving data DTH[11:0] received by the interface circuit 44 to the capacitor driving circuit 20. The display controller 300 may include a configuration similar to the first detailed configuration example of the processing circuit 42 described in FIG. 8, or may include a configuration similar to the second detailed configuration example of the processing circuit 42 described in FIG. 10.

[0061] 12 to 17 show specific examples of calculation of correction. FIG. 12 shows an example of calculation of correction coefficients. The correction coefficients are coefficients used in calculating correction data CC. In the following, an example will be described in which the grayscale data GDM[9:0] of the previous frame is acquired from the frame memory 450 as explained in FIG. 8 to calculate the correction data CC. When the frame memory 450 is not used as explained in FIG. 10, "grayscale values ​​of the current frame" and "grayscale data in the current frame" can be used instead of "grayscale values ​​of the previous frame" and "grayscale data in the previous frame" in the following explanation.

[0062] The grayscale voltage range is 5V, the grayscale range is 1024, the maximum grayscale value of the previous frame is 1024, and the pixel capacitance value is 100fF. The grayscale voltage range refers to the data voltage amplitude for each of positive and negative drive. As explained in FIG. 9, positive drive has a 5V amplitude of 7.5V to 12.5V, and negative drive has a 5V amplitude of 7.5V to 2.5V. The grayscale range refers to the range of the grayscale data GD[9:0]. Since the grayscale data GD[9:0] ranges from 0 to 1023, the range is 1024 grayscales. The pixel capacitance value refers to the capacitance value of the pixel capacitance contained in one pixel.

[0063] The excess or deficiency charge value is calculated as pixel capacitance value × gradation voltage range / gradation range × gradation value of the previous frame. If the previous frame has a maximum gradation value of 1024, the excess or deficiency charge value is 100 fF × 5 V / 1024 × 1024 = 0.5 pC. The LSB capacitance value of capacitive driving, i.e., the capacitance value of capacitor CD1 of capacitor circuit 10, is set to 11.11 fF. The drive voltage of capacitive driving, i.e., the power supply voltage of drive circuits DR1 to DR12 of capacitor drive circuit 20, is set to 15 V. In this case, the correction coefficient is (excess or deficiency charge value / LSB capacitance value of capacitive driving / drive voltage of capacitive driving) / gradation range = (0.5 pC / 11.11 fF / 15 V) / 1024 = 3 / 1024. In other words, in this example, the maximum value of the data voltage error corresponds to three gradations.

[0064] Figure 13 shows an example of the gradation values ​​of the gradation data GD[9:0] in the previous frame. The gradation data GD[9:0] corresponding to the first to eighth pixels driven in sequence in demultiplex driving are designated as GD_PX1 to GD_PX8. The values ​​of each gradation data are as shown in Figure 13.

[0065] Figure 14 shows a first example of calculation of the correction value for the current frame. The correction value is the value of the correction data CC. INT() is a function that rounds off the decimal part of the real number in the parentheses and outputs an integer value. 3 / 1024 is the correction coefficient. 0.5 is added to round up the decimal part. When q is an integer between 2 and 8, SUM(GD_PX1:GD_PXq) indicates the integrated value from GD_PX1 to GD_PXq. From the second pixel onwards, the charge error up to that point accumulates, so the correction data CC is calculated using SUM(GD_PX1:GD_PXq).

[0066] FIG. 15 is an example of gradation values ​​after correction by correction data CC in the current frame. The input gradation value means the gradation value of gradation data GD[9:0], and here it is assumed that it is 1023 for all of the first to eighth pixels. The corrected gradation value is the gradation value after correction by correction data CC, and here it is assumed that correction has been performed on the gradation data GD[9:0]. If the current frame is positive polarity drive, the previous frame was negative polarity drive, so the charge error will be negative, and a correction value is added to the input gradation value to correct this. If the current frame is negative polarity drive, the previous frame was positive polarity drive, so the charge error will be positive, and a correction value is subtracted from the input gradation value to correct this.

[0067] FIG. 16 shows a second calculation example of the correction value for the current frame. In the first calculation example of FIG. 14, the charge error was calculated by accumulating the gradation values ​​of the previous frame, and then the charge error was converted into a correction value. In the second calculation example of FIG. 16, the charge error occurring for each pixel is calculated, then the charge error is accumulated, and the accumulated value is converted into a correction value. Specifically, as shown in FIG. 16, the errors corresponding to the first to eighth pixels are designated CC_PX1 to CC_PX8. The error CC_PX1 is calculated from the gradation value GD_PX1 of the first pixel in the previous frame. Similarly, the errors CC_PX2 to CC_PX8 are calculated from the gradation values ​​GD_PX2 to GD_PX8 of the second to eighth pixels in the previous frame, and no accumulation of gradation values ​​is performed. The correction value for the first pixel is the error CC_PX1. When q is an integer between 2 and 8, the correction values ​​for the second pixel and thereafter are calculated by accumulating the errors using SUM(CC_PX1:CC_PXq).

[0068] The second calculation example has a smaller calculation load than the first calculation example because the values ​​to be multiplied are smaller. On the other hand, the first calculation example has higher calculation accuracy because the values ​​are rounded to integers after multiplication.

[0069] FIG. 17 shows a third calculation example of the correction value for the current frame. In the first and second calculation examples, correction data was calculated using all bits of the gradation data of the previous frame, but in the third calculation example, correction data is calculated using the most significant bits of the gradation data of the previous frame. Below, an example using the most significant two bits is shown, but the most significant three bits or more may also be used. FIG. 17 shows the gradation values ​​of the previous frame in decimal and binary notation. The errors CC_PX1 to CC_PX8 for each pixel in the current frame are the most significant two bits of the gradation values ​​expressed in binary notation. Specifically, the errors are calculated by shifting the gradation values ​​8 bits toward the LSB. The correction value is calculated by accumulating the errors in the same way as in the second calculation example of FIG. 16.

[0070] In the third calculation example, the error for each pixel can be calculated by bit shifting, so the calculation load is smaller than in the first and second calculation examples. In this example, the correction coefficient is 3 / 1024, so the errors CC_PX1 to CC_PX8 in FIG. 17 match the errors CC_PX1 to CC_PX8 in FIG. 16. If the correction coefficient is not 3 / 1024, the errors CC_PX1 to CC_PX8 in FIG. 17 may not match the errors CC_PX1 to CC_PX8 in FIG. 16. Even in such cases, the charge error is corrected to some extent, so it is possible to reduce the excess or deficiency of charge in capacitive driving.

[0071] In this embodiment, a driver 100 performs polarity inversion driving on an electro-optical panel 200 including a plurality of data lines DLj1 to DLj8 and a plurality of pixels PX provided on each data line. The driver 100 includes first to n-th capacitors CD1 to CDn provided between an output terminal TQj and first to n-th capacitor driving nodes NDR1 to NDRn, where n is an integer equal to or greater than 2. The driver 100 includes a capacitor driving circuit 20 that outputs first to n-th capacitor driving voltages corresponding to capacitive driving data DTH[n-1:0] to the first to n-th capacitor driving nodes NDR1 to NDRn. The driver 100 includes a control circuit 40 that supplies the capacitor driving circuit 20 with capacitive driving data DTH[n-1:0] generated by adding correction data CC corresponding to reference grayscale data, which is grayscale data of the previous frame or the current frame, and grayscale data GD[9:0] of the current frame.

[0072] As described with reference to FIGS. 6 and 7, a data voltage error occurs in the current frame due to the charge accumulated in the pixel in the previous frame. According to this embodiment, the error between the target voltage and the data voltage can be reduced by correcting the data voltage error using correction data CC corresponding to the reference grayscale data. That is, when the grayscale data of the previous frame is used as the reference grayscale data, the charge accumulated in the pixel in the previous frame can be determined from the grayscale data of the previous frame, and correction data CC for correcting the charge can be calculated. Even when the grayscale data of the current frame is used as the reference grayscale data, the charge accumulated in the pixel in the previous frame can be estimated by regarding the grayscale data of the current frame as the grayscale data of the previous frame. By correcting the data voltage error as described above, it is possible to omit an amplifier circuit from the output circuit DDj. Alternatively, even if an amplifier circuit is provided in the output circuit DDj, it is possible to reduce the power consumption or circuit area of ​​the amplifier circuit, or to increase design flexibility by, for example, fabricating the amplifier circuit using a low-voltage process.

[0073] An example in which the gradation data of the previous frame is used as the reference gradation data corresponds to Fig. 8, and an example in which the gradation data of the current frame is used as the reference gradation data corresponds to Fig. 10. In the calculation examples described in Figs. 12 to 17, the gradation data of the previous frame is used as the reference gradation data, but when the gradation data of the current frame is used as the reference gradation data, it is sufficient to use the gradation data of the current frame instead of the gradation data of the previous frame in the calculation examples.

[0074] The addition process may be any process that substantially adds the correction data CC and the gradation data GD[9:0] of the current frame. In the examples of Figures 8 to 10, adding the correction data CC to the converted gradation data DT[11:0] is equivalent to adding the correction data CC to the gradation data GD[9:0] of the current frame. Alternatively, without being limited to the examples of Figures 8 to 10, the correction data CC may be added to the gradation data GD[9:0] of the current frame, and then the capacitive driving data DTH[11:0] may be obtained from the added value.

[0075] The correction may be performed in the driver 100 as described with reference to FIGS. 2, 8, 10, etc., or may be performed in the display controller 300 as described with reference to FIG.

[0076] As described with reference to FIGS. 12 to 16, the correction data CC may be data generated based on a value obtained by multiplying the reference gradation data by a correction coefficient.

[0077] According to this embodiment, since the charge error is proportional to the grayscale data of the previous frame, the correction data CC can be calculated by multiplying the reference grayscale data by the correction coefficient. As described in FIG. 12, the correction coefficient can be determined from circuit constants such as pixel capacitance values. Alternatively, the correction coefficient may be determined by circuit simulation or sample evaluation.

[0078] As described with reference to FIG. 17, the correction data CC may be data generated based on the upper bits of the reference grayscale data.

[0079] According to this embodiment, by using the upper bits of the reference gradation data, it is possible to substitute for multiplying the reference gradation data by a correction coefficient. This makes it possible to obtain the upper bits of the reference gradation data by bit shifting or the like, thereby reducing the calculation load compared to multiplying the reference gradation data by a correction coefficient. Note that the method of multiplying the reference gradation data by a correction coefficient increases the accuracy of the correction data CC compared to the method of using the upper bits of the reference gradation data.

[0080] In this embodiment, the correction data CC may be data that increases as the gradation value of the reference gradation data increases.

[0081] The greater the grayscale data of the previous frame, the greater the charge error. Therefore, by increasing the correction data CC as the grayscale value of the reference grayscale data increases, the data voltage error due to the charge error can be corrected.

[0082] In this embodiment, the correction data CC may be data for correcting a data voltage error caused by the charge held in the pixel in the previous frame.

[0083] By correcting the grayscale data using such correction data CC, the data voltage error due to the charge held in the pixel in the previous frame can be corrected, and the error between the data voltage and the target voltage can be reduced.

[0084] As described with reference to FIG. 1 and other figures, the electro-optical panel 200 may include a signal supply line SLj and first to p-th switches SWj1 to SWjp, where p is an integer equal to or greater than 2. The first to p-th switches SWj1 to SWjp may be provided between the signal supply line SLj and the first to p-th data lines DLj1 to DLjp and turned on sequentially during a horizontal scanning period. As described with reference to FIG. 14, the reference grayscale data and correction data corresponding to the first to p-th data lines DLj1 to DLjp are defined as first to p-th reference grayscale data and first to p-th correction data. The t-th correction data may be data generated based on a value obtained by multiplying the integrated value of the first to t-th reference grayscale data by a correction coefficient. t is an integer equal to or greater than 1 and equal to p.

[0085] According to this embodiment, after accumulating the reference gradation data, the correction data CC can be calculated based on the accumulated value. Since the gradation value is an integer, the correction data CC also has an integer value, but since the correction data CC is rounded to an integer value after accumulation, the calculation accuracy can be improved.

[0086] 14, p=8, and the first to eighth reference gradation data correspond to gradation values ​​GD_PX1 to GD_PX8. The integrated value of the first to t-th reference gradation data corresponds to SUM(GD_PX1:GD_PXt) included in the calculation formula for the correction value, and the correction coefficient corresponds to 3 / 1024.

[0087] As described with reference to FIG. 16, the t-th correction data may be data generated based on the integrated values ​​of the 1st to t-th errors obtained by multiplying each of the 1st to t-th reference grayscale data by a correction coefficient.

[0088] According to this embodiment, after determining the error for each pixel that is demultiplexed, the errors are accumulated and correction data CC can be calculated based on the accumulated value. Since the correction data CC has fewer bits than the gradation data, the calculation load can be reduced compared to when accumulating gradation data.

[0089] 16, p=8, the first to eighth reference gradation data correspond to gradation values ​​GD_PX1 to GD_PX8, and the first to eighth errors correspond to errors CC_PX1 to CC_PX8. The integrated value of the first to t-th errors corresponds to SUM(CC_PX1:XX_PXt) included in the calculation formula for the correction value.

[0090] 2 and the like, the control circuit 40 may obtain the correction data CC based on the reference grayscale data, and may generate the capacitive driving data DTH[11:0] by adding the correction data CC and the grayscale data GD[9:0] of the current frame. In this embodiment, the display system 600 may include a driver 100 and a processing device that transmits the grayscale data GD[9:0] to the driver 100.

[0091] According to this embodiment, a function for correcting data voltage errors caused by charges accumulated in pixels in the previous frame can be built into the driver 100. In the example of Fig. 2, the processing device corresponds to the display controller 300, but the processing device is not limited to this. The processing device may be a processor such as an MPU or a CPU.

[0092] 11 and other drawings, the display system 600 may include a driver 100 and a processing device. The processing device may obtain correction data CC based on reference grayscale data, generate capacitive driving data DTH[11:0] by adding the correction data CC and the grayscale data GD[9:0] of the current frame, and transmit the capacitive driving data DTH[11:0] to the driver 100.

[0093] According to this embodiment, a function for correcting data voltage errors caused by charges accumulated in pixels in the previous frame can be built into the processing device. In the example of FIG. 11, the processing device corresponds to the display controller 300, but the processing device is not limited to this. The processing device may be a processor such as an MPU or a CPU.

[0094] 5.Electronic equipment 18 shows an example of the configuration of an electronic device including a driver according to this embodiment. Various electronic devices incorporating a display device are envisioned as examples of the electronic device according to this embodiment. For example, the electronic device may be a projector, a television device, an information processing device, a portable information terminal, a car navigation system, or a portable game terminal.

[0095] The electronic device 500 includes an electro-optical device 400, a display controller 300, a processing unit 310, a storage unit 320, a user interface unit 330, and a data interface unit 340. The electro-optical device 400 includes a driver 100 and an electro-optical panel 200.

[0096] The user interface unit 330 is an interface unit that accepts various operations from the user. The user interface unit 330 is composed of, for example, buttons, a mouse, a keyboard, or a touch panel attached to the electro-optical panel 200. The data interface unit 340 is an interface unit that inputs and outputs image data or control data. The data interface unit 340 is, for example, a wired communication interface such as USB, or a wireless communication interface such as wireless LAN. The memory unit 320 stores image data input from the data interface unit 340. Alternatively, the memory unit 320 functions as a working memory for the processing device 310 or the display controller 300. The processing device 310 performs control processing of each component of the electronic device and various data processing. The processing device 310 is, for example, a processor such as a CPU or a microcomputer. The display controller 300 performs control processing for the driver 100. For example, the display controller 300 converts image data transferred from the data interface unit 340 or the memory unit 320 into a format acceptable to the driver 100 and outputs the converted image data to the driver 100. The driver 100 drives the electro-optical panel 200 based on image data transferred from the display controller 300 .

[0097] Although the present embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, a term described at least once in the specification or drawings with a different term having a broader or equivalent meaning may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of the present embodiment and modifications are also intended to be included within the scope of the present disclosure. Furthermore, the configurations and operations of the control circuit, output circuit, driver, electro-optical panel, electro-optical device, display driver, electronic device, etc. are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0098] 10...capacitor circuit, 20...capacitor driving circuit, 30...variable capacitance circuit, 40...control circuit, 42...processing circuit, 44...interface circuit, 48...register circuit, 100...driver, 200...electro-optical panel, 300...display controller, 310...processing device, 320...storage unit, 330...user interface unit, 340...data interface unit, 400...electro-optical device, 410...correction value calculation unit, 420...conversion unit, 430...addition unit, 450...frame memory, 500...electronic device, 600...display system, CC...correction data, CD1 to CD12...capacitors, DLj1 to DLj8...data lines, DMj...demultiplexer, DTH[11:0]...capacitance driving data, GD[9:0]...grayscale data, NDR1 to NDR12...capacitor driving node, PX...pixel, SWj1 to SWj8...switch

Claims

1. A driver for polarity inversion driving an electro-optical panel including a plurality of data lines and a plurality of pixels provided on each data line, first to n-th capacitors provided between the output terminal and first to n-th capacitor driving nodes (n is an integer of 2 or more); a capacitor driving circuit that outputs first to n-th capacitor driving voltages corresponding to capacitance driving data to the first to n-th capacitor driving nodes; a control circuit that supplies the capacitance driving data generated by adding correction data corresponding to reference gray scale data, which is gray scale data of a previous frame or a current frame, and the gray scale data of the current frame to the capacitor driving circuit; A driver comprising:

2. 2. The driver according to claim 1, The driver, wherein the correction data is data generated based on a value obtained by multiplying the reference grayscale data by a correction coefficient.

3. 2. The driver according to claim 1, The driver is characterized in that the correction data is data generated based on upper bits of the reference grayscale data.

4. 2. The driver according to claim 1, The driver is characterized in that the correction data is data that increases as the gradation value of the reference gradation data increases.

5. 2. The driver according to claim 1, The driver, wherein the correction data is data for correcting a data voltage error caused by charges held in pixels in the previous frame.

6. 2. The driver according to claim 1, The electro-optical panel comprises: A signal supply line; first to p-th switches that are provided between the signal supply line and the first to p-th data lines (p is an integer of 2 or more) and are sequentially turned on during a horizontal scanning period; Including, When the reference gray scale data and the correction data corresponding to the first to p-th data lines are first to p-th reference gray scale data and first to p-th correction data, A driver characterized in that the t-th correction data (t is an integer greater than or equal to 1 and less than or equal to p) is data generated based on a value obtained by multiplying the integrated value of the first to t-th reference gradation data by a correction coefficient.

7. 2. The driver according to claim 1, The electro-optical panel comprises: A signal supply line; first to p-th switches that are provided between the signal supply line and the first to p-th data lines (p is an integer of 2 or more) and are sequentially turned on during a horizontal scanning period; Including, When the reference gray scale data and the correction data corresponding to the first to p-th data lines are first to p-th reference gray scale data and first to p-th correction data, A driver characterized in that the t-th correction data (t is an integer greater than or equal to 1 and less than or equal to p) is data generated based on the integrated values ​​of the 1st to t-th errors obtained by multiplying each of the 1st to t-th reference gradation data by a correction coefficient.

8. 2. The driver according to claim 1, The driver is characterized in that the control circuit determines the correction data based on the reference grayscale data, and generates the capacitive driving data by adding the correction data and the grayscale data of the current frame.

9. A driver according to claim 8; a processing device that transmits gradation data to the driver; A display system comprising:

10. A driver according to any one of claims 1 to 7; a processing device that calculates the correction data based on the reference grayscale data, generates the capacitive driving data by adding the correction data and the grayscale data of the current frame, and transmits the capacitive driving data to the driver; A display system comprising:

11. A driver according to any one of claims 1 to 8; the electro-optical panel; An electro-optical device comprising:

12. A driver according to any one of claims 1 to 8; the electro-optical panel; 1. An electronic device comprising:

Images