Ram

Abstract

To provide a RAM capable of suppressing interference between ports.SOLUTION: In a RAM (100), a first bit line (bita) and a second bit line (bitb) are arranged on different layers (Ly), and one of them has a first connection part (Cb1) formed on the same layer (Ly) as the other and connected to a memory cell (50). A first inversion bit line (bitab) and a second inversion bit line (bitbb) are arranged on the different layers (Ly), and one of them has a second connection part (Cb2) formed on the same layer as the other and connected to the memory cell (50).SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The invention disclosed herein relates to RAM (Random Access Memory), and more particularly to multi-port RAM, including dual-port RAM and two-port RAM. [Background technology]

[0002] The RAM disclosed in Patent Document 1 can read data from a first memory cell and write data to a second memory cell simultaneously or almost simultaneously. Such RAM can process data at high speed. It is known that such RAM can cause port-to-port interference (see Patent Document 1, for example). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2007 / 018043 [Summary]

[0004] In the RAM disclosed in Patent Document 1, there is an increasing demand for suppressing interference between ports.

[0005] The RAM disclosed in this specification includes a plurality of memory cells, a first bit line and a first inverted bit line connected to each of the plurality of memory cells and configured to be used for a write operation to write information to the memory cell or a read operation to read information from the memory cell based on a first clock signal, and a second bit line and a second inverted bit line connected to each of the plurality of memory cells and configured to be used for the write operation or the read operation based on a second clock signal different from the first clock signal. The first bit line and the second bit line are arranged on different layers, and one of the first bit line and the second inverted bit line is formed on the same layer as the other and has a first connection portion connected to the memory cell. The first inverted bit line and the second inverted bit line are arranged on different layers, and one of the first bit line and the second inverted bit line is formed on the same layer as the other and has a second connection portion connected to the memory cell. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic block diagram of a dual port RAM according to this embodiment. [Figure 2] FIG. 2 is a circuit diagram showing the basic configuration of a memory cell. [Figure 3] FIG. 3 is a timing chart showing voltage waveforms at various points in the dual port RAM according to this embodiment. [Figure 4] FIG. 4 is a diagram showing a part of the dual port RAM according to this embodiment. [Figure 5] FIG. 5 is a diagram showing a part of the dual port RAM according to this embodiment. [Figure 6] FIG. 6 is a schematic diagram showing the wiring layout of a dual-port RAM. [Figure 7] FIG. 7 is a schematic layout diagram of each wiring in a layer in which bit wiring, power supply wiring, and ground wiring are configured.

[0007] [Detailed explanation] In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor refers to a field effect transistor whose gate structure consists of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance, an insulating layer, and a P-type, N-type, or intrinsic semiconductor layer. In other words, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor. An N-channel MOS field effect transistor is called an NMOS transistor, and a P-channel MOS field effect transistor is called a PMOS transistor.

[0008] <Dual-port RAM> FIG. 1 is a schematic block diagram of a dual-port RAM 100.

[0009] The dual port RAM 100 includes an A port, which is a first input / output port, and a B port, which is a second input / output port, which are independent of each other.

[0010] The dual port RAM 100 includes a row decoder 11 dedicated to the A port, a column decoder 12 dedicated to the A port, and a row selector 13 dedicated to the A port.

[0011] The row decoder 11 supplies row information obtained by decoding the A port address ADRA supplied from the A port to the row selector 13 .

[0012] The column decoder 12 decodes the A port address ADRA supplied from the A port to obtain column information, which is then supplied to a column selector 33, which will be described later.

[0013] The row selector 13 selects a row of a memory array 35 (to be described later) based on row information supplied from the row decoder 11 .

[0014] The dual port RAM 100 includes a row decoder 21 dedicated to the B port, a column decoder 22 dedicated to the B port, and a row selector 23 dedicated to the B port.

[0015] The row decoder 21 supplies row information obtained by decoding the B port address ADRB supplied from the B port to the row selector 23 .

[0016] The column decoder 22 decodes the B port address ADRB supplied from the B port to obtain column information, which is then supplied to a column selector 33, which will be described later.

[0017] The row selector 23 selects a row of a memory array 35 (to be described later) based on row information supplied from the row decoder 21 .

[0018] The dual port RAM 100 includes a write driver 31, a sense amplifier 32, a column selector 33, and a precharge circuit .

[0019] When the write driver 31 receives a write command and input data IA from the A port, it writes the input data IA to a memory cell selected based on the A port address ADRA in the memory array 35 via the column selector 33 and precharge circuit 34. When the write driver 31 receives a write command and input data IB from the B port, it writes the input data IB to a memory cell selected based on the B port address ADRB in the memory array 35 via the column selector 33 and precharge circuit 34.

[0020] When the sense amplifier 32 receives a read command from the A port, it reads data from a memory cell selected based on the A port address ADRA in the memory array 35 via the column selector 33 and the precharge circuit 34, and outputs the read data as output data OA to the A port. When the sense amplifier 32 receives a read command from the B port, it reads data from a memory cell selected based on the B port address ADRB in the memory array 35 via the column selector 33 and the precharge circuit 34, and outputs the read data as output data OB to the B port.

[0021] The column selector 33 selects a column for the A port of the memory array 35 based on column information supplied from the column decoder 12. The column selector 33 also selects a column for the B port of the memory array 35 based on column information supplied from the column decoder 22.

[0022] The precharge circuit 34 precharges the columns (bit lines) of the memory array 35 in the standby state.

[0023] The memory array 35 includes a plurality of memory cells 50 arranged in a matrix. The memory cells 50 will now be described in detail.

[0024] <Memory cell 50> FIG. 2 is a circuit diagram showing the basic configuration of a memory cell 50. FIG. 2 shows the circuit configuration of the kth memory cell 50. In the following description, when it is necessary to distinguish between memory cells 50, the kth memory cell 50 will be referred to as memory cell 50[k]. The memory cell 50 shown in FIG. 2 has a 6T structure (a structure consisting of six transistors). The memory cell 50 has NMOS transistors M2 and M4, PMOS transistors M1 and M3, and NMOS transistors M5, M6, M7, and M8. For convenience of description, these will be abbreviated as transistors M1 to M8 below. The transistors M5 to M8 may or may not be included in the memory cell 50.

[0025] The sources of transistors M1 and M3 are both connected to the power supply line VDD (= the terminal where the power supply voltage is applied). The drains of transistors M1 and M2 and the gates of transistors M3 and M4 are both connected to the internal node Node0. The drains of transistors M3 and M4 and the gates of transistors M1 and M2 are both connected to the internal node Node1. The sources of transistors M2 and M4 are both connected to the ground line VSS (= the terminal where the ground voltage GND is applied).

[0026] The transistors M1 and M2 form an inverter whose input terminal is connected to the internal node Node1 and whose output terminal is connected to the internal node Node0. The transistors M3 and M4 form an inverter whose input terminal is connected to the internal node Node0 and whose output terminal is connected to the internal node Node1. That is, the transistors M1 to M4 function as an inverter loop connected between the internal nodes Node0 and Node1.

[0027] The transistor M5 is connected between the internal node Node0 and the second bit line bitb, and is turned on / off in response to the voltage applied to the word line WLB[k] connected to its gate. The transistor M6 is connected between the drains of the transistors M1 and M2 and the first bit line bita, and is turned on / off in response to the voltage applied to the word line WLA[k] connected to its gate.

[0028] The transistor M7 is connected between the drains of the transistors M3 and M4 and the second inverted bit line bitbb, and is turned on / off in response to the voltage applied to the word line WLB[k] connected to its gate. The transistor M8 is connected between the internal node Node1 and the first inverted bit line bitab, and is turned on / off in response to the voltage applied to the word line WLA[k] connected to its gate.

[0029] In the dual-port RAM 100, the write driver 31, sense amplifier 32, column selector 22, and precharge circuit 34 are configured to receive information and commands from both the A port and the B port and perform the corresponding operations, but this is not limiting. The dual-port RAM 100 may also include a write driver 31, sense amplifier 32, column selector 22, and precharge circuit 34 dedicated to both the A port and the B port.

[0030] The dual port RAM 100 includes a signal generator 41 dedicated to the A port and a signal generator 42 dedicated to the B port.

[0031] The signal generation unit 41 generates a one-shot pulse signal 1shotA synchronized with the clock signal CLKA supplied from port A. The signal generation unit 41 supplies the one-shot pulse signal 1shotA to the row decoder 11, the column decoder 12, the row selector 13, the write driver 31, the sense amplifier 32, the column selector 33, and the precharge circuit 34.

[0032] The signal generation unit 42 generates a one-shot pulse signal 1shotB synchronized with the clock signal CLKB supplied from the B port. The clock signals CLKA and CLKB are asynchronous. The signal generation unit 42 supplies the one-shot pulse signal 1shotB to the row decoder 21, the column decoder 22, the row selector 23, the write driver 31, the sense amplifier 32, the column selector 33, and the precharge circuit 34.

[0033] Next, the inter-port interference will be described.

[0034] 3 is a timing chart showing the voltage waveforms of each part of the dual-port RAM 100 when port A receives a write command and port B receives a read command to write and read data to different memory cells in the same column. As shown in FIG. 3, RAM 100 can perform write and read operations on different memory cells 50 in one cycle.

[0035] 4 and 5 are diagrams showing relevant parts of a comparative dual-port RAM 100 when port A receives a write command and port B receives a read command to write and read different memory cells in the same column.

[0036] 3 shows the operation of writing data to memory cell 50[0] and reading data from memory cell 50[N-1]. As shown in FIG. 3, the write operation starts at a first timing T1 (see FIG. 3) when a rising edge of clock signal CLKA appears.

[0037] Next, at a second timing T2 (see FIG. 3) when the precharge control signal PRCA switches from the LOW level to the HIGH level, the first bit line bita and the first inverted bit line bitab are brought into a floating state.

[0038] Next, at the third timing T3 (see FIG. 3), the voltage applied to the word line WLA[0] switches from a low level to a high level, and data corresponding to the input data IA is written to the memory cell 50[0] as shown in FIG. 5.

[0039] Next, at the fourth timing T4 (see FIG. 3) when the rising edge of the clock signal CLKB appears, the read operation starts.

[0040] Next, at a fifth timing T5 (see FIG. 3) when the precharge control signal PRCB switches from the LOW level to the HIGH level, the second bit line bitb and the second inverted bit line bitbb are brought into a floating state.

[0041] Next, at the sixth timing T6 (see FIG. 3), the voltage applied to the word line WLB[N-1] switches from the LOW level to the HIGH level, and the second inversion bit line bitbb is discharged by the memory cell 50[N-1].

[0042] Thereafter, the write operation is completed, the precharge control signal PRCA is switched from HIGH level to LOW level, and at the seventh timing T7 (see FIG. 3), the first inverted bit line bitab is switched from LOW level to HIGH level.

[0043] Since the first inversion bit line bitab and the second inversion bit line bitbb are arranged in parallel, a parasitic capacitance C2 is formed between the first inversion bit line bitab and the second inversion bit line bitbb (see FIGS. 4 and 5). Since the signal on the first inversion bit line bitab and the signal on the second inversion bit line bitbb are in opposite phase to each other, noise is carried on the second inversion bit line bitbb due to the influence of capacitive crosstalk of the parasitic capacitance C2.

[0044] 3, the ideal voltage of the second inverted bit line bitbb is shown by the dashed line, and the voltage of the second inverted bit line bitbb that is not sufficiently discharged due to the influence of inter-port interference is shown by the solid line. As described above, when noise is introduced into the second inverted bit line bitbb due to capacitive crosstalk from the parasitic capacitance C2, the discharge of the second inverted bit line bitbb is prevented, and the drop in the voltage applied to the second inverted bit line bitbb becomes insufficient.

[0045] Then, at the eighth timing T8 (see Figure 3), the sense amplifier enable signal SAE switches from LOW level to HIGH level, and the sense amplifier 32 determines the logic of the difference between the voltage applied to the second bit line bitb and the voltage applied to the second inverted bit line bitbb to determine the read data.

[0046] In Fig. 3, the correct output data OB is indicated by a dashed line, and the erroneous output data OB due to the influence of inter-port interference is indicated by a solid line. As shown in Fig. 3, if the voltage drop of the second inversion bit line bitbb is insufficient, the difference between the voltage applied to the second bit line bitb and the voltage applied to the second inversion bit line bitbb becomes small. If the difference between the voltage applied to the second bit line bitb and the voltage applied to the second inversion bit line bitbb is less than the voltage difference that allows the sense amplifier 32 to discriminate logic, the erroneous output data OB (solid line in Fig. 3) is read out.

[0047] In addition, there may be cases where data is written to memory cell 50[N-1] and read from memory cell 50[0], and in such cases, the same crosstalk occurs. Furthermore, a parasitic capacitance C1 is also formed between the first bit line bita and the second bit line bitb. There is also a risk that erroneous data may be read due to crosstalk of the parasitic capacitance C1.

[0048] <Device configuration> The dual port RAM 100 according to this embodiment has a device configuration that reduces the parasitic capacitance C1, thereby reducing the influence of interference between ports. The device configuration of the dual port RAM 100 according to this embodiment will be described below with reference to the drawings.

[0049] Fig. 6 is a schematic diagram showing the wiring layout of a dual-port RAM. Fig. 7 is a schematic diagram showing a layer in which bit lines and contacts are arranged. Fig. 6 shows the kth memory cell 50[k] and the k-1th memory cell 50[k-1] among a plurality of memory cells. Note that in Fig. 6, the active regions A1 to A8 will be described with reference to the kth memory cell 50[k], but the k-1th memory cell 50[k-1] has a similar configuration.

[0050] As shown in Fig. 6, the dual port RAM 100 has active regions A1 to A8, metal wiring 61, gate wiring 62, and contacts 63. In Fig. 6, the metal wiring 61 is hatched in a grid pattern. The active regions A1 to A8 are enclosed in thick lines. The contacts 63 are shaded.

[0051] As shown in FIG. 6, the dual port RAM 100 includes a first active area A1, a second active area A2, a third active area A3, a fourth active area A4, an active area A5, an active area A6, an active area A7, and an active area A8.

[0052] The active regions A1 to A8 constitute transistors M1 to M8, respectively. Both ends of each of the active regions A1 to A8 are the source or drain of the transistors M1 to M8, and the center is the gate. Both ends of the active regions A1 to A8 overlap with metal wiring 61. The sources and drains of the active regions A1 to A8 are electrically connected to the metal wiring 61 via contacts 63, and the active regions A1 to A8 are supplied with any of signals from each bit line, power supply voltage, and ground voltage via the metal wiring 61.

[0053] The gate wiring 62 is connected via contacts 63 to metal wiring 61 connected to one of the bit lines or to metal wiring 61 connected to one of the word lines. Signals from each bit line or word line are input to the gate wiring 62. The gate wiring 62 is connected to portions that form the gates of the transistors M1 to M8 configured in the active regions A1 to A8. The transistors M1 to M8 configured in the active regions A1 to A8 are driven by signals supplied from the gate wiring 62.

[0054] The dual port RAM 100 has two wiring layers: a first layer Ly1 and a second layer Ly2. A first bit line bita and a first inverted bit line bitab are arranged in the first layer Ly1. The first bit line bita and a metal wiring 61, and the first inverted bit line bitab and the metal wiring 61 are electrically connected via contacts 63. Also arranged in the first layer Ly1 are a first connection line Cb1 arranged parallel to the first bit line bita and a second connection line Cb2 arranged parallel to the first inverted bit line bitab. In the first layer Ly1, the first bit line bita, the first inverted bit line bitab, the first connection line Cb1, the second connection line Cb2 and the metal wiring are electrically connected via the contacts 63.

[0055] The second bit line bitb and the second inverted bit line bitbb are arranged on a second layer Ly2, which is a wiring layer different from the first layer Ly1. The second bit line bitb and the second inverted bit line bitbb extend along the column direction (Y direction). The second bit line bitb and the first connection portion Cb1, which are arranged on different layers, are electrically connected via a via 64. The second inverted bit line bitbb and the second connection portion Cb2, which are also arranged on different layers, are electrically connected via a via 64. That is, a signal from the second bit line bitb is supplied to the active region A5 via the first connection portion Cb1. A signal from the second inverted bit line bitbb is supplied to the active region A7 via the second connection portion Cb2.

[0056] In the dual-port RAM 100, an input / output port is provided at one end in the column direction (Y direction). Therefore, the first bit line bita, the second bit line bitb, the first inverted bit line bitab, and the second inverted bitbb must have at least a length sufficient to electrically connect to each of the memory cells 50 arranged in the column direction. In other words, the first bit line bita, the second bit line bitb, the first inverted bit line bitab, and the second inverted bitbb are configured with a length L1 in the column direction (Y direction).

[0057] The length L21 of the first connection portion Cb1 in the column direction (Y direction) is shorter than the length L1 of the second bit line bitb in the column direction (Y direction).The length L22 of the second connection portion Cb2 in the column direction (Y direction) is shorter than the length L1 of the second inverted bit line bitbb in the column direction (Y direction).

[0058] In the dual-port RAM 100, the first bit lines bita, which are arranged in parallel in the column direction (Y direction), are arranged on a first layer Ly1, and the second bit lines bitb are arranged on a second layer Ly2 different from the first layer Ly1. Therefore, no parasitic capacitance C1 is generated between the first bit lines bita and the second bit lines bitb. Furthermore, signals on the second bit lines bitb are transmitted and received via a first connection Cb1 connected to the second bit lines bitb via a via 64. Therefore, when write and read operations are performed in the dual-port RAM 100, a parasitic capacitance C12 is generated between the first bit lines bita and the first connection Cb1.

[0059] The column-direction length L21 of the first connection portion Cb1 is shorter than the column-direction length L1 of the second bit line bitb. Therefore, the parasitic capacitance C12 is smaller than the parasitic capacitance C1 that would be generated between the first bit line bita and the second bit line bitb when the first bit line bita and the second bit line bitb are arranged in the same wiring layer. In the dual-port RAM 100, capacitive crosstalk due to the parasitic capacitance C12 when write and read operations are performed is smaller than the capacitive crosstalk due to the parasitic capacitance C1. As a result, the effects of port interference in the dual-port RAM 100 can be reduced, enabling accurate writing and reading of information.

[0060] t In the dual-port RAM 100, the first inverted bit line bitab and the second inverted bit line bitbb, which are arranged in parallel in the column direction, are arranged on different layers. Therefore, no parasitic capacitance C2 is generated between the first inverted bit line bitab and the second inverted bit line bitbb. Furthermore, the signal of the second inverted bit line bitbb is transmitted and received through the second connection portion Cb2, which is connected to the second inverted bit line bitbb through the via 64. Therefore, when a write operation or a read operation is performed in the dual-port RAM 100, a parasitic capacitance C22 is generated between the second bit line bitb and the second connection portion Cb2.

[0061] The column-direction length L22 of the second connection portion Cb2 is shorter than the column-direction length L1 of the second inverted bit line bitbb. Therefore, the parasitic capacitance C22 is smaller than the parasitic capacitance C2 generated between the first inverted bit line bitab and the second inverted bit line bitbb when the first inverted bit line bitab and the second inverted bit line bitbb are arranged in the same wiring layer. When write and read operations are performed in the dual-port RAM 100, the capacitive crosstalk due to the parasitic capacitance C22 is smaller than the capacitive crosstalk due to the parasitic capacitance C2. As a result, the effects of port interference in the dual-port RAM can be reduced, enabling accurate writing and reading of information.

[0062] In this embodiment, the first bit line bita and the first inverted bit line bitab are arranged on the first layer Ly1 to which the metal wiring 61 can be connected, but the present invention is not limited to this. For example, the first bit line bitb and the first inverted bit line bitbb may be arranged on the first layer Ly1 to which the metal wiring 61 can be connected.

[0063] Alternatively, one of the first bit wire bita and the second bit wire bitb may be arranged on the first layer Ly1 to which the metal wire 61 can be connected, and the other may be arranged on the second layer Ly2, and one of the first inverted bit wire bitab and the second inverted bit wire bitbb may be arranged on the first layer Ly1 to which the metal wire 61 can be connected, and the other may be arranged on the second layer Ly2. That is, the first bit wire bita and the second bit wire bitb, which are arranged in parallel, may be arranged on different layers, and the first inverted bit wire bitab and the second inverted bit wire bitbb, which are arranged in parallel, may be arranged on different layers.

[0064] Furthermore, while the dual-port RAM 100 is configured to have two wiring layers Ly1 and Ly2, the present invention is not limited to this. For example, the dual-port RAM 100 may have three or more wiring layers. In such a configuration, the first bit line bita and the second bit line bitb may be arranged on different layers and electrically connected to the metal wiring 61 via a first connection portion. Furthermore, the first inverted bit line bitab and the second inverted bit line bitbb may be arranged on different layers and electrically connected to the metal wiring 61 via a second connection portion.

[0065] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0066] For example, the RAM in each of the above embodiments is a dual-port RAM having an A port, which is a first input / output port, and a B port, which is a second input / output port, which are independent of each other, but instead of the dual-port RAM, a two-port RAM having an input-only port and an output-only port may be used.

[0067] <Additional Notes> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0068] The RAM (100) of the present disclosure is a RAM configured to be capable of performing a write operation based on one of a first clock signal and a second clock signal asynchronous with the first clock signal, and a read operation based on the other of the first clock signal and the second clock signal, and is configured to include signal generating circuits (51, 52) configured to generate a first pulse signal and a second pulse signal synchronized with the first pulse signal in a test mode, and to perform a write operation based on one of the first pulse signal and the second pulse signal and a read operation based on the other of the first pulse signal and the second pulse signal in the test mode (first configuration).

[0069] In the RAM of the first configuration described above, the test mode may be configured (second configuration) to include at least one first mode in which the signal generation circuit generates the first pulse signal and the second pulse signal from the second clock signal, and at least one second mode in which the signal generation circuit generates the first pulse signal and the second pulse signal from the first clock signal.

[0070] In the RAM of the second configuration, the first mode may include a first test mode, and in the first test mode, the falling edge of the second pulse signal and the rising edge of the first pulse signal may appear at the same timing (third configuration).

[0071] In the RAM of the second or third configuration, the first mode may include a second test mode, and in the second test mode, the rising edge of the second pulse signal and the rising edge of the first pulse signal may appear at the same timing or delayed by a first predetermined time from the rising edge of the second pulse signal (fourth configuration).

[0072] In the RAM of any of the second to fourth configurations, the second mode may include a third test mode, and in the third test mode, the falling edge of the first pulse signal and the rising edge of the second pulse signal may appear at the same timing (fifth configuration).

[0073] In the RAM of any of the second to fifth configurations, the second mode may include a fourth test mode, and in the fourth test mode, the rising edge of the first pulse signal and the rising edge of the second pulse signal may appear at the same timing or delayed by a second predetermined time from the rising edge of the first pulse signal (sixth configuration). [Explanation of symbols]

[0074] 11, 21 row decoder 12, 22 column decoder 13, 23 Row Selector 31, 32 Light driver 33, 34 Sense amplifier 35, 36 Column Selector 37, 38 Precharge circuit 39 Memory Array 41, 42 Signal generation unit 51, 52 Signal generation unit 511, 521 1-shot pulse signal generator 512, 513, 522, 523 Delay circuits 514, 524 NOR gates 515, 516, 525, 526 selector 100 Dual port RAM according to the comparative example 101 Dual port RAM according to an embodiment C1 parasitic capacitance

Claims

1. a plurality of memory cells; a first bit line and a first inverted bit line connected to each of the plurality of memory cells and configured to be used for a write operation for writing information to the memory cells or a read operation for reading information from the memory cells based on a first clock signal; a second bit line and a second inverted bit line connected to each of the plurality of memory cells and configured to be used for the write operation or the read operation based on a second clock signal different from the first clock signal; the first bit line and the second bit line are arranged in different layers, and one of the first bit lines has a first connection portion formed in the same layer as the other and connected to the memory cell; The first inverted bit line and the second inverted bit line are arranged in different layers, and one of the first inverted bit lines has a second connection portion formed in the same layer as the other and connected to the memory cell.

2. 2. The RAM according to claim 1, wherein the first connection portion is configured to be shorter than either the first bit line or the second bit line arranged in the same layer.

3. 2. The RAM according to claim 1, wherein the second connection portion is configured to be shorter than either the first inverted bit line or the second inverted bit line that is arranged in the same layer.

4. 2. The RAM of claim 1, wherein when one of the write operation and the read operation is performed by the first bit line and the first inverted bit line, the other of the write operation and the read operation is performed by the second bit line and the second inverted bit line.

5. 5. The RAM according to claim 4, wherein the first clock signal and the second clock signal are output in one cycle, and wherein a write operation to one memory cell and a read operation to another memory cell can be executed in the one cycle.

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