Integrated circuit having regulator circuit

Abstract

To provide an integrated circuit having a regulator circuit that limits the rise in regulator output voltage.SOLUTION: There is provided an integrated circuit having a regulator circuit that generates a specific output voltage based on a reference voltage generated by a reference voltage circuit and is equipped with: an overvoltage detection circuit that determines whether the output voltage is in an overvoltage state and outputs an overvoltage signal indicating that the output voltage is in an overvoltage state; and a switch that suppresses an increase in the output voltage of the regulator circuit when the overvoltage signal is output.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to an integrated circuit including a regulator circuit. [Background technology]

[0002] The regulator circuit disclosed in Patent Document 1 converts a constant current from a constant current source into a reference voltage (VREF) by passing the constant current through a resistor via a transistor in a current mirror circuit. The regulator circuit amplifies this reference voltage with an operational amplifier, controls the amplified voltage to be a constant voltage, and outputs the constant voltage as the regulator output voltage (VREG) from the VREG terminal.

[0003] When a negative current flows in such a regulator circuit during a latch-up test, the drain voltage of the output bias transistors (e.g., Qob1 and Qob2 in Patent Document 1) connected to the transistors (e.g., power transistors Qp1 and Qp2) that make up the current mirror circuit is pulled down by the parasitic NPN of the transistor. This causes a large current to flow through the transistors that make up the current mirror circuit, causing VREF and VREG to rise. In this case, since a low-voltage (LV) circuit with a low withstand voltage is connected to the VREG terminal, the LV circuit may be destroyed due to an overvoltage. Conventionally, measures to prevent such destruction during latch-up tests have been taken by surrounding the ESD protection elements of terminals and the reference voltage circuit of integrated circuits equipped with regulator circuits with guard rings to reduce the current caused by the parasitic NPN. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2024-000546 Summary of the Invention [Problem to be solved by the invention]

[0005] However, even if the ESD protection element and reference voltage circuit are surrounded by a guard ring, it may not be possible to completely block the parasitic NPN current depending on the element layout within the integrated circuit. Furthermore, depending on the element layout within the integrated circuit, a parasitic thyristor structure may form, which also increases the regulator output voltage and can destroy the LV circuit. Thus, conventional technology leaves room for improvement in terms of suppressing the increase in regulator output voltage.

[0006] In view of the above circumstances, an object of the present disclosure is to provide an integrated circuit including a regulator circuit that suppresses an increase in regulator output voltage. [Means for solving the problem]

[0007] In order to solve the above problems, an integrated circuit having a regulator circuit according to the present disclosure is an integrated circuit having a regulator circuit that generates a specific output voltage based on a reference voltage generated by a reference voltage circuit, and is equipped with an overvoltage detection circuit that determines whether the output voltage is in an overvoltage state and outputs an overvoltage signal indicating that the output voltage is in an overvoltage state, and a switch that suppresses an increase in the output voltage of the regulator circuit when the overvoltage signal is output. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a configuration diagram of an integrated circuit 200 including a regulator circuit 100 according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a configuration diagram of an integrated circuit 200A according to a comparative example. [Figure 3] FIG. 3 is a configuration diagram of an integrated circuit 200-1 including a regulator circuit 100-1 according to a first modification. [Figure 4] FIG. 4 is a configuration diagram of an integrated circuit 200-2 including a regulator circuit 100-2 according to the second modification. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings. Note that the same or similar reference numerals are used to designate the same functions or configurations, and descriptions thereof will be omitted as appropriate.

[0010] (Embodiment) 1 is a configuration diagram of an integrated circuit 200 including a regulator circuit 100 according to an embodiment of the present disclosure. The integrated circuit 200 may include the regulator circuit 100 and a plurality of terminals T1, T2, and T3.

[0011] A specific signal may be input to terminal T1, and a protective element may be connected to terminal T2. An external power supply VDD for driving regulator circuit 100 may be applied to terminal T2. Hereinafter, the external power supply VDD may be simply referred to as "VDD." A regulator output voltage VREG may be output to terminal T3. Hereinafter, the regulator output voltage VREG may be simply referred to as "VREG."

[0012] The regulator circuit 100 may generate a specific output voltage based on a reference voltage VREF generated by a reference voltage circuit 10. Hereinafter, the reference voltage VREF may be simply referred to as "VREF." The regulator circuit 100 may include the reference voltage circuit 10, an inverter INV, an amplifier AMP which is an amplifier circuit, an overvoltage detection circuit VDET, a P-type transistor P4, a voltage divider circuit SC, and a low-voltage circuit LVC.

[0013] (Reference voltage circuit 10) The reference voltage circuit 10 may be interpreted as a circuit that generates VREF based on VDD. The reference voltage circuit 10 may include a P-type transistor P1, a P-type transistor P2, a constant current source 12, an N-type transistor N1, a resistor R1, and a P-type transistor P3. The P-type transistor P1 and the P-type transistor P2 may form a current mirror circuit 11.

[0014] (P-type transistor P1) The source of the P-type transistor P1 may be connected to VDD, and the drain of the P-type transistor P1 may be connected to the drain of the N-type transistor N1, the drain of the P-type transistor P3, the gate of the P-type transistor P2, and the gate of the P-type transistor P1.

[0015] (P-type transistor P2) The source of the P-type transistor P2 may be connected to VDD. The drain of the P-type transistor P2 may be connected to one input terminal of the amplifier AMP and one terminal of the resistor R1. The gate of the P-type transistor P2 may be connected to the gate of the P-type transistor P1, the drain of the P-type transistor P1, and the drain of the P-type transistor P3.

[0016] (P-type transistor P3) The P-type transistor P3 may be considered as a switch that stops the operation of the current mirror included in the reference voltage circuit 10 when the overvoltage detection circuit VDET outputs the overvoltage signal S. The source of the P-type transistor P3 may be connected to VDD. The drain of the P-type transistor P3 may be connected to the gate of the P-type transistor P1, the drain of the P-type transistor P1, and the gate of the P-type transistor P2. The gate of the P-type transistor P3 may be connected to the output terminal of the inverter INV.

[0017] (N-type transistor N1) The source of the N-type transistor N1 may be connected to the constant current source 12. The drain of the N-type transistor N1 may be connected to the drain of the P-type transistor P1, the gate of the P-type transistor P1, and the gate of the P-type transistor P2. The gate of the N-type transistor N1 may input a specific signal.

[0018] (AMP) The amplifier AMP can be thought of as an operational amplifier that receives VREF and the voltage divided by the voltage divider circuit SC as inputs, amplifies the difference between these inputs, and outputs it. The output of the amplifier AMP is input to the gate of the P-type transistor P4.

[0019] (P-type transistor P4) The P-type transistor P4 may have a source connected to VDD and a drain connected to the voltage divider circuit SC, the terminal T3, and the input terminal of the overvoltage detection circuit VDET. The P-type transistor P4 may be considered as the output transistor of the regulator.

[0020] (Overvoltage detection circuit VDET) The overvoltage detection circuit VDET may determine whether or not VREG is in an overvoltage state, and output an overvoltage signal S indicating that VREG is in an overvoltage state.

[0021] For example, the overvoltage detection circuit VDET may be set with a threshold value for determining whether VREG is in an overvoltage state. The threshold value may be set to a voltage that is greater than the maximum value of VREG when the regulator circuit 100 operates in a normal state and lower than the voltage value that may destroy a circuit (e.g., a low-voltage circuit LVC) that uses VREG as a drive source.

[0022] The overvoltage detection circuit VDET determines whether VREG has exceeded the threshold value, and outputs a signal with a low level potential if VREG is not in an overvoltage state, and outputs a signal with a high level potential as an overvoltage signal S if VREG is in an overvoltage state.

[0023] (Inverter INV) The inverter INV may have an input terminal connected to the output terminal of the overvoltage detection circuit VDET, and an output terminal connected to the gate of the P-type transistor P3.

[0024] The inverter INV may invert the potential of the signal from the overvoltage detection circuit VDET and output the inverted signal. For example, the inverter INV may output a signal with a high potential when it receives a signal with a low potential from the overvoltage detection circuit VDET, and may output a signal with a low potential when it receives a signal with a high potential from the overvoltage detection circuit VDET.

[0025] (Low voltage circuit LVC) The low-voltage circuit LVC may be interpreted as a low-voltage drive circuit that uses VREG, which has a lower voltage than VDD, as its drive source.

[0026] Next, the operation of the integrated circuit 200 will be described. During a latch-up test, for example, when a negative current flows by applying a negative potential to terminal T1, a parasitic NPN is generated in N-type transistor N1. This parasitic NPN pulls down the drain potential of N-type transistor N1. In other words, it pulls down the potential of the N-well connected to the drain of N-type transistor N1. When current flows through the parasitic NPN, the current flowing through P-type transistor P1 and P-type transistor P2 increases, causing VREF to rise. As the input potential (VREF) of amplifier AMP increases, VREG also rises.

[0027] At this time, when the overvoltage detection circuit VDET detects that VREG exceeds the threshold, i.e., detects an overvoltage, the potential of the overvoltage signal S changes from low to high, and the signal is inverted by the inverter INV, causing its potential to become low, which changes the P-type transistor P3 from off to on.

[0028] When the P-type transistor P3 is turned on, the current from the parasitic NPN flows via the P-type transistor P3, causing the gate potential of the P-type transistor P2 to rise, and the P-type transistor P2 changes from the on state to the off state.

[0029] As a result, no current flows through the P-type transistor P2 and the resistor R1, and the input potential (VREF) of the amplifier AMP drops, thereby suppressing the rise in VREG.

[0030] In this way, in the integrated circuit 200, by detecting an overvoltage of VREG and suppressing the rise of VREF and VREG, it is possible to suppress the breakdown of the low-voltage circuit LVC during the latch-up test.

[0031] In the above description, the constant current source circuit (current mirror circuit 11) is a simple one-stage current mirror circuit, but the configuration of the integrated circuit 200 is not limited to this, and the integrated circuit 200 may utilize a cascode current mirror or other types of current mirror circuit.

[0032] In the above explanation, the overvoltage signal S is inverted by the inverter INV, but the overvoltage detection circuit VDET may be configured so that the overvoltage signal S goes low when an overvoltage is detected, thereby eliminating the need for the inverter INV.

[0033] Although the above has been described in connection with latch-up testing, the configuration of the integrated circuit 200 is also effective as a latch-up countermeasure during normal use.

[0034] 2 is a configuration diagram of an integrated circuit 200A according to a comparative example. The integrated circuit 200A does not include the P-type transistor P3 and the overvoltage detection circuit VDET shown in FIG. 1. Therefore, during a latch-up test, a parasitic NPN is generated in the N-type transistor N1, and current flows through the parasitic NPN, increasing the current flowing through the P-type transistors P1 and P2, and causing VREF and VREG to rise. As a result, the low-voltage circuit LVC may be destroyed.

[0035] 3 is a configuration diagram of an integrated circuit 200-1 including a regulator circuit 100-1 according to the first modification. The regulator circuit 100-1 may include a P-type transistor P5 instead of the P-type transistor P3 shown in FIG.

[0036] The P-type transistor P5 may be considered as a switch that stops the current output by the regulator circuit 100-1, that is, the current output by the P-type transistor P4, when the overvoltage detection circuit outputs the overvoltage signal S.

[0037] The source of the P-type transistor P5 may be connected to VDD. The drain of the P-type transistor P5 may be connected to the output terminal of the amplifier AMP and the gate of the P-type transistor P4. The gate of the P-type transistor P5 may be connected to the output terminal of the inverter INV. The input terminal of the inverter INV may be connected to the output terminal of the overvoltage detection circuit VDET, and the output terminal may be connected to the gate of the P-type transistor P5.

[0038] Next, the operation of the integrated circuit 200-1 will be described. During a latch-up test, a current flows through the parasitic NPN, causing VREF to rise, and VREG to also rise.

[0039] At this time, when the overvoltage detection circuit VDET detects an overvoltage, the potential of the overvoltage signal S changes from low to high, and the signal is inverted by the inverter INV, causing its potential to go low, which changes the P-type transistor P5 from off to on.

[0040] When the P-type transistor P5 is turned on, the potential of the gate of the P-type transistor P4 becomes high, and the P-type transistor P4 changes from on to off. Therefore, the current flowing through the P-type transistor P4 decreases, and the increase in VREG is suppressed.

[0041] In this way, in the integrated circuit 200-1, by detecting an overvoltage of VREG and turning on the P-type transistor P5, the P-type transistor P4 can be turned off. Therefore, by stopping the current output by the P-type transistor P4, the rise in VREG can be suppressed, thereby suppressing the breakdown of the low-voltage circuit LVC during the latch-up test.

[0042] In the integrated circuit 200-1, even when a parasitic NPN operates in the circuit inside the operational amplifier and VREG rises, VREG can be lowered to prevent breakdown of the low-voltage circuit LVC.

[0043] 4 is a configuration diagram of an integrated circuit 200-2 including a regulator circuit 100-2 according to the second modification. The regulator circuit 100-2 may include a P-type transistor P5 and a transistor NPN1 shown in FIG. 3, instead of the P-type transistor P3 shown in FIG.

[0044] The connection configuration of the P-type transistor P5 is as described above.

[0045] The transistor NPN1 may be provided between the P-type transistor P4 and a terminal T2 to which an external power supply VDD is applied. The P-type transistor P4 may be interpreted as a transistor that controls the base current of the transistor NPN1. The collector of the transistor NPN1 may be connected to VDD, and the base may be connected to the drain of the P-type transistor P4 via the terminal T4. The emitter of the transistor NPN1 may be connected to the voltage divider circuit SC via the terminal T3.

[0046] Next, the operation of the integrated circuit 200-2 will be described. During a latch-up test, a current flows through the parasitic NPN, causing VREF to rise, and VREG to also rise.

[0047] At this time, when the overvoltage detection circuit VDET detects an overvoltage, the potential of the overvoltage signal S changes from low to high, and the signal is inverted by the inverter INV, causing its potential to go low, which changes the P-type transistor P5 from off to on.

[0048] When P-type transistor P5 turns on, the potential of the gate of P-type transistor P4 becomes high, causing P-type transistor P4 to change from on to off. Therefore, the current flowing through P-type transistor P4 decreases, reducing the base current of transistor NPN1 and the current flowing between the collector and emitter of transistor NPN1. This suppresses the rise in the emitter voltage of transistor NPN1, i.e., VREG.

[0049] In this way, in the integrated circuit 200-2, by detecting an overvoltage of VREG and turning on the P-type transistor P5, the P-type transistor P4 is turned off, that is, the current output by the P-type transistor P4 is stopped, thereby suppressing the rise in VREG and suppressing the destruction of the low-voltage circuit LVC during the latch-up test.

[0050] In the integrated circuit 200-2, even when a parasitic NPN operates in the circuit inside the operational amplifier and VREG rises, VREG can be lowered to prevent breakdown of the low-voltage circuit LVC.

[0051] In addition, the following supplementary notes are provided in relation to the above description.

[0052] (Appendix 1) An integrated circuit including a regulator circuit that generates a specific output voltage based on a reference voltage generated by a reference voltage circuit, an overvoltage detection circuit that determines whether the output voltage is in an overvoltage state and outputs an overvoltage signal indicating that the output voltage is in an overvoltage state; a switch that suppresses an increase in the output voltage of the regulator circuit when the overvoltage signal is output; 1. An integrated circuit comprising a regulator circuit, comprising: (Appendix 2) a threshold value for making the determination is set in the overvoltage detection circuit; an integrated circuit including the regulator circuit according to claim 1, wherein the threshold is set to a voltage that is greater than a maximum value of the output voltage when the regulator circuit is operating and lower than a voltage value that may destroy a circuit that is driven by the output voltage. (Appendix 3) 2. An integrated circuit comprising the regulator circuit according to claim 1, wherein the switch stops operation of a current mirror included in the reference voltage circuit when the overvoltage detection circuit outputs the overvoltage signal. (Appendix 4) 2. An integrated circuit comprising the regulator circuit according to claim 1, wherein the switch stops the current output by the regulator circuit when the overvoltage detection circuit outputs the overvoltage signal. (Appendix 5) a transistor that is turned on when the regulator circuit is outputting a current, thereby increasing the output voltage, and that is turned off when the regulator circuit is not outputting the current, thereby suppressing the increase in the output voltage; 2. An integrated circuit including the regulator circuit according to claim 1, wherein the switch stops the output of the current from the regulator circuit to the transistor when the overvoltage detection circuit outputs the overvoltage signal. [Explanation of symbols]

[0053] 10 Reference voltage circuit 11 Current mirror circuit 12 Constant current source 100 Regulator circuit 100A regulator circuit 100-1 Regulator circuit 100-2 Regulator circuit 200 Integrated Circuits 200A Integrated Circuit 200-1 Integrated Circuits 200-2 Integrated Circuits AMP INV Inverter LVC Low Voltage Circuit N1 N-type transistor NPN1 transistor P1 P-type transistor P2 P-type transistor P3 P-type transistor P4 P-type transistor P5 P-type transistor R1 Resistor S Overvoltage signal SC voltage divider circuit T1 terminal T2 terminal T3 terminal T4 terminal VDD external power supply VDET Overvoltage detection circuit VREF Reference voltage VREG Regulator output voltage

Claims

1. An integrated circuit including a regulator circuit that generates a specific output voltage based on a reference voltage generated by a reference voltage circuit, an overvoltage detection circuit that determines whether the output voltage is in an overvoltage state and outputs an overvoltage signal indicating that the output voltage is in an overvoltage state; a switch that suppresses an increase in the output voltage of the regulator circuit when the overvoltage signal is output; 1. An integrated circuit comprising a regulator circuit, comprising:

2. a threshold value for making the determination is set in the overvoltage detection circuit; 2. The integrated circuit including the regulator circuit according to claim 1, wherein the threshold value is set to a voltage that is greater than a maximum value of the output voltage when the regulator circuit is operating and lower than a voltage value that may destroy a circuit that is driven by the output voltage.

3. 2. The integrated circuit including a regulator circuit according to claim 1, wherein the switch stops operation of a current mirror included in the reference voltage circuit when the overvoltage detection circuit outputs the overvoltage signal.

4. 2. The integrated circuit including the regulator circuit according to claim 1, wherein the switch stops the current output by the regulator circuit when the overvoltage detection circuit outputs the overvoltage signal.

5. a transistor that is turned on when the regulator circuit is outputting a current, thereby increasing the output voltage, and that is turned off when the regulator circuit is not outputting the current, thereby suppressing the increase in the output voltage; 2. The integrated circuit including the regulator circuit according to claim 1, wherein the switch stops the output of the current from the regulator circuit to the transistor when the overvoltage detection circuit outputs the overvoltage signal.

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