Verification device and verification method

Abstract

To provide a verification device and a verification method with which, for a semiconductor device equipped with a first chip and a second chip, it is possible to perform verification regarding a function unit included in the first chip without having to use the second chip.SOLUTION: Provided is a verification device used for verification of a semiconductor device equipped with a processor, a first chip including at least one first function unit controlled by the processor, and a second chip including at least one second function unit controlled by the processor. The verification device comprises: a connection unit electrically connected to the first chip; at least one third function unit which is of the same type as the first function unit and is controlled by the processor; and a first output terminal for outputting the verification result data forwarded from the third function unit to the outside.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a verification device and a verification method. [Background technology]

[0002] Various tests and verifications are performed on semiconductor devices having multiple chips. For example, Patent Document 1 describes a technology for performing a functional test to identify the functional capabilities of components and circuits mounted for each function in a manufacturing method for a three-dimensional integrated circuit in which a first component substrate and a second component substrate are stacked. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 8-213548 Summary of the Invention [Problem to be solved by the invention]

[0004] In the conventional technology in which multiple chips are electrically connected and functional units provided on each chip are verified, it is difficult to verify each functional unit until each chip is manufactured. For example, in a semiconductor device including a first chip and a second chip, it is sometimes impossible to verify the functional unit provided on the first chip without using the second chip.

[0005] The present disclosure aims to provide a verification device and a verification method for a semiconductor device having a first chip and a second chip, which can verify the functional units provided in the first chip without using the second chip. [Means for solving the problem]

[0006] In order to achieve the above-mentioned object, the verification device of the present disclosure is a verification device used to verify a semiconductor device having a processor, a first chip having at least one first functional unit controlled by the processor, and a second chip having at least one second functional unit controlled by the processor, and is equipped with a connection unit electrically connected to the first chip, at least one third functional unit of the same type as the first functional unit and controlled by the processor, and a first output terminal that outputs verification result data output from the third functional unit to the outside.

[0007] In order to achieve the above-mentioned object, the verification method of the present disclosure is a verification method for verifying a semiconductor device including a processor, a first chip having at least one first functional unit controlled by the processor, and a second chip having at least one second functional unit controlled by the processor, using a verification device including a connection unit electrically connected to the first chip, at least one third functional unit of the same type as the first functional unit and controlled by the processor, and an output terminal for outputting verification result data output from the third functional unit to the outside, wherein the processor operates the third functional unit of the same type as the first functional unit in place of the first functional unit, and outputs the verification result data output from the third functional unit to the outside via the output terminal. [Effects of the Invention]

[0008] According to the present disclosure, for a semiconductor device including a first chip and a second chip, it is possible to verify the functional unit provided in the first chip without using the second chip. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a circuit diagram showing an example of a configuration of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of the inspection die according to the first embodiment. [Figure 3]FIG. 10 is a circuit diagram illustrating an example of the configuration of an inspection die according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the following embodiments do not limit the technology of the present disclosure.

[0011] [First embodiment] 1 shows a circuit diagram illustrating an example of the configuration of a semiconductor memory device 10 to be inspected in this embodiment. The semiconductor device 10 of this embodiment includes two dies: a die 1_D1 and a die 2_D2.

[0012] The die 1_D1 includes a CPU 20, a bus control circuit 22, and IPs 30_1 and 30_2 controlled by the CPU 20.

[0013] Furthermore, die 2_D2 includes IPs 52_1 and 52_2 controlled by the CPU 20. As an example, the semiconductor device 10 of this embodiment is a so-called three-dimensional semiconductor device in which die 1_D1 and die 2_D2 are stacked. Note that, for convenience of illustration, in FIG. 1, die 1_D1 and die 2_D2 are shown side by side, not stacked. Die 1_D1 of this embodiment is an example of a first chip of the present disclosure, and die 1_D2 of this embodiment is an example of a second chip of the present disclosure.

[0014] The configuration of die 1_D1 will be further explained. The CPU (Central Processing Unit) 20 operates in response to a system clock and a system reset input via the die 2_D2 and the connection part 49_3, and has a function of controlling the entire semiconductor device 10. As described above, the CPU 20 has a function of controlling the IPs 30_1 and 30_2 and the IPs 52_1 and 52_2 provided on the die 2_D2. The CPU 20 of this embodiment is an example of a processor of the present disclosure.

[0015] IP30_1 and IP30_2 are intellectual property (IP) cores that perform various functions. As an example, IP30_1 and IP30_2 in this embodiment are different types. IP30_1 is an IP of type "DIE1_IP_00," and IP30_2 is an IP of type "DIE_IP_02." In this embodiment, the "type" refers to a type classified at least by function, and also refers to at least one of types classified by product type and lot number. The specific "type" can be determined based on the verification content and the functions of the semiconductor device 10. Here, when IP30_1 and IP30_2 are referred to collectively without distinguishing between them, the distinguishing reference numerals are omitted and they are referred to as "IP30." That is, IP30 refers to an IP provided on die 1_D1. Data output from IP30 is output to die 2_D2 via connection 49_2. The IP 30_1 and IP 30_2 of this embodiment are an example of a first functional unit of the present disclosure.

[0016] The bus control circuit 22 outputs control information for IPs controlled by the CPU 20 and acquires execution results executed by each IP. The bus control circuit 22 and IP30 are connected by a control bus D1dc and a data bus D1db. The control bus D1dc is a bus for communicating address mapping information, write and read information, etc. as control signals for IP30. The data bus D1db is a bus for transmitting and receiving data for reading and writing special function registers (SFRs) held by IP30. The bus control circuit 22 and IP50 are connected by a control bus D2dc and a data bus D2db. The control bus D2dc is a bus for communicating address mapping information, write and read information, etc. as control signals for IP52. The data bus D2db is a bus for transmitting and receiving data for reading and writing special function registers held by IP52.

[0017] The configuration of die 2_D2 will be further described. IP52_1 and IP52_2 are IPs that perform various functions similar to IP30 and are so-called IP cores. As an example, IP52_1 and IP52_2 in this embodiment are different types. IP52_1 is an IP of the type "DIE2_IP_01," and IP52_2 is an IP of the type "DIE2_IP_02." Note that, when IP52_1 and IP52_2 are referred to collectively without distinguishing between them, the distinguishing reference numerals are omitted and they are referred to as "IP52." In other words, IP52 refers to an IP provided on die 2_D2. Data output from IP52 is output to the signal switching circuit 54. Note that IP52_1 and IP52_2 in this embodiment are an example of a first functional unit of the present disclosure.

[0018] The signal switching circuit 54 has a function of connecting the IPs 52 and 30 to the terminal 56 in accordance with the control of the terminal control register 50. The terminal control register 50 is connected to the bus control circuit 22 of the die 1_D1 via the connection part 49_1, and controls the function of the terminal 56.

[0019] Furthermore, the die 2_D2 includes, for example, h terminals 56 (56_1 to 56_h) and terminals 58 (58_1, 58_2). The terminals 56 are terminals for transmitting and receiving various data to and from external devices. The terminals 58 are terminals through which various data and information related to verification are input from external devices.

[0020] Next, verification of the semiconductor device 10 of this embodiment will be described. First, the verification of the IP30 of the die 1_D1 will be described. Fig. 2 shows a circuit diagram illustrating an example of the configuration of the inspection die Dt used to verify the IP30 of the die 1_D1.

[0021] The inspection die Dt is provided with, as the IP 68, an IP of the same type as the IP 30, and an IP of a type that can be provided on the die 1_D1 as the IP 30. The inspection die Dt is a verification device for verifying the operation of the type of IP provided on the die 1_D1 by outputting verification result data output from the IP 68, which operates under the control of the CPU 20, to an external device.

[0022] The die 1_D1 and the inspection die Dt are electrically connected by a connection portion 79_1 and a connection portion 79_2. The connection portion 79_1 and the connection portion 79_2 are interfaces for connecting the die 1_D1 and the inspection die Dt. The inspection die Dt is connected by the connection portion 79_1 and the connection portion 79_2 when verifying the IP30 of the die 1_D1, and is detached from the die 1_D1 after the verification.

[0023] The test die Dt includes a test circuit 60, an IP validating logic circuit 66, an IP 68, a signal switching circuit 70, terminals 72 (72_1 to 72_k), and terminals 78 (78_1, 78_2).

[0024] IP68_1 to IP68_n are types of IPs that can be provided on the die 1_D1. IP68_1 is the same type of IP as IP30_1, and IP68_3 is the same type of IP as IP30_2. IP68_1 and IP68_2 are examples of a third functional unit of the present disclosure. Other IP68s such as IP68_2 and IP68_n are IPs that can be provided on the die 1_D1 and may be provided in the future. These other IP68s are examples of a fourth functional unit of the present disclosure. Note that here, when IP68_1 to IP68_n are referred to collectively without distinguishing between them, the reference numerals that distinguish them are omitted and they are referred to as "IP68."

[0025] The test circuit 60 includes IP valid / invalid signal selection logic 62, product type selection logic 63, and test mode discrimination circuit 64. The test mode discrimination circuit 64 has a plurality of test modes depending on which of the IPs, IP 30 or IP 52, is to be verified, and the test mode discrimination circuit 64 determines which test to perform from the plurality of test modes. When the test mode is the test mode for verifying IP 30, the data input from terminal 78_1 is output to the product type selection logic 63.

[0026] The product type selection logic 63 selects the type of IP68 to be verified based on the data input from the test mode discrimination circuit 64. The product type selection logic 63 shown in Figures 1 and 2 is a logic circuit that selects one of IP68_1 to IP68_n. The product type selection logic 63 outputs information indicating the selected type of IP68 to the IP valid / invalid signal selection logic 62.

[0027] The IP valid / invalid signal selection logic 62 is a circuit that outputs a valid signal to the IP 68 to be verified to make it valid, and outputs an invalid signal to make it invalid to other IP 68.

[0028] The IP validity logic circuit 66 is a logic circuit for validating the IP 68 to be inspected, and includes AND circuits 67 (67_1 to 67_n) corresponding to the IP 68. A signal is input to the AND circuit 67 from the die 1_D1 via the connection part 79_1 and the control bus D1cb. When performing verification on the IP 30, the signal input to the AND circuit 67 from the die 1_D1 becomes "1". Also, the signal input from the IP valid / invalid signal selection logic 62 to the AND circuit 67 corresponding to the IP 68 to be inspected becomes "1". Therefore, the signal output from the AND circuit 67 becomes "1", and the IP 68 to be inspected operates under the control of the CPU 20 of the die 1_D1.

[0029] On the other hand, the signal input from the IP valid / invalid signal selection logic 62 to the AND circuit 67 corresponding to the IP 68 other than the inspection target is "0." Therefore, the signal output from the AND circuit 67 is "0," and the IP 68 other than the inspection target does not operate.

[0030] The signal switching circuit 70 has a function of connecting the IP 68 and the terminal 72. The signal switching circuit 70 corresponding to the IP 68 to be verified connects the terminal 72 corresponding to the IP 68 to be verified with the IP 68 to be verified, inputs data used for verification to the IP 68 to be verified from the terminal 72, and outputs verification result data output from the IP 68 from the terminal 72. Note that the terminal 72 of this embodiment is an example of the first output terminal and second output terminal of the present disclosure.

[0031] As described above, verification is performed based on the operational results of the IP68 of the inspection die Dt instead of the IP30 of the die 1_D1, so the IP30 of the die 1_D1 does not need to be operated.

[0032] Thus, die 1_D1 includes multiplexer 24, ROM 28, test circuitry 40, and IP invalidation logic circuitry 46, as shown in FIGS.

[0033] The test circuit 40 includes an IP enable / disable signal selection logic 42, a product type selection logic 43, and a test mode discrimination circuit 44, and is the same circuit as the test circuit 60. That is, the IP enable / disable signal selection logic 42 is the same as the IP enable / disable signal selection logic 62, the product type selection logic 43 is the same as the product type selection logic 63, and the test mode discrimination circuit 44 is the same as the test mode discrimination circuit 64.

[0034] The IP invalidation logic circuit 46 is a logic circuit for invalidating the IP 30, and includes AND circuits 47 (47_1, 47_2) corresponding to the IP 30. A signal is input to the AND circuit 47 via the control bus D1cb. When verifying the IP 30, the signal input to the AND circuit 47 via the control bus D1cb becomes "1." Meanwhile, the signal output from the IP valid / invalidation signal selection logic 62 becomes "1," but the signal input to the AND circuit 67 is the inverse of the signal output from the IP valid / invalidation signal selection logic 62, so the signal input to the AND circuit 67 becomes "0." Therefore, the IP 30 being inspected is invalidated and does not operate. In addition, IPs 30 other than the inspected IPs are also invalidated and do not operate.

[0035] Furthermore, based on the information input to the ROM 28 via the terminal 78_1 and the connection part 79_2 of the test die Dt, the ROM 28 outputs to the multiplexer 24 information required to test the IP 30 under test.

[0036] The ROM 26 stores normal programs for operating the IP 30 of the die 1_D1 and the IP 52 of the die 2_D2. On the other hand, the ROM 28 stores a verification program. When verifying the IP 30 based on a control signal input from the test mode determination circuit 44, the multiplexer 24 outputs information corresponding to the IP 30 to be verified to the CPU 20. The CPU 20 controls the verification of the IP 30 based on the information input from the multiplexer 24.

[0037] In this way, when the IP 30 of the die 1_D1 is to be verified, verification data corresponding to the IP 30 to be inspected is input from the terminal 72 and input to the IP 68 corresponding to the IP 30 to be inspected.

[0038] Furthermore, based on the information input from the terminal 78_1, the test circuit 40 of the die 1_D1 operates to disable the IP 30, thereby preventing the IP 30 of the die 1_D1 from operating.

[0039] Meanwhile, based on the information input from the terminal 78_1, the test circuit 60 of the inspection die Dt operates to enable only the IP 68 corresponding to the IP 3074 to be inspected and operate that IP 68. The verification result data output from the IP 68 to be inspected is output from the terminal 72 to an external device.

[0040] The external device compares the expected value with the verification result data to verify whether the IP68 is functioning properly and presents the verification result.

[0041] In this way, by using the inspection die Dt of this embodiment, it is possible to verify the operation of the IP30 by operating an IP68 of the same type as the IP30 to be verified, which is provided on the inspection die Dt, instead of the IP30 to be verified.

[0042] In this embodiment, since die 1_D1 is equipped with a test circuit 40, when die 1_D1 and die 2_D2 are connected to form semiconductor device 10 (Figure 1), IP30 can be verified using test circuit 40.

[0043] In the present embodiment, the inspection die Dt is described as having the same type of IP as the IP 30 of the die 1_D1 and the IP 68 as the type of IP that can be provided on the die 1_D1 as the IP 30, but is not limited to this embodiment. For example, the inspection die Dt may be provided with at least one of the same type of IP as the IP 30 of the die 1_D1 and the type of IP that can be provided on the die 1_D1 as the IP 30.

[0044] [Second embodiment] In the first embodiment, the IP30 of the die 1_D1 is verified by the inspection die Dt, but the IP52 of the die 2_D2 may also be verified by the inspection die Dt. Fig. 3 shows a circuit diagram illustrating an example of the configuration of the inspection die Dt that can also verify the IP52 of the die 2_D2.

[0045] 3 differs from the inspection die Dt of the first embodiment in that it further includes a terminal control register 80, IPs 82_1 and 82_2, and is further connected to the die 1_D1 by a connection portion 79_1.

[0046] The IP82_1 is the same type of IP as the IP52_1 of the die 2_D2, and the IP82_2 is the same type of IP as the IP52_2 of the die 2_D2. The IP82_1 and IP82_2 are examples of a fifth functional unit of the present disclosure.

[0047] In this way, by providing the same type of IP 68 as the IP 52 of the die 2_D2, the IP 82 can be operated instead of the IP 52, and the verification result data output from the IP 82 can be output from the corresponding terminal 84 among the terminals 84_1 to 84_r connected by the signal switching circuit 83, thereby making it possible to verify the IP 52 in the same way as the IP 30 described above in the first embodiment. Note that the terminal 84 in this embodiment is an example of the third output terminal and the fourth output terminal of the present disclosure.

[0048] In addition, in the verification of the IP 52 of the die 2_D2, similarly to the first embodiment, by providing the inspection die Dt with IPs of a type that can be provided in the IP 52 as IP 82, the verification of these IPs can also be performed. In this case, the IP 82 other than the IP 82_1 and the IP 82_2 is an example of a sixth functional unit of the present disclosure.

[0049] As described above, the inspection die Dt of the first and second embodiments allows verification of the IP 30 provided on the die 1_D1 of a semiconductor device 10 including the die 1_D1 and the die 2_D2 without using the die 2_D2. For example, if the die 2_D2 is not connected to the die 1_D1, the potential of the connection 49_2 connecting the two is not determined. Therefore, it may be impossible to directly input test data and output verification result data to the bonding surface of the die 1_D1 alone. In contrast, in this embodiment, connecting the inspection die Dt to the die 1_D1 determines the potential of the connection 79_1, etc., allowing appropriate acquisition of verification result data. Therefore, the inspection die Dt of the first and second embodiments allows verification of the IP 30 of the die 1_D1, for example, even before the die 2_D2 is manufactured.

[0050] The following additional notes are provided regarding the above-described embodiments. (Appendix 1) A verification device used to verify a semiconductor device including a processor, a first chip provided with at least one first functional unit controlled by the processor, and a second chip provided with at least one second functional unit controlled by the processor, a connection part electrically connected to the first chip; at least one third functional unit of the same type as the first functional unit and controlled by the processor; a first output terminal for outputting the verification result data output from the third functional unit to an external device; A verification device comprising:

[0051] (Appendix 2) a fourth functional unit that can be provided in the first chip and that is controlled by the processor; a second output terminal for outputting the verification result data output from the fourth functional unit to an external device; Further equipped 10. The verification device of claim 1.

[0052] (Appendix 3) at least one fifth functional unit of the same type as the second functional unit and controlled by the processor; a third output terminal for outputting the verification result data output from the fifth functional unit to an external device; 3. The verification device according to claim 1 or 2, further comprising:

[0053] (Appendix 4) a sixth functional unit that can be provided in the second chip and that is controlled by the processor; a fourth output terminal for outputting the verification result data output from the sixth functional unit to an external device; Further equipped 10. A verification device as described in Appendix 3.

[0054] (Appendix 5) A verification method for verifying a semiconductor device including a processor, a first chip provided with at least one first functional unit controlled by the processor, and a second chip provided with at least one second functional unit controlled by the processor, by using a verification device including a connection unit electrically connected to the first chip, at least one third functional unit of the same type as the first functional unit and controlled by the processor, and an output terminal for outputting verification result data output from the third functional unit to an external device, the method comprising: causing the processor to operate the third functional unit, which is the same type as the first functional unit, in place of the first functional unit; The verification result data output from the third functional unit is output to the outside via the output terminal. Verification method. [Explanation of symbols]

[0055] 10 Semiconductor devices 30_1, 30_2, 52_1, 52_2, 68_1~68_n IP 49_1, 49_2, 49_3 connection parts 56_1~56_h terminal D1 Die 1, D2 Die 2 Dt Inspection Die

Claims

1. A verification device used to verify a semiconductor device including a first chip provided with a processor and at least one first functional unit controlled by the processor, and a second chip provided with at least one second functional unit controlled by the processor, a connection portion electrically connected to the first chip; at least one third functional unit of the same type as the first functional unit and controlled by the processor; a first output terminal for outputting the verification result data output from the third functional unit to an external device; A verification device comprising:

2. a fourth functional unit that can be provided on the first chip and that is controlled by the processor; a second output terminal for outputting the verification result data output from the fourth functional unit to an external device; Further equipped The verification device according to claim 1 .

3. at least one fifth functional unit of the same type as the second functional unit and controlled by the processor; a third output terminal for outputting the verification result data output from the fifth functional unit to an external device; The verification device of claim 1 further comprising:

4. a sixth functional unit that can be provided on the second chip and that is controlled by the processor; a fourth output terminal for outputting the verification result data output from the sixth functional unit to an external device; Further equipped The verification device according to claim 3 .

5. A verification method for verifying a semiconductor device including a processor, a first chip provided with at least one first functional unit controlled by the processor, and a second chip provided with at least one second functional unit controlled by the processor, by using a verification device including a connection unit electrically connected to the first chip, at least one third functional unit of the same type as the first functional unit and controlled by the processor, and an output terminal for outputting verification result data output from the third functional unit to an external device, the method comprising: causing the processor to operate the third functional unit, which is the same type as the first functional unit, in place of the first functional unit; The verification result data output from the third functional unit is output to the outside via the output terminal. Verification method.

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