Semiconductor device, processing method, control program, and recording medium

Abstract

To suppress an increase in computation time in a semiconductor device while further improving resistance to side-channel attacks.SOLUTION: A semiconductor device (1) according to one embodiment of the present invention includes: a dividing unit (10) for dividing data into at least two pieces of divided data; a block cipher execution unit (10) for applying a specific process included in a block cipher algorithm only to at least one of the pieces of divided data among the at least two pieces of divided data; and a data holding unit (11) for holding, in each block, the pieces of divided data to which the process has been applied only to a part thereof, the data holding unit (11) being configured such that side-channel information radiated differs at least partially among the blocks.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, a processing method, a control program, and a recording medium. [Background technology]

[0002] The threat of side-channel attacks, which analyze side-channel information such as power changes that occur when data is stored in a computer register to obtain secret key (shared key) information used in AES (Advanced Encryption Standard) and other encryption algorithms, is increasing. Specific side-channel attack methods include power analysis attacks, which infer confidential information by analyzing changes in power consumption, and electromagnetic field analysis attacks, which infer confidential information by analyzing changes in the electromagnetic field radiated from a target device. One countermeasure against side-channel attacks is masking, which uses random numbers or other methods to convert data being processed into a different value and reduce the correlation between intermediate values ​​of encryption and side-channel information. Patent Document 1 discloses a cryptographic processing device that simultaneously processes random numbers and regular data and can conceal the power consumption of processing the regular data by using the power consumption of the random numbers. Patent Document 2 discloses an encryption device that is secure against side-channel attacks without increasing the circuit size. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-115579 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-175039 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the above-mentioned conventional techniques, when masking is applied to AES, there is a problem that pre-processing is required, which increases the calculation time. Furthermore, in the invention described in Patent Document 1, for example, when plaintext is encrypted using the same encryption key, there is a problem that it is possible to extract only the legitimate data by analyzing the average value of the power consumption waveform and removing the random number component. Furthermore, in the invention described in Patent Document 2, although the increase in calculation time is relatively suppressed, there is still room for improvement in tamper resistance.

[0005] One aspect of the present invention has been made in view of the above problems, and aims to further improve tamper resistance against side channel attacks while suppressing an increase in the calculation time in a semiconductor device. [Means for solving the problem]

[0006] In order to solve the above problem, a semiconductor device according to one embodiment of the present invention includes a division unit that divides data into two or more divided data pieces, a block cipher execution unit that applies a specific process included in a block cipher algorithm to only one or more of the divided data pieces, and a data storage unit that stores the divided data pieces to which the process has been applied in each block, wherein radiated side channel information differs from one another between at least some of the blocks.

[0007] In order to solve the above problem, a processing method according to one embodiment of the present invention is a data processing method executed by an apparatus, and includes: a division step of dividing the data into two or more divided data; a block cipher execution step of applying a specific process included in a block cipher algorithm to only one or more partial divided data of the two or more divided data; and a data storage step of storing the divided data to which the process has been applied in only a portion in each block, wherein radiated side channel information differs from one another between at least some of the blocks. [Effects of the Invention]

[0008] According to one aspect of the present invention, it is possible to further improve tamper resistance against side channel attacks while suppressing an increase in the calculation time in a semiconductor device. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is an example of a block diagram illustrating a functional configuration of a computer including a semiconductor device. [Figure 2] 1 is an example of a flowchart showing a processing flow of a semiconductor device. [Figure 3] 1 is an example of a data diagram showing processing on data in a register. [Figure 4] 10 is a table showing an example of the relationship between a clock and an intermediate value d, and a table showing an example of the relationship between a first clock and a subsequent second clock and a Hamming distance. [Figure 5] 1 is an example of a flowchart showing a processing flow of a semiconductor device. [Figure 6] 10 is a table showing an example of the correspondence between each 8 bits of input data, each 2 bits of random numbers, and divided data into which each 8 bits of input data is allocated. [Figure 7] 10 is a table showing an example of the correspondence between a 32-bit random number to which ShiftRows processing has been applied, divided data to which each 2 bits of the random number corresponds, and a first divided data. [Figure 8] 1 is an example of a data diagram showing processing on data in a register. DETAILED DESCRIPTION OF THE INVENTION

[0010] [Embodiment 1] Hereinafter, one embodiment of the present invention will be described in detail.

[0011] 1. Configuration of the Semiconductor Device 1 is an example of a block diagram showing a functional configuration of a computer 100 including a semiconductor device 1 according to the present disclosure. The computer 100 includes the semiconductor device 1 and a memory 2 that temporarily or non-temporarily stores data.

[0012] The semiconductor device 1 is a device realized as a CPU (Central Processing Unit), GPU (Graphics Processing Unit), DSP (Digital Signal Processor), MPU (Micro Processing Unit), FPU (Floating point number Processing Unit), PU (Physics Processing Unit), microcontroller, or a combination thereof, and is equipped with a control circuit 10 and a register 11.

[0013] The control circuit 10 is a circuit that executes various operations in synchronization with a clock signal, and also functions as a division unit 10 that executes the division means, and a block cipher execution unit 10 that executes the block cipher execution means. Alternatively, the control circuit 10 may include the division unit 10 and the block cipher execution unit 10. Furthermore, the control circuit 10 may operate according to a program obtained from the memory 2 each time.

[0014] The dividing unit 10 divides the data to be processed into two or more divided data pieces. For example, the dividing unit 10 divides 128-bit data pieces into two 64-bit divided data pieces.

[0015] The block cipher execution unit 10 applies a block cipher algorithm to data to be processed. For example, the block cipher execution unit 10 applies a specific process included in the block cipher algorithm to only one or more pieces of divided data out of two or more pieces of divided data. The AddRoundKey process in this embodiment is an example of the specific process included in the block cipher algorithm.

[0016] In this disclosure, the block cipher algorithm will be described using the Advanced Encryption Standard (AES) as an example, but the present invention is not limited to this and other block cipher algorithms may also be used.

[0017] In the AES processing executed by the block cipher execution unit 10, a SubBytes processing, a ShiftRows processing, a MixColumns processing, and an AddRoundKey processing are repeatedly performed. The SubBytes processing is a processing to convert data into a predetermined value for each byte. There is a one-to-one correspondence between the value of one byte before conversion and the value of one byte after conversion. The ShiftRows processing is a processing to arrange the values ​​of each byte in multiple columns to form an array, and to shift each row in the column direction by a different number of columns. The MixColumns processing is a processing to convert values ​​by multiplying an array having values ​​of each byte by a constant matrix from the left. The AddRoundKey processing is a processing to perform an XOR (exclusive OR) operation on the bit string of the round key corresponding to the round number and the bit string of the data for each round, i.e., each time the AddRoundKey processing is performed.

[0018] The block cipher execution unit 10 is capable of collectively executing a plurality of processes, such as the SubBytes process included in the AES process, by using, for example, a matrix operation.

[0019] In many existing semiconductor devices, AES processing involves first performing an AddRoundKey operation once, followed by a SubBytes operation, a ShiftRows operation, a MixColumns operation, and an AddRoundKey operation repeated a predetermined number of times. Subsequently, the SubBytes operation, the ShiftRows operation, and the AddRoundKey operation are each performed once. The predetermined number of times corresponds to the key length of the round key used in the AddRoundKey operation, and is also referred to as the number of rounds, including the number of times for the first AddRoundKey operation. For example, if the key length of the round key is 128 bits, the predetermined number of times is 9, and the number of rounds is 10.

[0020] The register 11 is a storage element that temporarily stores various information, and also functions as a data holding unit 11 that executes data holding means. Alternatively, the register 11 may be equipped with the data holding unit 11.

[0021] The data storage unit 11 stores, in each block, the divided data to which a specific process included in the block cipher algorithm, such as AddRoundKey processing, has been applied to only some of the divided data. From another perspective, the blocks refer to storage areas of the register 11 that are conveniently divided into sections for each divided data to be stored.

[0022] 2. Processing of Semiconductor Devices Next, a description will be given of the flow of processing executed by the semiconductor device 1. In this embodiment, a case will be described in which the control circuit 10 divides data into two divided data. Fig. 2 is an example of a flowchart showing the flow of processing executed by the semiconductor device 1 according to this embodiment.

[0023] In S101 (step S101), the control circuit 10 acquires input data to be subjected to AES processing and stores it in the register 11. Hereinafter, an example will be described in which the input data is a 128-bit value "A0A1A2A3A4A5A6A7A8A9AAABACADAEAF".

[0024] In S102, the control circuit (division unit) 10 divides the data in the register 11 into two divided data pieces: first divided data piece and second divided data piece. The first divided data piece is stored in a first block of the register 11, and the second divided data piece is stored in a second block of the register 11. As an example, the control circuit 10 divides a 128-bit value "A0A1A2A3A4A5A6A7A8A9AAABACADAEAF" into a 64-bit first divided data piece "A0A1A2A3A4A5A6A7" and a 64-bit second divided data piece "A8A9AAABACADAEAF." As described above, the AddRoundKey process is an XOR operation between bit strings, so the division positions of the data are not limited, and it is not necessary to divide the data at a position that is a multiple of 8 bits (1 byte).

[0025] In S103, the control circuit (block cipher execution unit) 10 applies the AddRoundKey process to only the first data segment. For example, if the first round key is a 64-bit value "FFFFFFFFFFFFFFFF," the control circuit 10 applies the AddRoundKey process only to the first data segment "A0A1A2A3A4A5A6A7" to convert it to the value "5F5E5D5C5B5A5958." In other words, the control circuit 10 updates the value in the first block of the register 11 from "A0A1A2A3A4A5A6A7" to "5F5E5D5C5B5A5958." Note that, because the second data segment has not been converted at the time of S103, the value "A8A9AAABACADAEAF" is stored in the second block. As a result, in S103, the data holding means for holding, in each block, the divided data to which the AddRoundKey process has only been applied, is executed by the register (data holding unit) 11. That is, divided data to which different processes have been applied is stored in each block of the register 11. Therefore, in the data holding means, the side channel information radiated differs from one block to another, resulting in high tamper resistance.

[0026] Here, the aforementioned side-channel information refers to information such as power consumption that occurs during operation of the control circuit 10 and the register 11 and can be observed from the outside, and refers to information corresponding to the processing content of the control circuit 10 and the register 11. Therefore, if the processing content differs for each divided data, the side-channel information radiated from each block will differ from one another.

[0027] In S104, the control circuit 10 (block cipher execution unit 10) applies the AddRoundKey process to only the second divided data. For example, the control circuit 10 applies the AddRoundKey process to only the second divided data "A8A9AAABACADAEAF" to convert it to a value "5756555453525150." In other words, the control circuit 10 updates the value on the second block of the register 11 from "A8A9AAABACADAEAF" to "5756555453525150." The AddRoundKey process in S104 uses the same round key as in S103.

[0028] In S105, the control circuit 10 combines the first and second divided data. For example, the control circuit 10 combines the 64-bit first divided data "5F5E5D5C5B5A5958" with the 64-bit second divided data "5756555453525150" to obtain a 128-bit value "5F5E5D5C5B5A59585756555453525150." The control circuit 10 combines the divided data to enable MixColumns processing in a later step. From another perspective, the SubBytes, ShiftRows, and AddRoundKey operations can be performed even when the data is divided, but the MixColumns operation requires that the data be undivided.

[0029] 3 is an example of a data diagram showing the above-mentioned processing from S101 to S105 on the data in the register 11. The registers 11a to 11e in FIG. 3 correspond to the register 11 in each step of S101 to S105, respectively.

[0030] In S106, the control circuit 10 executes SubBytes processing, ShiftRows processing, and MixColumns processing on the combined data. Note that the processing from S106 to S110 is repeatedly executed (number of rounds-1) times.

[0031] In S107, the control circuit 10 performs the same process as in S102, and divides the data in the register 11 into first divided data in the first block and second divided data in the second block.

[0032] In S108, the control circuit 10 performs the same process as in S103, applying the AddRoundKey process to only the first divided data. In the AddRoundKey process, a round key corresponding to the number of rounds is used, and this also applies to the following description. In S108, the register 11 also functions as a data holding means for holding, in each block, the divided data to which the AddRoundKey process has only been applied.

[0033] In S109, the control circuit 10 performs the same process as in S104, and applies the AddRoundKey process to only the second divided data. In the AddRoundKey process in S109, the same round key as in S108 is used.

[0034] In S110, the control circuit 10 performs the same process as in S105 to combine the first divided data and the second divided data.

[0035] In S111, the control circuit 10 determines whether the processes from S106 to S110 have been executed a specified number of times (number of rounds - 1). If the control circuit 10 determines that the processes from S106 to S110 have been executed a specified number of times (S111: YES), then in S112, the control circuit 10 executes SubBytes processing, ShiftRows processing, and AddRoundKey processing on the data in register 11 to update the data. The updated data in register 11 is used for other subsequent processing as output data after AES processing. On the other hand, if the control circuit 10 determines that the processes from S106 to S110 have not been executed the specified number of times (S111: NO), it repeats the processes from S106.

[0036] The data processing method executed by the semiconductor device 1 has been described above, including the division steps (S102 and S107), the block cipher execution steps (S103, S104, S108 and S109) and the data storage steps (S103 and S108).

[0037] According to the processing of this embodiment, it is possible to further improve tamper resistance against side channel attacks while suppressing an increase in the calculation time in the semiconductor device without performing pre-processing such as masking.

[0038] The processing of this embodiment and the processing described in the second embodiment below can be applied to cases where the semiconductor device encrypts data, and can also be applied to cases where the semiconductor device decrypts data.

[0039] [3. Effects of the semiconductor device] Next, the effects of the semiconductor device 1 according to the present disclosure will be supplemented. Table 30 in Fig. 4 shows an example of the relationship between the clock (signal) that synchronizes the control circuit 10 and the intermediate value d held by the register 11 in the AES processing at each clock stage.

[0040] In Figure 4, m represents plaintext data or divided data obtained by dividing the plaintext data. S(x) represents the result of applying SubBytes processing and ShiftRows processing to data x in that order, and M(x) represents the result of applying MixColumns processing to data x. A function with -1 in the upper right corner represents the inverse transformation of the transformation by the original function. c and C represent output data to which AES processing has been applied, and kn represents the round key used in the nth round.

[0041] Also, "+" means an XOR operation between bit strings. For example, "m+k0" in division A of the first clock means the result of the XOR operation between plaintext data m and round key k0.

[0042] Table 31 shows an example of the relationship between each first clock and the next second clock and the Hamming distance between the intermediate value d corresponding to the first clock and the intermediate value d corresponding to the second clock. Here, the Hamming distance means the number of bits whose values ​​differ when bits at the same position in each bit string are compared. For example, the Hamming distance between the bit strings "1000" and "1110" is 2.

[0043] In the AES process, if the Hamming distance satisfies all of the conditions (1) to (4), a side channel attack such as DPA (Differential Power Analysis) becomes applicable, resulting in a high risk state.

[0044] (1) Contains plaintext data m or output data c or C.

[0045] (2) Contains only one type of round key kn.

[0046] (3) M(x) or M -1 Does not contain (x).

[0047] (4) S(x) or S -1 Contains exactly one (x).

[0048] For example, as shown in the row for clocks "1 and 2" in Table 31, the Hamming distance "m+k0+M(S(m+k0))+k1" of the first divided data between the first and second clocks includes multiple types of round keys k0 and k1, as well as M(x). In addition, the Hamming distance "m+M(S(m+k0))" of the second divided data includes M(x). Therefore, a side channel attack cannot be applied to the data in register 11 at this time.

[0049] On the other hand, as shown in the row of clocks "10 and 11", the Hamming distance of the first divided data between the 10th clock and the 11th clock is "S -1 (c+k10)+c" satisfies all of the above-mentioned conditions (1) to (4). In this case, in the AES processing of the conventional technology, a side channel attack can be applied to the register 11 that holds the data corresponding to the first divided data. However, in the configuration of the semiconductor device 1 according to the present disclosure, the Hamming distance "S -1 "(C+k10)+k9+c" contains multiple types of round keys k9 and k10 and does not satisfy condition (2). In this case, the first block and the second block radiate different side channel information, and the division position is unknown to an attacker. Therefore, a side channel attack cannot be applied to register 11 as a whole, and register 11 is highly tamper-resistant.

[0050] 4. Modification of the First Embodiment In the processing shown in the flowchart of FIG. 2, an example has been described in which the data to be processed is divided and then combined by applying only the AddRoundKey processing to each divided data, but the processing is not limited to this configuration.

[0051] For example, the control circuit 10 may be configured to perform AddRoundKey processing and SubBytes processing on each data segment, combine the data segments, and then perform ShiftRows processing and MixColumns processing in S106.

[0052] Alternatively, the control circuit 10 may be configured to apply AddRoundKey processing, SubBytes processing, and ShiftRows processing to each data segment, combine the data segments, and then perform MixColumns processing in S106.

[0053] However, when the control circuit 10 is configured to apply SubBytes processing or ShiftRows processing to each divided data, the minimum amount of information for each divided data is 8 bits (1 byte), and the divided data position is limited to a position that is a multiple of 8 bits. Note that the "amount of information" in this disclosure may include the number of bits, the number of bytes, and other data sizes.

[0054] [Embodiment 2] A second embodiment of the present invention will be described below. For ease of explanation, components having the same functions as those described in the above embodiment will be denoted by the same reference numerals, and redundant explanations will not be repeated. In this embodiment, a configuration will be described in which data to be processed in AES processing is divided into four parts according to the value of a random number.

[0055] 1. Configuration of the Semiconductor Device This embodiment also uses the same configuration as that shown in Fig. 1. However, as will be described later, a control circuit (division unit) 10 according to this embodiment divides data to be processed into four divided data, namely, first to fourth divided data. In addition, the control circuit 10 generates any one of 00, 01, 10, and 11 as a 2-bit, i.e., four different random numbers. Furthermore, a register (data holding unit) 11 holds the first to fourth divided data in the first to fourth blocks using data holding means.

[0056] 2. Processing of Semiconductor Devices Next, an example of the flow of processing executed by the semiconductor device 1 will be described. Fig. 5 is an example of a flowchart showing the flow of processing executed by the semiconductor device 1 according to this embodiment.

[0057] In S201, the control circuit 10 acquires input data to be subjected to AES processing and stores it in the register 11. In this embodiment as well, an example will be described in which the input data is a 128-bit value "A0A1A2A3A4A5A6A7A8A9AAABACADAEAF".

[0058] In S202, the control circuit 10 generates a 2-bit random number for each predetermined amount of information in the input data. If the input data is 128 bits and a 2-bit random number is generated for every 8 bits, for example, the control circuit 10 generates a 32-bit random number with the value "11111010011000100101000011010011." Each 8 bits of the input data and each 2 bits of the random number correspond to each other.

[0059] In S203, the control circuit (division unit) 10 divides the data in the register 11 by allocating each 8-bit portion of the input data to one of the first to fourth divided data portions according to the associated 2-bit random number. From another perspective, the random number defines to which divided data portion each bit string of a predetermined amount of information contained in the data is allocated.

[0060] 6 is a table showing an example of the correspondence between each 8 bits of input data, each 2 bits of random numbers, and the divided data into which each 8 bits of input data is allocated. In this embodiment, the random number "00" corresponds to the first divided data, the random number "01" corresponds to the second divided data, the random number "10" corresponds to the third divided data, and the random number "11" corresponds to the fourth divided data.

[0061] In FIG. 6, the first 8 bits of the input data, "A0," are associated with the random number "11" and assigned to the fourth data segment. Furthermore, "A6," "AA," "AB," and "AE" are assigned to the first data segment, among the 8 bits of the input data. The 8 bits of each data segment that are not assigned a value are filled with the value "00," resulting in a 128-bit value. For example, the value of the first data segment is "000000000000A6000000AAAB0000AE00." The value used to fill the unassigned bits is not limited to "00," and may be "FF," etc.

[0062] Similarly, the second to fourth divided data also have 128-bit values ​​with the missing bits filled with the value "00." From another perspective, as shown in Fig. 8 described later, the divided divided data in this embodiment occupies an area on register 11 equal to the amount of information of the original input data (128 bits) multiplied by the division number (4).

[0063] In S204, the control circuit (block cipher execution unit) 10 executes each process on the first to third data segments. Specifically, AddRoundKey, SubBytes, and ShiftRows processes are executed on the first data segment, and AddRoundKey and SubBytes processes are executed on the second data segment. Furthermore, AddRoundKey processes are executed on the third data segment. At the time of S204, no conversion is performed on the fourth data segment. As a result, in S204, the register 11 operates as a data holding means for holding, in each block, data segments to which different processes included in the AES processing have been applied or not. In other words, data segments to which different processes have been applied are stored in each block of the register 11.

[0064] In the data holding means, the radiated side-channel information is different for all blocks. In this way, when the control circuit (division unit) 10 is configured to divide the data to be processed into three or more divided data, it is more desirable that the radiated side-channel information is different for all blocks in the register (data holding unit) 11. In addition, since the divided positions of the data, i.e., the divided data to which each bit string of the data is assigned, are unknown to an attacker, the data holding means has a very high tamper resistance.

[0065] For example, if the first round key is a 128-bit value "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF," the control circuit 10 applies AddRoundKey processing to the first divided data "000000000000A6000000AAAB0000AE00" to convert it to the value "FFFFFFFFFFFF59FFFFFF5554FFFF51FF." The control circuit 10 also applies SubBytes processing to the value after AddRoundKey processing to convert it to the value "16161616161616CB161616FC201616D116." The control circuit 10 also applies ShiftRows processing to the value after SubBytes processing to convert it to the value "1616FC1616CB20161616161616161616D1." The control circuit 10 may also perform each process on the divided data collectively using a matrix operation.

[0066] In addition, the control circuit 10 applies only the ShiftRows process to the 32-bit random number generated in S202. As a result, for example, the value "11111010011000100101000011010011" is converted to the value "11100011110000111010010110010100".

[0067] In S205, the control circuit (block cipher execution unit) 10 executes each process on the second to fourth data segments. Specifically, it executes a ShiftRows process on the second data segment, and a SubBytes process and a ShiftRows process on the third data segment. It also executes an AddRoundKey process, a SubBytes process, and a ShiftRows process on the fourth data segment. In S205, the first data segment is not converted. Note that the same round key is used in the AddRoundKey processes on each data segment in S204 and S205.

[0068] In S206, the control circuit 10 combines the first to fourth divided data.

[0069] FIG. 7 is a table showing an example of the correspondence between a 32-bit random number to which the ShiftRows process has been applied, the divided data to which each 2 bits of the random number corresponds, and the first divided data at the completion of the process in S205.

[0070] In the example shown in Figure 7, in a column where the value of each 2 bits of the random number is "00" corresponding to the first divided data, the value of the 8 bits of the first divided data is a value other than "16." Also, in a column where the value of each 2 bits of the random number is "01" corresponding to the second divided data, "10" corresponding to the third divided data, or "11" corresponding to the fourth divided data, the value of the 8 bits of the first divided data is "16." The value "16" corresponds to the positions that were filled with the value "00" when the input data was divided.

[0071] The control circuit 10 extracts values ​​from the first divided data corresponding to columns where the value of each 2 bits of the random number is "00." Similarly, the control circuit 10 extracts values ​​from the second divided data corresponding to columns where the value of each 2 bits of the random number is "01," and extracts values ​​from the third divided data corresponding to columns where the value of each 2 bits of the random number is "10." Furthermore, the control circuit 10 extracts values ​​from the fourth divided data corresponding to columns where the value of each 2 bits of the random number is "11."

[0072] The control circuit 10 then combines the 8-bit values ​​of each location extracted from each piece of divided data while maintaining the position of each location to form a 128-bit value.

[0073] Fig. 8 is an example of a data diagram showing the above-mentioned processing from S201 to S206 on data in the register 11. Registers 11f to 11j in Fig. 8 correspond to the register 11 in steps S201 and S203 to S206, respectively.

[0074] In S207, the control circuit 10 executes MixColumns processing on the combined data. Note that the processing from S207 to S212 is repeatedly executed (number of rounds - 1) times.

[0075] In S208, the control circuit 10 performs the same process as in S202 to generate a 2-bit random number for each predetermined amount of data. Note that the process of S208 may not be performed, and the same random number generated in S202 may be used in the subsequent processes.

[0076] In S209, the control circuit 10 performs the same process as S203 to divide the data, and allocates each 8-bit piece of data to one of the first to fourth divided data pieces according to the associated 2-bit random number.

[0077] In S210, the control circuit 10 performs the same process as in S204, and executes each process included in the AES process on the first to third divided data.

[0078] In S211, the control circuit 10 performs the same process as in S205, and executes each process included in the AES process on the second to fourth divided data.

[0079] In S212, the control circuit 10 performs the same process as in S206 to combine the first to fourth divided data.

[0080] In S213, the control circuit 10 determines whether the processes from S207 to S212 have been executed a specified number of times (number of rounds - 1). If the control circuit 10 determines that the processes from S207 to S212 have been executed a specified number of times (S213: YES), then in S214, the control circuit 10 executes SubBytes processing, ShiftRows processing, and AddRoundKey processing on the data in the register 11 to update the data. The updated data in the register 11 is used for other subsequent processing as output data after AES processing. On the other hand, if the control circuit 10 determines that the processes from S207 to S212 have not been executed the specified number of times (S213: NO), the control circuit 10 repeats the processes from S207.

[0081] According to the processing of this embodiment, it is possible to further improve tamper resistance against side channel attacks compared to the processing described in the first embodiment.

[0082] 3. Modification 1 of Embodiment 2 In the process shown in the flowchart of FIG. 5, an example has been described in which the data to be processed is divided into four parts, but the present invention is not limited to this configuration.

[0083] For example, the control circuit 10 may be configured to generate and associate three random numbers, 00, 01, and 10, for each predetermined amount of data. In this configuration, the control circuit 10 performs a process of allocating each bit string of the amount of information to one of the first to third divided data according to the associated random number.

[0084] Alternatively, the control circuit 10 may be configured to generate and associate one bit, i.e., two random numbers, of either 0 or 1, for each predetermined amount of data. In this configuration, the control circuit 10 performs a process of allocating each bit string of the amount of data to either the first divided data or the second divided data according to the associated random number. Also, in this configuration, if the input data is 128 bits and a 1-bit random number is generated for every 8 bits, the control circuit 10 will generate a 16-bit random number.

[0085] 4. Modification 2 of Embodiment 2 The control circuit 10 is not limited to a configuration in which each bit string of data to be processed is assigned to one of the divided data according to the value of the random number.

[0086] For example, the configuration may be such that it is predetermined which data segment a bit string is assigned to depending on the location of each bit string in the data. Furthermore, the bit strings of data assigned to the same data segment may be contiguous or discontinuous. Furthermore, the amount of information in each data segment may differ from one another; for example, if the input data is 128 bits, the amounts of information in the first to fourth data segments may be 16 bits, 48 ​​bits, 32 bits, and 32 bits, respectively. Furthermore, the amount of information in each data segment may change each time the data is divided.

[0087] [Software implementation example] The functions of the semiconductor device 1 (hereinafter referred to as the "device") can be realized by a program that causes the semiconductor device to function as the device, and a program that causes the semiconductor device to function as each control block of the device.

[0088] The program may be stored non-transitory on one or more computer-readable storage media. The storage media may or may not be included in the computer 100 that includes the device. In the latter case, the program may be supplied to the device via any wired or wireless transmission medium.

[0089] Furthermore, some or all of the functions of the control blocks can be realized by logic circuits. For example, an integrated circuit in which a logic circuit that functions as each of the control blocks is formed is also included in the scope of the present invention. In addition, the functions of the control blocks can also be realized by, for example, a quantum computer.

[0090] Furthermore, each process described in each of the above embodiments may be executed by AI (Artificial Intelligence). In this case, the AI ​​may run on the control device or on another device (for example, an edge computer or a cloud server).

[0091] 〔summary〕 A semiconductor device (1) according to a first aspect of the present invention has a configuration including a division unit (10) that divides data into two or more divided data, a block cipher execution unit (10) that applies a specific process included in a block cipher algorithm to only one or more partial data of the two or more divided data, and a data storage unit (11) that stores the partial data to which the process has been applied in each block, and the radiated side channel information differs from one another between at least some of the blocks.

[0092] A semiconductor device according to a second aspect of the present invention may be configured in the above-mentioned first aspect such that the dividing section divides the data into each of the divided data so that at least some of the divided data have different amounts of information.

[0093] A semiconductor device according to aspect 3 of the present invention may be configured such that, in aspect 1 or 2 above, the dividing unit performs a process of allocating each bit string of a predetermined amount of information contained in the data to one of the divided data depending on the value of a random number generated for each predetermined amount of information in the data.

[0094] A semiconductor device according to a fourth aspect of the present invention may be configured such that, in any of the first to third aspects above, the dividing unit divides the data into three or more divided data, and the data holding unit holds the divided data in each block so that the radiated side channel information is different from one another among all the blocks.

[0095] A semiconductor device according to a fifth aspect of the present invention may be configured in any one of the first to fourth aspects above, such that the block cipher algorithm is AES (Advanced Encryption Standard), and the specific processing includes an AddRoundKey processing.

[0096] A processing method according to aspect 6 of the present invention is a data processing method executed by device (1), and includes a division step of dividing the data into two or more divided data, a block cipher execution step of applying a specific process included in a block cipher algorithm to only one or more partial divided data of the two or more divided data, and a data storage step of storing the partial data to which the process has been applied in each block, wherein the radiated side channel information is different from each other between at least some of the blocks.

[0097] A control program according to a seventh aspect of the present invention is configured to cause the semiconductor device in any one of the first to fifth aspects to function as the division unit and the block cipher execution unit.

[0098] A recording medium according to an eighth aspect of the present invention is configured to be computer-readable and to store the control program according to the seventh aspect.

[0099] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment. [Explanation of symbols]

[0100] 1. Semiconductor device 2. Memory 10 Control circuit (division unit, block cipher execution unit) 11, 11a to 11i Registers (data storage units) 100 computers

Claims

1. a division unit that divides data into two or more divided data; a block cipher execution unit that applies a specific process included in a block cipher algorithm to only one or more partial data segments among the two or more data segments; a data storage unit that stores the divided data to which the processing has been applied in each block, the data storage unit being such that radiated side channel information differs from one another between at least some of the blocks; A semiconductor device having:

2. The dividing unit The data is divided into the divided data so that at least some of the divided data have different amounts of information. The semiconductor device according to claim 1 .

3. The dividing unit A process of allocating each bit string of a predetermined amount of information contained in the data to one of the divided data in accordance with the value of a random number generated for each predetermined amount of information of the data is performed.

3. The semiconductor device according to claim 1.

4. the division unit divides the data into three or more divided data pieces, The data storage unit The divided data is stored in each block so that the radiated side channel information is different from one another among all the blocks.

3. The semiconductor device according to claim 1.

5. the block cipher algorithm is AES (Advanced Encryption Standard), The specific processing includes an AddRoundKey processing.

3. The semiconductor device according to claim 1.

6. 1. A method of processing data performed by an apparatus, comprising: a dividing step of dividing the data into two or more divided data; a block cipher execution step of applying a specific process included in a block cipher algorithm to only one or more partial data segments among the two or more data segments; a data holding step of holding the divided data, to which the processing has been applied only to a part of the divided data, in each block, in which radiated side channel information differs from one another between at least some of the blocks; A processing method comprising:

7. A control program for causing a semiconductor device to function as the division unit and the block cipher execution unit according to claim 1 .

8. A computer-readable recording medium on which the control program according to claim 7 is recorded.

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