Semiconductor device, and manufacturing method

Abstract

To provide a semiconductor device and a manufacturing method that can prevent the generation of cracks in a passivation film.SOLUTION: A semiconductor device according to the present embodiment comprises a semiconductor member, an interlayer film, a metal layer, and a passivation film. The interlayer film is provided on an upper surface side of the semiconductor member. The metal layer is provided to cover at least part of an area on an upper surface side of the interlayer film. The passivation film is deposited on a top face of the interlayer film not provided with the metal layer and a side face and a top face at an end of the metal layer. An upper part of the end of the metal layer has a curved surface.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method. [Background technology]

[0002] BACKGROUND ART Conventionally, vertical MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), for example, have been developed as semiconductor devices for use in switching elements, such as for power control.

[0003] In such semiconductor devices, a passivation film is formed to prevent the intrusion of moisture and mobile ions. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6504313 Summary of the Invention [Problem to be solved by the invention]

[0005] However, semiconductor devices for power control and the like often use thick electrodes to pass large currents, and in such cases, even if a passivation film is formed on the metal layer of the electrode or wiring, cracks are likely to occur due to the difference in thermal expansion coefficient between the passivation film and the metal layer.

[0006] An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can suppress the occurrence of cracks in a passivation film. [Means for solving the problem]

[0007] The semiconductor device according to this embodiment includes a semiconductor member, an interlayer film, a metal layer, and a passivation film. The interlayer film is provided on the upper surface of the semiconductor member. The metal layer is provided so as to cover at least a portion of the upper surface of the interlayer film. The passivation film is formed on the upper surface of the interlayer film where the metal layer is not provided, and on the side surfaces and upper surface of the end of the metal layer. The upper portion of the end of the metal layer has a curved surface. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a top view showing a semiconductor device according to an embodiment. [Figure 2] 2 is a cross-sectional view taken along line A-A' shown in FIG. 1. [Figure 3] 2 is a cross-sectional view taken along line BB' shown in FIG. 1. [Figure 4] FIG. 4 is a cross-sectional view showing an end portion of a metal film. [Figure 5] FIG. 10 is a cross-sectional view showing an end portion of a metal film according to a comparative example. [Figure 6] FIG. 10 is a diagram for explaining stress acting on the upper part of the end portion. [Figure 7] 5A to 5C are diagrams showing a method for manufacturing a first relaxation region and a second relaxation region at the end portion. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, semiconductor devices and manufacturing methods according to embodiments of the present invention will be described in detail with reference to the drawings. Note that the embodiments described below are merely examples of embodiments of the present invention, and the present invention should not be construed as being limited to these embodiments. Furthermore, in the drawings referred to in this embodiment, identical or similar reference numerals are used for identical parts or parts having similar functions, and repeated explanations thereof may be omitted. Furthermore, for convenience of explanation, the dimensional ratios of the drawings may differ from the actual ratios, and some components may be omitted from the drawings.

[0010] In the following description and drawings, the notations n+, n-, and p represent the relative levels of each impurity concentration. That is, a notation with a "+" indicates a relatively higher impurity concentration than a notation with neither a "+" nor a "-" and a notation with a "-" indicates a relatively lower impurity concentration than a notation with neither a "+" nor a "-". When both p-type and n-type impurities are contained in each region, these notations represent the relative levels of the net impurity concentration after the impurities compensate for each other. In each embodiment described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0011] Fig. 1 is a top view showing a semiconductor device according to this embodiment. Fig. 2 is a cross-sectional view taken along line A-A' shown in Fig. 1. Fig. 3 is a cross-sectional view taken along line B-B' shown in Fig. 1. Fig. 1 is a diagram schematically showing an example of a semiconductor device 1 according to an embodiment.

[0012] As shown in Figures 1, 2, and 3, the semiconductor device 1 according to this embodiment is configured as, for example, a vertical MOSFET. The semiconductor device 1 includes a drain electrode 10, a source electrode 20, a gate electrode 30, a wiring portion 32, a buried electrode 40, an insulating member 50, an interlayer film 55, a semiconductor member 60, a metal film 70, a barrier metal layer 72, and a passivation film 74. The source electrode 20 and the wiring portion 32 according to this embodiment correspond to the metal layer. For simplicity of explanation, the passivation film 74 is not shown in Figures 1 and 3.

[0013] The drain electrode 10, the source electrode 20, the gate electrode 30, and the wiring portion 32 are made of metal. The insulating member 50 and the interlayer film 55 are made of an insulating material. The semiconductor member 60 is made of a semiconductor material.

[0014] The semiconductor member 60 is disposed between the drain electrode 10 and the source electrode 20. The gate electrode 30 is disposed within the semiconductor member 60 and extends in the Y direction. The semiconductor member 60 has, for example, a rectangular plate shape. The semiconductor member 60 has an upper surface parallel to the X and Y directions and a lower surface opposite the upper surface. The semiconductor member 60 is made of, for example, single-crystal silicon (Si), and impurities are locally introduced to make the conductivity type of each portion p-type or n-type. The configuration of the semiconductor member 60 will be described later. In this embodiment, the source electrode 20 corresponds to a first electrode, the drain electrode 10 corresponds to a second electrode, and the gate electrode 30 corresponds to a third electrode.

[0015] Hereinafter, for convenience of explanation, this specification will adopt an XYZ Cartesian coordinate system. The direction from the drain electrode 10 toward the source electrode 20 is referred to as the "Z direction," the direction in which the gate electrode 30 extends in this embodiment is referred to as the "Y direction," and the direction perpendicular to the Z direction and the Y direction is referred to as the "X direction." The X direction, Y direction, and Z direction are mutually perpendicular. The Z direction is also referred to as "up" and the opposite direction is also referred to as "down," but these expressions are also for convenience and are unrelated to the direction of gravity.

[0016] 1, a gate pad 31 and a frame-shaped wiring portion 32 are provided on the outer edge of an upper surface 62 of a semiconductor member 60. The gate pad 31 is provided, for example, on one corner of the upper surface 62 of the semiconductor member 60. The wiring portion 32 is connected to the gate pad 31. In this specification, "connection" means electrical connection.

[0017] A source electrode 20 is disposed on the upper surface 62 of the semiconductor member 60 in a region surrounded by the gate pad 31 and the wiring portion 32. The source electrode 20 is disposed in each of the regions R1 and R2. For example, the source electrode 20 disposed in the region R1 and the source electrode 20 disposed in the region R2 are connected to each other by a bonding wire, a connector, or the like that is connected to the bonding region A100 during package assembly, and are used as a single electrode. The source electrode 20 is spaced apart from the gate pad 31 and the wiring portion 32. A drain electrode 10 is disposed over the entire lower surface of the semiconductor member 60.

[0018] As shown in FIGS. 1 to 3 , a semiconductor member 60 has a plurality of trenches 63 formed from the upper surface 62 side. Each trench 63 extends in the Y direction. The plurality of trenches 63 are arranged along the X direction. The trenches 63 do not reach the lower surface of the semiconductor member 60. An insulating member 50 is disposed in each trench 63. The upper portion of the insulating member 50 protrudes upward from the upper surface 62 of the semiconductor member 60 and extends to both sides of the trench 63 in the X direction to form an interlayer film 55. However, two insulating members 50 and two interlayer films 55 adjacent to each other in the X direction are spaced apart from each other. The insulating members 50 and the interlayer film 55 contain, for example, either silicon oxide or silicon nitride. The insulating members 50 and the interlayer film 55 may or may not be formed integrally.

[0019] A metal film 70 is provided between the interlayer film 55 and the source electrode 20, and between the semiconductor member 60 and the source electrode 20. The metal film 70 covers the upper and side surfaces of the interlayer film 55, and covers the upper surface of the semiconductor member 60 between the interlayer films 55. The metal film 70 is in contact with the source electrode 20 and is connected to the source electrode 20.

[0020] Further, trench contacts 47 of the metal film 70 are formed between the interlayer films 55. Each trench contact 47 extends in the Y direction. A plurality of trench contacts 47 are arranged along the X direction.

[0021] The barrier metal layer 72 covers the lower surface, including the side surfaces, of the metal film 70. The barrier metal layer 72 prevents diffusion of metal atoms toward the semiconductor member 60 and mutual reactions between adjacent portions sandwiching the barrier metal layer 72. The barrier metal layer 72 is, for example, a tungsten (W) film, a titanium (Ti) film, a titanium nitride (TiN) film, or a laminated metal film of these.

[0022] A passivation film 74 is formed on the upper surface of the source electrode 20. A bonding region A100 exposed in an opening in the passivation film 74 functions as a bonding region for the source wiring. The source electrode 20 is formed up to the end of the terminal cell A200 outside the bonding region A100.

[0023] Similarly, in the wiring region A300, a passivation film 74 is formed on the upper surface of the wiring portion 32. Similar to the source electrode 20, a metal film 70 and a barrier metal layer 72 are laminated on the upper surface of the interlayer film 55 below the wiring portion 32. As will be described later, the wiring portion 32 and the metal film 70 may be integrated, for example. Alternatively, the wiring portion 32 and the metal film 70 may not be integrated.

[0024] The upper portions of the ends of the metal layers of the source electrode 20 and the wiring portion 32 on which the passivation film 74 is formed have curved surfaces, such as the end P100 of the source electrode 20 and the ends P200 and P300 of the wiring region A300. For example, the upper portions of the ends of the metal layers have an arc shape. The ends P100, P200, and P300 will be described in detail later.

[0025] As described above, at least one of the wiring portion 32 and the metal film 70, the source electrode 20 and the metal film 70 may be referred to as the metal layer (32(20)). The metal layer (32(20)) may or may not be integrally formed with the metal film 70. Thus, the semiconductor device 1 according to this embodiment includes a semiconductor member 60, an interlayer film 60 provided on the upper surface of the semiconductor member 60, a metal layer (32(20)) provided so as to cover at least a portion of the upper surface of the interlayer film 60, an upper surface of the interlayer film 60 on which the metal layer (32(20)) is not provided, and a passivation film 74 formed on the side and upper surface of the end of the metal layer (32(20)). The upper portion of the end of the metal layer (32(20)) has an arc shape.

[0026] A gate electrode 30 is disposed in each trench 63. The gate electrode 30 is separated from the semiconductor member 60 via a part of the insulating member 50. Both ends of the gate electrode 30 in the Y direction are extended to the upper surface 62 of the semiconductor member 60 and connected to the wiring portion 32. As a result, the gate electrode 30 is connected to the gate pad 31 via the wiring portion 32.

[0027] The insulating member 50 may be made of, for example, inorganic materials such as silicon dioxide (SiO2), silicon nitride (Si3N4), PSG (Phospho Silicate Glass), BPSG (Boron Phospho Silicate Glass), or SOG (Spin On Glass), or organic materials such as various polymers including polyimide.

[0028] In addition, a plurality of embedded electrodes 40 are arranged below the gate electrode 30 in each trench 63. The embedded electrodes 40 are arranged discontinuously in a line along the Y direction. In other words, a plurality of embedded electrodes 40 are provided along the Y direction. A portion of an insulating member 50 is arranged between adjacent embedded electrodes 40 in the Y direction. The embedded electrodes 40 contain silicon and are formed of, for example, polysilicon doped with impurities. The embedded electrodes 40 are separated from the gate electrode 30 via a portion of the insulating member 50.

[0029] The buried electrode 40 is in contact with the metal film 70. As a result, the buried electrode 40 is connected to the source electrode 20 via the metal film 70.

[0030] The metal film 70 and the source electrode 20 are, for example, integrally formed. The metal film 70 and the source electrode 20 are, for example, aluminum (Al) or a high-strength aluminum alloy (AlCu). The metal film 70 and the source electrode 20 contain at least one metal selected from the group consisting of aluminum (Al), a high-strength aluminum alloy (AlCu), copper (Cu), tungsten (W), titanium (Ti), cobalt (Co), and nickel (Ni), and may contain, for example, a metal compound or alloy made of any metal in the above metal group.

[0031] Similarly, the metal film 70 and the wiring portion 32 are, for example, integrally formed. The metal film 70 and the wiring portion 32 are, for example, aluminum (Al) or a high-strength aluminum alloy (AlCu). The metal film 70 and the wiring portion 32 contain at least one metal selected from the group consisting of aluminum (Al), a high-strength aluminum alloy (AlCu), copper (Cu), tungsten (W), titanium (Ti), cobalt (Co), and nickel (Ni), and may contain, for example, a metal compound or alloy made of any metal in the above metal group.

[0032] In this way, the insulating member 50 and the interlayer film 55 are arranged between the semiconductor member 60 and the gate electrode 30, between the gate electrode 30 and the buried electrode 40, between the gate electrode 30 and the metal film 70, and between the semiconductor member 60 and the buried electrode 40.

[0033] The semiconductor member 60 includes a drain layer 65 having an n+ conductivity type, a drift layer 66 having an n- conductivity type, a source layer 67 having an n+ conductivity type, and a base layer 68 having a p- conductivity type. The carrier concentration in the source layer 67 is higher than the carrier concentrations in the drain layer 65 and the drift layer 66. Note that "carriers" refer to electrons and positive arcs. The drain layer 65 constitutes the lower surface 61 of the semiconductor member 60 and is disposed between the drain electrode 10 and the drift layer 66. Therefore, the drift layer 66 is connected to the drain electrode 10 via the drain layer 65. The source layer 67 constitutes the upper surface 62 of the semiconductor member 60 and is in contact with the metal film 70. Therefore, the source layer 67 is connected to the source electrode 20 via the metal film 70.

[0034] The base layer 68 is disposed between the drift layer 66 and the source layer 67, and is in contact with the drift layer 66 and the source layer 67. The base layer 68 is connected to the source electrode 20 via a metal film 70.

[0035] Next, the operation of the semiconductor device 1 according to this embodiment will be described. A voltage is applied between the drain electrode 10 and the source electrode 20 so that the potential of the drain electrode 10 is higher than the potential of the source electrode 20. In this state, when a potential higher than the threshold is applied to the gate electrode 30, an inversion layer (channel) is formed in the region of the base layer 68 that contacts the insulating member 50. As a result, electrons flow from the source electrode 20 to the drain electrode 10 via the metal film 70, the source layer 67, the inversion layer formed in the base layer 68, the drift layer 66, and the drain layer 65. As a result, the semiconductor device 1 is turned on, and a current flows from the drain electrode 10 to the source electrode 20.

[0036] When the potential of the gate electrode 30 becomes lower than the threshold, the inversion layer formed in the base layer 68 disappears, and a depletion layer spreads from the pn interface between the drift layer 66 and the base layer 68. Because the same potential as that of the source electrode 20 is applied to the buried electrodes 40 and 40, the depletion layer also spreads from the surface of the drift layer 66 that contacts the insulating member 50. That is, in the drift layer 66, the depletion layer spreads downward from the pn interface and from the insulating member 50 in the X direction. This turns off the semiconductor device 1, and the current flowing from the drain electrode 10 to the source electrode 20 is cut off.

[0037] When the semiconductor device 1 switches from the on state to the off state, the voltage between the source electrode 20 and the drain electrode 10 increases rapidly. The potential of the source electrode 20 is also transmitted to the buried electrode 40 via the metal film 70. When the semiconductor device 1 switches to the off state and the potential of the buried electrode 40 increases, the insulating member 50 functions as a parasitic capacitance between the buried electrode 40 and the drain electrode 10, causing electrons to be charged and discharged. This causes the voltage between the source electrode 20 and the drain electrode 10 to oscillate and then converge to a predetermined voltage.

[0038] Here, a detailed configuration example of the ends P100, P200, and P300 (see FIG. 2) of the metal film on which the passivation film 74 is formed will be described. FIG. 4 is an enlarged view of the end P200. As described above, the ends P200 and P300 are examples of the wiring portion 32, but the end P100 of the source electrode 20 also has a similar configuration. As described above, the wiring portion 32 and the source electrode 20 may have the metal film 70. Furthermore, the wiring portion 32 and the source electrode 20 may be made of different metal materials from the metal film 70. In this case, the wiring portion 32 and the source electrode 20 are laminated bodies made of different metal materials.

[0039] Fig. 5 is a cross-sectional view showing an example of the configuration of the end portion P200a according to the comparative example. Stresses D100 to D106 in Fig. 4 indicate stresses that occur on the passivation film 74 during heat treatment. Similarly, stresses D100a to D106a in Fig. 5 indicate stresses that occur on the passivation film 74 during heat treatment. That is, because the thermal expansion coefficient of the wiring portion 32 (source electrode 20) is larger than that of the passivation film 74, stresses occur during heat treatment.

[0040] As shown in Fig. 4, the end P200 according to this embodiment differs from the end P200a of the comparative example in that it has a first stress relaxation region S100 and a second stress relaxation region S200. As shown in Fig. 5, in the end P200a of the comparative example, stresses D100a-D103a concentrate at the upper part of the end of the wiring portion 32 (source electrode 20). In addition, the end of the barrier metal layer 72 has a rectangular shape, and stresses D104a-D106a tend to concentrate at the lower part of the end of the wiring portion 32 (source electrode 20).

[0041] For example, stress D101a and stress D104a, and stress D103a and stress D106a are stresses in opposite directions. As a result, a compressive force is applied between crack lines C100a and C200a. Furthermore, stresses in opposite directions, stress D101a and stress D100a, and stress D103a and stress D102a, are generated in crack line C100. As a result, stress is generated in a direction that peels crack line C100a. In this way, as stresses D100a to D103a increase, the force in the direction that peels crack line C100a increases.

[0042] Furthermore, when the stresses D104a and D106a increase, the interaction between the stresses D101a and D104a, and the interaction between the stresses D103a and D106a makes it easier for cracks to occur along the crack lines C100a and C200a.

[0043] In contrast, in the first relaxation region S100, the upper end portion has a curved surface so as to prevent corners from forming in the wiring portion 32 (source electrode 20). This relieves the stresses D100 to D103 that concentrate on the upper end portion of the wiring portion 32 (source electrode 20). In this way, by having the curved surface at the upper end portion, the stresses D100 to D103 are relieved, and the occurrence of cracks along the crack line C100 is suppressed.

[0044] In the second relaxation region S200, the end of the barrier metal layer 72 is formed into a trapezoidal shape. This relieves stresses D104 to D106 that concentrate on the end of the lower part of the wiring portion 32 (source electrode 20). By forming the end of the barrier metal layer 72 into a trapezoidal shape in this way, the stresses D104 to D106 are relieved, and the occurrence of cracks along the crack lines C100 and C200 is suppressed. That is, the barrier metal layer 72 has a shape in which the lower surface in contact with the interlayer film 55 is longer than the upper surface in contact with the metal layer (32(20)).

[0045] In this way, the end face 72a of the barrier metal layer 72 formed between the lower surface of the metal layer (32(20)) and the upper surface of the interlayer film 55 is inclined. That is, the shape of the end face 72a of the barrier metal layer on the end side of the metal layer (32(20)) is inclined so as to approach from the end side to the other end side as it approaches the lower surface of the end of the metal layer (32(20)) from the interlayer film 55. By inclining the end face 72a of the barrier metal layer 72 in this way, stresses D104 to D106 are alleviated and the occurrence of cracks along the crack lines C100 and C200 is suppressed.

[0046] Now, referring to FIG. 6, the radius Rt of the arc shape F FIG. 6 is a diagram for explaining the stress applied to the end portion of the upper portion. Here, the radius of the arc of the end portion of the upper portion is Rt F and the metal thickness of the wiring portion 32 (source electrode 20) is t s The thickness of the passivation film 74 is t FThat is, the metal layer (32(20)) has upper and lower surfaces parallel to a first direction (X direction) and a second direction (Y direction) perpendicular to the first direction, and has a metal thickness t s Similarly, the passivation film 74 has upper and lower surfaces parallel to a first direction (X direction) and a second direction (Y direction) perpendicular to the first direction, and the thickness t F is the distance between the top and bottom surfaces. Thus, the top end of the metal layer (32(20)) has a curved surface. For example, the angle α between the top surface of the top end and the extension of the side surface is set to 90 degrees or more.

[0047] Radius Rt of the end of the upper part of the wiring portion 32 (source electrode 20) F There are two types of stresses acting on the arc: film stress σ and thermal stress σT. As described above, cracks occur in the passivation film 74 when heat treatment is performed after formation, resulting in a large difference in the thermal expansion coefficient between the underlying wiring portion 32 (source electrode 20) and the passivation film 74. This is because the thermal stress σT is large. In other words, cracks do not occur when the passivation film 74 is formed, so it is thought that cracks occur when the thermal stress σT becomes larger than the film stress σ. In other words, the radius Rt according to this embodiment F The arc shape of the passivation film 74 has a shape in which the thermal stress σT on the passivation film 74 is smaller than the film stress σ. F The arc shape has a shape that relieves the thermal stress σ T on the passivation film 74.

[0048] In this way, the arc shape according to this embodiment has a predetermined radius Rt F It has a given radius Rt F is the radius at which the thermal stress σT on the passivation film 74 is smaller than the film stress σ. Here, the radius Rt that satisfies the condition that the film stress σ≒thermal stress σT is F Consider the range of. From the Stoney equation, the membrane stress σ is expressed by equation (1).

[0049] A more specific example will be described in which the material of the wiring portion 32 (source electrode 20) is aluminum (Al) and the material of the passivation film 74 is silicon dioxide (SiO 2 ).

number

number

[0050] where E S is the Young's modulus of aluminum (Al) (70 GPa), and E F is the Young's modulus of silicon dioxide (SiO2) (73 GPa). Therefore, Es ≒ E F Calculate as follows: V s is the Poisson's ratio of aluminum (Al) (0.33), and V F is the Poisson's ratio of silicon dioxide (SiO2) (0.17). α s is the thermal expansion coefficient of aluminum (Al) (22 to 23.5 × 10^-6 / ℃), and α F is the thermal expansion coefficient of silicon dioxide (SiO2) (0.41~0.58×10^-6 / ℃).

[0051] Furthermore, substituting numerical values ​​into equation (1) gives equation (3).

number

[0052] Furthermore, substituting numerical values ​​into equation (2) gives equation (4).

number

[0053] As a result, when equation (4) is further substituted into equation (3), equation (5) is obtained.

number

[0054] Further rearranging equation (5) gives equation (6).

number

[0055] As can be seen from these, when the metal layer (32(20)) is made of aluminum (Al) and the passivation film 74 is made of silicon dioxide (SiO2), the predetermined radius Rt F is the thickness t of the metal layer (32(20)) s The square of the thickness t of the passivation film 74 F In the semiconductor device 1 according to this embodiment, for example, the thickness of the wiring portion 32 (source electrode 20) is set to 4 micrometers (um), and the thickness of the passivation film 74 is set to 1 micrometer (um). In this case, t s :t F =4:1, and can be calculated from equation (7) by substituting this into equation (6).

number

[0056] In this embodiment, the thickness of aluminum (Al) in the wiring portion 32 (source electrode 20) is 3 to 6 micrometers (um), and the thickness of the passivation film 74 is 0.5 to 1.5 micrometers (um). F The maximum thickness is 0.65 micrometers (um) when the thickness of the aluminum (Al) is 6 micrometers (um) and the thickness of the silicon dioxide (SiO2) is 0.5 micrometers (um).

[0057] On the other hand, the radius Rt FWhen the thickness of the aluminum (Al) is 3 micrometers (um) and the thickness of the silicon dioxide (SiO2) is 1.5 micrometers (um), the radius Rt F When the thickness is 41 to 650 nanometers (nm) or more, the occurrence of cracks is suppressed.

[0058] In particular, in order to suppress the occurrence of cracks, the thickness t s is 3 to 6 micrometers (um), and the thickness t F is between 0.5 and 1.5 micrometers (um), the radius Rt F is 100 to 650 nanometers (nm) or more.

[0059] A manufacturing example of the first relaxation region S100 and the second relaxation region S200 of the end portion P200 will now be described with reference to Fig. 7. Fig. 7 is a diagram showing a manufacturing method of the first relaxation region S100 and the second relaxation region S200 of the end portion P200.

[0060] FIG. 7(a) is a diagram showing the aluminum processing process. As shown in FIG. 7(a), a barrier metal layer 72 and a metal layer (32(20)) are formed on an interlayer film (insulating material 50). Next, the metal layer (32(20)) is processed by a method of removing unnecessary portions through a chemical reaction using wet etching (WET). In this way, the aluminum processing process is a process of stacking an interlayer film 55, a barrier metal layer 72, and a metal layer (32(20)) on the upper surface side of the semiconductor member 60, and processing the metal layer (32(20)) to generate end regions Pu200 and Pd200. This processing may be dry etching using reactive ion etching. The metal layer (32(20)) may or may not include a metal film 70.

[0061] FIG. 7(b) is a diagram showing the barrier metal processing step. As shown in FIG. 7(b), the barrier metal layer 72 is processed. For example, unnecessary portions of the barrier metal layer 72 are removed by a chemical reaction using wet etching (WET). In this way, the barrier metal processing step is a step in which the barrier metal layer 72 is processed down to the lower end region Pd200 of the metal layer (32(20)). This processing may also be dry etching using reactive ion etching.

[0062] FIG. 7(c) is a diagram showing the process of shaping aluminum. As shown in FIG. 7(c), a chemical reaction caused by wet etching (WET) causes the metal layer (32(20)) to retreat and generates an arc with a radius RtF at the upper end Pu200. At this time, the etching performed when retreating the metal layer (32(20)) processes the end of the barrier metal layer 72 into a trapezoidal shape. For example, if the barrier metal layer 72 is formed of tungsten and an etching solution such as phosphoric acid is used, the etching rate ratio between the metal layer and the barrier metal layer can be set to 10:1. By utilizing this difference in etching rates, the end of the barrier metal 72 can be processed into a trapezoidal shape. In this way, the aluminum shaping process forms a predetermined arc shape in the upper end region Pu200 of the metal layer (32(20)), while processing the lower end region Pd200 toward the other end, thereby forming an inclined surface 72a in the barrier metal layer 72 according to the position of the lower end region Pd200a. This processing may be dry etching using reactive ion etching.

[0063] 7(d) is a diagram showing a shaping process for forming a passivation film. As shown in FIG. 7(d), passivation film 74 is formed by chemical vapor deposition. After passivation film 74 is formed, it is processed by reactive ion etching. By this manufacturing method, a first relaxation region S100 and a second relaxation region S200 are formed.

[0064] As described above, according to this embodiment, when the barrier metal layer 72, the metal layer (the wiring portion 32, the source electrode 20), and the passivation film 74 are formed on the interlayer film 55, a curved surface (e.g., an arc shape having a predetermined radius RtF) is formed in the upper end region Pu200 of the metal layer (the wiring portion 32, the source electrode 20). This reduces stress generated in the passivation film 74 during heat treatment, thereby suppressing the occurrence of cracks in the passivation film 74. Furthermore, the shape of the end face 72a of the barrier metal layer 72 is inclined from the end side to the other end side as it approaches the undersurface of the end of the metal layer (the wiring portion 32, the source electrode 20) from the interlayer film 55. This reduces the stress that occurs in the passivation film 74 during heat treatment in the lower end region Pd200a of the metal layer (wiring portion 32, source electrode 20), and suppresses the occurrence of cracks at the lower end (within relaxation region S200) and upper end (within relaxation region S100) of the passivation film 74.

[0065] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel devices, methods, and programs described in this specification can be embodied in various other forms. Furthermore, various omissions, substitutions, and modifications can be made to the forms of the devices, methods, and programs described in this specification without departing from the spirit of the invention. [Explanation of symbols]

[0066] 1: semiconductor device, 10: drain electrode, 20: source electrode, 30: gate electrode, 32: wiring portion, 50: insulating member, 55: interlayer film, 72: barrier metal layer, 72a: end surface, 74: passivation film, P100, P200, P300: end portion, Pd200, Pd200a: lower end portion region, Pu200: upper end portion region, S100: first relaxation region, S200: second relaxation region.

Claims

1. A semiconductor member; an interlayer film provided on the upper surface side of the semiconductor member; a metal layer provided so as to cover at least a portion of an upper surface of the interlayer film; a top surface of the interlayer film on which the metal layer is not provided, and a passivation film formed on the side surface and top surface of the end of the metal layer; The semiconductor device, wherein the upper end of the metal layer has a curved surface.

2. 2. The semiconductor device according to claim 1, further comprising a barrier metal layer having a shape in which a lower surface in contact with said interlayer film is longer than an upper surface in contact with said metal layer.

3. 3. The semiconductor device according to claim 2, wherein the shape of the end face of said barrier metal layer on said end side is inclined so as to approach the other end as it approaches the undersurface of said end of said metal layer from said interlayer film.

4. 3. The semiconductor device according to claim 1, wherein the upper curved surface has a shape such that an angle α between an extension line of the top surface and the side surface at the end of the metal layer is 90 degrees or more, and thermal stress on the passivation film is smaller than film stress.

5. 3. The semiconductor device according to claim 1, wherein the upper curved surface is arc-shaped and has a shape that relieves thermal stress on the passivation film in the arc-shaped configuration.

6. 3. The semiconductor device according to claim 1, wherein said upper curved surface is arc-shaped, and said arc-shaped surface has a predetermined radius.

7. 7. The semiconductor device according to claim 6, wherein said predetermined radius is a radius at which said thermal stress on said passivation film is smaller than a film stress.

8. the metal layer has an upper surface and a lower surface parallel to a first direction and a second direction perpendicular to the first direction; 8. The semiconductor device according to claim 6, wherein the predetermined radius is equal to or greater than the thickness of the metal layer, which is the length between the upper surface and the lower surface.

9. When the metal layer is aluminum and the passivation film is silicon dioxide, 8. The semiconductor device according to claim 7, wherein the predetermined radius is greater than a value obtained by dividing the square of the thickness of the metal layer by the thickness of the passivation film and then dividing the result by a predetermined constant.

10. When the thickness of the metal layer is 3 to 6 micrometers (um) and the thickness of the passivation film is 0.5 to 1.5 micrometers (um), 10. The semiconductor device of claim 9, wherein the predetermined radius is 100 to 650 nanometers (nm) or greater.

11. 4. The semiconductor device according to claim 2, wherein the metal layer is an electrode or a wiring portion.

12. the metal layer is a first electrode; a second electrode provided on the lower surface of the semiconductor member; a third electrode provided in the semiconductor member and extending in a first direction from the first electrode toward the second electrode; The semiconductor device according to claim 1 , further comprising:

13. a step of laminating an interlayer film, a barrier metal layer, and a metal layer on the upper surface side of the semiconductor member, and processing the metal layer to generate an edge region; processing the barrier metal layer to an end region of the metal layer; forming a predetermined arc shape at an end portion of the upper portion of the end region while processing the end region toward the other end portion to form an inclined surface in the barrier metal layer according to the position of the end region; forming a passivation film on the processed metal layer and the inclined surface of the barrier metal layer; A method for manufacturing a semiconductor device, comprising:

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