Pulse power supply device for plasma etching apparatus and bias control method

Abstract

To achieve a good commutation while simplifying a circuit configuration and a control.SOLUTION: One aspect of the present invention includes a voltage source 13 that outputs a voltage V3, a voltage source 14 that outputs a voltage V4, switches S3 and S4 that selectively couple the voltage source 13 and the voltage source 14 to an output terminal 10, respectively, and a current source 12 coupled between the output terminal 10 and a ground terminal 9 via the switch S3. In a state where an output voltage Vop1 is maintained at a low level by holding a voltage lowered to a voltage V1 by a second half-wave resonance in a capacitor load, a control unit turns on the switch S3 to cause a current by a first half-wave resonance to flow through a resonance loop including the capacitor load, an inductor Ln, and the like, thereby raising the output voltage Vop1. When the output voltage Vop1 becomes a voltage V5 and a DC current from the current source 12 flows to rise to a voltage V6, the switch S4 is turned on, and the output voltage Vop1 is lowered to the voltage V1 by flowing the current by the second half-wave resonance in the resonance loop including the capacitor load, the inductor Ln, and the like.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a pulse power supply device used in a plasma etching device for semiconductor manufacturing and the like, and a method for controlling the bias of the pulse power supply device. [Background technology]

[0002] In semiconductor manufacturing processes, plasma etching systems are widely used to etch semiconductor substrates using plasma. Reactive ion etching systems typically generate plasma from an etching gas in a chamber using high-frequency inductive coupling or electron cyclotron resonance, and apply a bias voltage, such as a high-frequency voltage, to a substrate placed in the chamber. This generates a self-bias potential between the substrate and the plasma, causing ion and radical species in the plasma to accelerate toward the substrate and collide with its surface, resulting in etching.

[0003] To perform precise etching in a plasma etching apparatus, it is important to properly control the ion energy distribution (IED) on the substrate surface. Generally, it is desirable for the IED on the substrate surface to be a single IED with as narrow a peak width as possible. To achieve such an IED, the substrate surface voltage must be kept nearly constant. However, because the ion current derived from the plasma constantly charges the dielectric substrate surface, the substrate surface voltage does not remain constant even when a constant voltage is applied to the substrate. In contrast, the conventional pulse power supply described in Patent Document 1 compensates for the ion current by supplying a direct current during the processing period, thereby maintaining a nearly constant substrate surface voltage. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2022-530078 Summary of the Invention [Problem to be solved by the invention]

[0005] The conventional pulse power supply described in Patent Document 1 includes a current source for supplying a constant DC current, as well as a voltage source for charging auxiliary voltage during commutation operation to promote charging and discharging of substrate capacitors and floating capacitors. This pulse power supply also includes resonant commutation means for applying in advance a voltage that is approximately half the charging auxiliary voltage to an LC series circuit of a capacitor, including a substrate capacitor, etc., and a floating inductor, such as a wiring, thereby reducing losses during commutation operation and improving the bias waveform.

[0006] However, the conventional pulse power supply described above has, in addition to a voltage source for forming a current source and a voltage source for auxiliary charging, additional voltage sources for pulse-on commutation and pulse-off commutation, and also requires switches to connect these voltage sources to the output. This results in a large circuit size and correspondingly higher costs. Furthermore, the on / off operation of multiple switches must be controlled individually, and the control is complicated because accurate management of the half-wave resonance period is required.

[0007] Generally, the waveform of the pulse bias voltage in a plasma etching apparatus is a negative pulse waveform in which the voltage changes in the negative direction (downward in a typical waveform diagram), and the actual etching process occurs at the peak of this negative pulse waveform. Therefore, in this specification, a voltage change (negative change) toward the peak of the pulse waveform where the etching process occurs is referred to as a voltage rise (or increase), and conversely, a voltage change from the peak of the pulse waveform where the etching process occurs toward the positive direction is referred to as a voltage drop (or drop, decrease). Furthermore, the relationship between high and low voltages is defined according to this voltage rise or drop (i.e., when a voltage rises from a certain voltage A to another voltage B, it is expressed as voltage A being lower than voltage B (and conversely, voltage B being higher than voltage A)).

[0008] The present invention has been made to solve the above-mentioned problems, and its main object is to provide a pulse power supply device for a plasma etching apparatus, which can apply a pulse bias with a good waveform to a substrate or the like while simplifying the circuit configuration and control, and a bias control method therefor. [Means for solving the problem]

[0009] One aspect of a bias control method according to the present invention is a bias control method for forming a pulsed voltage waveform at an output terminal of a pulse power supply device in order to supply a bias to a plasma reactor (Pr) including a processing object in a plasma etching apparatus, the method comprising: selectively supplying a DC current having a predetermined current value, a third DC voltage having a third voltage value (V3) and a fourth DC voltage having a fourth voltage value (V4) referenced to a ground potential to the output terminal; a) a first step of maintaining the output voltage at the output terminal at a low level by holding, in a capacitor load of a plasma reactor, a voltage that has dropped to a first voltage value (V1) lower than the third voltage value (V3) and the fourth voltage value (V4) due to half-wave resonance in a fourth step described below; b) a second step of coupling the third DC voltage to the output terminal and causing a current to flow by half-wave resonance in a resonant loop including at least the capacitor load and an inductor including a wiring between the pulsed power supply device and the plasma reactor, thereby increasing the output voltage; c) a third step of coupling the DC current to the output terminal when the output voltage reaches a potential of a predetermined fifth voltage value (V5) higher than the third voltage value (V3) due to the voltage increase in the second step, and further linearly increasing the output voltage over time using the DC current; d) a fourth step of coupling the fourth DC voltage to the output terminal instead of the DC current after the output voltage has increased to a potential that is a predetermined sixth voltage value (V6) in the third step, and causing a current to flow by half-wave resonance in a resonance loop that includes at least the capacitor load and the inductor, thereby decreasing the output voltage to the first voltage value; It has.

[0010] In the above-described aspect of the bias control method according to the present invention, as an example, when ΔV and Vc are respectively predetermined positive voltage values, the third voltage value (V3) can be ΔV / 2, the fourth voltage (V4) can be (ΔV-Vc) / 2, the first voltage value (V1) can be ΔV, the fifth voltage value (V5) can be 0, and the sixth voltage value (V6) can be -Vc.

[0011] In the above-described aspect of the bias control method according to the present invention, as another example, when ΔV and Vc are each a predetermined positive voltage value, the third voltage value (V3) can be 0, the fourth voltage value (V4) can be -Vc / 2, the first voltage value (V1) can be ΔV / 2, the fifth voltage value (V5) can be -ΔV / 2, and the sixth voltage value (V6) can be -(ΔV / 2)-Vc.

[0012] In the above-described aspect of the bias control method according to the present invention, as another example, when ΔV and Vc are respectively predetermined positive voltage values, the third voltage value (V3) can be −ΔV / 2, the fourth voltage value (V4) can be −(ΔV+Vc) / 2, the first voltage value (V1) can be 0, the fifth voltage value (V5) can be −ΔV, and the sixth voltage value (V6) can be −ΔV-Vc.

[0013] Furthermore, one aspect of the pulse power supply device for a plasma processing apparatus according to the present invention is a device for realizing the bias control method of the above aspect, and is a pulse power supply device that generates a pulsed voltage waveform between an output terminal (10) connected to a plasma reactor (Pr) including a processing object via wiring and a ground terminal (9) in order to supply a bias to the plasma reactor (Pr) in a plasma etching apparatus, a) a third voltage source (13) that generates a third DC voltage having a third voltage value (V3) referenced to ground potential; b) a fourth voltage source (14) that generates a fourth DC voltage having a fourth voltage value (V4) referenced to ground potential; c) a third switch (S3) that couples the third voltage source to the output; d) a fourth switch (S4) coupling the fourth voltage source to the output; e) a current source (12) having a current inflow end and a current outflow end, the inflow end being coupled to the output end via the third switch, and the outflow end being coupled to the ground end, and supplying a DC current of a predetermined current value; f) a fifth switch (S5) connected in parallel with the current source; g) a third diode (Da) for reverse blocking, which is arranged between the third switch and the third voltage source or between the third voltage source and the ground terminal, and which blocks current flow from the ground terminal side to the third switch side; h) a fourth diode (Db) for reverse blocking, connected in series with the fourth switch and the fourth voltage source, for blocking current flow from the output terminal to the ground terminal; i) a second diode (Dc) for reverse blocking, which is arranged between the inflow end of the current source and the third switch and blocks current flow from the current source to the third switch; j) by holding, in a capacitor load of the plasma reactor, a voltage that has been reduced to a potential of a first voltage value that is lower than the third voltage value and the fourth voltage value by a second half-wave resonance described later, the output voltage at the output terminal is maintained at a low level, and by turning on the third switch to couple the third voltage source to the output terminal, a current due to the first half-wave resonance flows in a resonance loop that includes at least the capacitor load and an inductor including the wiring, thereby raising the output voltage, and the voltage rise causes the output voltage to reach a potential of a predetermined fifth voltage value that is higher than the third voltage value, and further, by changing the third diode from a conducting state to a reverse blocking state, a control unit (20) that, when the output voltage rises to a potential of a predetermined sixth voltage value as a result of a DC current from the current source passing through the second diode flowing to a load, turns on the fourth switch to couple the fourth voltage source to the output terminal, includes at least the capacitor load and the inductor, and causes a current due to a second half-wave resonance to flow in a resonance loop including the fourth diode, thereby lowering the output voltage to the first voltage value, and turns on the fifth switch while the current due to the second half-wave resonance is flowing, thereby controlling the on / off operations of the third switch, the fourth switch, and the fifth switch to circulate the current from the current source through the fifth switch; Equipped with.

[0014] In the pulse power supply device for a plasma processing apparatus according to the above aspect, when the third voltage value is 0, the fifth switch is a semiconductor switching element, and the function of the third diode is substituted by a series circuit of the second diode and a parasitic diode of the fifth switch, thereby making it possible to omit the current path through the third diode.

[0015] Another aspect of the pulse power supply for a plasma processing apparatus according to the present invention is a pulse power supply for forming a pulsed voltage waveform between an output terminal connected to a plasma reactor including a processing object via wiring and a ground terminal in order to supply a bias to the plasma reactor in a plasma etching apparatus, a) a third voltage source that generates a third DC voltage having a third voltage value referenced to ground; b) a fourth voltage source generating a fourth DC voltage having a fourth voltage value referenced to ground; c) a third switch coupling the third voltage source to the output; d) a fourth switch coupling the fourth voltage source to the output; e) a current source having a current inflow end and an outflow end, the inflow end being coupled to the output end via the third switch, and the outflow end being coupled to the ground end, the current source supplying a DC current of a predetermined current value, the current source being configured by connecting a voltage source on the outflow end side and an inductor on the inflow end side in series; f) a third diode for reverse blocking that is arranged between the third switch and the third voltage source or between the third voltage source and the ground end and that blocks current flow from the ground end side to the third switch side; g) a fourth reverse-blocking diode connected in series to the fourth switch and the fourth voltage source, and blocking current flow from the output terminal to the ground terminal; h) a series circuit in which a fifth switch and a second reverse-blocking diode that blocks current flow in a direction from the output terminal to the ground terminal are connected in series, the series circuit being connected in parallel to the inductor that configures the current source; i) By holding the voltage that has dropped to a potential of a first voltage value that is lower than the third voltage value and the fourth voltage value by a second half-wave resonance described later in a capacitor load of the plasma reactor, and by keeping the output voltage at the output terminal at a low level, the third switch is turned on to couple the third voltage source to the output terminal, and by causing a current due to the first half-wave resonance to flow in a resonance loop that includes at least the capacitor load and an inductor including the wiring, the output voltage is increased, and due to this voltage increase, the output voltage reaches a potential of a predetermined fifth voltage value that is higher than the third voltage value, and further the third diode changes from a conductive state to a reverse blocking state. a control unit that, when the output voltage rises to a potential of a predetermined sixth voltage value by causing a DC current from the current source to flow to a load, turns on the fourth switch to couple the fourth voltage source to the output terminal, and causes a current due to a second half-wave resonance to flow in a resonance loop including at least the capacitor load and the inductor, and includes the fourth diode, thereby decreasing the output voltage to the first voltage value, and turns on the fifth switch while the current due to the second half-wave resonance is flowing, and controls on / off operations of the third switch, the fourth switch, and the fifth switch so as to return the current from the current source through the fifth switch; Equipped with.

[0016] In any of the above-described pulse power supply devices for a plasma processing apparatus, a high-speed constant current power supply may be provided in parallel with the current source.

[0017] It should be clear to those skilled in the art that the "ground potential" in the phrase "based on ground potential" does not necessarily mean strictly 0 V. For example, in this type of device, a current-limiting resistor (limiting resistor) is often inserted in series on the line leading to the ground terminal or output terminal (usually the ground terminal on the low-voltage side). In this case, since there is a voltage drop across the current-limiting resistor, even if the potential at the ground terminal is ground potential (0 V), the potential at the end of the current-limiting resistor opposite the ground terminal will naturally not be 0 V, but this potential will be used as the reference within the device. [Effects of the Invention]

[0018] In the conventional pulse power supply described in Patent Document 1, in the step corresponding to the first step in the above-described aspect of the bias control method of the present invention, a voltage source for maintaining the voltage of the capacitor load at a first voltage value and a switch for connecting the voltage source to the output terminal were provided. In contrast, the present inventors noticed that, at the pulse frequency generally used in bias pulse power supplies in plasma processing apparatuses, the voltage drop due to the charge accumulated in the capacitor load in the above-described first step is so small that it can be practically ignored, and came up with a configuration that achieves good commutation with suppressed voltage and current oscillations when transitioning from the fourth step to the first step without using a voltage source for maintaining the voltage of the capacitor load and a corresponding switch.

[0019] Furthermore, the conventional pulse power supply described above includes a switch that connects the current source to the output terminal, and in the step corresponding to the third step in the bias control method according to the present invention, the switch is turned on to connect the current source to the output terminal. In contrast, the present inventors have devised a configuration that utilizes the fact that the reverse-blocking diode through which the first half-wave resonant current flows can be switched between a conducting state and a blocking state, and switches the current path of the parallel-connected current sources between two paths—a short circuit caused by the reverse current of the diode and the load (output terminal)—without a selection switch, thereby functioning as both a switch that connects the current source to the output terminal and a switch that connects the third voltage source to the output terminal in the conventional pulse power supply. This makes it possible to achieve good commutation with reduced voltage and current oscillations even when transitioning from the second step to the third step.

[0020] In this way, according to the present invention, compared to conventional pulsed power supply devices, it is possible to simplify the circuit configuration by reducing devices such as voltage sources and switches, and furthermore, it is possible to apply a pulsed bias with a good waveform to a processing object while omitting the complicated control of matching the half-wave resonance period with the switching timing of the switches, thereby achieving good etching processing of processing objects such as substrates. [Brief explanation of the drawings]

[0021] [Figure 1] 1 is a conceptual diagram showing an example of the overall configuration of a plasma etching apparatus including a pulse power supply device according to the present invention; [Figure 2] FIG. 1 shows a simplified electrical equivalent circuit of the plasma reactor Pr. [Figure 3] 3A and 3B are diagrams showing examples of voltage waveforms of a substrate surface voltage Vsub, an output voltage Vop1, and a stage voltage Vop2. [Figure 4] 1 is a circuit diagram showing the principle of a pulse power supply unit according to a first embodiment of the present invention; [Figure 5] FIG. 4 is a circuit diagram showing the principle of a pulse power supply unit according to a second embodiment of the present invention. [Figure 6] FIG. 10 is a circuit diagram showing the principle of a pulse power supply unit according to a third embodiment of the present invention. [Figure 7] FIG. 6 is a practical schematic circuit diagram of the pulse power supply unit according to the second embodiment shown in FIG. 5. [Figure 8] FIG. 8 is a schematic circuit diagram according to a modification of the configuration shown in FIG. 7. [Figure 9] FIG. 10 is a diagram showing an example of waveform shapes of an output voltage and a substrate surface voltage in a transient state in a pulse power supply unit according to the second embodiment. [Figure 10] 10A and 10B are diagrams showing an example of waveforms at various points during a commutation period Ta in a pulsed power supply unit according to a second embodiment. [Figure 11] 10A and 10B are diagrams showing an example of waveforms at various points during a commutation period Tb in a pulsed power supply unit according to a second embodiment. [Figure 12] FIG. 10 is a schematic diagram showing a current path during a commutation period Ta (t0 to t1) in a pulse power supply unit according to a second embodiment. [Figure 13]FIG. 10 is a schematic diagram showing a current path during an etching treatment period Tp (t1 to t2) excluding a commutation period Ta in a pulse power supply unit according to a second embodiment. [Figure 14] FIG. 10 is a schematic diagram showing a current path during a commutation period Tb (t2 to t3) in a pulse power supply unit according to a second embodiment. [Figure 15] FIG. 10 is a schematic diagram showing a current path during a commutation period Tb (t3 to t4) in a pulse power supply unit according to a second embodiment. [Figure 16] FIG. 10 is a schematic diagram showing a current path during a commutation period Tb (t4 to t5) in a pulse power supply unit according to a second embodiment. [Figure 17] FIG. 10 is a schematic diagram showing a current path during a discharge period Td (t5 to t0) excluding a commutation period Tb in a pulse power supply unit of a second embodiment. [Figure 18] FIG. 10 is a schematic circuit diagram of a pulse power supply unit according to a modified example. [Figure 19] FIG. 10 is a schematic circuit diagram of a pulse power supply unit according to another modified example. [Figure 20] FIG. 1 is a schematic circuit diagram of a conventional pulse power supply device. DETAILED DESCRIPTION OF THE INVENTION

[0022] [Plasma etching equipment configuration] FIG. 1 is a conceptual diagram showing a typical example of the overall configuration of a plasma etching apparatus using a pulse power supply device according to the present invention. As shown in FIG. 1, the plasma etching apparatus includes a process control unit 1, an ion source plasma power supply unit 2, a bias pulse power supply unit 3, and a processing chamber 4.

[0023] Although not shown, the processing chamber 4 is equipped with an ion source that receives power supplied from the ion source plasma power supply unit 2 and generates plasma 5 from the introduced etching gas by various methods, such as inductively coupled plasma (ICP), electron cyclone resonance (ECR) plasma, or helicon wave plasma (HWP).

[0024] On the other hand, the bias pulse power supply unit 3 applies a pulsed bias to the substrate 6 to be processed in order to attract ions in the plasma 5 by imparting kinetic energy to them. To obtain a desired (usually narrow, single) IED on the surface 6a of the dielectric substrate 6, the bias pulse power supply unit 3 supplies current to the substrate 6 via the stage 7 so that the voltage value on the surface 6a of the substrate 6 remains substantially constant during a predetermined processing period. In this plasma etching apparatus, the ion source plasma power supply unit 2 and the bias pulse power supply unit 3 are provided separately, and the process control unit 1 controls the power supplies 2 and 3 independently, thereby increasing the flexibility of the etching process. In the following description, the entire processing chamber 4 containing the plasma 5 will be referred to as the plasma reactor Pr, as is customary.

[0025] [Equivalent circuit of plasma reactor Pr] Fig. 2 is a diagram mainly showing a simplified electrical equivalent circuit of the plasma reactor Pr, which is the load of the bias pulse power supply unit 3. In Fig. 2, the equivalent circuit of the substrate-side ion sheath and the equivalent circuit of the wall-side ion sheath in the plasma reactor Pr are combined, and some of them are omitted.

[0026] 2, Rp is the DC resistance of the ion sheath (hereinafter referred to as "sheath resistance"), Cp is the inductive capacitor of the substrate 6 (hereinafter referred to as "substrate capacitor"), Dp is an equivalent diode due to the rectifying action of the ion sheath (hereinafter referred to as "sheath diode"), Cs is the capacitor of the ion sheath (hereinafter referred to as "sheath capacitor"), Zp is the plasma bulk resistance (hereinafter referred to as "plasma resistance"), and Cn is the total floating-to-ground capacitor (hereinafter referred to as "floating capacitor"). Furthermore, Ln is an inductor (hereinafter referred to as "wiring inductor") mainly resulting from the wiring connecting the pulse power supply unit 3 and the plasma reactor Pr, and Cb is a blocking capacitor provided on the wiring.

[0027] In Figure 2, the ion sheath rectification, which is caused by the difference in mobility between ions and electrons in the plasma, is represented by a parallel circuit consisting of a sheath diode Dp and a sheath resistance Rp. The sheath resistance Rp corresponds to the ion current, and the forward resistance of the sheath diode Dp corresponds to the electron current, each as a DC resistance. These elements, plus a sheath capacitor Cs, are connected in parallel. A plasma resistance Zp is connected to one end of this parallel circuit, and a substrate capacitor Cp is connected to the other end. A floating capacitor Cn is also connected to both ends of this series circuit. The junction between the plasma resistance Zp and the floating capacitor Cn is connected to the ground terminal 9 of the pulse power supply unit 3 and is also grounded. The junction between the substrate capacitor Cp and the floating capacitor Cn is connected to the output terminal 10 of the pulse power supply unit 3 via a series circuit consisting of a blocking capacitor Cb and a wiring inductor Ln.

[0028] The surface 6a of the substrate 6 is the connection point between the other end of the parallel circuit of the sheath diode Dp, sheath resistor Rp, and sheath capacitor Cs and the substrate capacitor Cp, and the voltage generated between this connection point and ground is the substrate surface voltage Vsub. The floating capacitor Cn, substrate capacitor Cp, and sheath capacitor Cs form a capacitor load, and in a typical example, their capacitance ratio is Cn ≒ 5 Cp, Cp ≒ 20 Cs. Typically, the capacitance of the sheath capacitor Cs is significantly smaller than the capacitance of the other components, so it can be effectively ignored in circuit operation. Therefore, in Figure 2, the connection line for the sheath capacitor Cs is shown with a dashed line.

[0029] In the following description, the symbols indicating each component and the symbols specifying the voltage or current at a specific location are also used as symbols representing the numerical values ​​of the parameters of the component itself. For example, a symbol indicating a specific capacitor, such as Cp described below, is also used as a symbol indicating the capacitance value of the capacitor, and a symbol indicating a voltage at a specific position, such as Vop1, is also used as a symbol indicating the voltage value of that voltage.

[0030] [Waveforms of substrate surface voltage Vsub and output voltage Vop1] 3 is a diagram showing an example of the waveforms of the substrate surface voltage Vsub, output voltage Vop1, and stage voltage Vop2 shown in FIG. 2. As described above, the substrate surface voltage Vsub is a voltage generated between the surface 6a of the substrate 6 and ground. The output voltage Vop1 is a voltage generated by the output from the pulse power supply unit 3 between the junction point between the wiring inductor Ln and the blocking capacitor Cb connected to the output terminal 10 and ground. The stage voltage Vop2 is a voltage generated between the stage 7 and ground.

[0031] The output voltages Vop1 shown in Figures 3(b1) to 3(b3) are the output voltages Vop1 of the pulsed power supply units 3 of the first to third embodiments, which are respectively different and shown in Figures 4 to 6, which will be described later. The numbers in brackets [ ] shown on the right side of Figures 3(b1) to 3(b3) correspond to the symbols indicating the voltage sources that generate the voltages shown in the waveform diagrams in the schematic circuit diagrams of the pulsed power supply units of the respective embodiments shown in Figures 4 to 6.

[0032] In Figure 3, period T is one cycle of the pulse waveform, and during etching, this pulsed bias is repeatedly applied to the substrate 6. The repetition frequency of the pulse waveform is determined appropriately, but as an example, the repetition frequency is several hundred kHz. For example, when the frequency is 400 kHz, the period T is 2.5 μs. Within this period T, Tp excluding period Ta is the etching processing period during which the actual etching processing of the substrate 6 is performed. Generally, when a narrow single IED is required on the substrate 6 as described above, the substrate surface voltage Vsub needs to be maintained at a certain voltage value during the etching processing period, as shown in Figure 3(a).

[0033] Between two adjacent etching processing periods Tp, a discharge period Td is provided to discharge the charges accumulated in the substrate capacitor Cp and the floating capacitor Cn during the etching process. Ta is the commutation period from the end of the discharge period Td to the transition to the etching processing period Tp, while Tb is the commutation period from the end of the etching processing period Tp to the transition to the discharge period Td. As described above, when T = 2.5 μs and the maximum duty ratio of the etching processing period Tp is 80%, Tp = 2 μs and Td = 0.5 μs. To increase the etching efficiency by widening the effective etching processing period Tp for a narrow single IED while keeping the period T constant, i.e., with a constant repetition frequency, it is desirable to shorten the commutation periods Ta and Tb as much as possible.

[0034] As described above, in order to maintain the substrate surface voltage Vsub at a constant voltage during the etching processing period Tp excluding the commutation period Ta, the pulse power supply unit 3 sets the current Icp flowing through the substrate capacitor Cp to a constant negative pulse current during that period Tp. The waveform of the output voltage Vop1 during this period Tp is a combination of the incremental change in the capacitor load voltage due to the output current Io (=Ic), Vc ≈ Ic·t / (Cp + Cn), and the auxiliary charging voltage change ΔV ≈ Vsub (both potential differences) for rapidly achieving the substrate surface voltage Vsub during the commutation period Ta when the pulse is on. The former forms a ramp-shaped waveform with a substantially constant slope during the period Tp.

[0035] In the pulsed power supply units of the first to third embodiments according to the present invention, the voltage value of the output voltage Vop1 at time t5 is the voltage V1 due to the charge accumulated in the capacitor load Cre, which is a combination of the substrate capacitor Cp and the floating capacitor Cn. The voltage V1 having a value of +ΔV is the output voltage Vop1 from the pulsed power supply unit of the first embodiment shown in Figure 3(b1), the voltage V1 having a value of +ΔV / 2 is the output voltage Vop1 from the pulsed power supply unit of the second embodiment shown in Figure 3(b2), and the voltage V1 having a value of 0 is the output voltage Vop1 from the pulsed power supply unit of the third embodiment shown in Figure 3(b3).

[0036] The substrate surface voltage Vsub is expressed as the voltage drop across the sheath resistance Rp and plasma resistance Zp due to the current Icp flowing through the substrate capacitor Cp (assuming the forward resistance of the sheath diode Dp is zero and the reverse resistance is infinite). During the etching process period Tp, excluding the commutation period Ta, Vsub = -Icp · (Rp + Zp) when the current Icp is constant. Also, after the sheath diode Dp becomes conductive during the discharge period Td, Vsub = Icp · Zp. The resistance of the plasma resistance Zp is small, at most a few ohms, and the current Icp can rapidly discharge the accumulated charge in the substrate capacitor Cp. As shown in Figure 2, the current Io output from the pulse power supply during the etching process period Tp is divided into Icn and Icp, and Icp ≈ -Io · Cp / (Cp + Cn).

[0037] In a pulsed power supply unit 3 of a second embodiment described later, the output voltage Vop1 during the discharge period Td, excluding the commutation period Tb, is V1 = +ΔV / 2. The specific operation of the pulsed power supply unit 3 will be described later. During the commutation period Ta, a half-wave resonant current is passed through the capacitor load Cre to rapidly charge the capacitor load. This causes the output voltage Vop1 to rapidly rise from +ΔV / 2 to -ΔV / 2. On the other hand, during the commutation period Tb, a half-wave resonant current is passed from the capacitor load Cre to rapidly discharge the capacitor. This causes the output voltage Vop1 to rapidly drop from -ΔV / 2 - Vc to +ΔV / 2. As a result, the output voltage Vop1 has the shape shown in Figure 3(b2).

[0038] The stage voltage Vop2 is the waveform of the output voltage Vop1, which is given a DC floating zero potential by the blocking capacitor Cb, shifted negatively (or positively) by the DC voltage, which is the average voltage of the substrate surface voltage Vsub. Therefore, as shown in Figures 3(b1) to 3(b3), when the potential difference (absolute value) between ΔV and Vc is the same, the stage voltage Vop2 has the same waveform as shown in Figure 3(c), regardless of the polarity of the voltage that generates the potential difference. The blocking capacitor Cb is provided to prevent DC current generated by an external voltage from flowing into the pulsed power supply unit 3, and its capacitance is set to, for example, Cb ≈ 50 · Cn. However, it will be clear to those skilled in the art that the blocking capacitor Cb is not an essential component of the present invention and can be omitted as appropriate.

[0039] [Configuration and operation of a pulse power supply unit according to one embodiment of the present invention] 4 to 6 are circuit diagrams showing the principle of the pulse power supply unit 3 according to first to third embodiments, which are aspects of the present invention.

[0040] 4 to 6, in the pulse power supply unit 3 of each of these embodiments, a series circuit of a third voltage source 13 outputting a voltage value V3, a third reverse-blocking diode Da, and a third switching unit S3, and a series circuit of a fourth voltage source 14 outputting a voltage value V4, a fourth diode Db, and a fourth switching unit S4 are connected between a first node N1 connected to a ground terminal 9 and a second node N2 connected to an output terminal 10. A series circuit of a current source 12 supplying a constant current Ic and a second reverse-blocking diode Dc is connected between a fourth node N4, which is a connection point between the third diode Da and the third switching unit S3, and the first node N1, and a fifth switching unit S5 is connected between the connection point between the current source 12 and the second diode Dc and the first node N1.

[0041] The voltage values ​​V3 and V4 are different in the first to third embodiments. In the pulsed power supply unit 3 of the first embodiment, V3 = ΔV / 2 and V4 = (ΔV - Vc) / 2. In the pulsed power supply unit 3 of the second embodiment, V3 = 0 and V4 = -Vc / 2. In the pulsed power supply unit 3 of the third embodiment, V3 = -ΔV / 2 and V4 = (ΔV + Vc) / 2. However, ΔV and Vc ≠ 0. That is, in the pulsed power supply unit 3 of the second embodiment, V3 = 0, so both ends of the third voltage source 13 are short-circuited, and the third voltage source 13 does not actually exist. However, for the purpose of explaining the operation, it is assumed that a third voltage source 13 that outputs 0 V is provided, and in FIG. 5, this voltage source 13 is indicated by a dashed line.

[0042] The operation of the pulse power supply unit of the second embodiment shown in Fig. 5 will be described in detail below. The reason why the second embodiment is chosen among the first to third embodiments is that, as is clear from Figs. 4 to 6, it has the advantage that the third voltage source 13 is substantially unnecessary, thereby reducing the number of voltage sources required. Fig. 7 is a circuit diagram focusing on a more practical schematic circuit of the pulse power supply unit 3 of the second embodiment.

[0043] In Figure 7, current source 12, which outputs a constant current Ic, is composed of a series circuit connecting inductor Lo (with an inductance of approximately 2 mH), voltage source 15, and current sensor Ct1 (although it is clear that current sensor Ct1 is not directly related to the current supply itself). Switching units S3, S4, and S5 each consist of semiconductor switching elements such as power MOSFETs, and anti-parallel diodes D3, D4, and D5 are parasitic diodes of the semiconductor switching elements. Other than these, the circuit is the same as in Figure 5: a fifth switching unit S5 for shorting is connected in parallel to current source 12, and a series circuit of a third diode Da for half-wave resonance and the third switching unit S3 is connected between a first node N1, which is the connection point of ground terminal 9, and a second node N2, which is the connection point of output terminal 10. The connection point between the third diode Da and the third switching unit S3 is a fourth node N4, and the other end of the voltage source 15 is connected to the first node N1, and the other end of the current sensor Ct1 is connected to the fourth node N4 via a second reverse-blocking diode Dc. In addition, one end of a fourth diode Db for half-wave resonance is connected to one end of a fourth voltage source 14, and the other end is connected to one end of a fourth switching unit S4, forming a series circuit, and the other end of the fourth voltage source 14 is connected to the first node N1, and the other end of the fourth switching unit S4 is connected to the second node N2.

[0044] It is also possible to adopt a configuration in which the other end of the fourth switching unit S4 is a third node N3 and an inductor Li is additionally inserted between this third node N3 and the second node N2. Although this is limited to the second embodiment (i.e., when V3=0), it is also possible to adopt a configuration in which the third diode Da is replaced by a series circuit of an anti-parallel diode D5, which is a parasitic diode of the fifth switching unit S5 connected in parallel to the third diode Da, and a second diode Dc for reverse blocking, thereby omitting the third diode Da. In other words, it is also possible to adopt a configuration in which the wiring between the fourth node N4 and the first node N1, which is connected via the third diode Da, is omitted. This configuration further reduces the number of devices used, which is advantageous in terms of cost.

[0045] The configuration around current source 12 can be modified as shown in Fig. 8. In this modification shown in Fig. 8, current source 12 is configured as a circuit in which inductor Lo, voltage source 15, and current sensor Ct1 are connected in series, but unlike the configuration shown in Fig. 7, a fifth switching unit S5 for short-circuiting is connected to the connection point between inductor Lo and voltage source 15 via a second diode Dc for reverse blocking. The connection point between the third diode Da and the third switching unit S3 may be set as a fourth node N4, and the end of current sensor Ct1 opposite to the side connected to inductor Lo may be connected to the fourth node N4.

[0046] The control unit 20 receives command signals from the process control unit 1, including values ​​such as the voltage value of the substrate surface voltage Vsub, the processing cycle T (pulse frequency: PW-f), and the processing period Tp. The control unit 20 also monitors the output voltage Vop1 and sends control signals G3, G4, and G5 to the switching units S3, S4, and S5, controlling their on / off operations according to a predetermined algorithm. The control unit 20 also detects the current flowing through the inductor Lo using a current sensor Ct1 and variably controls the current Ic of the current source 12 by varying the voltage Vo of the voltage source 15. The control unit 20 also samples the values ​​of the substrate surface voltage Vsub, the output current Io of the device, the output voltage Vop1, and other parameters over time during the period Tp, and variably controls the voltage V4 from the fourth voltage source 14 and, if necessary, the voltage V3 from the third voltage source 13 (although in the example of FIG. 7, the third voltage source 13 is short-circuited) to optimal values.

[0047] The control unit 20 can be configured to include a high-speed logic circuit, such as an FPGA (Field Programmable Gate Array), a microcomputer including a CPU, ROM, a timer, etc., and an AD converter, and can generate control signals, etc. for performing the processing described below by executing processing according to a pre-set program.

[0048] 3 shows steady-state operation during etching processing, but before explaining this steady-state operation, we will explain the operation in the initial state before transitioning to steady-state operation. In the initial state of operation, the voltage held in the capacitor load Cre is 0. In the pulsed power supply unit 3 of the second embodiment, as shown in FIG. 3(b2), initial operation accompanied by a transient phenomenon is performed until the output voltage Vop1 during the discharge period Td reaches V1=+ΔV / 2.

[0049] Figure 9 shows the waveforms of the substrate surface voltage Vsub and output voltage Vop1 in a transient state obtained by simulation using the pulse power supply unit 3 of the second embodiment shown in Figures 5 and 7, with the following element constants: Cn = 20 nF, Cp = 3.3 nF, Cs = 300 pF, Cb = 0.5 μF, Ln = 0.2 μH, Rp = 800 Ω, Zp = 5 Ω, Ic = 3.5 A, V4 = 90 V, fp = 400 kHz, Tp = 2 μs, and Td = 0.5 μs. This result shows that by repeating the same control as in the steady-state operation described below, the voltage held across the capacitor load Cre gradually changes and reaches a steady state after a certain amount of time. Under these conditions, the steady state is reached after approximately 10 cycles (25 μs) of transient state.

[0050] Next, steady-state operation of the pulse power supply unit will be described with reference to Figs. 10 to 17. Fig. 10 is a waveform diagram of various parts of the pulse power supply unit 3 of the second embodiment, including the output current Io during the commutation period Ta, the voltage Vop1 between the junction point of the blocking capacitor Cb and the wiring inductor Ln and ground, the substrate capacitor current Icp, the substrate surface voltage Vsub, and the control signals G3, G4, and G5 of the switching unit. Fig. 11 is a waveform diagram of various parts of the pulse power supply unit of the second embodiment, including the output current Io during the commutation period Tb, the output voltage Vop1, the substrate capacitor current Icp, the substrate surface voltage Vsub, and the control signals G3, G4, and G5 of the switching unit. Figs. 12 to 17 are schematic diagrams showing the current paths during the periods shown in Figs. 3(b2), 10, and 11.

[0051] As will be explained later, before time t0, the control signal G3 is low, the third switching unit S3 is off, and the anti-parallel diode D4 of the fourth switching unit S4 is not conductive due to reverse blocking by the fourth diode Db for half-wave resonance. Therefore, the capacitor load Cre is disconnected from the circuit within this device, and the output voltage Vop1 is the voltage maintained by the accumulated charge in the capacitor load Cre. In other words, the output voltage Vop1 is maintained at V1 = +ΔV / 2. Furthermore, the stage voltage Vop2, which is the voltage of the floating capacitor Cn (equal to the voltage of Cp in this case), is shifted from the output voltage Vop1 by the voltage across the blocking capacitor Cb.

[0052] 10, at time t0, the control signal G4 changes from high to low, and the control signal G3 changes from low to high. The control signal G5, which is high at that time, changes to low after an overlap period Tf, which may be substantially zero. When the control signal G5 is high and the fifth switching unit S5 is on, the current source 12 maintains the current of the inductor Lo (the constant current Ic of the current source 12 during the discharge period Td) by circulating it.

[0053] At time t0, when the control signal G3 changes to high and the third switching unit S3 turns on, the third diode Da becomes forward biased, and the voltage Vpn between the first node N1 and the fourth node N4 becomes approximately 0. As a result, a resonant current resulting from the capacitor load Cre and wiring inductor Ln combined with the output voltage Vop1(t0), which has been maintained at a voltage value ΔV / 2 as described above, flows as the output current Io through the path indicated by the solid arrow in Figure 12. This resonant current is Io=-[(ΔV / 2) / √(Ln / Cre)]·sinθ.

[0054] When the control signal G5 changes to low and the fifth switching unit S5 turns off, the resonant current Io flows, causing a constant current Ic to flow back from the current source 12 through the third diode Da, which is conductive. The output voltage Vop1 is expressed as (ΔV / 2)·cosθ. Since the output voltage Vop1 changes from ΔV / 2 (= V1) at time t0 to -(ΔV / 2) (= V5) at time t1, the voltage change during the commutation period Ta is equal to the auxiliary charging voltage change ΔV ≒ Vsub. Because the stage voltage Vop2 flows through the blocking capacitor Cb, it floats at zero point in a DC sense. Therefore, the stage voltage Vop2 is determined solely by the voltage difference between the two voltages, regardless of polarity, as shown in Figure 3(c). Therefore, there is no problem in obtaining the auxiliary charging voltage change ΔV during commutation operation from ΔV / 2 through resonance. The commutation period Ta at this time can be calculated using the half-wave resonance period determined by L·C = π√(Ln·Cre).

[0055] In this way, the difference between the stage voltage Vop2, which changes rapidly due to resonance, and the voltage across the substrate capacitor Cp, which changes slowly due to the action of the sheath resistance Rp, is the substrate surface voltage Vsub. The current Icp flowing through the path indicated by the dashed arrow in Figure 12 is roughly the voltage value of the substrate surface voltage Vsub at this time divided by the resistance value of the series circuit consisting of the sheath resistance Rp and the plasma resistance Zp, and this current joins with the current Icn to become the output current Io.

[0056] After time t1, the output current Io due to the resonant current attempts to reverse direction, but the resonant current stops because the third diode Da is reverse-biased. The constant current Ic supplied from current source 12, which had previously flowed backward through the third diode Da, now flows through the resonant path as Io = Ic, resulting in a current source with a very high output impedance connected in series with the resonant path. This prevents any voltage or current oscillations due to the wiring inductor Ln and the capacitor load Cre, even immediately after resonant commutation. However, when the output current Io switches from the resonant current to the constant current Ic, a momentary current interruption may occur due to the reverse recovery time of the third diode Da. To suppress the resulting surge voltage on Vpn, a voltage clamp circuit or voltage clamp element such as a TVS (Transient Voltage Suppressor) may be inserted between the first node N1 and the fourth node N4.

[0057] The operation during the commutation period Ta described above can be achieved without components such as the third voltage source 13 and the second switching unit S2 that are included in conventional pulse power supplies (see FIG. 20 described later), and without commutation time management that matches the half-wave resonance period.

[0058] After the commutation period Ta ends, the constant current Ic supplied from current source 12 flows as output current Io, as indicated by the bold arrow in Figure 13, and is divided into current Icp flowing through substrate capacitor Cp and current In flowing through floating capacitor Cn. As a result, output voltage Vop1 increases in the negative direction from V5 = -ΔV / 2 at a substantially constant rate, generating a ramp-shaped voltage waveform as shown in Figure 3(b2). At this time, current Icp and substrate surface voltage Vsub are determined by the following equations: Icp ≒ -Ic Cp / (Cp + Cn) Vsub=-Icp·(Rp+Zp) Here, the third switching unit S3, which is turned on to pass a resonant current in Fig. 12, is used to pass a constant current Ic in Fig. 13. In this way, in this pulse power supply unit 3, circuits (specifically, switching units) that were provided separately in a conventional pulse power supply device (see Fig. 20) are shared.

[0059] 11, just before time t2, the control signal G3 is high and the control signals G5 and G4 are both low, and at time t2, the control signals G4 and G5 both change to high, and then, after a predetermined overlap period Tf has elapsed, the control signal G3 changes to low. Tf may be substantially 0. After that, the state in which the control signal G3 is low and the control signals G5 and G4 are both high is maintained until just before the aforementioned time t0.

[0060] To explain in order, at the end of the steady-state etching period Tp, the control signal G3 is in a high state, the third switching unit S3 is in an on state, and the constant current Ic from the current source 12 is divided into the loads, the substrate capacitor Cp and the floating capacitor Cn, with Io=Ic as described above. The output voltage at time t2 is determined by Vop1(t2)=-((ΔV / 2)+Vc)=-[(ΔV / 2)+Ic·(Tp-Ta) / (Cp+Cn)].

[0061] At time t2, when the control signal G4 changes to high and the fourth switching unit S4 turns on, a resonant current Idb (=Io) due to the capacitor load Cre and the combined inductor (Ln+Li) flows through the path shown in FIG. 14 as a result of the confluence of the currents Icp and Icn. Here, the output voltage Vop1(t2)=-((ΔV / 2)+Vc) (=V6) at time t2 changes to the output voltage Vop1=+ΔV / 2 (=V1) at time t4 due to resonance, and the initial resonant voltage value in this case is (ΔV+Vc) / 2. The voltage value V4=-Vc / 2 of the voltage source 14 is a correction value based on the first node N1 to obtain this initial resonant voltage value from the output voltage Vop1 at time t2. The resonant current value is expressed as Io=Idb=[{(Vc+ΔV) / 2} / √{(Ln+Li) / Cre}]·sinθ. The inductor Li is provided to correct the increase in the resonant current caused by the increase in the difference Vc / 2 between the initial resonant voltages at time t0 and time t2, by increasing the characteristic impedance.

[0062] Furthermore, the substrate surface voltage Vsub is the potential difference between the stage voltage Vop2, which changes rapidly due to resonance, and the voltage Vcp of the substrate capacitor Cp, which changes slowly due to the sheath resistance Rp. Since Vop2 > Vcp in Figure 11, the substrate surface voltage Vsub becomes negative, and the diode Dp, which is rectified by the ion sheath, is reverse blocked and does not conduct. Therefore, the current Icp of the substrate capacitor Cp, shown by the dashed arrow in Figure 14, is roughly the substrate surface voltage Vsub in this case divided by the combined resistance (Rp + Zp).

[0063] On the other hand, when the control signal G5 changes to high and the switching unit S5 turns on, the current Ic flowing through the inductor Lo is circulated and maintained along the path indicated by the dashed-dotted arrow in Figure 14. Then, after the overlap period Tf has elapsed, the control signal G3 changes to low and the third switching unit S3 turns off.

[0064] At time t3, the stage voltage Vop2, which decreases rapidly, and the voltage Vcp of the substrate capacitor Cp, which changes slowly due to the sheath resistance Rp, become equal, and the substrate surface voltage Vsub becomes zero. After time t3, when Vcp > Vop2, the diode Dp becomes conductive due to the ion sheath rectification, and current Icp flows, as shown by the dashed arrow in Figure 15. This current Icp is calculated by dividing the substrate surface voltage Vsub by resistance Zp, and increases significantly. At this point, the substrate surface voltage Vsub exceeds zero and becomes a positive voltage, contributing to the discharge of the charge stored in the substrate capacitor Cp during the discharge period Td. Furthermore, the current Ic flowing through inductor Lo is maintained as described above.

[0065] At time t4, the resonant current Idb (=Io) becomes 0, and thereafter, the current Idb (=Io) remains 0 because the half-wave resonant diode Db prevents reverse flow. Here, the energy stored in inductors Ln and Li is lost, so Icp=Icn flows in the direction that charges the floating capacitor Cn, as shown by the dashed arrow in Figure 16. Also, as shown by the dashed-line arrow in Figure 16, the current Ic flowing through inductor Lo is maintained in the same manner as described above.

[0066] At time t5, the stage voltage Vop2 and the voltage Vcp of the substrate capacitor Cp become the same value, and the substrate surface voltage Vsub again becomes 0. Therefore, after time t5, as shown in Figure 17, the current Icp stops flowing, and the output voltage Vop1 is maintained at V1 = +ΔV / 2, which is the holding voltage due to the accumulated charge in the capacitor load Cre.

[0067] As will be described later, the operation during the commutation period Tb described above can be achieved without the need for voltage source 11, switching unit S1, and commutation time management in accordance with the half-wave resonance period, which were necessary in a conventional pulse power supply (see FIG. 20). Also, as shown by the dashed-dotted arrow in FIG. 17, the current Ic flowing through inductor Lo is maintained in the same manner as described above.

[0068] 7 does not require components such as voltage source 11, voltage source 13, first switching unit S1, and second switching unit S2, and does not require commutation time management during commutation periods Ta and Tb, as compared to conventional pulse power supplies, as will be described later. Furthermore, the only parts that require operational control are two: the voltage value Vo (constant current control value setting for Ic) of voltage source 15, which varies the current Ic from current source 12, and the voltage value V4=-Vc / 2 of voltage source 14, which is a correction value for obtaining the output voltage Vop1(t4) of +ΔV / 2 through resonance; and the control signals G3, G4, and G5, which control the on / off of three switching units S3, S4, and S5 according to the etching process period Tp.

[0069] The pulsed power supply unit of the first embodiment, which has the circuit principle shown in FIG. 4 for generating the output voltage Vop1 shown in FIG. 3(b1), and the pulsed power supply unit of the third embodiment, which has the circuit principle shown in FIG. 6 for generating the output voltage Vop1 shown in FIG. 3(b3), are similar to the pulsed power supply unit of the second embodiment, in that the current source 12 is configured as a series circuit of an inductor Lo, a voltage source 15, and a current sensor Ct1, and the switching units S3, S4, and S5 and the anti-parallel diodes D3, D4, and D5 are semiconductor switching elements (including parasitic diodes) such as power MOSFETs. The remaining configurations are similar to those shown in FIG. 4 for the first embodiment and FIG. 6 for the third embodiment. Therefore, practical schematic circuit diagrams for the pulsed power supplies of the first and third embodiments are easily conceivable, and therefore will not be described here.

[0070] The differences from the second embodiment are that the voltage value V3 of the third voltage source 13 is V3=0 (=short circuit) in the second embodiment, but V3=+ΔV / 2 in the first embodiment and V3=+ΔV in the third embodiment, and that the voltage value V4 of the fourth voltage source 14 is V4=-Vc / 2 in the second embodiment, but V4=(ΔV-Vc) / 2 in the first embodiment and V4=-(ΔV+Vc) / 2 in the third embodiment. The timings of the control signals G3, G4, and G5 for controlling the on / off of the third to fifth switching units in Figures 10 and 11 are common to the first to third embodiments.

[0071] That is, compared to the output voltage Vop1 of the pulsed power supply unit of the second embodiment shown in Fig. 3(b2), the output voltage Vop1 of the pulsed power supply unit of the first embodiment shown in Fig. 3(b1) has its entire waveform shifted to the positive side by +ΔV / 2, and the output voltage Vop1 of the pulsed power supply unit of the third embodiment shown in Fig. 3(b3) has its entire waveform shifted to the negative side by -ΔV / 2. Those skilled in the art will easily realize that the same is true for the waveforms shown in Fig. 10 and Fig. 11.

[0072] Furthermore, in the pulse power supply units of all the embodiments, there is no difference in the shapes of the waveforms Vsub, Io, Ic, Icp, and Idb other than the control signals shown in Figures 10 and 11, and it is clear that the current paths and directions for each period shown in Figures 12 to 17 are also the same.

[0073] Furthermore, the series of operations for generating the output voltage Vop1 in the pulsed power supply unit in each embodiment is basically the same, and as described above, the stage voltage Vop2 and the operation within the plasma reactor Pr are also the same in all embodiments, so an appropriate embodiment can be selected depending on the number of parts, the voltage shape from the ground terminal, etc.

[0074] [Comparison of the pulse power supply according to the present invention with the conventional pulse power supply] To clarify the advantages of the pulse power supply unit 3 of this embodiment described above over the conventional pulse power supply described in Patent Document 1, the configurations of the devices will be compared. Fig. 20 is a circuit diagram showing the principle of a conventional pulse power supply unit 3P. In Fig. 20, components that are the same as or equivalent to those in the pulse power supply unit 3 of the embodiment shown in Figs. 4 to 6 are assigned the same reference numerals to clearly show the comparison of the components. The load circuits are exactly the same.

[0075] That is, the conventional pulsed power supply 3P includes a series circuit between the first node N1 and the second node N2, which includes a voltage source 11 that outputs a voltage V1 and a switching unit S1, as a component not included in the pulsed power supply unit 3 of the embodiment of the present invention. When it is desired to generate an output voltage equivalent to the output voltage Vop1 generated by the pulsed power supply unit 3 of the first embodiment shown in Figure 3(b1), the voltage values ​​of the voltage sources 11, 13, and 14 are V1 = ΔV, V3 = ΔV / 2, and V4 = (ΔV - Vc) / 2, as shown in Figure 20. The switching unit S1 determines the timing at which this voltage V1 is coupled to the output terminal 10.

[0076] In the conventional pulse power supply 3P, the voltage V1 from the voltage source 11 is set to the same value as the voltage of the capacitor load formed by half-wave resonance between the capacitor load Cre and the wiring inductor Ln (the voltage value of the output voltage Vop1 at time t5 in Figure 3(b1)). In addition, by detecting zero of the resonant current in the half-wave resonant circuit during the commutation period Tb, the optimal commutation time is set to determine the timing for turning on the switching unit S1 and coupling the voltage V1 to the output terminal 10. This fixes the output voltage Vop1 to V1 = +ΔV during the discharge period Td and prevents ringing of the load voltage when the switching unit S1 is turned on.

[0077] In contrast, the pulse power supply unit 3 of this embodiment does not include the voltage source 11 and the switching unit S1, and does not set an optimal commutation time during the commutation period Tb. In a typical plasma reactor Pr, the capacitance of the capacitor load Cre is 10 to 20 nF, which is a sufficiently large value to maintain the charge accumulated in the capacitor load during the discharge period Td corresponding to a pulse frequency of approximately fp=400 kHz. That is, at a pulse frequency of approximately fp=400 kHz, the voltage of the capacitor load during the discharge period Td can be sufficiently maintained (the voltage drop is substantially negligible) without applying voltage V1 from the voltage source 11 as in the conventional pulse power supply 3P. Therefore, the pulse power supply unit 3 of this embodiment does not include the voltage source 11 and the switching unit S1, and setting the optimal commutation time using the switching unit S1 can also be eliminated.

[0078] Furthermore, the conventional pulse power supply 3P is provided with independent switching units S2, which determines the timing of flowing current Ic supplied from current source 12 to output terminal 10, and S3, which flows a resonant current due to capacitor load Cre (≈Cn) and wiring inductor Ln and determines the timing of coupling voltage V3 from voltage source 13 to output terminal 10. In contrast, in the pulse power supply 3 of this embodiment, a series circuit of third voltage source 13, reverse-blocking third diode Da, and third switching unit S3 is connected between the first node N1 and the second node N2, the junction of the third diode Da and the third switching unit S3 is set as a fourth node N4, a series circuit of current source 12 and reverse-blocking second diode Dc is connected between the first node N1 and the fourth node N4, and a fifth switching unit S5 for short-circuiting is connected across the current source 12. This makes it possible to omit the switching unit S2 in the conventional pulse power supply device 3P, and to have the third switching unit S3 also perform the function of this switching unit S2.

[0079] Thus, in the pulsed power supply unit 3 of this embodiment, the number of devices can be reduced compared to the conventional pulsed power supply 3P, simplifying the circuit configuration, and it is also possible to omit the complicated detection and control required to match the switching timing with the resonant commutation time.

[0080] [Modification of the pulse power supply unit of this embodiment] 18 is a schematic diagram of a pulse power supply unit of the fourth embodiment, in which a voltage clamp circuit is added to the pulse power supply unit 3 of the second embodiment. These voltage clamp circuits TVS1, TVS2, and TVS3 have the function of absorbing energy when inductors Lo, Ln, and Li are released, respectively. Here, the voltage clamp circuit is simply configured as a circuit using voltage clamp elements TVS1, TVS2, and TVS3, but it may also be a voltage source using a discharge prevention snubber circuit or a bidirectional converter. Of course, it is clear that voltage clamp circuits can also be added to the pulse power supplies of the first and third embodiments in a similar manner.

[0081] FIG. 19 is a schematic diagram of a pulse power supply section of a fifth embodiment, in which a high-speed constant current power supply Ap is provided in parallel with the current source 12 in the pulse power supply section of the second embodiment.

[0082] The high-speed constant-current power supply Ap adds ΔIc to the current Ic of the current source 12 in response to a set current value ΔIc instructed by a control unit (not shown). This ΔIc is used in response to a command from the process control unit 1 to correct the substrate surface voltage Vsub when sheath conditions change due to changes in the gas pressure in the plasma reactor Pr or fluctuations in the output of the ion source plasma power supply unit 2, causing the substrate surface voltage Vsub to change. ΔIc is sufficient to compensate for this change and can be a small current compared to the current Ic of the current source 12. Therefore, the output of the high-speed constant-current power supply Ap can have a small power capacity. This allows the use of a switching element with a small capacity and excellent high-frequency characteristics, such as gallium nitride (GAN). High-speed control is possible by increasing the PWM switching frequency and implementing multi-phase operation using a phase-shift multilevel cascade converter or the like. Alternatively, the high-speed constant-current power supply Ap may be increased in capacity to replace the current source 12, thereby supplying all of the current Ic from the high-speed constant-current power supply Ap.

[0083] It should be noted that the values ​​obtained from the formulas used in the above explanation are ideal values ​​that do not include circuit resistance, etc., and it goes without saying that it is desirable to appropriately correct all set values ​​according to the actual operating conditions.

[0084] Furthermore, the above-described embodiment and modified examples are merely examples of the present invention, and it is clear that any modifications, changes, or additions made within the spirit of the present invention will also be encompassed within the scope of the claims of this application. [Explanation of symbols]

[0085] 1...Process control section 2...Plasma power supply for ion source 3...Bias pulse power supply section 4...Processing chamber 5...Plasma 6...Substrate 6a…Surface 7...Stage 9...Grounding end 10...Output terminal 12…Current source 13, 14, 15...Voltage source S3, S4, S5...Switching section Da, Db, Dc, D3, D4, D5...Diodes N1, N2, N3, N4...nodes Ct1...Current sensor 20...Control unit TVS1, TVS2, TVS3...Voltage clamp circuits Ap…High speed constant current power supply Cb: Blocking capacitor Pr...Plasma reactor Cp: ​​Substrate capacitor Cs: sheath capacitor Cn: floating capacitor Dp...Sheath diode Ln: Wiring inductor Li, Lo... inductors Rp: sheath resistance Zp: Plasma resistance

Claims

1. 1. A bias control method for forming a pulsed voltage waveform at an output terminal of a pulsed power supply in order to supply a bias to a plasma reactor including a processing object in a plasma etching apparatus, comprising: selectively supplying a DC current having a predetermined current value, a third DC voltage having a third voltage value, and a fourth DC voltage having a fourth voltage value, the third DC voltage being referenced to a ground potential, to the output terminal; a) a first step of maintaining the voltage, which has dropped to a potential of a first voltage value lower than the third voltage value and the fourth voltage value due to half-wave resonance in a fourth step described later, in a capacitor load of a plasma reactor, thereby maintaining the output voltage at the output terminal at a low level; b) a second step of coupling the third DC voltage to the output terminal and causing a current to flow by half-wave resonance in a resonant loop including at least the capacitor load and an inductor including a wiring between the pulsed power supply device and the plasma reactor, thereby increasing the output voltage; c) a third step of coupling the DC current to the output terminal when the output voltage reaches a potential of a predetermined fifth voltage value higher than the third voltage value due to the voltage increase in the second step, and further linearly increasing the output voltage over time using the DC current; d) a fourth step of coupling the fourth DC voltage to the output terminal instead of the DC current after the output voltage has risen to a potential of a predetermined sixth voltage value in the third step, and causing a current to flow by half-wave resonance in a resonance loop including at least the capacitor load and the inductor, thereby decreasing the output voltage to the first voltage value; A bias control method for a plasma etching apparatus comprising:

2. 2. The bias control method for a plasma processing apparatus according to claim 1, wherein, when ΔV and Vc are respectively predetermined positive voltage values, the third voltage value is ΔV / 2, the fourth voltage value is (ΔV-Vc) / 2, the first voltage value is ΔV, the fifth voltage value is 0, and the sixth voltage value is -Vc.

3. 2. The bias control method for a plasma processing apparatus according to claim 1, wherein, when ΔV and Vc are predetermined positive voltage values, the third voltage value is 0, the fourth voltage value is -Vc / 2, the first voltage value is ΔV / 2, the fifth voltage value is -ΔV / 2, and the sixth voltage value is -(ΔV / 2)-Vc.

4. 2. The bias control method for a plasma processing apparatus according to claim 1, wherein, when ΔV and Vc are respectively predetermined positive voltage values, the third voltage value is −ΔV / 2, the fourth voltage value is −(ΔV+Vc) / 2, the first voltage value is 0, the fifth voltage value is −ΔV, and the sixth voltage value is −ΔV−Vc.

5. 1. A pulse power supply device for generating a pulsed voltage waveform between an output terminal connected to a plasma reactor via wiring and a ground terminal in order to supply a bias to the plasma reactor including a processing object in a plasma etching device, a) a third voltage source generating a third DC voltage having a third voltage value referenced to ground; b) a fourth voltage source generating a fourth DC voltage having a fourth voltage value referenced to ground; c) a third switch coupling the third voltage source to the output; d) a fourth switch coupling the fourth voltage source to the output; e) a current source having a current inflow end and a current outflow end, the inflow end being coupled to the output end via the third switch and the outflow end being coupled to the ground end, and supplying a DC current of a predetermined current value; f) a fifth switch connected in parallel with the current source; g) a third diode for reverse blocking, which is arranged between the third switch and the third voltage source or between the third voltage source and the ground terminal, and which blocks current flow from the ground terminal side to the third switch side; h) a fourth reverse-blocking diode connected in series to the fourth switch and the fourth voltage source, and blocking current flow from the output terminal to the ground terminal; i) a second diode for reverse blocking, which is arranged between the inflow end of the current source and the third switch and blocks current flow from the current source to the third switch; j) By holding the voltage that has dropped to a potential of a first voltage value that is lower than the third voltage value and the fourth voltage value by a second half-wave resonance described later in a capacitor load of the plasma reactor, and by keeping the output voltage at the output terminal at a low level, the third switch is turned on to couple the third voltage source to the output terminal, and by causing a current by first half-wave resonance to flow in a resonance loop that includes at least the capacitor load and an inductor including the wiring, the output voltage is raised, and due to this voltage rise, the output voltage reaches a potential of a predetermined fifth voltage value that is higher than the third voltage value, and further, the third diode changes from a conducting state to a reverse blocking state, thereby raising the output voltage. a control unit that, when the output voltage rises to a potential of a predetermined sixth voltage value as a result of a DC current from the current source passing through the second diode flowing to a load, turns on the fourth switch to couple the fourth voltage source to the output terminal, and causes a current due to a second half-wave resonance to flow in a resonance loop including the fourth diode, thereby decreasing the output voltage to the first voltage value, and turns on the fifth switch while the current due to the second half-wave resonance is flowing, thereby controlling on / off operations of the third switch, the fourth switch, and the fifth switch to circulate the current from the current source through the fifth switch; A pulse power supply device for a plasma processing apparatus comprising:

6. 6. The pulse power supply device for a plasma processing apparatus according to claim 5, wherein, when the third voltage value is 0, the fifth switch is a semiconductor switching element, and the function of the third diode is substituted by a series circuit of the second diode and a parasitic diode of the fifth switch, thereby eliminating a current path through the third diode.

7. 1. A pulse power supply device for generating a pulsed voltage waveform between an output terminal connected to a plasma reactor via wiring and a ground terminal in order to supply a bias to the plasma reactor including a processing object in a plasma etching device, a) a third voltage source generating a third DC voltage having a third voltage value referenced to ground; b) a fourth voltage source generating a fourth DC voltage having a fourth voltage value referenced to ground; c) a third switch coupling the third voltage source to the output; d) a fourth switch coupling the fourth voltage source to the output; e) a current source having a current inflow end and an outflow end, the inflow end being coupled to the output end via the third switch, and the outflow end being coupled to the ground end, the current source supplying a DC current of a predetermined current value, the current source comprising a voltage source on the outflow end side and an inductor on the inflow end side connected in series; f) a third diode for reverse blocking, which is arranged between the third switch and the third voltage source or between the third voltage source and the ground terminal, and which blocks current flow from the ground terminal side to the third switch side; g) a fourth reverse-blocking diode connected in series to the fourth switch and the fourth voltage source, and blocking current flow from the output terminal to the ground terminal; h) a series circuit in which a fifth switch and a second reverse-blocking diode that blocks current flow in a direction from the output terminal to the ground terminal are connected in series, the series circuit being connected in parallel to the inductor that constitutes the current source; i) By holding the voltage that has dropped to a potential of a first voltage value that is lower than the third voltage value and the fourth voltage value by a second half-wave resonance described later in a capacitor load of the plasma reactor, and by keeping the output voltage at the output terminal at a low level, the third switch is turned on to couple the third voltage source to the output terminal, and by causing a current by first half-wave resonance to flow in a resonance loop that includes at least the capacitor load and an inductor including the wiring, the output voltage is increased, and due to this voltage increase, the output voltage reaches a potential of a predetermined fifth voltage value that is higher than the third voltage value, and further the third diode changes from a conductive state to a reverse blocking state. a control unit that, when the output voltage rises to a potential of a predetermined sixth voltage value as a result of a DC current from the current source flowing to a load, turns on the fourth switch to couple the fourth voltage source to the output terminal, and causes a current due to a second half-wave resonance to flow in a resonance loop including at least the capacitor load and the inductor, and the fourth diode, thereby decreasing the output voltage to the first voltage value, and turns on the fifth switch while the current due to the second half-wave resonance is flowing, and controls on / off operations of the third switch, the fourth switch, and the fifth switch to circulate the current from the current source through the fifth switch; A pulse power supply device for a plasma processing apparatus comprising:

8. 8. The pulse power supply device for a plasma processing apparatus according to claim 5, further comprising a high-speed constant current power supply connected in parallel with said current source.

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