Semiconductor pattern evaluation method, semiconductor manufacturing process control system, and semiconductor pattern evaluation system

Abstract

To provide a semiconductor pattern evaluation method capable of precisely evaluating pattern shape and the processing conditions causing the same or variations in device characteristics and defect rates caused thereby or the like, using a relatively simple manner in the evaluation of semiconductor patterns.SOLUTION: The semiconductor pattern evaluation method is an evaluation method of patterns formed on the surface of a semiconductor wafer. The method includes the steps of: setting a feature space consisting of multiple features that can be calculated from the sensing data of the pattern; and calculating the deviation between the coordinates in the feature space calculated from the evaluation target and the reference point or coordinates in the reference space set in advance as a comparison target as a vector in the feature space.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a semiconductor pattern evaluation method and a semiconductor pattern evaluation system, and more particularly to a technique that is effective when applied to the evaluation of a semiconductor pattern having a three-dimensional (3D) shape. [Background technology]

[0002] In the quality control process at semiconductor manufacturing sites, it is essential to measure the dimensions of circuit patterns, such as gate spacing, and measurement technologies such as scanning electron microscopes (SEM), optical critical dimensions (OCD), and atomic force microscopes (AFM) are used.

[0003] A large number of tiny transistors are formed in semiconductor elements using microfabrication techniques such as lithography and dry etching, and in addition to conventional two-dimensional transistors, three-dimensional transistors, such as FinFETs, are now being put into practical use.

[0004] For transistors with a three-dimensional structure, the number of shape evaluation parameters required for quality control of semiconductor device manufacturing increases compared to two-dimensional structures. For example, in the case of FinFETs, in addition to line width, the main shape evaluation parameters of the fin also require measurement of three-dimensional (3D) shape dimensions such as fin height, sidewall angle, radius of curvature of the upper corner, sidewall roughness, and footing.

[0005] Furthermore, even in conventional two-dimensional structures, the line width varies depending on the height of the line pattern, so it is necessary to specify the height range before calculating the line width, which requires measurement of three-dimensional (3D) shape dimensions.

[0006] Background art in this technical field includes, for example, the technology described in Patent Document 1. Patent Document 1 discloses "a semiconductor device manufacturing process monitor apparatus that enables non-destructive measurement of the cross-sectional shape of a pattern to be evaluated, or the process conditions of the pattern to be evaluated, or the device characteristics of the pattern to be evaluated."

[0007] Patent Document 1 describes the following: "Image features effective for estimating the cross-sectional shape of the pattern to be evaluated, or the process conditions of the pattern to be evaluated, or the device characteristics of the pattern to be evaluated are calculated from an SEM image of the pattern to be evaluated, and the image features are compared with learning data that associates the cross-sectional shape of the pattern to be evaluated, or the process conditions of the pattern to be evaluated, or the device characteristics of the pattern to be evaluated, which has been stored in advance in a database, with the image features calculated from the SEM image, thereby calculating the cross-sectional shape of the pattern to be evaluated, or the process conditions of the pattern to be evaluated, or the device characteristics of the pattern to be evaluated." [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-129059 Summary of the Invention [Problem to be solved by the invention]

[0009] As mentioned above, semiconductor patterns are becoming increasingly miniaturized and processes are becoming more complex, and the three-dimensional pattern shape, including not only pattern width but also height and inclination, has a significant impact on device characteristics, resulting in increased demand for control of three-dimensional pattern shape. Cross-sectional measurements using cross-sectional observation equipment require FIB processing or other methods to prepare samples for cross-sectional observation, resulting in high measurement costs. Therefore, there is a need for a non-destructive, quantitative method for understanding semiconductor pattern shape.

[0010] In the above-mentioned Patent Document 1, the cross-sectional shape is estimated and measured by learning in advance the relationship between the cross-sectional shape (for example, dimensions) and a plurality of image feature amounts.

[0011] However, because multiple pieces of shape and dimension information are superimposed on each image feature, it is unclear what shape and dimension changes each feature represents. Therefore, to ensure the accuracy of estimation and measurement, training data covering a wide range of cross-sectional shape variations is required in order to separate the cross-sectional shape information contained in each image feature.

[0012] On the other hand, for the purpose of evaluating fluctuations in pattern shape, it is not essential to quantitatively grasp a specific dimension, but it is sufficient to grasp the presence or absence of fluctuations and their direction.

[0013] Therefore, an object of the present invention is to provide a semiconductor pattern evaluation method that can accurately evaluate, in a relatively simple manner, the pattern shape, the processing conditions that cause the pattern shape, or the variations in device characteristics, defect rates, etc. that are caused by the pattern shape, in the evaluation of semiconductor patterns, and a semiconductor manufacturing process management system and semiconductor pattern evaluation system that use the same. [Means for solving the problem]

[0014] In order to solve the above-mentioned problems, the present invention provides a method for evaluating a pattern formed on a surface of a semiconductor wafer, which method comprises: setting a feature space consisting of a plurality of feature quantities that can be calculated from sensing data of the pattern; and calculating, as a vector, a deviation between coordinates in the feature space calculated from an evaluation target and a reference point in the feature space or coordinates in the reference space that are set in advance as a comparison target.

[0015] The present invention also provides a semiconductor manufacturing process management system for managing a semiconductor manufacturing process, characterized by using the semiconductor pattern evaluation method described above.

[0016] The present invention also provides a semiconductor pattern evaluation system for evaluating a pattern formed on the surface of a semiconductor wafer, comprising a server that stores and processes data, wherein the server sets a feature space consisting of a plurality of feature quantities that can be calculated from sensing data of the pattern, and calculates, as a vector, a deviation between coordinates in the feature space calculated from an evaluation target and a reference point in the feature space or coordinates in the reference space that has been set in advance as a comparison target. [Effects of the Invention]

[0017] According to the present invention, it is possible to realize a semiconductor pattern evaluation method that can accurately evaluate, in a relatively simple manner, the pattern shape, the processing conditions that cause the pattern shape, or the variations in device characteristics, defect rates, etc. that are caused by the pattern shape, in the evaluation of semiconductor patterns, and a semiconductor manufacturing process management system and a semiconductor pattern evaluation system that use the same.

[0018] Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a block diagram showing a schematic configuration of a semiconductor pattern evaluation system according to each embodiment of the present invention. [Figure 2] 1A and 1B are diagrams showing an example of a top-view SEM image of a semiconductor pattern captured by a CD-SEM, its cross-sectional shape, and signal waveform. [Figure 3] FIG. 2 is a diagram showing image feature amounts according to the present invention. [Figure 4] 1 is a flowchart showing a pattern shape evaluation method based on an image feature amount according to the first and second embodiments of the present invention. [Figure 5] FIG. 2 is a diagram showing an evaluation target and a comparison target according to Example 1 of the present invention. [Figure 6] FIG. 2 is a diagram showing a change in a pattern shape according to the first embodiment of the present invention, expressed by coordinates and vectors in a feature space. [Figure 7] 10 is a flowchart showing a method for associating a change in a feature amount with a change in a process parameter according to a second embodiment of the present invention. [Figure 8] FIG. 10 is a diagram showing changes in coordinates and vectors in a feature space accompanying changes in process parameters. [Figure 9] FIG. 10 is a diagram showing an evaluation target according to Example 2 and Example 3 of the present invention. [Figure 10] FIG. 10 is a diagram showing the distance between an evaluation object and a target point in a feature amount space according to the second embodiment of the present invention. [Figure 11] FIG. 10 is a diagram showing the deviation of an evaluation target from a target point according to Example 2 of the present invention. [Figure 12] FIG. 10 is a diagram showing a guideline for changing process parameters to bring an evaluation object closer to a target space according to the second embodiment of the present invention. [Figure 13] 10 is a flowchart showing a method for evaluating the in-plane uniformity of a pattern shape according to a third embodiment of the present invention. [Figure 14] FIG. 10 is a diagram showing the coordinates of patterns in a feature space and a labeling result according to the third embodiment of the present invention. [Figure 15] FIG. 11 is a diagram illustrating a normalized distance between an evaluation object in a feature amount space and a target space according to a third embodiment of the present invention. [Figure 16] FIG. 10 is a diagram showing the deviation of an evaluation object from a target space according to the third embodiment of the present invention. [Figure 17] FIG. 11 is a diagram showing a guideline for changing process parameters to bring the evaluation object closer to the target space according to the third embodiment of the present invention. [Figure 18] FIG. 10 is a diagram showing an evaluation target according to Example 4 of the present invention. [Figure 19] FIG. 11 is a diagram showing a normalized distance between an evaluation object in a feature amount space and a target space according to Example 4 of the present invention. [Figure 20] FIG. 10 is a diagram showing the deviation of an evaluation object from a target space according to Example 4 of the present invention. [Figure 21] FIG. 10 is a diagram showing a guideline for changing process parameters to bring the evaluation object closer to the target space according to the fourth embodiment of the present invention. [Figure 22] FIG. 13 is a diagram showing changes in feature quantities in successive steps and a process window according to Example 6 of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and detailed description of overlapping parts will be omitted. [Example]

[0021] First Embodiment A semiconductor pattern evaluation system and a semiconductor pattern evaluation method according to a first embodiment of the present invention will be described with reference to FIGS.

[0022] The present invention aims to comparatively evaluate the shape of patterns on semiconductor wafers manufactured by semiconductor manufacturing equipment.

[0023] In this example, a line pattern is targeted, and the deviation of the pattern shape at different positions on the wafer surface is evaluated using the pattern shape at the wafer center as a reference. The evaluation is characterized by using multiple image feature quantities calculated from a top-view SEM image.

[0024] First, the system configuration for realizing this embodiment will be described with reference to Fig. 1. Fig. 1 is a block diagram showing the schematic configuration of a semiconductor pattern evaluation system according to this embodiment.

[0025] As shown in Fig. 1, the system mainly comprises a semiconductor manufacturing device (e.g., an etching device) 100, a scanning electron microscope (e.g., a CD-SEM) 101, an electrical characteristic inspection device (tester) 102, a data storage and processing server 103, an external input unit 105, a cross-section observation device 106, and a display device (display unit) 107, all of which are connected via a network 104. This simulates an in-line semiconductor manufacturing and inspection system.

[0026] Next, image feature quantities according to the present invention will be described with reference to Figures 2 and 3. Figure 2 shows an example of a top-view SEM image of a semiconductor pattern captured by a CD-SEM (Critical Dimension-Scanning Electron Microscope), its cross-sectional shape, and signal waveform. Figure 3 shows image feature quantities according to the present invention.

[0027] In SEM, an electron beam is irradiated onto a sample, and image signals are obtained by detecting secondary electrons that diffuse on the surface and inside of the sample. As a result, the number of detected electrons varies depending on the shape of the sample, making it possible to obtain images that are sensitive to shape information. Therefore, when comparing SEM image signals, if the image signals are similar, it can be said that the pattern shapes of the imaged objects are similar. Therefore, to evaluate image signals, the image signals are quantified in a generalized manner as multiple image feature quantities.

[0028] Figure 2 shows an example of an SEM image of a semiconductor line pattern and its image signal waveform.

[0029] An image signal cut out in a direction perpendicular to the pattern (for example, from a to b in the SEM image 201 in FIG. 2) on a two-dimensional SEM image 201 is a signal waveform 202 in the direction perpendicular to the line pattern.

[0030] Generally, the signal amount of the signal waveform changes with high sensitivity depending on the tilt angle of the object to be measured, and the signal amount at the sidewall of the pattern is larger than the signal amount at the flat part. Therefore, the signal amount at the sidewall of the pattern is large, and an area called a white band 203 appears on the signal waveform 202. In this way, the signal amount of the signal waveform changes depending on the shape of the cross section.

[0031] An example of image features is shown in Figure 3. These are various values ​​that quantitatively express the characteristics of the signal waveform, such as the left and right white band peaks 301 and 302 of the signal waveform 202, the left and right bottom signal amounts 303 and 304, the top signal amount 305, the signal waveform (profile) width 306, and the signal waveform slopes 307 to 310 calculated from the first derivative waveform. In addition, because local shape variations in the semiconductor pattern can also affect device performance, fluctuations due to local shape variations in the above image features can also be used as one feature.

[0032] In general, it is believed that the feature value indicating the signal amount of a signal waveform captures changes in the height direction of the pattern, the feature value indicating the width of the signal waveform captures changes in the width direction such as the line width of the cross-sectional shape, and the feature value indicating the slope of the signal waveform captures changes such as the rounding of the corners of the pattern, the tailing, and the slope angle of the sidewall.

[0033] However, as semiconductor patterns become finer, the diffusion range of irradiated electrons includes various geometric dimension information such as the line width, rounded corners, footing, sidewall inclination angle, and height of the pattern. Therefore, it is difficult to separate the various geometric dimension information and design image features that can independently capture the changes in each geometric dimension.

[0034] Therefore, in the present invention, N image features (Equation (1)) are calculated from one SEM image, and the pattern shape included in the SEM image is expressed as coordinates (vectors) (Equation (2)) in a feature space with each image feature as an axis. In other words, one feature set and its coordinates (vectors) in the feature space correspond to the pattern shape included in one SEM image.

[0035]

number

[0036]

number

[0037] By treating it in this way, even if it is not possible to separate and grasp the dimensional information contained in each feature, it is possible to evaluate that the close distance between coordinates in the feature space means that the image signals, that is, the pattern shapes, are similar.

[0038] In this way, by expressing a pattern shape using a plurality of sets of feature quantities and expressing the deviations as vectors, quantitative comparison and evaluation of the pattern shape becomes possible. Furthermore, in the present invention, even if a space is created using only some of the feature quantities (for example, one feature quantity), what is expressed by the feature quantity set is the subject of the coordinates and vectors of the present invention.

[0039] Next, the semiconductor pattern evaluation method of this embodiment will be described with reference to Figs. 4 to 6. Fig. 4 is a flowchart showing the pattern shape evaluation method based on image features. Fig. 5 is a diagram showing an evaluation target and a comparison target. Fig. 6 is a diagram expressing changes in pattern shape using coordinates and vectors in feature space.

[0040] In this embodiment, as shown in FIG. 5, the comparison target is a pattern at the center of a wafer 501, and the evaluation target is a pattern at a position X at a certain distance from the center of the wafer 501.

[0041] When the data storage and processing server (hereinafter simply referred to as the "server") 103 starts processing, first in step S401, it sets a target point (reference point) to be compared in feature space. A top-view SEM image of the pattern at the center of the wafer set as the comparison target is taken using CD-SEM 101, and the taken image is transmitted to server 103 via network 104. A feature set (Equation (3)) calculated from the SEM image in server 103 is set as a target point (reference point) in feature space, and the information is saved in server 103.

[0042]

number

[0043] Next, in step S402, a top-view SEM image of a pattern at position X, which is a certain distance from the center of the wafer set as the evaluation target, is taken using CD-SEM 101, and the taken image is transmitted to server 103 via network 104.

[0044] Next, in step S403, the server 103 calculates one or more image feature amounts (Equation (1)) from a top-view SEM image of the pattern to be evaluated.

[0045] Next, in step S404, the deviation of the coordinates (equation (2)) in the feature space of the feature calculated from each chip area on the wafer 501 from the coordinate information of the target point (reference point) stored in the server 103 is calculated as a vector (equation (4)) as shown in FIG. 6.

[0046]

number

[0047] Finally, in step S405, the quality of the pattern shape is evaluated based on the calculated vector. The distance indicated by the vector (Equation (5)) becomes smaller as the pattern shape being evaluated becomes more similar to the pattern shape set as the target point (reference point), and serves as an index that quantitatively indicates the difference from the target.

[0048]

number

[0049] Application examples of this embodiment will be described in the following examples. [Example]

[0050] Second Embodiment A semiconductor pattern evaluation system and a semiconductor pattern evaluation method according to a second embodiment of the present invention will be described with reference to FIGS.

[0051] In this embodiment, image feature values ​​calculated from a top-view SEM image are used to evaluate the in-plane uniformity of the line pattern shape on a semiconductor wafer manufactured by semiconductor manufacturing equipment, and process conditions are determined and controlled based on the evaluation results so that the in-plane uniformity meets the target value.

[0052] Generally, in processes such as etching, which process the entire wafer surface at once, the processed shape may vary depending on the chip position on the wafer surface even under the same process conditions. This may result in pattern shape variations between chip regions, and these in-plane variations in pattern shape affect device performance. Therefore, the purpose of this embodiment is to determine process conditions that form patterns that achieve the target device performance across the entire wafer and to adjust the process to maintain those conditions.

[0053] The system configuration for realizing this embodiment is the same as that of embodiment 1 (FIG. 1). Also, the image feature amount in this embodiment is the same as that of embodiment 1 (FIG. 3).

[0054] The processing steps of this embodiment are explained below. The processing steps can be broadly divided into four steps: (1) creating a model that associates the amount of change in feature values ​​with the amount of change in process parameters, (2) evaluating the in-plane uniformity of the pattern shape using coordinates in feature value space, (3) determining process conditions by comparing feature value vectors that indicate deviations with a model, and (4) process control by comparing feature value vectors that indicate deviations with a model. Each of these steps is explained below.

[0055] (1) Creating a model that correlates the amount of change in feature values ​​with the amount of change in process parameters The model creation step (1) will be described with reference to Fig. 7. Fig. 7 is a flowchart showing a method for associating changes in feature quantities with changes in process parameters.

[0056] When the server 103 starts processing, first, in step S701, a plurality of samples are created by varying process parameters (for example, gas amount, pressure, temperature, etc. in the case of an etching apparatus) that indicate process conditions in the semiconductor manufacturing equipment 100. Generally, when developing a semiconductor device manufacturing process, samples are created by varying various process parameters, and the samples obtained there are assumed.

[0057] Next, in step S702, a top-view SEM image of the sample is taken using a CD-SEM 101, and then the fracture surface is imaged using a cross-sectional observation device 106 such as a cross-sectional SEM or a transmission electron microscope (TEM). The process parameters and these images are transmitted as a set to a server 103 via a network 104 and stored.

[0058] Next, in step S703, the server 103 calculates one or more image feature quantities (Equation (1)) from the top-view SEM image.

[0059] Finally, in step S704, a model is created of the relationship between the change in feature quantity associated with the change in process parameters based on the process conditions and the feature quantity set of the pattern shape manufactured under those conditions, and the information is stored in the server 103.

[0060] As an example, Figure 8 shows feature values ​​calculated from a pattern generated under certain process conditions A, and feature values ​​calculated from patterns generated under process conditions B and C, which change the temperature of the etching equipment, plotted in feature value space.

[0061] In this way, by relating the temperature change amount to a vector that expresses the deviation between coordinates in the feature space, a model is created that takes the change amount of the feature amount as input and outputs the control amount and direction of the process parameter.

[0062] Although an example in which temperature is changed as a process parameter has been shown, even if there are multiple process parameters, the amount of change in each process parameter can be expressed as a vector as an element, and a model can be created by associating vectors with each other.

[0063] This makes it possible to calculate which process parameters should be changed and in which direction to improve in-wafer uniformity when feature variations occur within the wafer surface, and this information can be used to determine and control process conditions.

[0064] In this embodiment, a plurality of samples are created by varying the process parameters, and a new model is created that associates the process parameters with changes in the feature quantities, but if a model is already available, it can also be implemented by inputting the model via the external input unit 105. In that case, this step can be omitted.

[0065] (2) Evaluation of in-plane uniformity of pattern shape using coordinates in feature space The step (2) of evaluating the in-plane uniformity of the pattern shape will be described with reference to FIG.

[0066] When the server 103 starts the process, first, in step S401, a target point (reference point) to be compared in the feature amount space is set.

[0067] In the in-wafer uniformity evaluation, the purpose is to evaluate the deviation and similarity with other patterns on the wafer surface using a certain pattern shape on the wafer as a comparison standard. Therefore, in this embodiment, a pattern at the center of the wafer is selected as the comparison target, and a feature set (Equation (3)) calculated from an SEM image of that pattern taken by the CD-SEM 101 is set as a target point (reference point) in the feature space.

[0068] For example, the wafer center is selected because the wafer center generally produces the best pattern shape on the wafer. Alternatively, a target pattern may be set based on the performance of patterns manufactured under each process condition, as determined from cross-sectional SEM images or TEM images stored in the server 103.

[0069] Next, in step S402, a top-view SEM image of the evaluation target is taken using CD-SEM 101, and the taken image is transmitted to server 103 via network 104. Since the purpose of this embodiment is to evaluate the in-plane uniformity of the pattern shape on the wafer, the patterns of each chip area on wafer 501 are set as the evaluation target as shown in FIG.

[0070] Next, in step S403, the server 103 calculates one or more image feature quantities (Equation (1)) from the top-view SEM image.

[0071] Next, in step S404, the deviation of the coordinates (equation (2)) in the feature space of the feature calculated from each chip area from the coordinate information of the target point (reference point) stored in the server 103 is calculated as a vector (equation (4)).

[0072] Finally, in step S405, the performance of the pattern shape is evaluated based on the vector (equation (4)) calculated in step S404. The distance indicated by the vector (equation (5)) becomes smaller as the pattern shape being evaluated becomes more similar to the pattern shape set as the target point (reference point), and serves as an index that quantitatively indicates the difference from the target.

[0073] FIG. 10 shows an example of the result of calculating the distance (equation (5)) between the coordinates of the feature calculated from the pattern of each chip area and the target point.

[0074] This allows evaluation of the uniformity of the cross-sectional shape within the wafer surface relative to the target cross-sectional shape. Also, as deviation from the target space, the amount and direction of change of each feature amount are displayed on a display device (display unit) 107 such as a GUI (Graphical User Interface), as shown in FIG.

[0075] (3) Process condition determination by matching feature vectors with models The process condition determination step (3) by matching feature vectors with models will be described with reference to FIG.

[0076] For each evaluation pattern on the wafer surface, the vector (Equation (4)) indicating the deviation from the target point (center of the wafer) is compared with a model that associates feature value changes with process parameter changes, and it is calculated which process parameter needs to be changed in which direction to bring the evaluation target closer to the target point, and the result is output as shown in Figure 12.

[0077] This allows calculation of process conditions for improving the in-plane uniformity. In this embodiment, to improve the in-plane uniformity, a process parameter that can be changed depending on the position on the wafer (for example, the temperature distribution on the wafer during etching) is changed.

[0078] In addition, in the model generation step (1), image features are acquired from patterns with different positions on the wafer surface for process parameters that change depending on the position on the wafer surface, and variations in position on the wafer surface are also acquired to create a model for each position. This makes it possible to calculate the quantitative adjustment amount of the process conditions required for the evaluation object to approach the target space based on the distance from the target space.

[0079] By repeating the cycle of wafer manufacturing using process parameters that reflect these output results, evaluating in-plane uniformity, and outputting guidelines for improving the process parameters, it becomes possible to determine process conditions that provide good in-plane uniformity, and to develop a non-destructive process that provides good in-plane uniformity of pattern shapes.

[0080] (4) Process control by feature vector and model matching (4) Process control based on feature vector and model matching will be explained.

[0081] In the mass production process of semiconductor manufacturing, the process conditions determined in the process condition determination step (3) are fixed and patterns are continuously manufactured under those conditions. However, even if the process conditions are fixed, there is a risk that the pattern shape may change due to process fluctuations caused by changes over time.

[0082] Therefore, in order to maintain the in-plane uniformity against the process fluctuation, the in-plane uniformity is evaluated as a process monitor, and similarly to (3), for each evaluation pattern on the wafer, the vector (equation (4)) indicating the deviation calculated from the target point (center of the wafer) is compared with a model that associates the change in the feature value with the change in the process parameter, and the amount and direction of change of each process parameter required to maintain the uniformity is calculated and input into the semiconductor manufacturing equipment 100, thereby enabling the process condition control.

[0083] In this embodiment, an example of determining process conditions and controlling the process for an etching apparatus has been shown, but it is also possible to perform this for process parameters of other processing apparatuses, such as the exposure dose and focus height of a lithography apparatus.

[0084] Furthermore, in this embodiment, image features are calculated from signal waveforms, but image features can also be calculated from two-dimensional images without calculating signal waveforms, such as features obtained by Fourier transforming an image or brightness values ​​calculated from an image.

[0085] In addition, in this embodiment, a vector in the feature space is calculated as the deviation from the target space using multiple feature values. However, if there is only one feature value, this can be implemented by calculating the signed difference from the target point as the distance and direction.

[0086] In addition, in this embodiment, only one target point is set, but it is also possible to set multiple target points and calculate the distance taking into account the multiple target points, or to find the distance to a target space consisting of multiple target points.

[0087] Furthermore, in this embodiment, an example has been described in which the in-plane shape of one wafer is set as the evaluation object, but it is also possible to carry out the evaluation across a plurality of wafers / samples.

[0088] Furthermore, in this embodiment, an example has been described in which evaluation targets are set in different chip regions on the same wafer, but the evaluation targets may also be set by further dividing the same chip region.

[0089] In addition, in this embodiment, the target point is set based on an SEM image of a pattern created by the semiconductor manufacturing equipment 100, but it is also possible to set it based on an SEM image created by simulation, etc.

[0090] Furthermore, in this embodiment, an example has been described in which the target semiconductor pattern is a line pattern, but it is also possible to implement this if the target semiconductor pattern shape is one that is sensitive to SEM, such as a contact hole.

[0091] Furthermore, in this embodiment, an example was shown in which one line pattern exists in the SEM image, but it is also possible to implement this even if multiple lines, such as a periodic pattern, are included in the field of view of the SEM image.

[0092] Furthermore, although the present embodiment shows an example in which an SEM was used for evaluation, it is also possible to use data acquired from other sensing devices that are sensitive to cross-sectional shapes, such as optical sensing devices. For example, if data that is a set of combinations of reflectances at multiple wavelengths for one sample is output, these sets of reflectances are essentially the same as the feature set of the present invention, and can be similarly implemented by calculating coordinate vectors based on them.

[0093] Furthermore, in this embodiment, all the designed image features are used, but it is also possible to select and reduce the number of features to be used, for example, by selecting features that are sensitive to changes in process conditions based on their correlation with process parameters, by comparing the amount of change in a feature with the reproducibility of the feature or fluctuations due to local shape variations and selecting features that are highly sensitive to shape, or by selecting arbitrary features in advance.

[0094] The server 103 may be installed in a scanning electron microscope device, and a reference point in the feature space set as a comparison target or coordinates in the reference space may be input to the scanning electron microscope device, and the deviation from the coordinates in the feature space calculated from the image captured by the scanning electron microscope device may be calculated as a vector (equation (4)), and displayed on a display unit (GUI, etc.) of the scanning electron microscope device. [Example]

[0095] Third Embodiment A semiconductor pattern evaluation system and a semiconductor pattern evaluation method according to a third embodiment of the present invention will be described with reference to FIGS.

[0096] In this embodiment, image feature quantities calculated from a top-view SEM image are used to evaluate the in-plane uniformity of the shape of a line pattern on a semiconductor wafer manufactured by semiconductor manufacturing equipment 100, determine whether the pattern shape dimensions achieve the target tolerance range across the entire wafer, and, based on the evaluation results, determine and control process conditions that will satisfy the target value for in-plane uniformity. The purpose of this embodiment is the same as that of embodiment 2.

[0097] The system configuration for realizing this embodiment is the same as that of embodiment 1 (FIG. 1). Also, the image feature amount in this embodiment is the same as that of embodiment 1 (FIG. 3).

[0098] The processing steps of this embodiment are explained below. The processing steps can be broadly divided into four steps: (1) creating a model that associates the amount of change in feature values ​​with the amount of change in process parameters, (2) evaluating the in-plane uniformity of the pattern shape using coordinates in feature value space, (3) determining process conditions by comparing feature value vectors that indicate deviations with a model, and (4) process control by comparing feature value vectors that indicate deviations with a model. Each of these steps is explained below.

[0099] (1) Creating a model that correlates the amount of change in feature values ​​with the amount of change in process parameters This step is the same as the processing in steps S701 to S704 in the second embodiment (FIG. 7).

[0100] (2) Evaluation of in-plane uniformity of pattern shape using coordinates in feature space The step (2) of evaluating the in-plane uniformity of the pattern shape will be described with reference to Fig. 13. Fig. 13 is a flowchart showing a method of evaluating the in-plane uniformity of the pattern shape.

[0101] First, the step of setting a target space in feature space will be described. When the server 103 starts processing, first, in step S1301, the performance of the pattern manufactured under each process condition is judged as OK or NG based on the cross-sectional SEM images and TEM images stored in the server 103, and labeled. This judgment is made based on whether a specific dimension measured based on the cross-sectional SEM images and TEM images is within the tolerance for achieving the target device performance. Based on the labeling results, the boundary in the feature space is found, and the target space is set.

[0102] Figure 14 shows an example in which image feature values ​​calculated from top-view SEM images of each pattern with different manufacturing process conditions are plotted as coordinates in feature space. In this graph, the labeling results for each corresponding pattern are displayed as a color map.

[0103] The boundary between the OK and NG labels is calculated in the feature space, the space within the boundary is set as the target space, and this information is saved in the server 103. If it is not possible to draw a boundary that correctly distinguishes between the OK and NG labels, the label is corrected based on the cross-sectional SEM image or TEM image so that the boundary can be drawn. By setting the target space in the feature space in this way, it is possible to determine whether the cross-sectional shape meets the target cross-sectional shape based on the feature calculated from the top-view SEM image.

[0104] Next, in step S1302, a top-view SEM image of the evaluation target is taken using CD-SEM 101, and the taken image is transmitted to server 103 via network 104. Since the purpose of this embodiment is to evaluate the in-plane uniformity of the pattern shape on the wafer, the patterns of each chip area on wafer 501 are set as the evaluation target as shown in FIG.

[0105] Next, in step S1303, the server 103 calculates the image feature amount (Equation (1)) from the top-view SEM image.

[0106] Next, in step S1304, the deviation of the coordinates (equation (2)) in the feature space of the feature calculated from each chip area is calculated as a vector for the target space stored in the server 103. Here, the deviation of the coordinates (equation (3)) of the center of gravity of the target space is calculated as a vector (equation (4)).

[0107] Finally, in step S1305, the performance of the pattern is evaluated based on the vector (equation (4)) calculated in step S1304. To give meaning to the value of the distance (equation (5)) from the center of gravity of the target space to the evaluation object, this value is divided by the distance d to the boundary with the target space when a straight line is extended from the center of gravity in the direction of each evaluation object, and this value is defined as the normalized distance (equation (6)).

[0108]

number

[0109] If this normalized distance (Equation (6)) is 1 or less, it can be determined that the evaluation target is within the target space, and if it is greater than 1, it is not, allowing the pattern performance to be evaluated. Furthermore, this normalized distance (Equation (6)) becomes smaller the more similar the cross-sectional shape of the evaluation target is to the target cross-sectional shape, and serves as an index that quantitatively indicates the difference between the cross-sectional shape and the target.

[0110] FIG. 15 shows an example of the results of calculating the normalized distance (Equation (6)) between the coordinates of the feature amount calculated from the pattern of each chip area and the center of gravity of the target space.

[0111] This indicates the uniformity of the cross-sectional shape within the wafer surface relative to the target cross-sectional shape, and detects NG patterns in which the cross-sectional shape dimensions do not reach the target. Also, as deviations from the target space, the amount and direction of change of each feature amount are displayed on a display device (display unit) 107 such as a GUI, as shown in FIG.

[0112] (3) Process condition determination by matching feature vectors with models For patterns that are outside the target space as a result of the in-plane uniformity evaluation, i.e., are judged to be NG, the vector (Equation (4)) indicating the deviation from the target space is compared with a model that associates feature value changes with process parameter changes, and it is calculated which process parameter needs to be changed in which direction to bring the evaluation target closer to the target space, and the result is output as shown in Fig. 17.

[0113] This allows for the calculation of process conditions to improve the pattern shape and in-plane uniformity when a pattern shape that does not satisfy the tolerance within the wafer is obtained. In this embodiment, in order to improve the in-plane uniformity, a process parameter that can be changed depending on the position within the wafer (for example, the temperature distribution within the wafer during etching) is changed.

[0114] In addition, in the model generation step (1), image features are acquired from patterns with different positions on the wafer surface for process parameters that change depending on the position on the wafer surface, and variations in position on the wafer surface are also acquired to create a model for each position. This makes it possible to calculate the quantitative adjustment amount of the process conditions required for the evaluation object to approach the target space based on the distance from the target space.

[0115] By repeating the cycle of wafer manufacturing using process parameters that reflect these output results, evaluating the in-plane uniformity, and outputting guidelines for improving the process parameters, it becomes possible to determine the process conditions that will produce a pattern that achieves the target in-plane uniformity, i.e., is deemed OK across the entire wafer, and to develop a non-destructive process that produces good in-plane uniformity of the pattern shape.

[0116] (4) Process control by feature vector and model matching (4) Process control based on feature vector and model matching will be explained.

[0117] In the mass production process of semiconductor manufacturing, the process conditions determined in the process condition determination step (3) are fixed and patterns are continuously manufactured under those conditions. However, even if the process conditions are fixed, there is a risk that the pattern shape may change due to process fluctuations caused by changes over time.

[0118] Therefore, in order to maintain in-plane uniformity against process variations, the process monitor performs an OK / NG judgment on the patterns on the wafer surface, and similarly to (3), for each evaluation pattern on the wafer surface that is judged NG, the vector (equation (4)) indicating the deviation calculated with respect to the target space is compared with a model that associates feature changes with process parameter changes, and the amount and direction of change of each process parameter required to maintain uniformity is calculated and input into semiconductor manufacturing equipment 100, thereby enabling process condition control.

[0119] In this embodiment, an example of determining process conditions and controlling the process for an etching apparatus has been shown, but it is also possible to perform this for process parameters of other processing apparatuses, such as the exposure dose and focus height of a lithography apparatus.

[0120] In addition, in this embodiment, image features are calculated from signal waveforms, but image features can also be calculated from two-dimensional images without calculating signal waveforms, such as features obtained by Fourier transforming an image.

[0121] In addition, in this embodiment, a vector in the feature space is calculated as the deviation from the target space using multiple feature values. However, if there is only one feature value, this can be implemented by calculating the signed difference from the target point as the distance and direction.

[0122] Furthermore, although an example in which there is one target space has been shown in this embodiment, it is also possible to set multiple target spaces and update the overlapping area of ​​these multiple target spaces as a new target space.

[0123] Furthermore, in this embodiment, an example has been described in which the in-plane shape of one wafer is set as the evaluation object, but it is also possible to carry out the evaluation across a plurality of wafers / samples.

[0124] Furthermore, in this embodiment, an example has been described in which evaluation targets are set in different chip regions on the same wafer, but the evaluation targets may also be set by further dividing the same chip region.

[0125] In addition, in this embodiment, the target space is set based on an SEM image of a pattern created by the semiconductor manufacturing equipment 100, but it can also be set based on an SEM image created by simulation, etc.

[0126] Furthermore, in this embodiment, an example has been described in which the target semiconductor pattern is a line pattern, but it is also possible to implement this if the target semiconductor pattern shape is one that is sensitive to SEM, such as a contact hole.

[0127] Furthermore, in this embodiment, an example was shown in which one line pattern exists in the SEM image, but it is also possible to implement this even if multiple lines, such as a periodic pattern, are included in the field of view of the SEM image.

[0128] Furthermore, although the present embodiment shows an example in which an SEM was used for evaluation, it is also possible to use data acquired from other sensing devices that are sensitive to cross-sectional shapes, such as optical sensing devices. For example, if data that is a set of combinations of reflectances at multiple wavelengths for one sample is output, these sets of reflectances are essentially the same as the feature set of the present invention, and can be similarly implemented by calculating coordinate vectors based on them.

[0129] Furthermore, in this embodiment, all the designed image features are used, but it is also possible to select and reduce the number of features to be used, for example, by selecting features that are sensitive to changes in process conditions based on their correlation with process parameters, by comparing the amount of change in a feature with the reproducibility of the feature or fluctuations due to local shape variations and selecting features that are highly sensitive to shape, or by selecting arbitrary features in advance. [Example]

[0130] Fourth Embodiment A semiconductor pattern evaluation system and a semiconductor pattern evaluation method according to a fourth embodiment of the present invention will be described with reference to FIGS.

[0131] In this embodiment, an example will be described in which image feature quantities calculated from a top-view SEM image are used to evaluate changes over time in a line pattern on a semiconductor wafer manufactured by semiconductor manufacturing equipment 100, and process conditions are determined and process control is performed based on the evaluation results. Because the pattern shape affects device performance, the purpose of this embodiment is to monitor changes over time in the pattern shape that occur due to process fluctuations over time, and to determine and control new process conditions when a pattern that does not satisfy the target performance of the device is generated.

[0132] The system configuration for realizing this embodiment is the same as that of embodiment 1 (FIG. 1). Also, the image feature amount in this embodiment is the same as that of embodiment 1 (FIG. 3).

[0133] The processing steps of this embodiment are explained below. These processing steps can be broadly divided into four steps: (1) creating a model that associates the amount of change in feature values ​​with the amount of change in process parameters, (2) evaluating process variations in pattern shapes using coordinates in feature space, (3) determining process conditions by matching feature vectors that indicate deviations with a model, and (4) controlling the process by matching feature vectors that indicate deviations with a model. Each of these steps is explained below.

[0134] (1) Creating a model that correlates the amount of change in feature values ​​with the amount of change in process parameters This step is the same as the processing in steps S701 to S704 in the second embodiment (FIG. 7).

[0135] (2) Evaluation of process variations in pattern shapes using coordinates in feature space The step (2) of evaluating process variations in pattern shapes will be described with reference to FIG.

[0136] The step of setting the target space in the feature space is the same as step S1301 described in the third embodiment (FIG. 13).

[0137] Next, in step S1302, a top-view SEM image of the evaluation target is taken using CD-SEM 101, and the taken image is transmitted to server 103 via network 104. In this embodiment, with the aim of evaluating changes over time in the pattern shape on the wafer caused by process variations, patterns in the central chip regions on multiple wafers 501 manufactured at different times under the same process conditions are set as the evaluation target, as shown in Fig. 18. The aim of evaluating changes over time in the cross-sectional shape is that even with the same process parameters, the pattern shape after processing may change due to process variations over time.

[0138] Next, in step S1303, the server 103 calculates the image feature amount (Equation (1)) from the top-view SEM image.

[0139] Next, in step S1304, the deviation of the coordinates (equation (2)) in the feature space of the feature calculated from each chip area is calculated as a vector for the target space stored in the server 103. Here, the deviation of the coordinates (equation (3)) of the center of gravity of the target space is calculated as a vector (equation (4)).

[0140] Finally, in step S1305, the performance of the pattern is evaluated based on the vector (equation (4)) calculated in step S1304. To give meaning to the value of the distance (equation (5)) from the center of gravity of the target space to the evaluation object, this value is divided by the distance d to the boundary with the target space when a straight line is extended from the center of gravity in the direction of each evaluation object, and this value is defined as the normalized distance (equation (6)).

[0141] If this normalized distance (Equation (6)) is 1 or less, it can be determined that the evaluation target is within the target space, and if it is greater than 1, it is not, allowing the pattern performance to be evaluated. Furthermore, this normalized distance (Equation (6)) becomes smaller the more similar the cross-sectional shape of the evaluation target is to the target cross-sectional shape, and serves as an index that quantitatively indicates the difference between the cross-sectional shape and the target.

[0142] FIG. 19 shows an example of the results of calculating the normalized distance (Equation (6)) between the coordinates of the feature amounts calculated from the evaluation patterns with different manufacturing times and the center of gravity of the target space.

[0143] This makes it possible to show the time-dependent change in the pattern shape due to process fluctuations relative to the target, and detect NG patterns in which the pattern shape does not reach the target value. Also, as deviations from the target space, the amount and direction of change in each feature amount are displayed on a display device (display unit) 107 such as a GUI, as shown in FIG.

[0144] (3) Process condition determination by matching feature vectors with models This process assumes a case where process conditions are newly created in response to changes over time in semiconductor manufacturing equipment 100. For a pattern that is outside the target space as a result of evaluation of changes in the pattern shape over time, i.e., a pattern that is determined to be NG in quality, a vector (Equation (4)) indicating the deviation from the target space is compared with a model that associates changes in feature values ​​with changes in process parameters, and it is calculated which process parameters need to be changed in which direction and by how much to bring the evaluation target closer to the target space, and the result is output as shown in FIG.

[0145] By repeating the cycle of wafer manufacturing using process parameters that reflect these output results, pattern evaluation, and output of improvement guidelines for the process parameters, it becomes possible to determine process conditions for manufacturing patterns that achieve target values ​​in response to changes over time in the semiconductor manufacturing equipment 100.

[0146] (4) Process control by feature vector and model matching (4) Process control based on feature vector and model matching will be explained.

[0147] This process assumes dynamic process control in response to process fluctuations. For a pattern determined to be unacceptable as a result of evaluating the time-varying change in the pattern shape as a process monitor, the process monitor compares the vector (equation (4)) indicating the deviation calculated for the target space with a model that associates the feature change with the process parameter change, calculates the amount and direction of change of each process parameter required to maintain a pattern shape close to the target, and inputs the calculated amount and direction of change into semiconductor manufacturing equipment 100, thereby controlling the process conditions.

[0148] In this embodiment, an example of determining process conditions and controlling the process for an etching apparatus has been shown, but it is also possible to perform this for process parameters of other processing apparatuses, such as the exposure dose and focus height of a lithography apparatus.

[0149] In addition, in this embodiment, image features are calculated from signal waveforms, but image features can also be calculated from two-dimensional images without calculating signal waveforms, such as features obtained by Fourier transforming an image.

[0150] In addition, in this embodiment, a vector in the feature space is calculated as the deviation from the target space using multiple feature values. However, if there is only one feature value, this can be implemented by calculating the signed difference from the target point as the distance and direction.

[0151] Furthermore, although an example in which there is one target space has been shown in this embodiment, it is also possible to set multiple target spaces and update the overlapping area of ​​these multiple target spaces as a new target space.

[0152] In addition, in this embodiment, the target space is set based on an SEM image of a pattern created by the semiconductor manufacturing equipment 100, but it can also be set based on an SEM image created by simulation, etc.

[0153] In addition, in this embodiment, an example has been described in which the evaluation target is set to one chip pattern on a wafer manufactured by the same process, but it is also possible to set multiple chip patterns on a wafer manufactured by the same process as the evaluation target.

[0154] Furthermore, in this embodiment, an example has been described in which the target semiconductor pattern is a line pattern, but it is also possible to implement this if the target semiconductor pattern shape is one that is sensitive to SEM, such as a contact hole.

[0155] Furthermore, in this embodiment, an example was shown in which one line pattern exists in the SEM image, but it is also possible to implement this even if multiple lines, such as a periodic pattern, are included in the field of view of the SEM image.

[0156] Furthermore, although the present embodiment shows an example in which an SEM was used for evaluation, it is also possible to use data acquired from other sensing devices that are sensitive to cross-sectional shapes, such as optical sensing devices. For example, if data that is a set of combinations of reflectances at multiple wavelengths for one sample is output, these sets of reflectances are essentially the same as the feature set of the present invention, and can be similarly implemented by calculating coordinate vectors based on them.

[0157] Furthermore, in this embodiment, all the designed image features are used, but it is also possible to select and reduce the number of features to be used, for example, by selecting features that are sensitive to changes in process conditions based on their correlation with process parameters, by comparing the change in feature with the reproducibility of the feature or fluctuations due to local shape variations to select features that are highly sensitive to shape, or by selecting arbitrary feature values ​​specified by the user in advance. [Example]

[0158] Fifth Embodiment A semiconductor pattern evaluation system and a semiconductor pattern evaluation method according to a fifth embodiment of the present invention will be described with reference to FIG.

[0159] In this embodiment, an example will be described in which the target space is set based on the measurement results of the electrical characteristics of a semiconductor device in the third and fourth embodiments.

[0160] The system configuration for realizing this embodiment is the same as that of embodiment 1 (FIG. 1). Also, the image feature amount in this embodiment is the same as that of embodiment 1 (FIG. 3).

[0161] In this embodiment, in step S1301 for setting a target space in the feature space shown in FIG. 13 , a plurality of samples are created by varying the parameters that are the process conditions in semiconductor manufacturing equipment 100, and top-view SEM images of the samples are taken with CD-SEM 101. Thereafter, the electrical characteristics of the patterns are measured with tester 102, and the process condition parameters, image feature values ​​of these patterns, and electrical characteristic measurement values ​​are transmitted as a set to server 103 via network 104 and stored therein.

[0162] Then, the target space in the feature space is set based on the labeling performed based on the pass / fail judgement made based on the measured values ​​of the electrical characteristics. The other processes are the same as those in the third and fourth embodiments.

[0163] This allows the performance of the pattern to be evaluated quantitatively using the electrical characteristics as a comparison standard, and allows process conditions to be determined and controlled according to the evaluation results.

[0164] In this embodiment, the measurement value of the electrical characteristic tester (tester) 102 is used as the comparison standard for setting the target space, but if the semiconductor pattern shape has an effect, the output result of other test and measurement equipment can also be used as the comparison standard. Also, the output result can be not only a quantitative value, but also one that has already been labeled as OK / NG, etc. [Example]

[0165] Sixth Embodiment A semiconductor pattern evaluation system and a semiconductor pattern evaluation method according to a sixth embodiment of the present invention will be described with reference to FIG.

[0166] In this embodiment, for two consecutive processes, the process window (target space) of the earlier process (e.g., lithography process) is calculated on the assumption that the process conditions and target space in feature space of the later process (e.g., etching process) have already been determined.

[0167] The purpose of this embodiment is to improve manufacturing efficiency by checking how much process margin there is in the earlier process in order to achieve the target pattern shape in the later process when the process conditions for the later process have been determined.

[0168] The system configuration for realizing this embodiment is the same as that of embodiment 1 (FIG. 1). Also, the image feature amount in this embodiment is the same as that of embodiment 1 (FIG. 3).

[0169] The processing steps of this embodiment will now be described.

[0170] First, a plurality of samples are created by varying process parameters (for example, exposure dose and focus height in the case of a lithography device) that indicate process conditions in a semiconductor manufacturing device 100 at the upstream stage (for example, a lithography device).

[0171] Next, a top-view SEM image of the created sample is taken by the CD-SEM 101, and the process parameters and the SEM image are transmitted as a set to the server 103 via the network 104.

[0172] The sample is transmitted to a downstream semiconductor manufacturing equipment 100 (e.g., an etching equipment) and processed under predetermined process conditions. After processing, a top-view SEM image is taken of the sample using a CD-SEM 101, and the process parameters and these SEM images are transmitted as a set to a server 103 via a network 104.

[0173] The server 103 calculates an image feature set (Equation (7)) from a top-view SEM image of the pattern in the previous lithography process, and an image feature set (Equation (8)) from a top-view SEM image of the pattern in the subsequent etching process.

[0174]

number

[0175]

number

[0176] These are plotted in feature space as shown in Figure 22. The arrows in this figure indicate the correspondence between the pattern shape of the sample manufactured in the lithography process at the previous stage and the change caused by processing in the etching process at the subsequent stage.

[0177] Target space information for the subsequent process (etching process) is input to the external input unit 105, and based on whether the pattern shape (coordinates in feature space) after the etching process fits into that target space, the corresponding pattern shape of the previous lithography process is labeled as OK / NG. This makes it possible to determine the target space of the lithography process, i.e., the process window.

[0178] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0179] 100: semiconductor manufacturing equipment, 101: scanning electron microscope (CD-SEM), 102: electrical property testing equipment (tester), 103: server (for data storage and processing), 104: network, 105: external input unit, 106: cross-section observation device, 107: display device (display unit), 201: SEM image, 202: signal waveform, 203: white band, 301, 302: white band peak, 303, 304: bottom signal amount, 305: top signal amount, 306: width of signal waveform (profile), 307, 308, 309, 310: slope of signal waveform, 501: wafer.

Claims

1. A method for evaluating a pattern formed on a surface of a semiconductor wafer, comprising: A feature space is set that includes a plurality of feature amounts that can be calculated from the sensing data of the pattern; a semiconductor pattern evaluation method, characterized in that, in the feature space, a deviation between a coordinate in the feature space calculated from an evaluation target and a reference point in the feature space or a coordinate in a reference space set in advance as a comparison target is calculated as a vector.

2. 2. The semiconductor pattern evaluation method according to claim 1, A semiconductor pattern evaluation method, characterized in that the reference point or reference space is determined based on the feature amount calculated from the pattern shape to be compared.

3. 2. The semiconductor pattern evaluation method according to claim 1, A semiconductor pattern evaluation method characterized in that the reference point or reference space is determined based on the feature of a pattern that realizes an index representing a process state including at least one of device characteristics and defect rate to be compared.

4. 2. The semiconductor pattern evaluation method according to claim 1, A semiconductor pattern evaluation method, characterized in that at least one of evaluation of the performance of a semiconductor manufacturing process, determination of process conditions for the semiconductor manufacturing process, and adjustment of process conditions for the semiconductor manufacturing process is performed based on the vector.

5. 2. The semiconductor pattern evaluation method according to claim 1, The semiconductor pattern evaluation method, wherein the sensing data is a SEM image.

6. 6. The semiconductor pattern evaluation method according to claim 5, a semiconductor pattern evaluation method for determining a semiconductor manufacturing process based on a feature vector calculated by associating the feature calculated from the SEM image with parameters of the semiconductor manufacturing process;

7. 2. The semiconductor pattern evaluation method according to claim 1, The semiconductor pattern evaluation method is characterized in that the feature quantity is a value that quantitatively expresses a feature that captures a change in the three-dimensional cross-sectional shape of the pattern, including at least one of a value that quantitatively expresses a waveform feature of a line profile of the pattern, a feature quantity that indicates local fluctuations of the pattern, a brightness value calculated from a two-dimensional SEM image, or a value calculated by Fourier transform.

8. 2. The semiconductor pattern evaluation method according to claim 1, A semiconductor pattern evaluation method characterized in that a reference point in the feature space or coordinates in the reference space set as the comparison target is input into a scanning electron microscope device, and the deviation from the coordinates in the feature space calculated from an image captured by the scanning electron microscope device is calculated as the vector, and displayed on a display unit of the scanning electron microscope device.

9. 6. The semiconductor pattern evaluation method according to claim 5, associate the feature amount calculated from the SEM image with a parameter of a semiconductor manufacturing process; selecting a specific feature from the plurality of feature amounts based on a correlation with the parameter; A semiconductor pattern evaluation method, characterized in that a semiconductor manufacturing process is determined based on a feature vector calculated using selected feature quantities.

10. A semiconductor manufacturing process management system for managing a semiconductor manufacturing process, A semiconductor manufacturing process management system using the semiconductor pattern evaluation method according to any one of claims 1 to 9.

11. A semiconductor pattern evaluation system for evaluating a pattern formed on a surface of a semiconductor wafer, comprising: It has a server that stores and processes data, the server sets a feature space consisting of a plurality of feature amounts that can be calculated from the sensing data of the pattern; a semiconductor pattern evaluation system that calculates, as a vector, a deviation between coordinates in the feature space calculated from an evaluation target and a reference point in the feature space or coordinates in a reference space that is set in advance as a comparison target.

Images