Redistribution layer and manufacturing method of the same

Abstract

To provide a redistribution layer in which a small opening is formed in an insulating layer with high accuracy, and a manufacturing method of the same.SOLUTION: In a wiring substrate, a redistribution layer 20 includes a first insulating layer 21A, a first main conductive layer 25A including a portion located on a surface of the first insulating layer, a second insulating layer 21B located on the surface of the first insulating layer and including an opening 212 overlapping the first main conductive layer in a plan view, and a second main conductive layer 25B including a portion located on the surface of the second insulating layer and a portion located on a wall surface 213 of the opening. A part of the portion of the second main conductive layer located on the surface of the second insulating layer constitutes a second pad 27B including an auxiliary conductive layer 26 located between the surface of the second insulating layer and the second main conductive layer. The portion of the second main conductive layer located on a wall surface of the opening of the second insulating layer constitutes a second through electrode 28B connected to the first main conductive layer and the second pad. The auxiliary conductive layer includes an inner edge 26x located at an opening end 214 of the opening of the second insulating layer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] TECHNICAL FIELD Embodiments of the present disclosure relate to a redistribution layer and a method for fabricating the same. [Background technology]

[0002] Packaging technology that densely mounts multiple semiconductor elements with different functions, such as CPUs and memories, on a single substrate is attracting attention. A structure that electrically connects multiple semiconductor elements is also called an interposer. An interposer includes, for example, multiple insulating layers stacked in the thickness direction and conductive layers located on the surfaces of each insulating layer. The conductive layers perform the function of, for example, relocating pads or terminals of the semiconductor elements to different locations. A structure that includes multiple insulating layers and multiple conductive layers is also called a rewiring layer.

[0003] Patent Document 1 discloses a structure including a first conductive layer, an insulating layer partially covering the first conductive layer, and a second conductive layer. The insulating layer includes an opening that overlaps the first conductive layer in a plan view. The second conductive layer includes a portion located in the opening of the insulating layer and a portion located on the surface of the insulating layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-22894 Summary of the Invention [Problem to be solved by the invention]

[0005] There is a need to form small openings in insulating layers with high precision.

[0006] An object of the embodiments of the present disclosure is to provide a redistribution layer and a manufacturing method thereof that can effectively solve such problems. [Means for solving the problem]

[0007] The embodiments of the present disclosure relate to the following [1] to

[21] .

[0008] [1] A redistribution layer, a first insulating layer; a first main conductive layer including a portion located on a surface of the first insulating layer; a second insulating layer located on the surface of the first insulating layer and including an opening that overlaps the first main conductive layer in a plan view; a second main conductive layer including a portion located on the surface of the second insulating layer and a portion located on a wall surface of the opening, a portion of the second main conductive layer located on the surface of the second insulating layer constitutes a second pad; a portion of the second main conductive layer located on the wall surface of the opening of the second insulating layer constitutes a second through electrode connected to the first main conductive layer and the second pad; the second pad further includes an auxiliary conductive layer located between the surface of the second insulating layer and the second main conductive layer; The auxiliary conductive layer includes an inner edge positioned at an opening edge of the opening in the second insulating layer.

[0009] [2] In the redistribution layer according to [1], the auxiliary conductive layer may include an outer edge covered by the second main conductive layer.

[0010] [3] In the redistribution layer described in [1], the second pad may include an outer edge, and the auxiliary conductive layer may include an outer edge that forms the outer edge of the second pad.

[0011] [4] In the redistribution layer described in any one of [1] to [3], another part of the portion of the second main conductive layer located on the surface of the second insulating layer may constitute a second wiring extending along the surface of the second insulating layer, and the second wiring may further include the auxiliary conductive layer.

[0012] [5] In the redistribution layer according to any one of [1] to [4], the auxiliary conductive layer may include at least a layer containing titanium or copper.

[0013] [6] In the redistribution layer described in [5], the auxiliary conductive layer may include an auxiliary seed layer containing titanium or copper, and an auxiliary plating layer located on the auxiliary seed layer and containing copper.

[0014] [7] A redistribution layer, a first insulating layer; a first main conductive layer including a portion located on a surface of the first insulating layer; a second insulating layer located on the surface of the first insulating layer and including an opening that overlaps the first main conductive layer in a plan view; a second main conductive layer including a portion located on the surface of the second insulating layer and a portion located on a wall surface of the opening, a portion of the second main conductive layer located on the surface of the second insulating layer constitutes a second pad; a portion of the second main conductive layer located on the wall surface of the opening of the second insulating layer constitutes a second through electrode connected to the first main conductive layer and the second pad; the first main conductive layer includes an inner portion connected to the second through electrode and an outer portion located outside the inner portion in a plan view, The inner portion includes a recess that is recessed relative to the surface of the outer portion.

[0015] [8] In the redistribution layer described in any one of [1] to [7], the second main conductive layer may include a main seed layer containing titanium or copper, and a main plating layer located on the main seed layer and containing copper.

[0016] [9] In the redistribution layer described in any one of [1] to [8], the second insulating layer may include an inorganic layer located on the surface of the first insulating layer and at least partially covering the first main conductive layer, and an organic layer located on the inorganic layer.

[0017]

[10] In the redistribution layer according to any one of [1] to [9], the opening in the second insulating layer may have a dimension of 10 μm or less.

[0018]

[11] A method for manufacturing a redistribution layer, comprising: forming a first insulating layer; forming a first main conductive layer including a portion located on a surface of the first insulating layer; forming a second insulating layer on the surface of the first insulating layer; forming an auxiliary conductive layer including through holes on a surface of the second insulating layer; forming an opening in the second insulating layer that overlaps the through hole of the auxiliary conductive layer in a plan view; forming a second main conductive layer including a portion located on the surface of the second insulating layer and a portion located on a wall surface of the opening.

[0019]

[12] In the method for manufacturing a redistribution layer described in

[11] , the second main conductive layer may be formed at least partially on the auxiliary conductive layer located on the surface of the second insulating layer.

[0020]

[13] In the method for manufacturing a redistribution layer described in

[12] , the auxiliary conductive layer may include an outer edge, and the second main conductive layer may be formed to cover the outer edge of the auxiliary conductive layer.

[0021]

[14] In the method for manufacturing a redistribution layer described in

[12] , the step of forming the second main conductive layer may include the steps of forming a main seed layer, partially forming a resist layer on the main seed layer, partially forming a main plating layer on the main seed layer, removing the resist layer, and removing the portion of the main seed layer that overlaps the resist layer in a planar view.

[0022]

[15] In the method for manufacturing a redistribution layer described in

[14] , the step of forming the second main conductive layer may include a step of removing a portion of the auxiliary conductive layer that overlaps the resist layer in a planar view.

[0023]

[16] The method for manufacturing a redistribution layer according to

[11] may further include a step of removing the auxiliary conductive layer after forming the opening in the second insulating layer.

[0024]

[17] In the method for manufacturing a redistribution layer described in any one of [1] to

[16] , the step of forming the opening in the second insulating layer may include a step of irradiating the through hole in the auxiliary conductive layer with a laser.

[0025]

[18] In the method for manufacturing a redistribution layer described in any one of [1] to

[17] , the second insulating layer may include an inorganic layer located on the surface of the first insulating layer and at least partially covering the first main conductive layer, and an organic layer located on the inorganic layer, and the step of forming the opening in the second insulating layer may include a step of irradiating the organic layer exposed from the through hole of the auxiliary conductive layer with a laser to form an opening in the organic layer, and a step of forming an opening in the inorganic layer.

[0026]

[19] In the method for manufacturing a redistribution layer according to

[18] , the step of forming the opening in the inorganic layer may include the step of irradiating the inorganic layer with the laser.

[0027]

[20] In the method for manufacturing a redistribution layer according to

[18] , the step of forming the openings in the inorganic layer may include the step of forming the openings in the inorganic layer by dry etching.

[0028]

[21] In the method for manufacturing a redistribution layer according to any one of

[11] to

[20] , the opening in the second insulating layer may have a dimension of 10 μm or less. [Effects of the Invention]

[0029] According to embodiments of the present disclosure, small openings can be formed in insulating layers with high precision. [Brief explanation of the drawings]

[0030] [Figure 1] FIG. 1 is a plan view showing a wiring board group according to an embodiment. [Figure 2] 2 is a cross-sectional view of the wiring board group taken along line II-II in FIG. [Figure 3] FIG. 2 is a cross-sectional view showing an example of the configuration of a rewiring layer. [Figure 4] FIG. 2 is a cross-sectional view showing an example of the configuration of a conductive layer. [Figure 5] FIG. 10 is a diagram showing a step of forming a first insulating layer. [Figure 6] 10A to 10C are diagrams showing a step of forming a main seed layer of the first main conductive layer. [Figure 7] FIG. 10 is a cross-sectional view showing a step of forming a main plating layer of the first main conductive layer. [Figure 8] FIG. 10 is a cross-sectional view showing a step of removing a part of the main seed layer of the first main conductive layer. [Figure 9] FIG. 10 is a diagram showing a step of forming a second insulating layer. [Figure 10] 10A to 10C are diagrams illustrating steps of forming an auxiliary conductive layer and a second resist layer. [Figure 11] 10A to 10C are diagrams illustrating a step of forming a through hole in the auxiliary conductive layer. [Figure 12] 10A to 10C are diagrams illustrating a step of forming an opening in the second insulating layer. [Figure 13] 10A to 10C are diagrams illustrating a step of forming a main seed layer of a second main conductive layer. [Figure 14] FIG. 10 is a cross-sectional view showing a step of forming a main plating layer of the second main conductive layer. [Figure 15] FIG. 10 is a cross-sectional view showing a step of removing a part of the main seed layer of the second main conductive layer. [Figure 16] 10A and 10B are cross-sectional views showing a step of bonding the upper surface of the rewiring layer to the substrate. [Figure 17]10A and 10B are cross-sectional views showing a step of irradiating the peeling layer with light. [Figure 18] 10A to 10C are cross-sectional views showing a step of separating the redistribution layer from the carrier substrate. [Figure 19] FIG. 10 is a cross-sectional view showing the configuration of a redistribution layer in a first modified example. [Figure 20] FIG. 10 is a cross-sectional view showing the configuration of a redistribution layer in a second modified example. [Figure 21] FIG. 11 is a cross-sectional view showing the configuration of a redistribution layer in a third modified example. [Figure 22] FIG. 11 is a cross-sectional view showing an example of the configuration of a conductive layer in a third modified example. [Figure 23] 10A to 10C are diagrams illustrating steps of forming an auxiliary conductive layer and a second resist layer. [Figure 24] 10A to 10C are diagrams illustrating a step of forming a through hole in the auxiliary conductive layer. [Figure 25] 10A to 10C are diagrams illustrating a step of forming an opening in the second insulating layer. [Figure 26] 10A to 10C are diagrams illustrating a step of forming a main seed layer of a second main conductive layer. [Figure 27] FIG. 10 is a cross-sectional view showing a step of forming a main plating layer of the second main conductive layer. [Figure 28] FIG. 10 is a cross-sectional view showing a step of removing a part of the main seed layer and a part of the auxiliary conductive layer of the second main conductive layer. [Figure 29] FIG. 11 is a cross-sectional view showing the configuration of a redistribution layer in a fourth modified example. [Figure 30] 10A to 10C are diagrams illustrating a step of forming a second insulating layer including an inorganic layer and an organic layer. [Figure 31] 10A to 10C are diagrams illustrating a step of forming an auxiliary conductive layer. [Figure 32] 10A to 10C are diagrams illustrating a step of forming an opening in the organic layer of the second insulating layer. [Figure 33] 10A to 10C are diagrams illustrating a step of forming an opening in the inorganic layer of the second insulating layer. [Figure 34] FIG. 13 is a cross-sectional view showing the configuration of a rewiring layer in a fifth modified example. [Figure 35] 10A to 10C are diagrams illustrating a step of removing the auxiliary conductive layer. [Figure 36] 10A to 10C are diagrams illustrating a step of forming a main seed layer of a second main conductive layer. [Figure 37] 10A and 10B are diagrams illustrating examples of products on which a redistribution layer is mounted. DETAILED DESCRIPTION OF THE INVENTION

[0031] The configuration of the redistribution layer and its manufacturing method will be described in detail with reference to the drawings. The following embodiments are examples of embodiments of the present disclosure, and the present disclosure should not be construed as being limited to these embodiments. Terms such as "substrate," "base material," "sheet," and "film" are not distinguished from one another solely based on differences in name. For example, the concept of "substrate" includes components that may be called sheets or films. "Surface" refers to a surface that coincides with the planar direction of the target plate-like component when viewed holistically and comprehensively. The normal direction used with respect to a plate-like component refers to the normal direction to the component's surface. As used herein, terms such as "parallel" and "orthogonal," as well as length and angle values, that specify shape, geometric conditions, and their degrees, are interpreted without strict meaning, but rather include a range within which similar functions can be expected.

[0032] In this specification, when multiple upper limit candidates and multiple lower limit candidate values ​​are listed for a certain parameter, the numerical range of the parameter may be constructed by combining any one upper limit candidate with any one lower limit candidate. For example, consider a description that reads, "Parameter B is, for example, A1 or more, or may be A2 or more, or may be A3 or more. Parameter B is, for example, A4 or less, or may be A5 or less, or may be A6 or less." In this case, the numerical range of parameter B may be A1 or more and A4 or less, A1 or more and A5 or less, A1 or more and A6 or less, A2 or more and A4 or less, A2 or more and A5 or less, A2 or more and A6 or less, A3 or more and A4 or less, A3 or more and A5 or less, or A3 or more and A6 or less.

[0033] In the drawings referred to in this embodiment, the same parts or parts having similar functions are denoted by the same or similar reference numerals, and repeated explanations thereof may be omitted. Furthermore, the dimensional ratios of the drawings may differ from the actual ratios for the convenience of explanation, and some components may be omitted from the drawings.

[0034] FIG. 1 is a plan view showing an example of a wiring board group 10. FIG. 2 is a cross-sectional view of the wiring board group 10 of FIG. 1 taken along line II-II. The wiring board group 10 includes a plurality of wiring boards having the same structure. As will be described later, a plurality of wiring boards are obtained by dividing the wiring board group 10. Each of the plurality of wiring boards includes a rewiring layer. That is, the wiring board group 10 includes a plurality of rewiring layers 20.

[0035] The wiring board group 10 has a first direction D1, a second direction D2, and a third direction D3. The first direction D1 and the second direction D2 are included in the surface direction of the wiring board group 10. The first direction D1 is perpendicular to the second direction D2. The third direction D3 is the thickness direction of the wiring board group 10. The third direction D3 is perpendicular to the first direction D1 and the second direction D2.

[0036] The wiring board group 10 includes a carrier substrate 12, a release layer 13, and a plurality of redistribution layers 20. The release layer 13 is located between the carrier substrate 12 and the redistribution layers 20 in the thickness direction of the wiring board group 10. The release layer 13 is located on the carrier substrate 12.

[0037] Each component of the wiring board group 10 will be described.

[0038] (Rewiring layer) The multiple redistribution layers 20 have the same structure as one another. For example, as shown in FIG. 1, the multiple redistribution layers 20 may have the same structure in a planar view. As shown in FIG. 1, the multiple redistribution layers 20 may be regularly arranged in the surface direction of the wiring substrate group 10. For example, the multiple redistribution layers 20 may be regularly arranged in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may be parallel to the sides of the carrier substrate 12.

[0039] 2 is a cross-sectional view of the wiring board group 10 taken along line II-II in FIG. 1. The redistribution layer 20 includes a lower surface 201 and an upper surface 202. The lower surface 201 faces the carrier substrate 12. The upper surface 202 is located opposite the lower surface 201. The redistribution layer 20 includes a plurality of insulating layers 21 stacked in a third direction D3 and a plurality of main conductive layers 25 located on the surfaces of the insulating layers 21, for example. The insulating layers 21 may extend in the third direction D3 of the wiring board group 10 from the lower surface 201 to the upper surface 202.

[0040] In this specification, a "lower surface" such as the lower surface 201 means the surface facing the carrier substrate 12 in the state of the wiring substrate group 10. An "upper surface" means the surface located opposite the "lower surface" in the thickness direction.

[0041] Some of the main conductive layers 25 may form pads 27. The pads 27 are located on the surface of the insulating layer 21, for example, on the upper surface. The pads 27 may be connected to through electrodes (described later) in the third direction D3. The pads 27 have dimensions in a plan view that are larger than the dimensions of the wiring (described later) and the through electrodes.

[0042] Some of the multiple main conductive layers 25 may form through electrodes 28. The through electrodes 28 extend in the third direction D3. For example, the through electrodes 28 are located on the wall surfaces of openings formed in the insulating layer 21. The through electrodes 28 may be connected to pads 27 in the third direction D3. The through electrodes 28 may be connected to two pads 27 in the third direction D3. In this case, the through electrodes 28 can electrically connect the two pads 27.

[0043] Some of the multiple main conductive layers 25 may form wiring 29. The wiring 29 is located on the surface, for example, on the upper surface, of the insulating layer 21. The wiring 29 extends at least partially along the surface of the insulating layer 21 in the first direction D1 or the second direction D2.

[0044] The redistribution layer 20 has a thickness T1. The thickness T1 is, for example, 20 μm or more, and may be 30 μm or more, or 40 μm or more. The thickness T1 is, for example, 100 μm or less, and may be 90 μm or less, or 80 μm or less. The thickness T1 is the distance in the third direction D3 from the lower surface 201 to the upper surface 202. The dimensions of the components of the wiring board group 10 in the third direction D3, such as the thickness T1, are calculated based on a cross-sectional image of the wiring board group 10 taken by a scanning electron microscope.

[0045] The thickness T2 of each of the multiple insulating layers 21 in the redistribution layer 20 is, for example, 4.0 μm or more, and may be 6.0 μm or more. The thickness T2 of each of the multiple insulating layers 21 in the redistribution layer 20 is, for example, 12.0 μm or less, and may be 10.0 μm or less. The thicknesses T2 of the multiple insulating layers 21 may be the same or different.

[0046] 3 is a cross-sectional view showing an example of the configuration of the redistribution layer 20. The multiple insulating layers 21 include at least a first insulating layer 21A and a second insulating layer 21B. The second insulating layer 21B is located on the surface of the first insulating layer 21A, for example, on the upper surface 211. The lower surface of the first insulating layer 21A faces the release layer 13. The lower surface of the first insulating layer 21A may be in contact with the release layer 13. Although not shown, the multiple insulating layers 21 may further include a third insulating layer or the like located on the upper surface 211 of the second insulating layer 21B.

[0047] The second insulating layer 21B includes at least one opening 212. The opening 212 penetrates the second insulating layer 21B in the third direction D3. The opening 212 includes a wall surface 213 and an opening end 214. The wall surface 213 extends in the third direction D3 from the upper surface 211 to the lower surface of the second insulating layer 21B. The opening end 214 is an end of the wall surface 213 on the upper surface 211 of the second insulating layer 21B.

[0048] Opening 212 has dimension K2. Dimension K2 is calculated based on a cross-sectional image of wiring board group 10 taken by a scanning electron microscope. The cross-sectional image is an image of a cross section of wiring board group 10 cut along the direction in which multiple openings 212 are arranged.

[0049] The dimension K2 is, for example, 10.0 μm or less, and may be 8.0 μm or less, or 5.0 μm or less. The smaller the dimension K2, the higher the accuracy required for the processing method for forming the opening 212 in the first insulating layer 21A. The dimension K2 is, for example, 1.0 μm or more, and may be 2.0 μm or more, or 3.0 μm or more.

[0050] Although not shown, the first insulating layer 21A may also include an opening.

[0051] When describing a configuration common to insulating layers such as the first insulating layer 21A and the second insulating layer 21B, the term "insulating layer 21" and the reference numerals therefor are used.

[0052] The insulating layer 21 includes at least an organic layer. In this embodiment, the insulating layer 21 is made of an organic layer. The organic layer includes an organic material having insulating properties. Examples of the organic material include polyimide, epoxy, and acrylic.

[0053] The organic layer of the insulating layer 21 may include multiple fillers distributed in the organic material. By mixing multiple fillers into the organic material, the electrical properties, mechanical properties, thermal properties, etc. of the organic layer can be adjusted. The filler may include an inorganic compound such as an inorganic oxide or an inorganic nitride. An example of the inorganic oxide is silicon oxide. An example of the inorganic nitride is silicon nitride.

[0054] The size of the filler is, for example, 0.01 μm or more, and may be 0.05 μm or more, or 0.10 μm or more. The size of the filler is, for example, 1.00 μm or less, and may be 0.50 μm or less, or 0.20 μm or less. The size of the filler is the circle-equivalent diameter of the filler 38b. The circle-equivalent diameter is calculated based on the average value of the cross-sectional area of ​​the filler calculated from an image of the cross section of the organic layer of the insulating layer 21.

[0055] The organic layer of the insulating layer 21 may have a filler occupancy of 30% or more. When the organic layer has a filler occupancy of 30% or more, the dielectric constant or dielectric loss tangent of the organic layer is reduced. The filler occupancy of 30% or more is the ratio of the cross-sectional area of ​​the filler to the cross-sectional area of ​​the organic layer of the insulating layer 21. The filler occupancy is calculated based on an image of the cross section of the organic layer of the insulating layer 21.

[0056] The filler occupancy rate of the organic layer of insulating layer 21 may be 50% or more, or 70% or more. The filler occupancy rate of the organic layer of insulating layer 21 is, for example, 90% or less, or may be 85% or less, or may be 80% or less.

[0057] The filler content of the organic layer of insulating layer 21 is, for example, 10% by weight or more, optionally 20% by weight or more, or 25% by weight or more. The filler content of the organic layer of insulating layer 21 is, for example, 70% by weight or less, optionally 60% by weight or less, or optionally 50% by weight or less.

[0058] The organic layer of the insulating layer 21 preferably has a low dielectric constant. A low dielectric constant of the organic layer of the insulating layer 21 reduces dielectric loss in electrical signals transmitted in the redistribution layer 20. The dielectric constant of the organic layer of the insulating layer 21 is, for example, 3.4 or less, or may be 3.0 or less, or 2.7 or less. The dielectric constant of the organic layer of the insulating layer 21 is, for example, 2.0 or more, or may be 2.2 or more, or 2.4 or more.

[0059] The organic layer of the insulating layer 21 preferably has a low dielectric loss tangent. A low dielectric loss tangent of the organic layer of the insulating layer 21 reduces dielectric loss in electrical signals transmitted in the redistribution layer 20. The dielectric loss tangent of the organic layer of the insulating layer 21 is, for example, 0.030 or less, or may be 0.010 or less, or may be 0.008 or less. The dielectric loss tangent of the organic layer of the insulating layer 21 is, for example, 0.001 or more, or may be 0.002 or more, or may be 0.003 or more.

[0060] In this specification, physical properties such as the dielectric constant and the dielectric loss tangent are measured in an environment of a temperature of 23±2°C and a relative humidity of 50±5%, unless otherwise specified. In this specification, physical properties having frequency dependence, such as the dielectric constant and the dielectric loss tangent, are measured at a frequency of 1 kHz, unless otherwise specified.

[0061] Organic materials with low dielectric constants and low dielectric loss tangents generally do not have photosensitivity. Photosensitivity is the property of a substance undergoing a chemical change when irradiated with light. If the organic layer of the insulating layer 21 has photosensitivity, the organic layer can be processed by exposure and development processes. For example, openings can be formed in the organic layer by exposure and development processes. If the organic layer of the insulating layer 21 does not have photosensitivity, other processing methods are required. For example, openings can be formed in the organic layer of the insulating layer 21 by laser processing. In laser processing, the organic layer is processed by ablation caused by irradiating the organic layer with a laser.

[0062] In this embodiment, the organic material of the organic layer of the insulating layer 21 has a low relative dielectric constant and a low dielectric loss tangent. As will be described later, the opening 212 in the insulating layer 21 is formed by irradiating the insulating layer 21 with a laser.

[0063] An example of a material that constitutes the organic layer of the insulating layer 21 is PN2030 manufactured by Toray Industries, Inc.

[0064] As shown in FIG. 3, the plurality of main conductive layers 25 includes at least a plurality of first main conductive layers 25A and a plurality of second main conductive layers 25B.

[0065] The plurality of first main conductive layers 25A include at least a portion located on a surface such as the upper surface 211 of the first insulating layer 21A. The portion of the first main conductive layer 25A located on the upper surface 211 of the first insulating layer 21A constitutes a first pad 27A or a first wiring 29A. When the first insulating layer 21A includes an opening, the plurality of first main conductive layers 25A may include a portion located on a wall surface of the opening.

[0066] 3, the first pad 27A overlaps the opening 212 of the second insulating layer 21B in a plan view. In other words, the opening 212 of the second insulating layer 21B is formed to overlap the first pad 27A in a plan view. The first pad 27A has a dimension K1. The dimension K1 of the first pad 27A is larger than the dimension K2 of the opening 212.

[0067] The dimension K1 is the diameter of a circle equivalent to the area of ​​the first pad 27A in plan view.

[0068] The smaller the difference between dimensions K1 and K2, the higher the accuracy required for the processing method for forming opening 212 in first insulating layer 21A. The difference between dimensions K1 and K2 is, for example, 10.0 μm or less, or may be 8.0 μm or less, or 5.0 μm or less. The difference between dimensions K1 and K2 is, for example, 1.0 μm or more, or may be 2.0 μm or more, or 3.0 μm or more.

[0069] The multiple second main conductive layers 25B include portions located on a surface such as the upper surface 211 of the second insulating layer 21B. The portions of the second main conductive layers 25B located on the upper surface 211 of the second insulating layer 21B constitute second pads 27B or second wiring 29B. For example, some of the multiple second main conductive layers 25B located on the upper surface 211 constitute second pads 27B, and some other of the multiple second main conductive layers 25B constitute second wiring 29B.

[0070] The plurality of second main conductive layers 25B also include a portion located on the wall surface 213 of the opening 212 of the second insulating layer 21B. The portion of the second main conductive layer 25B located on the wall surface 213 of the opening 212 constitutes a second through electrode 28B. The second through electrode 28B is connected to the first pad 27A and the second pad 27B. The second through electrode 28B can electrically connect the first pad 27A and the second pad 27B.

[0071] When describing a configuration common to pads such as the first pad 27A and the second pad 27B, the term and symbol "pad 27" are used. When describing a configuration common to through electrodes such as the second through electrode 28B, the term and symbol "through electrode 28" are used. When describing a configuration common to wiring such as the first wiring 29A and the second wiring 29B, the term and symbol "wiring 29" are used.

[0072] When describing a configuration common to main conductive layers such as the first main conductive layer 25A and the second main conductive layer 25B, the term "main conductive layer 25" and reference numerals are used.

[0073] The main conductive layer 25 may include a main seed layer 251 and a main plating layer 252. The main seed layer 251 is a conductive layer formed by physical film formation such as sputtering. The main plating layer 252 is a conductive layer formed on the main seed layer 251 by electrolytic plating.

[0074] The main seed layer 251 may contain a metal material such as copper, nickel, titanium, chromium, or zinc. The main seed layer 251 may contain a compound of these metal materials. The main seed layer 251 may include multiple layers. The main seed layer 251 preferably contains titanium or copper. The material of the main plating layer 252 is a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, or zinc. The material of the main plating layer 252 may also be an alloy containing the above-mentioned metal. The main plating layer 252 preferably contains copper.

[0075] As shown in FIG. 3 , the second pad 27B may further include an auxiliary conductive layer 26 located between the upper surface 211 of the second insulating layer 21B and the second main conductive layer 25B. The auxiliary conductive layer 26 surrounds the opening 212 of the second insulating layer 21B in a planar view. The auxiliary conductive layer 26 includes an inner edge 26x and an outer edge 26y in a planar view. The inner edge 26x is the inner edge of the outline of the auxiliary conductive layer 26 in a planar view. The outer edge 26y is the outer edge of the outline of the auxiliary conductive layer 26 in a planar view. In this application, "inner" means a direction toward the center point of the opening 212 in a planar view. In this application, "outer" means a direction away from the center point of the opening 212 in a planar view.

[0076] Inner edge 26x of auxiliary conductive layer 26 surrounds opening 212 in second insulating layer 21B in plan view. As will be described later, opening 212 is formed by processing second insulating layer 21B using auxiliary conductive layer 26 as a mask. Therefore, inner edge 26x of auxiliary conductive layer 26 is located at opening edge 214 of opening 212.

[0077] 3, the outer edge 26y of the auxiliary conductive layer 26 may be covered by the second main conductive layer 25B of the second pad 27B. In this case, the second pad 27B includes an inner portion including the second main conductive layer 25B and the auxiliary conductive layer 26, and an outer portion located outside the inner portion in a plan view. The outer portion includes the second main conductive layer 25B but does not include the auxiliary conductive layer 26. A thickness T4 of the outer portion may be smaller than a thickness T3 of the inner portion.

[0078] The difference between the thickness T3 of the inner portion and the thickness T4 of the outer portion is, for example, 10 nm or more, or may be 30 nm or more, or 100 nm or more. The difference between the thickness T3 of the inner portion and the thickness T4 of the outer portion is, for example, 5.0 μm or less, or may be 3.0 μm or less, or may be 1.0 μm or less.

[0079] 3, the second wiring 29B may include the second main conductive layer 25B but not the auxiliary conductive layer 26. The thickness T5 of the second wiring 29B may be smaller than the thickness T3 of the inner portion of the second pad 27B.

[0080] 3, the second through electrode 28B includes a second main conductive layer 25B but does not include an auxiliary conductive layer 26. The second main conductive layer 25B of the second through electrode 28B may be continuous with the second main conductive layer 25B of the second pad 27B. For example, the main seed layer 251 of the second through electrode 28B may be continuous with the main seed layer 251 of the second pad 27B. For example, the main plating layer 252 of the second through electrode 28B may be continuous with the main plating layer 252 of the second pad 27B.

[0081] As shown in FIG. 3 , the main seed layer 251 of the second pad 27B extends along the upper surface 211 of the second insulating layer 21B. Meanwhile, the main seed layer 251 of the second through-hole electrode 28B extends along the wall surface 213 of the opening 212 of the second insulating layer 21B. If the auxiliary conductive layer 26 is not disposed on the upper surface 211, the main seed layer 251 of the second pad 27B and the main seed layer 251 of the second through-hole electrode 28B are connected at the opening edge 214 of the opening 212. As described above, the main seed layer 251 is formed by physical film deposition such as sputtering. It is not easy to form a main seed layer 251 with sufficient thickness at an edge such as the opening edge 214 by physical film deposition. In particular, if the second insulating layer 21B contains a filler, unevenness occurs on the surface of the second insulating layer 21B, which tends to reduce the thickness of the main seed layer 251 at the opening edge 214.

[0082] In the present embodiment, the second pad 27B includes an auxiliary conductive layer 26 including an inner edge 26x located at the opening edge 214 of the opening 212. The step of forming the main seed layer 251 by physical deposition is performed with the auxiliary conductive layer 26 disposed at the opening edge 214 of the opening 212. The main seed layer 251 is stably formed by physical deposition on the upper surface of the auxiliary conductive layer 26, the side surface of the auxiliary conductive layer 26, i.e., the inner edge 26x, and the wall surface 213 of the opening 212. Therefore, the main seed layer 251 located on the upper surface 211 of the second insulating layer 21B and the main seed layer 251 located on the wall surface 213 of the opening 212 are stably electrically connected. Therefore, the main plating layer 252 of the second pad 27B and the main plating layer 252 of the second through electrode 28B are stably formed in the plating step.

[0083] The auxiliary conductive layer 26 includes at least an auxiliary seed layer 261. Like the main seed layer 251, the auxiliary seed layer 261 is a layer having electrical conductivity that is formed by physical film formation such as sputtering.

[0084] The auxiliary seed layer 261 may contain a metal material such as copper, nickel, titanium, chromium, or zinc. The auxiliary seed layer 261 may also contain a compound of these metal materials. The auxiliary seed layer 261 may include multiple layers. The auxiliary seed layer 261 preferably contains titanium or copper.

[0085] 4 is a cross-sectional view showing an example of the configuration of the main conductive layer 25 and the auxiliary conductive layer 26. The main seed layer 251 of the main conductive layer 25, such as the second main conductive layer 25B, may include a first layer 2511 and a second layer 2512. The second layer 2512 is located between the first layer 2511 and the main plating layer 252.

[0086] The material of the first layer 2511 is different from the material of the second layer 2512 and the material of the main plating layer 252. Examples of materials for the first layer 2511 include titanium, molybdenum, tungsten, tantalum, nickel, chromium, aluminum, compounds thereof, and alloys thereof. The first layer 2511 preferably contains titanium. The first layer 2511 may have higher adhesion to the insulating layer 21 than the second layer 2512.

[0087] The second layer 2512 may include a metal material such as copper, nickel, titanium, chromium, or zinc. The second layer 2512 may also include a compound of these metal materials. The material of the second layer 2512 may be the same as the material of the main plating layer 252.

[0088] The auxiliary seed layer 261 of the auxiliary conductive layer 26 may include a first layer 2611 and a second layer 2612, similar to the main seed layer 251 of the main conductive layer 25. The second layer 2612 is located between the first layer 2611 and the main conductive layer 25. Examples of materials for the first layer 2611 are the same as the examples of materials for the first layer 2511. Examples of materials for the second layer 2612 are the same as the examples of materials for the second layer 2512.

[0089] (carrier board) The carrier substrate 12 is a member that supports the redistribution layer 20. The carrier substrate 12 may include, for example, a glass substrate, a quartz substrate, a sapphire substrate, a resin substrate, a silicon substrate, a silicon carbide substrate, an alumina (Al2O3) substrate, an aluminum nitride (AlN) substrate, a zirconia oxide (ZrO2) substrate, a lithium niobate substrate, or a tantalum niobate substrate. The resin substrate may include an organic material. For example, the resin substrate may include epoxy resin, polyethylene, polypropylene, or the like. The thickness of the carrier substrate 12 is, for example, 100 μm or more, or may be 200 μm or more, or may be 500 μm or more. The thickness of the carrier substrate 12 is, for example, 2 mm or less, or may be 1.5 mm or less, or may be 1 mm or less.

[0090] (peeling layer) The release layer 13 is a layer that facilitates the operation of peeling the redistribution layer 20 from the carrier substrate 12. The release layer 13 includes a first lower surface 131 that faces the carrier substrate 12 and a first upper surface 132 that is located on the opposite side of the first lower surface 131. The release layer 13 includes, for example, a resin.

[0091] The release layer 13 is configured so that the adhesion between the release layer 13 and the redistribution layer 20 is reduced by some kind of trigger. The trigger may be irradiation of the release layer 13 with light of a specific wavelength. For example, the release layer 13 may be decomposed by being irradiated with light of a specific wavelength. The trigger may be heating the release layer 13. For example, the release layer 13 may contain a thermoplastic resin.

[0092] The thickness of the release layer 13 is, for example, 0.1 μm or more, optionally 0.2 μm or more, or 0.3 μm or more. The thickness of the release layer 13 is, for example, 1.0 μm or less, optionally 0.8 μm or less, or optionally 0.5 μm or less.

[0093] (Method of manufacturing a wiring board group) A method for manufacturing the wiring board group 10 will now be described.

[0094] A carrier substrate 12 is prepared. Then, as shown in FIG. 5, a release layer 13 is formed on the carrier substrate 12. The process of forming the release layer 13 includes, for example, a coating process of coating a solution containing a resin and a solvent, and a drying process of evaporating the solvent after the coating process. Examples of the solvent include propylene glycol monomethyl ether, 2-methoxy-1-methylethyl acetate, N-methyl-2-pyrrolidone, γ-butyrolactone, ethyl lactate, and toluene. The drying process includes, for example, a step of heating the carrier substrate 12.

[0095] 5, a step of forming a first insulating layer 21A on the release layer 13 is performed. The step of forming the first insulating layer 21A includes, for example, a coating step of coating a solution containing an organic material and a solvent on the release layer 13, and a drying step of evaporating the solvent after the coating step. Examples of the solvent include propylene glycol monomethyl ether, 2-methoxy-1-methylethyl acetate, N-methyl-2-pyrrolidone, γ-butyrolactone, ethyl lactate, and toluene. The drying step includes, for example, a step of heating the carrier substrate 12.

[0096] The step of forming first insulating layer 21A may include a step of attaching a film including a layer of resin that constitutes a surface layer to release layer 13, instead of the coating step.

[0097] Although not shown, before the step of forming first insulating layer 21A, a step of forming an intermediate layer on release layer 13 may be performed. The intermediate layer may be, for example, a layer that blocks light irradiated onto release layer 13.

[0098] 6, a main seed layer 251 is formed on the upper surface 211 of the first insulating layer 21A. The main seed layer 251 is formed by, for example, sputtering.

[0099] Next, as shown in FIG. 7, a first resist layer 71 is formed partially on the main seed layer 251. The first resist layer 71 has an opening 711 penetrating the first resist layer 71 in the thickness direction. In a plan view, the opening 711 has a shape corresponding to the main plating layer 252 of the first main conductive layer 25A. The opening 711 is formed by processing the first resist layer 71 by, for example, photolithography. Next, a plating process is carried out. In the plating process, as shown in FIG. 7, the main plating layer 252 is formed in the opening 711 by electrolytic plating.

[0100] Next, the first resist layer 71 is removed, as shown in Fig. 8. Next, the main seed layer 251 that overlapped the first resist layer 71 is removed, as shown in Fig. 8. In this manner, the first main conductive layer 25A including the main seed layer 251 and the main plating layer 252 is formed. The first main conductive layer 25A includes at least a portion located on the upper surface 211 of the first insulating layer 21A.

[0101] 9, a step of forming a second insulating layer 21B on the upper surface 211 of the first insulating layer 21A is performed. The second insulating layer 21B is formed so as to cover the plurality of first main conductive layers 25A on the first insulating layer 21A. The step of forming the second insulating layer 21B may include a coating step and a drying step, similar to the step of forming the first insulating layer 21A. The step of forming the second insulating layer 21B may include a step of attaching a film to the upper surface 211 of the first insulating layer 21A instead of the coating step, similar to the step of forming the first insulating layer 21A.

[0102] 10, an auxiliary seed layer 261 is formed on the upper surface 211 of the second insulating layer 21B. The auxiliary seed layer 261 is formed by, for example, sputtering.

[0103] 10, a second resist layer 72 is formed partially on the auxiliary seed layer 261. The second resist layer 72 has an opening 721 penetrating the second resist layer 72 in the thickness direction. In a plan view, the opening 721 has a shape corresponding to the above-mentioned opening 212 in the second insulating layer 21B. The opening 721 is formed by processing the second resist layer 72 by, for example, photolithography.

[0104] Next, a step of processing the auxiliary seed layer 261 is performed using the second resist layer 72 as a mask. For example, the auxiliary seed layer 261 is processed by wet etching. As a result, as shown in FIG. 11, through-holes 26c are formed in the auxiliary seed layer 261. The outline of the auxiliary seed layer 261 surrounding the through-holes 26c forms the inner edge 26x. Next, the second resist layer 72 is removed.

[0105] 12, a step of forming opening 212 in second insulating layer 21B is performed. For example, a laser is irradiated toward second insulating layer 21B exposed from through hole 26c in auxiliary seed layer 261. By processing second insulating layer 21B with the laser, opening 212 overlapping with through hole 26c in plan view is formed in second insulating layer 21B. Opening edge 214 of opening 212 coincides with inner edge 26x of auxiliary seed layer 261.

[0106] After the opening 212 is formed in the second insulating layer 21B, a step may be performed to remove the resin remaining inside the opening 212. For example, plasma etching may be performed.

[0107] 13, a main seed layer 251 is formed on the upper surface 211 of the second insulating layer 21B and on the auxiliary seed layer 261. The main seed layer 251 is also formed on the wall surface 213 of the opening 212 and on the upper surface of the first main conductive layer 25A exposed from the opening 212. The main seed layer 251 is formed by, for example, sputtering. The main seed layer 251 may cover the outer edge 26y of the auxiliary seed layer 261.

[0108] Next, as shown in FIG. 14, a third resist layer 73 is formed partially on the main seed layer 251. The third resist layer 73 has an opening 731 penetrating the third resist layer 73 in the thickness direction. In a plan view, the opening 731 has a shape corresponding to the main plating layer 252 of the second main conductive layer 25B. The opening 731 is formed by processing the third resist layer 73 by, for example, photolithography. Next, a plating process is performed. In the plating process, as shown in FIG. 14, the main plating layer 252 is formed in the opening 731 by electrolytic plating.

[0109] Next, as shown in FIG. 15, the third resist layer 73 is removed. Next, as shown in FIG. 15, the main seed layer 251 that overlapped the third resist layer 73 is removed. In this manner, a second main conductive layer 25B including the main seed layer 251 and the main plating layer 252 is formed. The second main conductive layer 25B includes a portion located on the upper surface 211 of the second insulating layer 21B and a portion located on the wall surface 213 of the opening 212 in the second insulating layer 21B. Through the above-described multiple steps, a redistribution layer 20 including multiple insulating layers 21 and multiple conductive layers is obtained. By forming multiple redistribution layers 20 on the carrier substrate 12, a wiring substrate group 10 is obtained.

[0110] According to the present embodiment, the opening 212 in the second insulating layer 21B is formed by processing the second insulating layer 21B using the auxiliary conductive layer 26 as a mask. The through hole 26c in the auxiliary conductive layer 26 is formed by processing the auxiliary conductive layer 26 using, for example, a second resist layer 72 processed by photolithography. Even if the second insulating layer 21B does not have photosensitivity, the opening 212 is formed in the second insulating layer 21B with the precision of photolithography. Therefore, the opening 212 is stably formed on the first pad 27A. Therefore, the second through electrode 28B formed in the opening 212 is stably connected to the first pad 27A.

[0111] When plasma etching is performed after the opening 212 is formed in the second insulating layer 21B, filler is likely to appear on the surface of the second insulating layer 21B. In the present embodiment, an auxiliary seed layer 261 including an inner edge 26x located at the opening edge 214 of the opening 212 is disposed on the upper surface 211 of the second insulating layer 21B. Therefore, even if the surface of the second insulating layer 21B is uneven, the seed layer can have a sufficient thickness at the opening edge 214 of the opening 212. This improves the stability of the plating process for forming the main plating layer 252 of the second main conductive layer 25B.

[0112] (Method of manufacturing a wiring board) Next, a method for manufacturing the wiring board 11 will be described.

[0113] A wiring board group 10 is prepared. Then, a dividing process is performed to divide the wiring boards 11. As a result, a plurality of wiring boards 11 are manufactured. The wiring board 11 includes a carrier substrate 12, a release layer 13 located on the carrier substrate 12, and a rewiring layer 20 located on the release layer 13.

[0114] 16 and 17 , after the dividing step, a bonding step may be performed in which the wiring substrate 11 is bonded to a substrate 81. The substrate 81 may include a base material 811 and a plurality of terminals 812 located on the base material 811. The substrate 81 may include an adhesive layer 813 covering the plurality of terminals. The adhesive layer 813 may be provided on the wiring substrate 11. In the bonding step, as shown in FIG. 17 , the main conductive layer 25 located on the upper surface 202 of the redistribution layer 20 may be electrically connected to the terminals 812 of the substrate 81.

[0115] 17 and 18, a peeling process may be performed to peel the redistribution layer 20 from the carrier substrate 12. The peeling process may include an irradiation process of irradiating the peeling layer 13 with light L, as shown in FIG. 17. In the irradiation process, the light L may reach the peeling layer 13 after passing through the carrier substrate 12. The peeling layer 13 may be decomposed by heat generated by the irradiation of the light L. The decomposition reduces the adhesion between the carrier substrate 12 and the redistribution layer 20. Therefore, as shown in FIG. 18, the redistribution layer 20 is transferred from the carrier substrate 12 to a substrate 81.

[0116] The structure including the transferred redistribution layer 20 includes a substrate 81 and the redistribution layer 20 located on the substrate 81. This structure may also be referred to as a wiring substrate. In the wiring substrate shown in FIG. 18, the upper surface 202 of the redistribution layer 20 faces the substrate 81.

[0117] Although not shown, the method of use and distribution of the redistribution layer 20 are not particularly limited. For example, a semiconductor element may be mounted on the lower surface 201 of the redistribution layer 20. The semiconductor element includes a transistor formed of a semiconductor such as silicon. The semiconductor element may be, for example, a CPU, a GPU, an FPGA, a sensor, a memory, or the like. The semiconductor element may be a chiplet in which semiconductor elements such as a CPU, a GPU, an FPGA, a sensor, a memory, or the like are divided according to function.

[0118] Although not shown, the redistribution layer 20 may be manufactured on a member including a conductive layer such as the terminal 812, such as the substrate 81. In this case, the redistribution layer 20 is used with the lower surface 201 of the redistribution layer 20 facing the substrate 81. In this case, a semiconductor element may be mounted on the upper surface 202 of the redistribution layer 20.

[0119] The redistribution layer 20 may be distributed in the form of a wiring substrate group 10. The redistribution layer 20 may be distributed in the form of a wiring substrate 11. The redistribution layer 20 may be distributed after being transferred from the carrier substrate 12 to the substrate 81.

[0120] The above-described embodiment can be modified in various ways. Below, modified examples will be described with reference to the drawings as necessary. In the following description and the drawings used in the following description, parts that can be configured similarly to the above-described embodiment will be designated by the same reference numerals as those used for corresponding parts in the above-described embodiment. Duplicate descriptions will be omitted. Furthermore, if it is clear that the effects obtained in the above-described embodiment can also be obtained in modified examples, the description of those effects may be omitted.

[0121] (First Modification) 19 is a cross-sectional view showing the redistribution layer 20 in the first modified example. The auxiliary conductive layer 26 of the second pad 27B may include an auxiliary seed layer 261 and an auxiliary plating layer 262. The auxiliary plating layer 262 is located between the auxiliary seed layer 261 and the second main conductive layer 25B.

[0122] The auxiliary plating layer 262 is a conductive layer formed on the auxiliary seed layer 261 by electrolytic plating, similar to the main seed layer 251. The material of the auxiliary plating layer 262 is, for example, a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, or zinc. The material of the auxiliary plating layer 262 may also be an alloy containing the above-mentioned metals. The auxiliary plating layer 262 preferably contains copper.

[0123] (Second Modification) 20 is a cross-sectional view showing the redistribution layer 20 in the second modification. Similar to the second pad 27B, the second wiring 29B may further include an auxiliary conductive layer 26 located between the upper surface 211 of the second insulating layer 21B and the second main conductive layer 25B. The side surfaces of the auxiliary conductive layer 26 of the second wiring 29B may be covered by the second main conductive layer 25B.

[0124] The auxiliary conductive layer 26 of the second wiring 29B includes at least an auxiliary seed layer 261. Although not shown, the auxiliary conductive layer 26 of the second wiring 29B may further include an auxiliary plating layer 262.

[0125] (Third Modification) Fig. 21 is a cross-sectional view showing the redistribution layer 20 in a third modified example. Fig. 22 is a cross-sectional view showing an example of the configuration of the second pad 27B and the second wiring 29B of Fig. 21. The outer edge 27y of the auxiliary conductive layer 26 of the second pad 27B may constitute the outer edge 27y of the second pad 27B. For example, in the second pad 27B, the outer edge of the main seed layer 251 of the second main conductive layer 25B and the outer edge 26y of the auxiliary seed layer 261 of the auxiliary conductive layer 26 may coincide with each other.

[0126] 21, like the second pad 27B, the second wiring 29B may further include an auxiliary conductive layer 26 located between the upper surface 211 of the second insulating layer 21B and the second main conductive layer 25B. In the second wiring 29B, the side surface of the auxiliary conductive layer 26 may coincide with the side surface of the second main conductive layer 25B.

[0127] A method for manufacturing the rewiring layer 20 shown in FIGS. 21 and 22 will be described.

[0128] 5 to 9, a release layer 13, a first insulating layer 21A, a first main conductive layer 25A, and a second insulating layer 21B are formed on a carrier substrate 12. Then, as shown in Fig. 23, an auxiliary seed layer 261 is formed on an upper surface 211 of the second insulating layer 21B. The auxiliary seed layer 261 is formed by, for example, sputtering.

[0129] 23, a second resist layer 72 is formed partially on the auxiliary seed layer 261. The second resist layer 72 has an opening 721 penetrating the second resist layer 72 in the thickness direction. In a plan view, the opening 721 has a shape corresponding to the above-mentioned opening 212 in the second insulating layer 21B. The opening 721 is formed by processing the second resist layer 72 by, for example, a photolithography method. As shown in FIG. 23, the second resist layer 72 may cover the entire area of ​​the auxiliary seed layer 261 except for the opening 721.

[0130] Next, a step of processing the auxiliary seed layer 261 is performed using the second resist layer 72 as a mask. For example, the auxiliary seed layer 261 is processed by wet etching. As a result, as shown in FIG. 24, through holes 26c are formed in the auxiliary seed layer 261. The outline of the auxiliary seed layer 261 surrounding the through holes 26c forms the inner edge 26x. Next, the second resist layer 72 is removed. As shown in FIG. 24, the auxiliary seed layer 261 may cover the entire second insulating layer 21B except for the through holes 26c.

[0131] 25, a step of forming openings 212 in second insulating layer 21B is performed. For example, second insulating layer 21B exposed from through holes 26c in auxiliary seed layer 261 is irradiated with a laser.

[0132] 26, the main seed layer 251 is formed on the auxiliary seed layer 261. The main seed layer 251 is formed by, for example, sputtering. The main seed layer 251 may overlap the auxiliary seed layer 261 over the entire area.

[0133] 27, a third resist layer 73 is formed partially on the main seed layer 251. Then, a plating process is carried out. In the plating process, a main plating layer 252 is formed in the openings 731 of the third resist layer 73 by electrolytic plating.

[0134] Next, as shown in Fig. 28, the third resist layer 73 is removed. Next, as shown in Fig. 28, the main seed layer 251 and the auxiliary seed layer 261 that overlapped the third resist layer 73 are removed. For example, the main seed layer 251 and the auxiliary seed layer 261 are partially removed by wet etching. In this manner, the second main conductive layer 25B including the main seed layer 251 and the main plating layer 252 is formed. The auxiliary seed layer 261 is disposed between the second main conductive layer 25B and the upper surface 211 of the second insulating layer 21B.

[0135] In this modification, opening 212 in second insulating layer 21B is also formed by processing second insulating layer 21B using auxiliary conductive layer 26 as a mask. Therefore, opening 212 is stably formed above first pad 27A.

[0136] (Fourth Modification) 29 is a cross-sectional view showing the redistribution layer 20 in the fourth modification. The insulating layer 21, such as the second insulating layer 21B, may include an organic layer 22 and an inorganic layer 23. In the example shown in FIG. 29, the second insulating layer 21B includes the organic layer 22 and the inorganic layer 23.

[0137] The inorganic layer 23 of the second insulating layer 21B is located on the upper surface 211 of the first insulating layer 21A. The inorganic layer 23 may at least partially cover the first main conductive layer 25A. For example, the inorganic layer 23 may cover the first pad 27A except for the portion of the first pad 27A that overlaps the opening 212. For example, the inorganic layer 23 may cover the first wiring 29A.

[0138] The inorganic layer 23 includes an inorganic material. Examples of the inorganic material include a metal material, an inorganic oxide, and an inorganic nitride. The inorganic material may have insulating properties. For example, the inorganic material may be an insulating inorganic oxide or inorganic nitride. The inorganic oxide may be, for example, a silicon oxide such as SiO2. The inorganic nitride may be, for example, a silicon nitride such as SiN. The inorganic material may be, for example, SiOC, SiC, SiOF, SiON, SiCN, or the like.

[0139] The organic layer 22 may be located on the inorganic layer 23. For example, the organic layer 22 of the second insulating layer 21B may be located on the inorganic layer 23 and may form the upper surface 211 of the second insulating layer 21B. The organic layer 22 includes the above-mentioned organic material of the insulating layer 21. The organic layer 22 may include a plurality of fillers distributed in the organic material.

[0140] The insulating layer 21 including the inorganic layer 23 suppresses the stress caused by the organic layer 22 from affecting components other than the inorganic layer 23. This suppresses, for example, warping of the redistribution layer 20, the wiring board group 10, or the wiring board 11. For example, suppressing the occurrence of stress in the main conductive layer 25 suppresses the occurrence of defects in the main conductive layer 25, such as deformation or breakage.

[0141] A method for manufacturing the rewiring layer 20 shown in FIG. 29 will now be described.

[0142] 5 to 8, a release layer 13, a first insulating layer 21A, and a first main conductive layer 25A are formed on a carrier substrate 12. Then, as shown in FIG. 30, an inorganic layer 23 is formed on an upper surface 211 of the first insulating layer 21A. For example, the inorganic layer 23 is formed by plasma CVD. The inorganic layer 23 covers the plurality of first main conductive layers 25A.

[0143] 30, a step of forming organic layer 22 on inorganic layer 23 is carried out. The step of forming organic layer 22 may include a coating step and a drying step, similar to the step of forming the organic layer of first insulating layer 21A. The step of forming organic layer 22 may include a step of attaching a film onto inorganic layer 23 instead of a coating step, similar to the step of forming the organic layer of first insulating layer 21A.

[0144] 10 and 11, an auxiliary seed layer 261 is then formed on the upper surface 211 of the second insulating layer 21B, as shown in Fig. 31. The auxiliary seed layer 261 includes through-holes 26c.

[0145] 32, a step of forming openings 221 in organic layer 22 of second insulating layer 21B is performed. For example, a laser is irradiated toward organic layer 22 exposed from through holes 26c of auxiliary seed layer 261. By processing organic layer 22 with the laser, openings 221 that overlap with through holes 26c in a plan view are formed in organic layer 22.

[0146] 33, a step of forming openings 231 in inorganic layer 23 of second insulating layer 21B is performed. For example, a laser is irradiated toward inorganic layer 23 exposed from through holes 26c of auxiliary seed layer 261. By processing inorganic layer 23 with the laser, openings 231 overlapping with through holes 26c in a plan view are formed in inorganic layer 23. In this way, openings 212 including openings 221 in organic layer 22 and openings 231 in inorganic layer 23 overlapping with openings 221 in organic layer 22 are formed in second insulating layer 21B.

[0147] The step of forming the opening 231 in the inorganic layer 23 of the second insulating layer 21B may include a dry etching step. For example, the opening 231 may be formed in the inorganic layer 23 by dry etching a portion of the inorganic layer 23 exposed from the opening 221 in the organic layer 22.

[0148] Subsequently, the second main conductive layer 25B is formed in the same manner as in the above-described embodiment shown in Figures 13 to 15. In this manner, the redistribution layer 20 shown in Figure 29 is obtained.

[0149] In this modification, the opening 212 in the second insulating layer 21B is also formed by processing the organic layer 22 of the second insulating layer 21B using the auxiliary conductive layer 26 as a mask. Therefore, the opening 212 is stably formed above the first pad 27A.

[0150] (Fifth Modification) 34 is a cross-sectional view showing the redistribution layer 20 in the fifth modification. The pad 27 of the redistribution layer 20 may not include the auxiliary conductive layer 26. For example, the second pad 27B overlapping the opening 212 of the second insulating layer 21B in a plan view includes the second main conductive layer 25B but may not include the auxiliary conductive layer 26.

[0151] 34, the first main conductive layer 25A constituting the first pad 27A may include an inner portion 253 and an outer portion 254. The inner portion 253 is a portion of the first main conductive layer 25A connected to the second through-electrode 28B. The outer portion 254 is a portion of the first main conductive layer 25A located outside the inner portion 253 in a plan view.

[0152] The inner portion 253 may include a recess 255 recessed relative to the upper surface of the outer portion 254. The recess 255 may be in contact with the main seed layer 251 of the second through-hole electrode 28B. When the first pad 27A includes the recess 255, the adhesion of the main seed layer 251 of the second through-hole electrode 28B to the first pad 27A is improved by, for example, an anchor effect.

[0153] A method for manufacturing the rewiring layer 20 shown in FIG. 34 will now be described.

[0154] 5 to 11, a release layer 13, a first insulating layer 21A, a first main conductive layer 25A, a second insulating layer 21B, and an auxiliary conductive layer 26 are formed on a carrier substrate 12. Then, as in the case of the above-described embodiment shown in Fig. 12, an opening 212 is formed in the second insulating layer 21B by laser processing using the auxiliary conductive layer 26 as a mask.

[0155] Next, as shown in FIG. 35, a step of removing the auxiliary conductive layer 26 is performed. For example, the auxiliary conductive layer 26 is removed by wet etching. In the wet etching, an etching solution capable of dissolving the auxiliary conductive layer 26 is used. If the etching solution can also dissolve the main plating layer 252 of the first main conductive layer 25A, a recess 255 is formed in the upper surface of the first main conductive layer 25A, as shown in FIG.

[0156] 36, a main seed layer 251 is formed on the upper surface 211 of the second insulating layer 21B. The main seed layer 251 is also formed on the wall surface 213 of the opening 212 and on the upper surface of the first main conductive layer 25A exposed from the opening 212. The main seed layer 251 is formed by, for example, sputtering. Since the first main conductive layer 25A includes the recess 255, the adhesion of the main seed layer 251 to the first main conductive layer 25A is improved by, for example, an anchor effect.

[0157] 14 and 15, the main plating layer 252 of the second main conductive layer 25B is then formed. In this manner, the rewiring layer 20 shown in FIG.

[0158] In this modification, opening 212 in second insulating layer 21B is also formed by processing second insulating layer 21B using auxiliary conductive layer 26 as a mask. Therefore, opening 212 is stably formed above first pad 27A.

[0159] 37 is a diagram showing an example of a product in which the redistribution layer 20 is mounted. The redistribution layer 20 can be used in a variety of products. For example, the redistribution layer 20 is mounted in a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smartphone 140, a digital video camera 150, a digital camera 160, a digital clock 170, a server 180, and the like.

[0160] Although several modifications to the above-described embodiment have been described, it is of course possible to combine a plurality of modifications as appropriate and apply them to the above-described embodiment. [Explanation of symbols]

[0161] 10. Wiring board group 11 Wiring board 12 Carrier board 20 Redistribution layer 21 Insulating layer 21A First insulating layer 21B Second insulating layer 211 Top surface 212 Aperture 213 Wall 214 Open End 22 Organic layer 221 Aperture 23 Inorganic layer 231 Aperture 25 Main conductive layer 25A 1st main conductive layer 25B Second main conductive layer 251 Main seed layer 2511 1st layer 2512 2nd layer 252 Main plating layer 253 Inner part 254 Outer part 255 recess 26 Auxiliary conductive layer 261 Auxiliary Seed Layer 2611 1st layer 2612 2nd layer 262 Auxiliary plating layer 26x inner edge 26y outer edge 27 Pads 27A 1st pad 27B 2nd pad 27y outer edge 28 Through electrode 28A 1st through electrode 28B 2nd through electrode 29 Wiring 29A 1st wiring 29B Second wiring

Claims

1. A redistribution layer, a first insulating layer; a first main conductive layer including a portion located on a surface of the first insulating layer; a second insulating layer located on the surface of the first insulating layer and including an opening overlapping the first main conductive layer in a plan view; a second main conductive layer including a portion located on the surface of the second insulating layer and a portion located on a wall surface of the opening, a portion of the second main conductive layer located on the surface of the second insulating layer constitutes a second pad; a portion of the second main conductive layer located on the wall surface of the opening of the second insulating layer constitutes a second through electrode connected to the first main conductive layer and the second pad; the second pad further includes an auxiliary conductive layer located between the surface of the second insulating layer and the second main conductive layer; The auxiliary conductive layer includes an inner edge positioned at an opening edge of the opening in the second insulating layer.

2. The redistribution layer according to claim 1 , wherein the auxiliary conductive layer includes an outer edge that is covered by the second main conductive layer.

3. the second pad includes an outer edge; The redistribution layer according to claim 1 , wherein the auxiliary conductive layer includes an outer edge that forms the outer edge of the second pad.

4. another part of the second main conductive layer located on the surface of the second insulating layer constitutes a second wiring extending along the surface of the second insulating layer; The redistribution layer according to claim 1, wherein the second wiring further includes the auxiliary conductive layer.

5. 4. The redistribution layer according to claim 1, wherein the auxiliary conductive layer comprises at least a layer containing titanium or copper.

6. The redistribution layer according to claim 5 , wherein the auxiliary conductive layer comprises: an auxiliary seed layer containing titanium or copper; and an auxiliary plating layer located on the auxiliary seed layer and containing copper.

7. A redistribution layer, a first insulating layer; a first main conductive layer including a portion located on a surface of the first insulating layer; a second insulating layer located on the surface of the first insulating layer and including an opening overlapping the first main conductive layer in a plan view; a second main conductive layer including a portion located on the surface of the second insulating layer and a portion located on a wall surface of the opening, a portion of the second main conductive layer located on the surface of the second insulating layer constitutes a second pad; a portion of the second main conductive layer located on the wall surface of the opening of the second insulating layer constitutes a second through electrode connected to the first main conductive layer and the second pad; the first main conductive layer includes an inner portion connected to the second through electrode and an outer portion located outside the inner portion in a plan view, The redistribution layer, wherein the inner portion includes a recess that is recessed relative to the surface of the outer portion.

8. The redistribution layer according to any one of claims 1 to 3 and 7, wherein the second main conductive layer comprises a main seed layer containing titanium or copper, and a main plating layer located on the main seed layer and containing copper.

9. The redistribution layer according to any one of claims 1 to 3 and 7, wherein the second insulating layer includes an inorganic layer located on the surface of the first insulating layer and at least partially covering the first main conductive layer, and an organic layer located on the inorganic layer.

10. 8. The redistribution layer according to claim 1, wherein the opening in the second insulating layer has a dimension of 10 μm or less.

11. A method for manufacturing a redistribution layer, comprising: forming a first insulating layer; forming a first main conductive layer including a portion located on a surface of the first insulating layer; forming a second insulating layer on the surface of the first insulating layer; forming an auxiliary conductive layer including through holes on a surface of the second insulating layer; forming an opening in the second insulating layer that overlaps the through hole of the auxiliary conductive layer in a plan view; forming a second main conductive layer including a portion located on the surface of the second insulating layer and a portion located on a wall surface of the opening.

12. The method of claim 11 , wherein the second main conductive layer is at least partially formed on the auxiliary conductive layer located on the surface of the second insulating layer.

13. the auxiliary conductive layer includes an outer edge; The method of claim 12 , wherein the second main conductive layer is formed to cover the outer edge of the auxiliary conductive layer.

14. 13. The method for manufacturing a redistribution layer according to claim 12, wherein the step of forming the second main conductive layer includes the steps of: forming a main seed layer; partially forming a resist layer on the main seed layer; partially forming a main plating layer on the main seed layer; removing the resist layer; and removing a portion of the main seed layer that overlaps the resist layer in a planar view.

15. The method for manufacturing a redistribution layer according to claim 14 , wherein the step of forming the second main conductive layer includes the step of removing a portion of the auxiliary conductive layer that overlaps the resist layer in a plan view.

16. The method for manufacturing a redistribution layer according to claim 11 , further comprising the step of removing the auxiliary conductive layer after forming the opening in the second insulating layer.

17. The method for manufacturing a redistribution layer according to claim 11, wherein the step of forming the opening in the second insulating layer includes the step of irradiating the through hole in the auxiliary conductive layer with a laser.

18. the second insulating layer includes an inorganic layer located on the surface of the first insulating layer and at least partially covering the first main conductive layer, and an organic layer located on the inorganic layer; The method for manufacturing a redistribution layer according to any one of claims 11 to 16, wherein the step of forming the opening in the second insulating layer includes a step of irradiating the organic layer exposed from the through hole of the auxiliary conductive layer with a laser to form an opening in the organic layer, and a step of forming an opening in the inorganic layer.

19. The method for manufacturing a redistribution layer according to claim 18 , wherein the step of forming the opening in the inorganic layer includes the step of irradiating the inorganic layer with the laser.

20. The method for manufacturing a redistribution layer according to claim 18 , wherein the step of forming the openings in the inorganic layer includes the step of forming the openings in the inorganic layer by dry etching.

21. The method for manufacturing a redistribution layer according to any one of claims 11 to 16, wherein the opening in the second insulating layer has a dimension of 10 μm or less.

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