Binary neural network circuit using quasi-nonvolatile memory device

Abstract

To provide a binary neural network by a memory array formed of a quasi-nonvolatile memory device which carries out a memory and a switching function as a single device.SOLUTION: A binary neural network circuit 300 according to the present invention has a gate terminal located on a diode structure of a channel region between a drain and a source, determines an operation state by a latch-up / -down phenomenon by a positive feedback loop in the channel region based on different voltages on the drain and the gate, has a plurality of quasi-non-volatile memory devices for storing a memory state by accumulation of positive holes or electrons in a potential well in the channel region, makes a pair of two quasi-non-volatile memory devices operate as a synapse cell 301 and form an array circuit connected to each other in parallel, determines a memory state of the synapse cell based on an input signal from an input line processing unit 302 and a weight value update signal from a synapse line processing unit 303, and outputs a MAC calculation result by using combination of the memory states.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of priority based on Korean Patent Application No. 10-2024-0039833, filed on March 22, 2024, the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to a binary neural network circuit using quasi-nonvolatile memory (QNVM) elements, and more particularly to a technology for implementing a binary neural network capable of performing both memory and logic operation functions in a memory array composed of quasi-nonvolatile memory elements that perform memory and switching functions in a single element based on a positive feedback loop. [Background technology]

[0003] In the existing von Neumann-based computer system, the processor and memory are separated, and data signals are transmitted via a bus line.

[0004] However, as computing performance increases, bottlenecks occur due to the difference in data processing speed between the processor and memory, and large-volume data processing begins to show its limitations.

[0005] In other words, von Neumann-based systems, a revolutionary development in the semiconductor industry, have increased the integration density and performance of modern computers, but have the drawback of high energy consumption and long data transmission and latency due to the physical separation between the processor and memory hierarchy.

[0006] Since the Fourth Industrial Revolution, a new computing paradigm is essential to meet the requirements of large-scale data processing, considering the increase in data-intensive applications such as 5G communication standards, Internet of Things (IoT), and Artificial Intelligence (AI).

[0007] To solve the above problems, research into logic-in-memory (LIM) technology, which combines computing and memory functions, is being intensively and accelerated.

[0008] Logic-in-memory technology performs the processor's calculation functions and memory's storage functions in the same space, reducing delays and power consumption that occur during data transmission and significantly improving system integration.

[0009] Conventional logic-in-memory technology has been actively researched based on volatile memory elements such as SRAM (static random access memory) and DRAM (dynamic RAM), as well as non-volatile memory elements such as ReRAM (resistive RAM), MRAM (magnetoresistive RAM), and PCRAM (phase-change RAM).

[0010] To overcome the limitations of large-volume data processing, research is being conducted on POP (Package On Package) and TSV (Through Silicon Via) technologies that integrate logic memory into a single chip. However, as logic and memory functions are not yet performed simultaneously by transistors, bottlenecks, power consumption, computing efficiency, and integration density problems still exist.

[0011] In addition, logic-in-memory technology based on non-volatile memory elements requires complex processing steps because it uses non-silicon materials, and is difficult to put into practical use due to low element uniformity and stability.

[0012] In addition, each logic-in-memory technology that has been researched so far has a low degree of integration because it cannot implement all basic CMOS (complementary metal-oxide semiconductor) logic operations in a single cell and requires individual circuits and wiring for each logic operation.

[0013] Therefore, there is a need to develop binary neural network technology that utilizes quasi-nonvolatile memory elements that can be applied to CMOS processes and perform both switching and memory functions, and self-activating neural network technology that enables the neural network itself to perform the activation function of neuron circuits. [Prior art documents] [Patent documents]

[0014] [Patent Document 1] Korean Patent Application Publication No. 10-2023-0053195 [Patent Document 2] Korean Patent Application Publication No. 10-2022-0110774 [Patent Document 3] Korean Patent Application Publication No. 10-2023-0020840 [Patent Document 4] Korean Patent Application Publication No. 10-2022-0107808 Summary of the Invention [Problem to be solved by the invention]

[0015] The present invention aims to realize a binary neural network that can perform both memory and logic operation functions in a memory array composed of quasi-nonvolatile memory elements that perform memory and switching functions in a single element based on a positive feedback loop.

[0016] The present invention aims to realize a logic operation binary neural network with little characteristic deviation and excellent uniformity and stability by using a quasi-nonvolatile memory device that can be applied to a CMOS process as a synaptic device.

[0017] The present invention aims to realize a binary neural network circuit with excellent uniformity and stability, in which a memory array composed of positive feedback loop-based quasi-nonvolatile memory elements performs the activation function of a neuron circuit by itself.

[0018] The present invention aims to realize a binary neural network circuit that can be used in next-generation artificial intelligence computing technology by reducing standby power using the excellent memory characteristics of a quasi-nonvolatile memory device and increasing computing efficiency with low power consumption through excellent switching characteristics. [Means for solving the problem]

[0019] In a binarized neural network circuit according to an embodiment of the present invention, a diode structure is located in a channel region between a drain terminal and a source terminal, and a gate terminal is located on the diode structure. An operating state is determined by a latch-up or latch-down phenomenon occurring in the channel region due to a positive feedback loop based on different voltages applied to the drain terminal and the gate terminal, and holes or electrons are accumulated in a potential well in the channel region due to the positive feedback loop. The plurality of quasi-nonvolatile memory devices include a pair of quasi-nonvolatile memory devices that operate as one synapse cell and are connected in parallel to form an array circuit. The array circuit determines and stores memory states of the two quasi-nonvolatile memory devices based on an input signal applied from an input line processor connected to the array circuit and a weight update signal applied from a synapse line processor connected to the array circuit, and outputs a multiply-accumulate (MAC) operation result using a combination of the memory states.

[0020] The synapse cell stores a synapse weight value through a combination of the operating states of the two quasi-nonvolatile memory elements, and when the input signal is applied, performs an XNOR logic operation on the input signal and the synapse weight value, and outputs the XNOR logic operation result.

[0021] The synapse cell is configured such that each of the two quasi-nonvolatile memory devices is determined to be in one of a first operating state and a second operating state based on the input signal, and the input signal is at a voltage V equal to or greater than a reference voltage. High is determined as the first operating state, and the input signal is below a reference voltage V Low The second operating state can be determined as:

[0022] When the input signal is negative, a voltage below the reference voltage is applied to the upper quasi-nonvolatile memory element of the two quasi-nonvolatile memory elements, and a voltage above the reference voltage is applied to the lower quasi-nonvolatile memory element; when the input signal is positive, a voltage above the reference voltage is applied to the upper quasi-nonvolatile memory element of the two quasi-nonvolatile memory elements, and a voltage below the reference voltage is applied to the lower quasi-nonvolatile memory element.

[0023] The synapse cell is configured such that each of the two quasi-nonvolatile memory devices is determined to be in one of a first operating state and a second operating state based on the input signal, and the input signal is at a voltage V equal to or greater than a reference voltage. High is determined as the first operating state, and the input signal is below a reference voltage V Low The second operating state is determined as being equal to or less than the first operating state, and the synapse weight value can be determined as either a negative value or a positive value based on a combination of the first operating state and the second operating state.

[0024] The synapse cell may determine the synapse weight as the positive value when a first quasi-nonvolatile memory element of the two quasi-nonvolatile memory elements is in the second operating state and the second quasi-nonvolatile memory element is in the first operating state, determine the synapse weight as the negative value when the first quasi-nonvolatile memory element is in the first operating state and the second quasi-nonvolatile memory element is in the second operating state, determine the synapse weight as the negative value when the first quasi-nonvolatile memory element is in the second operating state and the second quasi-nonvolatile memory element is in the first operating state, and determine the synapse weight as the positive value when the first quasi-nonvolatile memory element is in the first operating state and the second quasi-nonvolatile memory element is in the second operating state.

[0025] The synapse cells may be configured in plurality based on the plurality of quasi-nonvolatile memory elements, the plurality of synapse cells may be connected in parallel, and a synapse weight matrix may be provided that is configured of the synapse weights stored in each of the plurality of synapse cells. A vector matrix multiplication operation may be performed between the provided synapse weight matrix and a matrix of input vectors based on input signals for determining the synapse weights, and an XNOR binary operation result may be output.

[0026] When the synapse cells are configured in two rows and two columns, if the current sensed in relation to the output XNOR binary operation result is adjacent to the reference current, the logic state is output as “0”, if the current is twice the reference current, the logic state is output as “+2”, and if the reference current is adjacent to “0”, the logic state is output as “−2”.

[0027] The quasi-nonvolatile memory device receives a drain voltage of the drain terminal as the input signal, generates a latch-up phenomenon due to the positive feedback loop that occurs when the applied input signal increases in a positive direction, has one of two memory states for the channel region, receives a gate voltage of the gate terminal as the weight update signal, adjusts the input signal that generates the latch-up phenomenon, updates a synapse state associated with one of the memory states by applying the input signal and the weight update signal, and can perform the MAC operation function according to the synapse weight.

[0028] The memory array may connect the drain terminals, the gate terminals, and the source terminals of the plurality of quasi-nonvolatile memory devices in parallel to form input lines, weighted value lines, and output lines, respectively, and the input lines may be arranged perpendicular to the weighted value lines and the output lines, and the weighted value lines and the output lines may be arranged in parallel.

[0029] The input line receives the input signal from the input line processing unit, the weight line receives the weight update signal from the weight line processing unit, and the output line is connected to a current sensing processing unit, and the MAC calculation result based on the input signal and the weight update signal can be output to the next artificial neural network stage via the current sensing processing unit.

[0030] The quasi-nonvolatile memory device may include any one of a single-gate quasi-nonvolatile memory device, a double-gate quasi-nonvolatile memory device, and a triple-gate quasi-nonvolatile memory device. [Effects of the Invention]

[0031] The present invention can realize a binary neural network that can perform both memory and logic operation functions in a memory array composed of quasi-nonvolatile memory elements that perform memory and switching functions in a single element based on a positive feedback loop.

[0032] The present invention uses a quasi-nonvolatile memory device, to which a CMOS process can be applied, as a synapse element, which has almost no characteristic deviation, and thus can realize a logic operation binary neural network with excellent uniformity and stability.

[0033] The present invention enables the realization of a binary neural network circuit with excellent uniformity and stability by using a memory array composed of positive feedback loop-based quasi-nonvolatile memory elements that independently perform the activation function of a neuron circuit.

[0034] The present invention reduces standby power by using the excellent memory characteristics of a quasi-nonvolatile memory device, and increases computing efficiency with low power consumption through its excellent switching characteristics, thereby realizing a binary neural network circuit that can be used in next-generation artificial intelligence computing technology. [Brief explanation of the drawings]

[0035] [Figure 1a] 1A and 1B are diagrams illustrating the structure and circuit symbols of a quasi-nonvolatile memory element that constitutes a binary neural network circuit according to an embodiment of the present invention. [Figure 1b] 1A and 1B are diagrams illustrating the structure and circuit symbols of a quasi-nonvolatile memory element that constitutes a binary neural network circuit according to an embodiment of the present invention. [Figure 1c] 1A and 1B are diagrams illustrating the structure and circuit symbols of quasi-nonvolatile memory elements that constitute a binary neural network circuit according to an embodiment of the present invention. [Figure 1d] 1A and 1B are diagrams illustrating the structure and circuit symbols of a quasi-nonvolatile memory element that constitutes a binary neural network circuit according to an embodiment of the present invention. [Figure 2a] 10A and 10B are diagrams illustrating the operating characteristics of a quasi-nonvolatile memory element constituting a binary neural network circuit according to an embodiment of the present invention. [Figure 2b] 10A and 10B are diagrams illustrating the operating characteristics of a quasi-nonvolatile memory element constituting a binary neural network circuit according to an embodiment of the present invention. [Figure 2c] 10A and 10B are diagrams illustrating the operating characteristics of a quasi-nonvolatile memory element constituting a binary neural network circuit according to an embodiment of the present invention. [Figure 2d] 10A and 10B are diagrams illustrating the operating characteristics of a quasi-nonvolatile memory element constituting a binary neural network circuit according to an embodiment of the present invention. [Figure 3] FIG. 1 is a diagram illustrating a binarized neural network circuit using a quasi-nonvolatile memory element according to an embodiment of the present invention. [Figure 4a] 10A and 10B are diagrams illustrating logical operation of a binary neural network using a quasi-nonvolatile memory device according to an embodiment of the present invention. [Figure 4b] 10A and 10B are diagrams illustrating logical operation of a binary neural network using a quasi-nonvolatile memory device according to an embodiment of the present invention. [Figure 5a]FIG. 1 is a diagram illustrating a matrix MAC (multiply-accumulate) operation of a binarized neural network using a quasi-nonvolatile memory device according to an embodiment of the present invention. [Figure 5b] FIG. 1 is a diagram illustrating a matrix MAC (multiply-accumulate) operation of a binarized neural network using a quasi-nonvolatile memory device according to an embodiment of the present invention. [Figure 5c] FIG. 1 is a diagram illustrating a matrix MAC (multiply-accumulate) operation of a binarized neural network using a quasi-nonvolatile memory device according to an embodiment of the present invention. [Figure 6] 4A and 4B are diagrams illustrating a memory operation of a quasi-nonvolatile memory device according to an embodiment of the present invention; [Figure 7] FIG. 1 is a diagram illustrating a simulation structure of a binarized neural network circuit using a quasi-nonvolatile memory element according to an embodiment of the present invention. [Figure 8a] 10A and 10B are diagrams illustrating simulation results of a binarized neural network circuit using a quasi-nonvolatile memory element according to an embodiment of the present invention. [Figure 8b] 10A and 10B are diagrams illustrating simulation results of a binarized neural network circuit using a quasi-nonvolatile memory element according to an embodiment of the present invention. [Figure 8c] 10A and 10B are diagrams illustrating simulation results of a binarized neural network circuit using a quasi-nonvolatile memory element according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0036] Various embodiments of the present document will now be described with reference to the accompanying drawings.

[0037] The examples and the terms used therein are not intended to limit the technology described herein to a particular embodiment, but should be understood to include various modifications, equivalents, and / or alternatives to the examples.

[0038] In the following description of various embodiments, if it is determined that a detailed description of related well-known functions or configurations may obscure the gist of the invention, the detailed description thereof will be omitted.

[0039] Furthermore, the terms described below are defined taking into consideration the functions in various embodiments, and as these may vary depending on the intentions or practices of users and operators, they should be defined based on the overall content of this specification.

[0040] In connection with the description of the drawings, like reference numerals may be used for like components.

[0041] A singular expression can include a plural expression unless the context clearly indicates otherwise.

[0042] In this document, phrases such as "A or B" or "at least one of A and / or B" may include all possible combinations of the items listed together.

[0043] The terms "first," "second," "first," or "second" may modify the respective components regardless of order or importance, and are merely used to distinguish one component from other components, and do not limit the respective components.

[0044] When one (e.g., first) component is referred to as being "coupled (functionally or communicatively)" or "connected" to another (e.g., second) component, the one component may be directly coupled to the other component or may be coupled through another component (e.g., third component).

[0045] As used herein, "configured to" may be used interchangeably with, for example, hardware or software "suitable for," "capable of," "modified to," "made to," "capable of," or "designed to," depending on the context.

[0046] In one context, the phrase "a device configured to" can mean that the device is "capable of" in conjunction with other devices or components.

[0047] For example, the phrase "a processor configured (or set) to perform A, B, and C" may refer to a processor that is dedicated to performing those operations (e.g., an embedded processor), or to a general-purpose processor (e.g., a CPU or application processor) that can perform those operations by executing one or more software programs stored in a memory device.

[0048] Also, the term "or" means an inclusive or rather than an exclusive or.

[0049] That is, unless otherwise stated or clear from the context, the phrase "x employs a or b" means any one of the natural inclusive permutations.

[0050] As used below, the terms "module" and "machine" refer to a unit that processes at least one function or operation, and may be realized as hardware, software, or a combination of hardware and software.

[0051] 1a to 1d are diagrams illustrating the structure and circuit symbols of a quasi-nonvolatile memory element constituting a binarized neural network circuit according to an embodiment of the present invention.

[0052] 1a and 1b illustrate the structure and circuit symbol of a quasi-nonvolatile memory device using a single gate that constitutes a binarized neural network circuit according to one embodiment of the present invention.

[0053] Referring to FIG. 1a, a quasi-nonvolatile memory device 100 constituting a binary neural network circuit according to one embodiment of the present invention has a channel region between a drain terminal 101 and a source terminal 104, which includes a first channel region 102 and a second channel region 103.

[0054] A gate insulating film 105 is located on the second channel region 103 , and a gate terminal 106 is located on the gate insulating film 105 .

[0055] In a circuit symbol 110 of a quasi-nonvolatile memory device constituting a binary neural network circuit according to one embodiment of the present invention, a channel region is located between a drain terminal 111 and a source terminal 112, and a gate terminal 113 is connected thereto.

[0056] Referring to FIG. 1b, a quasi-nonvolatile memory device 120 constituting a binary neural network circuit according to one embodiment of the present invention has a channel region between a drain terminal 121 and a source terminal 124, which includes a first channel region 122 and a second channel region 123.

[0057] A gate insulating film 125 is located on the first channel region 122 , and a gate terminal 126 is located on the gate insulating film 125 .

[0058] In the circuit symbol 130 of a quasi-nonvolatile memory device constituting a binary neural network circuit according to one embodiment of the present invention, a channel region is located between a drain terminal 131 and a source terminal 132, and a gate terminal 133 is connected thereto.

[0059] According to one embodiment of the present invention, an input line is connected to the drain terminal 111 or the drain terminal 131, an output line is connected to the source terminal 112 or the source terminal 132, and the memory state of the channel region is determined by updating the synaptic weight value.

[0060] FIG. 1c illustrates the structure and circuit symbol of a quasi-nonvolatile memory device using double gates that constitutes a binarized neural network circuit according to one embodiment of the present invention.

[0061] Referring to FIG. 1c, a quasi-nonvolatile memory element 140 constituting a binary neural network circuit according to one embodiment of the present invention has an intrinsic region 142 located between a drain terminal 141 and a source terminal 143, a gate insulating film 144 located on the intrinsic region 142, and a first gate terminal 145 and a second gate terminal 146 located on the gate insulating film 144.

[0062] The intrinsic region 142 operates as a channel region based on a gate voltage input from either a first gate terminal 145 or a second gate terminal 146 .

[0063] In a circuit symbol 150 of a quasi-nonvolatile memory device constituting a binary neural network circuit according to one embodiment of the present invention, an intrinsic region is located between a drain terminal 151 and a source terminal 152, and a first gate terminal 153 and a second gate terminal 154 are connected to each other.

[0064] FIG. 1d illustrates the structure and circuit symbol of a quasi-nonvolatile memory device using triple gates that constitutes a binarized neural network circuit according to one embodiment of the present invention.

[0065] Referring to FIG. 1d, a quasi-nonvolatile memory element 160 constituting a binary neural network circuit according to one embodiment of the present invention has an intrinsic region 162 located between a drain terminal 161 and a source terminal 163, a gate insulating film 164 located on the intrinsic region 162, and a programming gate terminal 165 and a control gate terminal 166 located on the gate insulating film 164.

[0066] The intrinsic region 162 acts as a channel region based on the gate voltage input from the programming gate terminal 165 .

[0067] More specifically, the programming voltage V PG When the level is high, it operates as n-channel, which corresponds to the first channel operation, and the program voltage V PG When the level of is low, it can operate as a p-channel, which corresponds to the second channel operation.

[0068] When the quasi-nonvolatile memory device 160 performs a first channel operation, the control voltage V CG is determined to be in an on state when the level of the control voltage V applied via the control gate terminal 166 is high. CG When the level of the signal is low, the signal is determined to be in the OFF state.

[0069] In a circuit symbol 170 of a quasi-nonvolatile memory device constituting a binary neural network circuit according to one embodiment of the present invention, an intrinsic region is located between a drain terminal 171 and a source terminal 172, to which a programming gate terminal 173 and a control gate terminal 174 are connected.

[0070] For example, the drain terminal, the gate terminal, and the source terminal may be referred to as a drain electrode, a source electrode, and a gate electrode, respectively, by replacing the term "terminal" with "electrode."

[0071] That is, a quasi-nonvolatile memory device constituting a binary neural network circuit according to one embodiment of the present invention may have a structure in which a single gate electrode terminal is deposited on an n- or p-type doped channel region on a silicon channel, or multiple gate electrode terminals are deposited on an intrinsically doped region.

[0072] Furthermore, the quasi-nonvolatile memory element operates by inducing a positive feedback loop with a potential barrier, and has switching and memory properties, so it can be configured as a synaptic element in a binary neural network.

[0073] Therefore, the present invention can realize a self-activating binarized neural network circuit that performs its activation function by using a quasi-nonvolatile memory element that performs memory and switching functions in a single element based on a positive feedback loop.

[0074] For example, the quasi-nonvolatile memory device may include any one of a single-gate quasi-nonvolatile memory device, a double-gate quasi-nonvolatile memory device, and a triple-gate quasi-nonvolatile memory device.

[0075] 2a to 2d are diagrams illustrating the operating characteristics of a quasi-nonvolatile memory element constituting a binary neural network circuit according to an embodiment of the present invention.

[0076] FIG. 2a illustrates an optical image of a quasi-nonvolatile memory device according to one embodiment of the present invention.

[0077] Referring to FIG. 2a, image 200 shows an enlarged view of a portion of a quasi-nonvolatile memory device, and image 200 may be an optical image of the quasi-nonvolatile memory device for performing a matrix-MAC operation between binarized weight values ​​of a binarized neural network circuit and an analog input.

[0078] Image 200 shows a silicon-on-insulator (SOI) wafer heavily doped with p (p + ) drain, highly doped (n + ) source, and n- and p-doped regions.

[0079] SiO2 gate oxide and p+ A poly-Si gate (1.0-μm wide) layer is located on top of the n-doped region.

[0080] The poly-Si gate is + The drain region can control hole injection and adjust the potential barrier of the n-doped region.

[0081] The accumulation of holes injected into the p-doped region reduces the potential barrier height of the p-doped region, so that + Inducing electron injection in the source region.

[0082] This iterative interplay between carrier injection and modulation of the potential barrier height (i.e., the PF loop mechanism) is essential for using paired quasi-nonvolatile memory elements as synaptic cells in binarized neural network circuits.

[0083] FIG. 2b illustrates an operating state of a quasi-nonvolatile memory device according to one embodiment of the present invention.

[0084] FIG. 2b illustrates a first operating state 210 and a second operating state 211 of a quasi-nonvolatile memory device according to an embodiment of the present invention.

[0085] The first operational state 210 indicates a programmed state, and the second operational state 211 indicates an erased state.

[0086] The first operating state 210 is + Source and p + Excess charge carriers injected in the drain region accumulate in the potential wells of the n- and p-doped regions, lowering the potential barrier height.

[0087] Conversely, the second operating state 211 results in a higher potential barrier and depletion of excess charge carriers from the potential well.

[0088] Thus, the first and second operating states are determined by the presence or absence of excess charge carriers in the potential well.

[0089] 2c and 2d illustrate the operation states of a quasi-nonvolatile memory device according to an embodiment of the present invention.

[0090] Referring to Figures 2c and 2d, graphs 220 and 230 illustrate the switching characteristics of a quasi-nonvolatile memory device.

[0091] According to graph 220, the drain voltage V DS When V is swept from 0.0V to 2.0V (forward sweep), a positive feedback loop is created, causing the gate voltage V GS From V respectively DS = 1.3V and 0.8V DS increases suddenly.

[0092] Then, according to graph 230, for a reverse sweep of the drain voltage from 2.0 V to 0.0 V, I DS can be gradually reduced by reducing carrier injection in the drain and source regions.

[0093] Similarly, a quasi-nonvolatile memory element operates at a gate voltage V GS and I DS It exhibits abrupt switching characteristics.

[0094] In addition, the excess charge carriers stored in the potential wells allow the quasi-nonvolatile memory element to achieve a charge transfer rate of 3.5 × 10 7 High on / off current ratio (I ON / I OFF ), and such excellent electrical properties can be used to operate binarized neural network circuits.

[0095] A quasi-nonvolatile memory device has two states, where latch-up occurs due to a positive feedback loop as the drain voltage increases in the positive direction.

[0096] In a quasi-nonvolatile memory device, the drain voltage generated without latching may change depending on the gate voltage.

[0097] The binarized neural network according to an embodiment of the present invention can apply drain and gate voltages based on the characteristics of such single elements to perform synapse weight update and MAC calculation functions.

[0098] FIG. 3 is a diagram illustrating a binarized neural network circuit using a quasi-nonvolatile memory element according to an embodiment of the present invention.

[0099] FIG. 3 illustrates a binarized neural network circuit using a quasi-nonvolatile memory device according to one embodiment of the present invention.

[0100] Referring to FIG. 3, a binary neural network circuit 300 using a quasi-nonvolatile memory device according to an embodiment of the present invention may include a plurality of quasi-nonvolatile memory devices, each having a diode structure located in a channel region between a drain terminal and a source terminal, a gate terminal located on the diode structure, and implementing unidirectional switching by adjusting a potential barrier in the channel region based on different voltages applied to the drain terminal and the gate terminal, respectively, and implementing memory characteristics by accumulating holes or electrons in a potential well through a positive feedback loop.

[0101] For example, the binarized neural network circuit 300 using quasi-nonvolatile memory elements can be an artificial neural network that binarizes synaptic weight values ​​and reduces calculation time and power consumption.

[0102] Therefore, the present invention can realize a self-activating binary neural network circuit that has excellent memory characteristics of a quasi-nonvolatile memory device, which has unidirectional switching characteristics through adjustment of the potential barrier and memory characteristics due to the accumulation of holes or electrons in the potential well by a positive feedback loop, and has a self-activating function through the linearity of the output signal according to the input signal, thereby increasing the area and calculation efficiency of the artificial neural network.

[0103] A plurality of quasi-nonvolatile memory elements are connected in parallel to operate as synapse elements 301 in a memory array, and can output a MAC (multiply-accumulate) calculation result based on an input signal applied from an input line processing unit 302 connected to the memory array and a weight value update signal applied from a synapse line processing unit 303 connected to the memory array.

[0104] For example, the input line processing unit 302 may be a bit line switch matrix input processing unit, and the synapse line processing unit 303 may be a word line decoder.

[0105] As the binarized neural network circuit 300, the memory array has a plurality of quasi-nonvolatile memory elements whose drain terminals, gate terminals, and source terminals are connected in parallel to form input lines BL, weight lines WL, and output lines SL, respectively. The input lines BL may be arranged perpendicular to the weight lines WL and output lines SL, and the weight lines WL and output lines SL may be arranged in parallel.

[0106] The drain terminal is connected to an input line IL, the gate terminal is connected to a weight line WL, and the source terminal is connected to an output line SL.

[0107] The output line SL is connected to the current sensing processor (CSA) and can output the MAC calculation result based on the input signal IL and the weight value update signal WL to the next artificial neural network stage via the current sensing processor.

[0108] For example, the current sense processing unit may be referred to as a current sense amplifier (CSA).

[0109] The gate terminal and the source terminal may form a weight line WL and an output line SL, respectively.

[0110] For example, in the memory array, the first weight line WL0 to the Mth weight line WL1 are arranged according to the number M of rows of the semi-non-volatile memory devices. m are configured, and the first output line SL0 to the Mth output line SL m can be configured.

[0111] The number of input lines BL corresponding to columns and the number of output lines SL corresponding to rows may be the same or different.

[0112] However, the number of weight lines WL and the number of output lines BL must be the same (M).

[0113] For example, since the number of elements constituting the rows and columns can be configured to be equal to the number of inputs and outputs, N and M can be the same or different from each other.

[0114] For example, in a memory array, the first input line BL0 to the Nth input line BL1 are connected to the Nth input line BL2, where N is the number of columns of the semi-non-volatile memory devices. n can be configured.

[0115] The quasi-nonvolatile memory element receives the drain voltage of the drain terminal as an input signal, and when the applied input signal increases in the positive direction, a latch-up phenomenon occurs due to a positive feedback loop.

[0116] The quasi-nonvolatile memory device has one of two memory states for the channel region, and receives a gate voltage of the gate terminal as a weight update signal, thereby adjusting an input signal at which a latch-up phenomenon occurs.

[0117] In addition, the synapse cell 301, which is composed of two quasi-nonvolatile memory elements, updates the synapse state associated with one of the memory states by applying an input signal and a weight value update signal, and can perform a MAC calculation function based on the synapse weight value.

[0118] According to one embodiment of the present invention, the binarized neural network circuit 300 may include a plurality of quasi-nonvolatile memory devices that have a diode structure located in a channel region between a drain terminal and a source terminal, a gate terminal located on the diode structure, an operating state determined by a latch-up or latch-down phenomenon occurring in the channel region due to a positive feedback loop based on different voltages applied to the drain terminal and the gate terminal, and a memory state stored by accumulating holes or electrons in a potential well in the channel region due to the positive feedback loop.

[0119] For example, a pair of two quasi-nonvolatile memory elements operates as one synapse cell 301, and are connected in parallel to form an array circuit. The array circuit determines and stores the memory states of the two quasi-nonvolatile memory elements based on an input signal applied from an input line processing unit connected to the array circuit and a weight value update signal applied from a synapse line processing unit connected to the array circuit, and outputs a MAC (multiply-accumulate) calculation result using a combination of the memory states.

[0120] According to one embodiment of the present invention, the synapse cell 301 stores a synapse weight value through a combination of the operating states of two quasi-nonvolatile memory elements, and when an input signal is applied, performs an XNOR logic operation on the input signal and the synapse weight value, and outputs the XNOR logic operation result.

[0121] For example, when the input signal to synapse cell 301 is negative, a voltage below the reference level is applied to the uppermost quasi-nonvolatile memory element of the two quasi-nonvolatile memory elements, and a voltage above the reference level is applied to the lowermost quasi-nonvolatile memory element; on the other hand, when the input signal is positive, a voltage above the reference level is applied to the uppermost quasi-nonvolatile memory element of the two quasi-nonvolatile memory elements, and a voltage below the reference level is applied to the lowermost quasi-nonvolatile memory element.

[0122] A binarized neural network circuit 300 according to an embodiment of the present invention includes a plurality of synapse cells 301 configured based on a plurality of quasi-nonvolatile memory elements, a plurality of synapse cells connected in parallel, and a synapse weight matrix configured of the synapse weights stored in each of the synapse cells. The binarized neural network circuit 300 performs a vector matrix multiplication operation between the provided synapse weight matrix and a matrix of input vectors based on input signals for determining synapse weights, and outputs an XNOR binary operation result.

[0123] Therefore, the present invention can realize a binary neural network that can perform both memory and logic operation functions in a memory array composed of quasi-nonvolatile memory elements that perform memory and switching functions in a single element based on a positive feedback loop.

[0124] Furthermore, the present invention uses a quasi-nonvolatile memory device, to which a CMOS process can be applied, as a synapse element, thereby realizing a logic operation binary neural network with almost no characteristic deviation and excellent uniformity and stability.

[0125] 4a and 4b are diagrams illustrating the logical operation of a binarized neural network using a quasi-nonvolatile memory device according to an embodiment of the present invention.

[0126] FIG. 4a illustrates a circuit related to the logical operation of a binary neural network using a quasi-nonvolatile memory device according to one embodiment of the present invention, and FIG. 4b illustrates a table of inputs and outputs of the logical operation of a binary neural network using a quasi-nonvolatile memory device according to one embodiment of the present invention.

[0127] Referring to FIG. 4a, there is shown circuits corresponding to a first embodiment 400, a second embodiment 401, a third embodiment 402 and a fourth embodiment 403, as well as inputs and outputs of the circuits.

[0128] According to the first embodiment 400, when the first quasi-nonvolatile memory device of the two quasi-nonvolatile memory devices is in the second operating state and the second quasi-nonvolatile memory device is in the first operating state, the synapse cell determines the synapse weight value as a positive value.

[0129] According to the second embodiment 401, the synapse cell determines the synapse weight as a negative value when the first quasi-nonvolatile memory device is in the first working state and the second quasi-nonvolatile memory device is in the second working state.

[0130] According to the third embodiment 402, the synapse cell determines the synapse weight as a negative value when the first quasi-nonvolatile memory device is in the second working state and the second quasi-nonvolatile memory device is in the first working state.

[0131] According to the fourth embodiment 403, the synapse cell can determine the synapse weight as a positive value when the first quasi-nonvolatile memory device is in the first working state and the second quasi-nonvolatile memory device is in the second working state.

[0132] For example, the first operational state may be a program state and the second operational state may be an erase state.

[0133] More specifically, the input signal is V Low , V High When is applied, it indicates that the input signal IN is negative, which corresponds to "-1", and conversely, when the BL voltage combination is VHigh , V Low When this is the case, it indicates that the input signal A is "+1", which corresponds to a positive value.

[0134] where V High denotes the voltage at which the memory state of the element is read, and V Low can indicate the voltage at which the memory state of the element cannot be read.

[0135] Both the first embodiment 400 and the second embodiment 401 show the case where the weight value W is "-1", that is, the combination of the memory states of the upper and lower elements is the second operating state and the first operating state.

[0136] First, in the first embodiment 400, V is applied to the BL of the upper element in the erase state and the lower element in the program state. Low and V High When applied, the memory state of the lower element, which is in the programmed state, is read and the output current I OUT can flow at high levels.

[0137] This may mean that in the MAC operation of the XNOR operation binarized neural network, the result of multiplying an input IN of "-1" by a synaptic weight value W of "-1" is "+1".

[0138] In the third embodiment 402, the upper and lower input signals BL are V High and V Low When applied, the memory state of the upper element, which is in the erase state, is read and the output current I OUT flows at a very low level.

[0139] This may mean that in the MAC operation of the XNOR operation binarized neural network, the result of the multiplication of an input IN of "+1" and a synaptic weight value W of "-1" is "-1".

[0140] Both the second embodiment 401 and the fourth embodiment 403 can represent the case where W is "+1", that is, the combination of the memory states of the upper and lower elements is the first operating state and the second operating state.

[0141] In the case of the second embodiment 401, V is applied to the input BL of the upper end element in the first operating state and the lower end element in the second operating state. Low and V High When applied, the memory state of the lower element, which is in the erase state, is read and the output current I OUT flows at a very low level.

[0142] This means that in the MAC operation of the XNOR operation binarized neural network, the result of the multiplication of the input IN of "-1" and the synaptic weight value W of "+" is "-1".

[0143] In the fourth embodiment 403, the upper and lower input signals BL are V High and V Low When applied, it reads the memory state of the upper element, which is in the first operating state, and outputs a current I OUT flows at a high level.

[0144] This can show that in the MAC operation of the XNOR operation binarized neural network, the product operation result of the input IN of "+1" and the synaptic weight value W of "+1" is "+1".

[0145] That is, the synapse cell determines whether the input signal is at a voltage V above a reference level so that each of the two quasi-nonvolatile memory devices is set to one of a first operating state and a second operating state based on the input signal. High When the input signal is below the reference voltage V Low may be determined as the second operating state.

[0146] Referring to FIG. 4b, a truth table 410 illustrates the inputs IN, weights W, and corresponding outputs OUT associated with the first through fourth embodiments 400 through 403 described above.

[0147] In the truth table 410, a first embodiment 411, a second embodiment 412, a third embodiment 413, and a fourth embodiment 414 are shown together.

[0148] 5a to 5c are diagrams illustrating a matrix multiply-accumulate (MAC) operation of a binary neural network using a quasi-nonvolatile memory device according to an embodiment of the present invention.

[0149] 5a to 5c, in relation to the matrix MAC operation of a binarized neural network using a quasi-nonvolatile memory device according to one embodiment of the present invention, a 2x2 cell array is illustrated that performs a matrix MAC operation using vector matrix multiply (VMM) of a 2x1 IN vector.

[0150] Referring to FIG. 5a, image 500 shows an optical image of a 2×2 cell array associated with a matrix-MAC operation of a binary operation network.

[0151] Referring to FIG. 5b, circuit diagram 510 shows a circuit diagram of a 2×2 cell array associated with a matrix MAC operation of a binary operation network.

[0152] Referring to FIG. 5c, timing diagram 520 shows a timing diagram for the inputs and outputs in a 2×2 cell array associated with a matrix-MAC operation of a binary operation network.

[0153] As shown in circuit diagram 510 and timing diagram 520, the W matrix is

number

[0154] On the other hand, the input matrix is

number

[0155] In relation to the matrix MAC operation, it can be defined as Equation 1 below.

[0156]

number

[0157] In Equation 1, W may represent a binarized weighted value (conductance), IN may represent an input signal (voltage), and OUT may represent an output signal (current) obtained by matrix calculation.

[0158] The binarized neural network cell array is driven by the word line voltage V WL is applied only to the weight update, after which the cell array performs matrix MAC operations using the various IN vectors.

[0159] The binarized neural network cell array maintains synaptic weights without consuming energy.

[0160] A plurality of synapse cells are configured based on a plurality of quasi-nonvolatile memory elements, and a synapse weight matrix is ​​provided in which the plurality of synapse cells are connected in parallel and each of the synapse cells is configured with stored synapse weights. A vector matrix multiplication operation is performed between the provided synapse weight matrix and a matrix of input vectors based on input signals for determining the synapse weights, and an XNOR binary operation result can be output.

[0161] When synapse cells are configured with two rows and two columns, the sensed current I associated with the output XNOR binary operation result is SL is the reference current I REF When adjacent to , it outputs a logic state of "0" and the current I SL is the reference current I REF If it is twice the reference current IREF When adjacent to a "0", the logic state can be output as "-2".

[0162] Reference current I REF is the maximum sensed current I SL At half the value (0.33 mA), the logic value can be equal to 0.

[0163] When performing an arithmetic operation, the final arithmetic result is divided into "+2", "0", and "-2" depending on the combination of the synapse weight matrix and the input vector.

[0164] It is confirmed that the calculation result of "+2" has exactly twice the value of "0", and the calculation result of "-2" has a very low level of sensed current of 0 mA.

[0165] The matrix MAC operation of the XNOR binarized neural network is implemented through parallel-connected quasi-nonvolatile memory elements based on the combination between the synapse weight matrix and the input vector.

[0166] The quasi-nonvolatile memory elements that are components of the synapse cells exhibit disturbance-free VBL characteristics during weight update and matrix MAC operations.

[0167] Quasi-nonvolatile memory devices have well-defined p + -npn + The rectification properties inherent in the structure make the cell array immune to the sneak path problem.

[0168] As a result, p + -npn + Due to the excellent characteristics of the quasi-nonvolatile memory element with this structure, a two-transistor (T)-based synapse cell architecture can be realized, and a compact synapse array can be constructed with binarized neural network circuits.

[0169] FIG. 6 is a diagram illustrating a memory operation of a quasi-nonvolatile memory device according to an embodiment of the present invention.

[0170] FIG. 6 illustrates a memory function related to the memory operation of a quasi-nonvolatile memory device according to an embodiment of the present invention.

[0171] Referring to FIG. 6, a graph 600 illustrates the sequence of program, erase, hold, and read operations for a quasi-nonvolatile memory device.

[0172] During program operation, the voltage V DS is -1 V, which injects charge carriers into the n- and p-doped regions, while the voltage V GS is -1V, it reduces the potential barrier height of the n-doped region.

[0173] As a result, the device is in a programmed state, creating a positive feedback loop and accumulating charge carriers in the potential wells.

[0174] During the hold operation, the quasi-nonvolatile memory element has a well-defined p + -npn + The structure maintains excess charge carriers in the potential well without an external bias.

[0175] Therefore, the current I DS is the voltage V DS = 1V, voltage V GS It can be seen that a high level of 0.3 mA is reached in the read operation where V = 0V.

[0176] On the other hand, the voltage V DS = 1V, voltage V GS In the deletion operation, where V = -1 V, the positive feedback loop is removed and the accumulated charge carriers are recombined.

[0177] In the erase state, a low level of current I DS is measured.

[0178] As a result, according to graph 600, the quasi-nonvolatile memory element operates in a positive feedback loop mechanism and + -npn + It can be seen that the structure exhibits the characteristics of a quasi-nonvolatile memory element.

[0179] Therefore, the present invention can realize a binary neural network circuit that can be used in next-generation artificial intelligence computing technology by reducing standby power using the excellent memory characteristics of a quasi-nonvolatile memory device and increasing computing efficiency with low power consumption through excellent switching characteristics.

[0180] FIG. 7 is a diagram for explaining a simulation structure of a binarized neural network circuit using a quasi-nonvolatile memory element according to an embodiment of the present invention.

[0181] FIG. 7 illustrates a simulation structure of a binarized neural network circuit using a quasi-nonvolatile memory element according to an embodiment of the present invention.

[0182] Referring to FIG. 7, a binarized neural network circuit structure 700 shows that the binarized neural network circuit of the present invention can be utilized in performing MNIST image recognition simulation using open source code to investigate and evaluate the validity of the binarized neural network.

[0183] The binarized neural network circuit structure 700 includes the binarized neural network circuit 701 described in FIG.

[0184] The binarized neural network circuit structure 700 has a multi-layer perceptron structure for MNIST recognition simulation, and the synapse array between the input layer consisting of 400 neurons that receive pixel data of the MNIST image and the hidden layer consisting of 100 neurons is made up of a total of 80,000 (400 × 100 synapse cells) quasi-nonvolatile memory elements.

[0185] Each neuron in the output layer corresponds to an MNIST image recognition result, and the synapse array between the input layer and the hidden layer receives MNIST image data through 400 BL pairs and sends matrix MAC results to the hidden layer through 100 SL pairs.

[0186] Each neuron layer may be a binarized neural network circuit 701, and the synaptic arrangement between the hidden layer and the output layer may be implemented in a manner similar to the arrangement mentioned above.

[0187] Simulation results based on the binarized neural network circuit structure 700 are supplemented and explained with reference to FIGS. 8a to 8c.

[0188] 8a to 8c are diagrams illustrating simulation results of a binarized neural network circuit using a quasi-nonvolatile memory device according to an embodiment of the present invention.

[0189] Referring to FIG. 8a, a graph 800 shows the conductance standard deviation σ ON / μ ON We show the influence of the constituent quasi-nonvolatile memory elements on the recognition accuracy of MNIST images.

[0190] Measured data obtained on the devices, including conductance and actuation voltage, were used as simulation parameters.

[0191] σ less than 60% ON / μ ON In the case of , the median recognition accuracy remained above 90%, while σ above 60% ON / μ ON In this case, the recognition accuracy decreased significantly.

[0192] σ ON / μ ON The decrease in accuracy when I is high is due to the parallelized interpretation mechanism of the binarized neural network circuit. SL and Iref This is caused by an increased probability of error when comparing

[0193] Referring to FIG. 8b, graph 810 shows that the quasi-nonvolatile memory device exhibits a low σ of 1.35% across 35 devices with identical structures on a single die. ON / μ ON It shows excellent reproducibility.

[0194] Referring to FIG. 8c, graph 820 shows the recognition accuracy of the binarized neural network circuit for the MINIST image.

[0195] The MINIST image recognition accuracy for 125 training epochs of the binarized neural network circuit is shown.

[0196] For each epoch, 8,000 training datasets (1 million MNIST images in total), 60,000 training labels, and 10,000 test labels are applied.

[0197] Due to the high uniformity and repeatability of the quasi-nonvolatile memory elements, together with the excellent bistability characteristics, the binarized neural network circuit achieves a high accuracy of approximately 93.32%.

[0198] As a result, the high reliability, repeatability, and uniformity of the quasi-nonvolatile memory device can be used to implement miniaturized binarized neural network circuits without loss of accuracy.

[0199] Therefore, the present invention enables a memory array composed of positive feedback loop-based quasi-nonvolatile memory elements to perform the activation function of a neuron circuit by itself, thereby realizing a binary neural network circuit with excellent uniformity and stability.

[0200] In each of the specific embodiments described above, elements included in the invention are expressed as singular or plural depending on the specific embodiment presented.

[0201] However, the expressions "singular" or "plural" are selected to suit the context presented for the convenience of explanation, and each of the above-described embodiments is not limited to singular or plural elements, and elements expressed in the plural may also be composed of singular elements, and elements expressed in the singular may also be composed of plural elements.

[0202] Meanwhile, in the description of the invention, specific embodiments have been described, but it is natural that various modifications are possible within the scope of the technical ideas contained in the various embodiments.

[0203] Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the following claims and their equivalents. [Explanation of symbols]

[0204] 300 Binarized Neural Network Circuit 301 Synaptic Cells 302 Input line processing section 303 Weighted line processing section

Claims

1. a diode structure is located in a channel region between a drain terminal and a source terminal, a gate terminal is located on the diode structure, an operating state is determined by a latch-up or latch-down phenomenon caused by a positive feedback loop in the channel region based on different voltages applied to the drain terminal and the gate terminal, and holes or electrons are accumulated in a potential well in the channel region by the positive feedback loop, thereby realizing a memory characteristic for storing a memory state; The plurality of quasi-nonvolatile memory elements are connected in parallel to form an array circuit, with each pair of the quasi-nonvolatile memory elements operating as one synapse cell, and the circuit determines and stores memory states of the two quasi-nonvolatile memory elements based on an input signal applied from an input line processing unit connected to the array circuit and a weight value update signal applied from a synapse line processing unit connected to the array circuit, and outputs a result of a MAC (multiply-accumulate) operation using a combination of the memory states.

2. 2. The binarized neural network circuit of claim 1, wherein the synapse cell stores a synapse weight value through a combination of the operating states of the two quasi-nonvolatile memory elements, and when the input signal is applied, performs an XNOR logic operation on the input signal and the synapse weight value, and outputs the XNOR logic operation result.

3. The synapse cell determines whether each of the two quasi-nonvolatile memory devices is in a first operating state or a second operating state based on the input signal, and determines whether the input signal is in a voltage (V) greater than or equal to a reference voltage. High ) is determined as the first operating state, and the input signal is a voltage below the reference voltage (V Low 2. The binarized neural network circuit of claim 1, wherein the second operating state is determined to be:

4. When the input signal is a negative value, a voltage equal to or less than the reference voltage is applied to the upper quasi-nonvolatile memory element of the two quasi-nonvolatile memory elements, and a voltage equal to or greater than the reference voltage is applied to the lower quasi-nonvolatile memory element; 4. The binarized neural network circuit according to claim 3, wherein, when the input signal is a positive value, a voltage equal to or greater than the reference voltage is applied to the upper quasi-nonvolatile memory element of the two quasi-nonvolatile memory elements, and a voltage equal to or less than the reference voltage is applied to the lower quasi-nonvolatile memory element.

5. The synapse cell determines whether each of the two quasi-nonvolatile memory devices is in a first operating state or a second operating state based on the input signal, and determines whether the input signal is in a voltage (V) greater than or equal to a reference voltage. High ) is determined as the first operating state, and the input signal is a voltage below the reference voltage (V Low 2. The binarized neural network circuit according to claim 1, wherein the second operating state is determined to be a positive or negative synapse weight based on a combination of the first operating state and the second operating state.

6. 6. The binarized neural network circuit of claim 5, wherein the synapse cell determines the synapse weight as the positive value when a first quasi-nonvolatile memory element of the two quasi-nonvolatile memory elements is in the second operating state and a second quasi-nonvolatile memory element of the two quasi-nonvolatile memory elements is in the first operating state, determines the synapse weight as the negative value when the first quasi-nonvolatile memory element is in the first operating state and the second quasi-nonvolatile memory element is in the second operating state, determines the synapse weight as the negative value when the first quasi-nonvolatile memory element is in the second operating state and the second quasi-nonvolatile memory element is in the first operating state, and determines the synapse weight as the positive value when the first quasi-nonvolatile memory element is in the first operating state and the second quasi-nonvolatile memory element is in the second operating state.

7. 7. The binarized neural network circuit according to claim 6, wherein the synapse cells are configured as a plurality of synapse cells based on a plurality of the quasi-nonvolatile memory elements, the plurality of synapse cells are connected in parallel, and a synapse weight matrix configured of the synapse weights stored in each of the synapse cells is provided, and a vector matrix multiplication operation is performed between the provided synapse weight matrix and a matrix of input vectors based on input signals for determining the synapse weights, and an XNOR binary operation result is output.

8. 8. The binarized neural network circuit of claim 7, wherein when the synapse cells are configured in two rows and two columns, if a current sensed in relation to the output XNOR binary operation result is adjacent to a reference current, the binarized neural network circuit outputs a logic state of "0", if the current is twice the reference current, the binarized neural network circuit outputs a logic state of "+2", and if the reference current is adjacent to "0", the binarized neural network circuit outputs a logic state of "-2".

9. 3. The binarized neural network circuit of claim 2, wherein the quasi-nonvolatile memory device receives a drain voltage of the drain terminal as the input signal, generates a latch-up phenomenon due to the positive feedback loop that occurs when the applied input signal increases in a positive direction, has one of two memory states for the channel region, receives a gate voltage of the gate terminal as the weight update signal, adjusts the input signal that generates the latch-up phenomenon, updates a synapse state associated with the one memory state by applying the input signal and the weight update signal, and performs the MAC operation function according to the synapse weight.

10. the array circuit connects the drain terminals, the gate terminals, and the source terminals of the plurality of quasi-nonvolatile memory devices in parallel to form input lines, weight lines, and output lines, respectively; the input lines are arranged perpendicular to the weight lines and the output lines; 2. The binarized neural network circuit according to claim 1, wherein the weight line and the output line are arranged in parallel.

11. the input line receives the input signal from an input line processing section; The weight line receives the weight update signal from a weight line processing unit; 11. The binarized neural network circuit of claim 10, wherein the output line is connected to a current sensing processor, and outputs a result of the MAC operation based on the input signal and the weight value update signal to a next artificial neural network stage via the current sensing processor.

12. 2. The binarized neural network circuit of claim 1, wherein the quasi-nonvolatile memory device comprises one of a single-gate quasi-nonvolatile memory device, a double-gate quasi-nonvolatile memory device, and a triple-gate quasi-nonvolatile memory device.

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