Display device and electronic device including the same

Abstract

To provide a display device and an electronic device including the display device.SOLUTION: A display device includes: a plurality of pixels including a first pixel, a second pixel adjacent to the first pixel in a first direction, a third pixel adjacent to the first pixel in a second direction, and a fourth pixel adjacent to the third pixel in the first direction and adjacent to the second pixel in the second direction, the first to fourth pixels each including a first subpixel, a second subpixel, and a third subpixel emitting light of different colors; a first data line extending in the first direction and transmitting a data voltage to the second subpixel of the first pixel and the second subpixel of the second pixel; a second data line extending in the first direction and transmitting a data voltage to the second subpixel of the third pixel and the second subpixel of the fourth pixel; a first data connection pattern electrically connected to the first data line through a first contact hole and electrically connected to the second subpixel of the second pixel; and a second data connection pattern electrically connected to the second data line through a second contact hole and electrically connected to the second subpixel of the fourth pixel.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a display device and an electronic device including the display device. [Background technology]

[0002] Recently, the applications of display devices have become more diverse. As the range of use of display devices has expanded, the demand for high-resolution display devices has also increased. To manufacture high-resolution display devices, it is necessary to arrange electronic components with various configurations in a small area. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Korean Patent No. 10-2081650 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention aims to provide a display device structure for reducing color shift due to viewing angles, but such a problem is merely an example and is not intended to limit the scope of the present invention. [Means for solving the problem]

[0005] A display device according to an embodiment of the present invention includes a plurality of pixels including a first pixel, a second pixel adjacent to the first pixel in a first direction, a third pixel adjacent to the first pixel in a second direction perpendicular to the first direction, and a fourth pixel adjacent to the third pixel in the first direction and adjacent to the second pixel in the second direction, the first to fourth pixels including first, second, and third sub-pixels emitting light of different colors; a first data line extending in the first direction and transmitting a data voltage to the second sub-pixel of the first pixel and the second sub-pixel of the second pixel; a second data line extending in the first direction and transmitting a data voltage to the second sub-pixel of the third pixel and the second sub-pixel of the fourth pixel; a first data line electrically connected to the first data line by a first contact hole, the second data line being electrically connected to the second sub-pixel of the third pixel by a first contact hole; a first data connection pattern electrically connected to the second sub-pixel of the fourth pixel; and a second data connection pattern electrically connected to the second data line by a second contact hole and electrically connected to the second sub-pixel of the fourth pixel, wherein in a planar view, a distance between a light-emitting region of the third sub-pixel of the first pixel and a light-emitting region of the third sub-pixel of the second pixel is smaller than a distance between a light-emitting region of the third sub-pixel of the third pixel and a light-emitting region of the third sub-pixel of the fourth pixel, wherein in a planar view, the first contact hole is located between the light-emitting region of the third sub-pixel of the first pixel and the light-emitting region of the third sub-pixel of the second pixel, and wherein in a planar view, the first contact hole and the second contact hole are arranged in a line along the second direction.

[0006] In an exemplary embodiment, the first contact hole may be spaced apart from the light emitting region of the third subpixel of the first pixel and the light emitting region of the third subpixel of the second pixel in a plan view.

[0007] In one embodiment, the second contact hole may be located between the light-emitting region of the third sub-pixel of the third pixel and the light-emitting region of the third sub-pixel of the fourth pixel in a plan view.

[0008] In one embodiment, the display device may further include: a third data line extending in the first direction and transmitting a data voltage to the first sub-pixel of the first pixel and the first sub-pixel of the second pixel; and a third data connection pattern electrically connected to the third data line by a third contact hole and electrically connected to the first sub-pixel of the second pixel, wherein in a plan view, the third contact hole may be arranged in a line with the first contact hole and the second contact hole along the second direction.

[0009] In one embodiment, the display device may further include: a fourth data line extending in the first direction and transmitting a data voltage to the third sub-pixel of the first pixel and the third sub-pixel of the second pixel; and a fourth data connection pattern electrically connected to the fourth data line by a fourth contact hole and electrically connected to the third sub-pixel of the second pixel, wherein in a plan view, the fourth contact hole may be arranged in a line with the first contact hole, the second contact hole, and the third contact hole along the second direction.

[0010] In one embodiment, the display device further includes a first vertical voltage line extending in the first direction and transmitting a first voltage, which is a constant voltage, to each of the first pixel, the second pixel, the third pixel, and the fourth pixel; and a first voltage connection pattern electrically connected to the first vertical voltage line by a fifth contact hole, and in a plan view, the fifth contact hole may be arranged in a line with the first contact hole and the second contact hole along the second direction.

[0011] In one embodiment, the display device further includes a second vertical voltage line extending in the first direction and transmitting a second voltage, which is a constant voltage, to each of the first pixel, the second pixel, the third pixel, and the fourth pixel; and a second voltage connection pattern electrically connected to the second vertical voltage line by a sixth contact hole, and in a plan view, the sixth contact hole may be arranged in a row along the second direction with the first contact hole, the second contact hole, and the fifth contact hole.

[0012] In one embodiment, in a planar view, the fifth contact hole may be located between the light-emitting region of the third sub-pixel of the first pixel and the light-emitting region of the third sub-pixel of the second pixel, and the sixth contact hole may be located between the light-emitting region of the third sub-pixel of the third pixel and the light-emitting region of the third sub-pixel of the fourth pixel.

[0013] In an embodiment, the first data line, the second data line, the first vertical voltage line, and the second vertical voltage line may be disposed on the same layer.

[0014] In one embodiment, the first data connection pattern, the second data connection pattern, the first voltage connection pattern, and the second voltage connection pattern may be disposed on the same layer.

[0015] In an embodiment, the display device may further include a first horizontal voltage line extending in the second direction and electrically connected to the first voltage connection pattern.

[0016] In an embodiment, the display device may further include a second horizontal voltage line disposed on a different layer from the first horizontal voltage line, extending in the second direction, and electrically connected to the second voltage connection pattern.

[0017] In one embodiment, the display device further includes a plurality of separators, and in a planar view, one of the plurality of separators can surround the light-emitting region of the third sub-pixel of the first pixel and the light-emitting region of the third sub-pixel of the second pixel.

[0018] In one embodiment, the third subpixel can emit blue light.

[0019] In an exemplary embodiment, the area of ​​the light-emitting region of the third sub-pixel may be greater than the area of ​​the light-emitting region of the first sub-pixel and the area of ​​the light-emitting region of the second sub-pixel.

[0020] A display device according to an embodiment of the present invention may include a plurality of pixels, each including a first subpixel, a second subpixel, and a third subpixel, each emitting light of a different color; a data line extending in a first direction and transmitting a data voltage to at least one of the plurality of pixels; a first vertical voltage line extending in the first direction and transmitting a first voltage, which is a constant voltage, to the plurality of pixels; a data connection pattern electrically connected to the data line by a first contact hole; and a first voltage connection pattern electrically connected to the first vertical voltage line by a second contact hole, wherein, in a plan view, the first contact hole and the second contact hole may be arranged in a line along a second direction perpendicular to the first direction.

[0021] In one embodiment, the plurality of pixels include a first pixel, a second pixel adjacent to the first pixel in a first direction, a third pixel adjacent to the first pixel in a second direction perpendicular to the first direction, and a fourth pixel adjacent to the third pixel in the first direction and adjacent to the second pixel in the second direction, wherein, in a planar view, a distance between a light-emitting region of the third subpixel of the first pixel and a light-emitting region of the third subpixel of the second pixel is smaller than a distance between a light-emitting region of the third subpixel of the third pixel and a light-emitting region of the third subpixel of the fourth pixel, and wherein, in a planar view, the second contact hole may be located between the light-emitting region of the third subpixel of the first pixel and the light-emitting region of the third subpixel of the second pixel.

[0022] In one embodiment, the display device further includes a second vertical voltage line extending in the first direction and transmitting a second voltage, which is a constant voltage, to the plurality of pixels; and a second voltage connection pattern electrically connected to the second vertical voltage line by a third contact hole, and in a plan view, the third contact hole may be arranged in a line with the first contact hole and the second contact hole along the second direction.

[0023] In one embodiment, the third contact hole may be located between the light-emitting region of the third sub-pixel of the third pixel and the light-emitting region of the third sub-pixel of the fourth pixel in a plan view.

[0024] In an embodiment, the display device may further include a first horizontal voltage line extending in the second direction and electrically connected to the first voltage connection pattern.

[0025] In an embodiment, the display device may further include a second horizontal voltage line disposed on a different layer from the first horizontal voltage line, extending in the second direction, and electrically connected to the second voltage connection pattern.

[0026] In one embodiment, the third subpixel can emit blue light.

[0027] a first semiconductor layer disposed on the substrate and including a silicon semiconductor; a first conductive layer disposed on the first semiconductor layer; a second conductive layer disposed on the first conductive layer; a second semiconductor layer disposed on the second conductive layer and including an oxide semiconductor; a third conductive layer disposed on the second semiconductor layer; a fourth conductive layer disposed on the third conductive layer and including a plurality of connection conductive patterns; a fifth conductive layer disposed on the fourth conductive layer and including a plurality of vertical conductive lines electrically connected to the plurality of connection conductive patterns, each extending in a first direction; and a via insulating layer disposed between the fourth conductive layer and the fifth conductive layer, and including a plurality of contact holes electrically connecting the plurality of connection conductive patterns and the plurality of vertical conductive lines, wherein the plurality of contact holes in the via insulating layer may be separated from light emitting regions of the first to third subpixels in a plan view.

[0028] In one embodiment, the plurality of pixels include a first pixel, a second pixel adjacent to the first pixel in a first direction, a third pixel adjacent to the first pixel in a second direction perpendicular to the first direction, and a fourth pixel adjacent to the third pixel in the first direction and adjacent to the second pixel in the second direction, wherein, in a planar view, a distance between a light-emitting region of the third subpixel of the first pixel and a light-emitting region of the third subpixel of the second pixel is smaller than a distance between a light-emitting region of the third subpixel of the third pixel and a light-emitting region of the third subpixel of the fourth pixel, and a first contact hole among the plurality of contact holes may be located between the light-emitting region of the third subpixel of the first pixel and the light-emitting region of the third subpixel of the second pixel.

[0029] In one embodiment, in a plan view, a second contact hole among the plurality of contact holes may be located between the light-emitting region of the third sub-pixel of the first pixel and the light-emitting region of the third sub-pixel of the second pixel.

[0030] In an embodiment, the first contact hole and the second contact hole may be arranged in a line along the second direction. [Effects of the Invention]

[0031] According to one embodiment of the present invention, a contact hole electrically connecting a pixel electrode of an LED to a conductive line disposed in an adjacent layer toward the top surface of the substrate and a conductive pattern disposed below the conductive line does not overlap with a light-emitting region of the LED, and a via insulating layer defining the contact hole provides a flat upper surface in an area overlapping the light-emitting region, thereby forming a substantially flat pixel electrode of the LED. As a result, the display device of the present invention may reduce color shift or image quality shift due to viewing angle. The above-described effects are merely examples, and the effects of the present invention are not limited to those described above. [Brief explanation of the drawings]

[0032] [Figure 1] 1 is a plan view schematically illustrating a display device according to an embodiment of the present invention; [Figure 2] 1 is a block diagram illustrating a display device according to an embodiment of the present invention; [Figure 3] 2 is an equivalent circuit diagram showing one light emitting diode and a pixel circuit arranged in a display device according to an embodiment of the present invention. FIG. [Figure 4] 1 is a cross-sectional view showing a part of a display area of ​​a display device according to an embodiment of the present invention. [Figure 5] 1 is a plan view schematically showing a part of wiring arranged in a display area of ​​a display device according to an embodiment of the present invention; [Figure 6] 1 is a plan view schematically illustrating the arrangement of wirings arranged in a display area and light-emitting areas of a plurality of pixels in a display device according to an embodiment of the present invention; [Figure 7] FIG. 7 is an enlarged view showing a partial area of ​​FIG. 6. [Figure 8] 1 is a plan view showing first to third pixel circuits extracted from a display device according to one embodiment of the present invention. [Figure 9] 9A to 9C are plan views showing steps of forming the first to third pixel circuits shown in FIG. 8. [Figure 10] 9A to 9C are plan views showing steps of forming the first to third pixel circuits shown in FIG. 8. [Figure 11] 9A to 9C are plan views showing steps of forming the first to third pixel circuits shown in FIG. 8. [Figure 12] 9A to 9C are plan views showing steps of forming the first to third pixel circuits shown in FIG. 8. [Figure 13] 9A to 9C are plan views showing steps of forming the first to third pixel circuits shown in FIG. 8. [Figure 14] 9A to 9C are plan views showing steps of forming the first to third pixel circuits shown in FIG. 8. [Figure 15] 9A to 9C are plan views showing steps of forming the first to third pixel circuits shown in FIG. 8. [Figure 16] 9A to 9C are plan views showing steps of forming the first to third pixel circuits shown in FIG. 8. [Figure 17] 9A to 9C are plan views showing steps of forming the first to third pixel circuits shown in FIG. 8. [Figure 18] 9A to 9C are plan views showing steps of forming the first to third pixel circuits shown in FIG. 8. [Figure 19] FIG. 19 is a cross-sectional view taken along line II' in FIG. 18. [Figure 20A] FIG. 19 is a cross-sectional view taken along line II-II' in FIG. [Figure 20B] FIG. 19 is a cross-sectional view taken along line II-II' in FIG. [Figure 21] 1 is a plan view showing electrical connections between four adjacent pixels according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0033] The present invention can be modified in various ways and can have various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. The advantages and features of the present invention, and methods for achieving them, will become clearer with reference to the embodiments described in detail below in conjunction with the drawings. However, the present invention is not limited to the embodiments described below, and can be embodied in various forms.

[0034] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the drawings, identical or corresponding components will be denoted by the same reference numerals, and duplicate descriptions thereof will be omitted.

[0035] In the following embodiments, terms such as first and second are used to distinguish one component from another, without any limiting meaning.

[0036] In the following embodiments, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0037] In the following embodiments, terms such as "comprise" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0038] In the following embodiments, when a part such as a film, region, or component is said to be on or above another part, this does not only include the case where it is directly on top of the other part, but also the case where another film, region, component, etc. is interposed between them.

[0039] In the drawings, the size of components may be exaggerated or reduced for the sake of convenience. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for the sake of convenience, and the present invention is not necessarily limited to what is shown in the drawings.

[0040] If an embodiment can be implemented differently, the order of certain steps may be performed differently than described. For example, two steps described in succession may be performed substantially simultaneously or may be performed in the reverse order of that described.

[0041] In the following embodiments, when a film, region, component, etc. is said to be connected, it includes not only the case where the film, region, component, etc. are directly connected, but also the case where the film, region, component, etc. are indirectly connected by another film, region, component, etc. being interposed between them. For example, in this specification, when a film, region, component, etc. is said to be electrically connected, it includes not only the case where the film, region, component, etc. are directly electrically connected, but also the case where the film, region, component, etc. are indirectly electrically connected by another film, region, component, etc. being interposed between them.

[0042] FIG. 1 is a plan view schematically showing a display device according to one embodiment of the present invention.

[0043] 1, a display device 1 may include a display area DA for displaying an image and a peripheral area PA outside the display area DA. The display device 1 may provide a predetermined image using light emitted from a plurality of pixels arranged in the display area DA. The display device 1 includes a substrate 100, and therefore the substrate 100 may have the display area DA and the peripheral area PA.

[0044] In a plan view, the display area DA may be rectangular. In other embodiments, the display area DA may be other polygonal shapes, circular shapes, oval shapes, irregular shapes, etc. The display area DA may have rounded corners. In one embodiment, the display device 1 may have a display area DA whose length in a first direction (e.g., y direction) is shorter than its length in a second direction (e.g., x direction) as shown in FIG. 1 . In other embodiments, the display device 1 may have a display area DA whose length in a first direction (e.g., y direction) is longer than its length in a second direction (e.g., x direction).

[0045] The peripheral area PA is an area disposed around the display area DA and may surround at least a portion of the display area DA. In one embodiment, the peripheral area PA may be a type of non-display area where no pixels are disposed. The peripheral area PA may include various wirings and circuits for transmitting electrical signals to the display area DA, as well as pads to which a printed circuit board or a driver IC chip is attached.

[0046] An electronic device may include a display device 1 according to an embodiment of the present invention. The display device 1 according to an embodiment of the present invention is a device for displaying moving or still images and may be used in portable electronic devices such as mobile phones, laptops, tablet personal computers (PCs), smartphones, mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs). The display device 1 may also be used in electronic devices for the Internet of Things (IoT), such as televisions, monitors, billboards, and wearable electronic devices such as smart watches, watch phones, eyeglass displays, and head-mounted displays (HMDs). The display device 1 according to an embodiment may also be used in automotive dashboards, center information displays (CIDs) located in the center fascia or dashboard of an automobile, room mirror displays replacing the side mirrors of an automobile, and display electronic devices located behind the front seats for rear-seat entertainment in an automobile.For example, the electronic device may be one of a flat panel display, a curved display, a computer monitor, a medical monitor, a television, an advertising billboard, indoor or outdoor lighting, a signal light, a head-up display, a fully or partially transparent display, a flexible display, a rollable display, a foldable display, a stretchable display, a laser printer, a telephone, a mobile phone, a tablet, a phablet, a personal digital assistant (PDA), a wearable device, a laptop computer, a digital camera, a camcorder, a viewfinder, a microdisplay, a 3D display, a virtual reality or augmented reality display, a vehicle, a video wall including multiple displays tiled together, a theater or stadium screen, a phototherapy device, or a sign. According to one embodiment, the electronic device including the display device 1 of FIG. 1 may include a bottom cover disposed below the display device 1 and / or a cover window disposed on the display device 1. In one embodiment, the bottom cover and the cover window of the electronic device may be combined to form the exterior of the electronic device.

[0047] FIG. 2 is a block diagram that schematically illustrates a display device 1 according to an embodiment of the present invention.

[0048] 1 and 2, a display device 1 according to an embodiment may include a pixel unit 11, a gate driving circuit 13, a data driving circuit 15, a power supply circuit 17, and a controller 19.

[0049] The pixel unit 11 may include a plurality of pixels arranged in a display area DA (FIG. 1). The plurality of pixels may include sub-pixels emitting different colors. The sub-pixels may be, for example, one of red, green, and blue sub-pixels. The sub-pixels may be arranged in various patterns, such as a stripe pattern, a pentile (diamond) pattern, or a mosaic pattern, to implement an image. Each sub-pixel may include a light-emitting diode (LED) that emits light. The light-emitting diode (LED) of each of the plurality of sub-pixels may be electrically connected to a pixel circuit (PC). Each pixel circuit (PC) may be electrically connected to a gate line (GL) and a data line (DL) and may include a plurality of transistors and at least one capacitor.

[0050] The peripheral area PA (FIG. 1) may include various conductive lines transmitting electrical signals to the display area DA (FIG. 1), outer circuitry electrically connected to the pixel circuits, and pads to which a printed circuit board or driver IC chip is attached. For example, the peripheral area PA (FIG. 1) may include a gate driver circuit 13, a data driver circuit 15, a power supply circuit 17, and a controller 19.

[0051] The gate driving circuit 13 is electrically connected to the plurality of gate lines GL, and can generate gate signals in response to a control signal GCS from the controller 19 and sequentially supply the gate signals to the gate lines GL. The gate signals may be gate control signals that control the turn-on and turn-off of transistors electrically connected to the gate lines GL. The gate signals may be square wave signals including an on voltage at which the transistors are turned on and an off voltage at which the transistors are turned off. In one embodiment, the on voltage may be a high-level voltage (first-level voltage) or a low-level voltage (second-level voltage).

[0052] 2, any one pixel circuit PC is shown connected to one gate line GL, but this is merely an example, and one pixel circuit PC may be connected to two or more gate lines GL, and the gate driving circuit 13 may supply two or more gate signals having different timings for applying an on-voltage to the gate line GL. For example, the pixel circuit PC may be electrically connected to a plurality of gate lines GL, and the gate driving circuit 13 may apply the scan signal GW, the first initialization control signal GI, the second initialization control signal GB, the compensation scan signal GC, and the emission control signal EM to the pixel circuit PC via the gate lines GL, respectively.

[0053] The data driving circuit 15 is connected to a plurality of data lines DL and can supply a data signal Dm to the data lines DL in response to a control signal DCS from the controller 19. The data signal Dm supplied to the data lines DL can be provided to the pixel circuits PC. The data driving circuit 15 can convert input image data having gray levels input from the controller 19 into the data signal Dm in the form of a voltage or current.

[0054] The power supply circuit 17 can generate voltages required to drive the pixel circuits PC and the light emitting diodes LED in response to a control signal PCS from the controller 19. The power supply circuit 17 can generate a drive voltage ELVDD and a common voltage ELVSS and supply them to the pixel circuits PC and the light emitting diodes LED, respectively. The drive voltage ELVDD may be a high-level voltage provided to a first electrode (or pixel electrode, anode) of the light emitting diode LED. The common voltage ELVSS may be a low-level voltage provided to a second electrode (or counter electrode, cathode) of the light emitting diode LED. The power supply circuit 17 can generate a bias voltage Vobs, a first initialization voltage Vint, and a second initialization voltage Vaint and supply them to the pixel circuits PC.

[0055] The voltage level of the driving voltage ELVDD may be higher than the voltage level of the common voltage ELVSS. The voltage levels of the first initialization voltage Vint and the second initialization voltage Vaint may be higher than the voltage level of the common voltage ELVSS. The voltage level of the bias voltage Vobs may be higher than the voltage level of the driving voltage ELVDD.

[0056] The controller 19 can generate control signals GCS, DCS, and PCS based on an externally input signal and supply them to the gate drive circuit 13, the data drive circuit 15, and the power supply circuit 17. The control signal GCS output to the gate drive circuit 13 can include a plurality of clock signals and a gate start signal. The control signal DCS output to the data drive circuit 15 can include a source start signal and a clock signal.

[0057] FIG. 3 is an equivalent circuit diagram showing one of the light emitting diodes LED and pixel circuits PC arranged in the display device 1 according to one embodiment of the present invention.

[0058] 3, the pixel circuits PC are connected to gate lines, for example, the scan lines GWL, the first initialization control lines GIL, the second initialization control lines GBL, the compensation scan lines GCL, and the emission control lines EML, and may receive the scan signals GW, the first initialization control signals GI, the second initialization control signals GB, the compensation scan signals GC, and the emission control signals EM. For example, the scan lines GWL, the first initialization control lines GIL, the second initialization control lines GBL, the compensation scan lines GCL, and the emission control lines EML in FIG. 3 may be gate lines connected to the pixel circuits PC located in the ith row (i is a natural number).

[0059] The pixel circuits PC may receive a data signal Dm via a data line DL. For example, the data line DL in FIG. 3 may be a signal line connected to the pixel circuits PC located in the j-th column (j is a natural number).

[0060] The pixel circuit PC of the display device according to this embodiment is electrically connected to a light-emitting diode LED that emits light of a predetermined color, and the light-emitting diode LED may include a first electrode (pixel electrode, anode), a second electrode (counter electrode, cathode), and an intermediate layer therebetween.

[0061] The pixel circuit PC may include a plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 and capacitors Cst and Ca. The plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 may include a drive transistor T1, a data write transistor T2, a compensation transistor T3, a first initialization transistor T4, an operation control transistor T5, a light-emitting control transistor T6, a second initialization transistor T7, and a bias transistor T8. The capacitors Cst and Ca may include a first capacitor Cst and a second capacitor Ca.

[0062] In one embodiment, some of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be PMOS (p-channel MOSFETs), and the remaining transistors may be NMOS (n-channel MOSFETs). For example, the driving transistor T1, the data writing transistor T2, the operation control transistor T5, the light-emitting control transistor T6, the second initialization transistor T7, and the bias transistor T8 of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be PMOS, and the compensation transistor T3 and the first initialization transistor T4 of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be PMOS, and the remaining transistors may be NMOS. Alternatively, all of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be NMOS or PMOS. Hereinafter, an embodiment will be mainly described in which the compensation transistor T3 and the first initialization transistor T4 are NMOS (n-channel MOSFETs) including an oxide semiconductor, and the rest are PMOS (p-channel MOSFETs).

[0063] In one embodiment, at least one of the plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and at least one of the plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be a transistor having an oxide semiconductor layer.

[0064] The driving transistor T1, which directly affects the brightness of the display device, is configured to include a semiconductor layer made of highly reliable polycrystalline silicon, thereby enabling a high-resolution display device. Meanwhile, oxide semiconductors have high carrier mobility and low leakage current, so voltage drop is not significant even with long drive times. That is, even during low-frequency drive, low-frequency drive is possible because image hue change due to voltage drop is not significant. Because oxide semiconductors have the advantage of low leakage current, at least one of the compensation transistor T3 and the first initialization transistor T4, which are connected to the drive gate electrode of the driving transistor T1, can be made of an oxide semiconductor to prevent leakage current from flowing through the drive gate electrode and reduce power consumption. For example, the driving transistor T1, the data write transistor T2, the operation control transistor T5, the light-emitting control transistor T6, the second initialization transistor T7, and the bias transistor T8 may be transistors having low-temperature polysilicon semiconductor layers, and the compensation transistor T3 and the first initialization transistor T4 may be transistors having oxide semiconductor layers.

[0065] The driving transistor T1 may be connected between a driving voltage line (or vertical driving voltage line, PL) that provides a driving voltage ELVDD and the light emitting diode LED. A gate electrode of the driving transistor T1 may be connected to one end of a first capacitor Cst, which is a storage capacitor. A gate electrode of the driving transistor T1 may be connected to a first node N1. A source electrode of the driving transistor T1 may be connected to the driving voltage line PL via an operation control transistor T5. A drain electrode of the driving transistor T1 may be electrically connected to a first electrode (or pixel electrode, anode) of the light emitting diode LED via an emission control transistor T6. The driving transistor T1 receives a data signal Dm transmitted through a data line DL via a switching operation of the data write transistor T2 and supplies a driving current to the light emitting diode LED.

[0066] The gate electrode of the data write transistor T2 may be connected to the scan line GWL. The first electrode of the data write transistor T2 may be connected to the data line DL, and the second electrode may be connected to the source electrode of the drive transistor T1. The data write transistor T2 is turned on by the scan signal GW transmitted through the scan line GWL to transmit the data signal Dm transmitted to the data line DL to the source electrode of the drive transistor T1. At the same time, the data signal Dm may be transmitted to the gate electrode of the drive transistor T1 by the compensation transistor T3 which is turned on.

[0067] The gate electrode of the compensation transistor T3 may be connected to the compensation scan line GCL. The first electrode of the compensation transistor T3 may be connected to the drain electrode of the driving transistor T1, and the second electrode of the compensation transistor T3 may be connected to the first node N1. The compensation transistor T3 is turned on by a compensation scan signal GC transmitted through the compensation scan line GCL to connect the gate electrode and drain electrode of the driving transistor T1 to each other, thereby diode-connecting the driving transistor T1 and compensating for the threshold voltage Vth of the driving transistor T1.

[0068] The gate electrode of the first initialization transistor T4 may be connected to a first initialization control line GIL. The first electrode of the first initialization transistor T4 may be connected to a first initialization voltage line VIL, and the second electrode may be connected to a first node N1. The first initialization transistor T4 is turned on by a first initialization control signal GI applied from the first initialization control line GIL to transmit a first initialization voltage Vint to the gate electrode of the driving transistor T1, thereby initializing the potential of the gate electrode of the driving transistor T1 (i.e., the potential of the first node N1) to a predetermined voltage. The first initialization voltage Vint may have a voltage level higher than or similar to the common voltage ELVSS.

[0069] The gate electrode of the operation control transistor T5 may be connected to the emission control line EML, the first electrode of the operation control transistor T5 may be connected to the driving voltage line PL, and the second electrode of the operation control transistor T5 may be connected to the source electrode of the driving transistor T1.

[0070] The gate electrode of the emission control transistor T6 may be connected to an emission control line EML. The first electrode of the emission control transistor T6 may be connected to the drain electrode of the driving transistor T1, and the second electrode may be electrically connected to a first electrode (or pixel electrode, anode) of the light emitting diode LED. The operation control transistor T5 and the emission control transistor T6 may be simultaneously turned on by an emission control signal EM applied from the emission control line EML. The driving voltage ELVDD applied via the turned-on operation control transistor T5 may be compensated via the driving transistor T1 and then transmitted to the light emitting diode LED.

[0071] The gate electrode of the second initialization transistor T7 may be connected to a second initialization control line GBL. The first electrode of the second initialization transistor T7 may be connected to a first electrode (or pixel electrode, anode) of the light emitting diode LED, and the second electrode may be connected to a second initialization voltage line VAL. The second initialization transistor T7 may be turned on by a second initialization control signal GB applied from the second initialization control line GBL to initialize the first electrode (or pixel electrode, anode) of the light emitting diode LED. The second initialization control signal GB may be the same as or different from the first initialization control signal GI.

[0072] As a comparative example of the present invention, even if the minimum current of the driving transistor T1 for displaying a black image flows as a driving current, if the light emitting diode LED is lit, the black image may not be properly displayed. However, according to the present invention, the second initialization transistor T7 can disperse a portion of the minimum current of the driving transistor T1 as a bypass current to a current path other than the current path toward the light emitting diode LED. Here, the minimum current of the driving transistor T1 may refer to a current under a condition where the gate-source voltage Vgs of the driving transistor T1 is lower than a threshold voltage (Vth) and the driving transistor T1 is turned off. In this way, a minimum driving current (e.g., a current of 10 pA or less) under the condition of turning off the driving transistor T1 is transmitted to the light emitting diode LED, thereby displaying a black image. When the minimum driving current for displaying a black image flows, the bypass current has a significant effect. On the other hand, when a large driving current for displaying an image such as a normal image or a white image flows, the bypass current has almost no effect. Therefore, when a driving current for displaying a black image flows, an accurate black luminance image can be realized from the driving current using the second initialization transistor T7, thereby improving the contrast ratio and providing a display device with improved display quality.

[0073] The gate electrode of the bias transistor T8 may be connected to the second initialization control line GBL, the first electrode of the bias transistor T8 may be connected to the bias voltage line VOL to which the bias voltage Vobs is provided, and the second electrode of the bias transistor T8 may be connected to the source electrode of the driving transistor T1.

[0074] One end of the first capacitor Cst may be connected to the gate electrode of the driving transistor T1, and the other end may be connected to the driving voltage line PL. The first capacitor Cst may be connected between the driving voltage line PL and a first node N1. The first capacitor Cst may store a voltage between the driving voltage ELVDD and the first node N1.

[0075] The second capacitor Ca may serve as an auxiliary capacitor and be electrically connected to the light-emitting control transistor T6, the second initialization transistor T7, and the first electrode (or pixel electrode, anode) of the light-emitting diode LED. The second capacitor Ca stores and maintains a voltage corresponding to the voltage difference between the first electrode (or pixel electrode, anode) of the light-emitting diode LED and the common voltage line VSL while the second initialization transistor T7 is turned on, thereby preventing the problem of increased black luminance when the light-emitting control transistor T6 is turned off.

[0076] The first electrode (or pixel electrode, anode) of the light emitting diode LED receives a driving current from the driving transistor T1 to emit light and display an image. The driving voltage ELVDD may be a predetermined high-level voltage, and the common voltage ELVSS may be a voltage lower than the driving voltage ELVDD.

[0077] The operation of the pixel circuit PC and the light emitting diode LED will now be described.

[0078] During the initialization period, a high-level first initialization control signal GI may be supplied to the first initialization transistor T4 via the first initialization control line GIL, and a low-level second initialization control signal GB may be supplied to the second initialization transistor T7 via the second initialization control line GBL. As a result, the first initialization transistor T4 and the second initialization transistor T7 may be turned on. The first initialization voltage Vint applied from the first initialization voltage line VIL may be transmitted to the gate electrode of the driving transistor T1 via the first initialization transistor T4 and to the anode via the second initialization transistor T7. As a result, the voltages of the gate electrode and anode of the driving transistor T1 may be initialized.

[0079] Thereafter, during a data write period, a low-level scan signal GW is supplied via the scan line GWL, turning on the data write transistor T2 and the compensation transistor T3. The data write transistor T2 transfers a data signal Dm from the data line DL to the source electrode of the drive transistor T1, and the drive transistor T1 is diode-connected by the compensation transistor T3. As a result, a compensation voltage, which is reduced from the data signal Dm by the threshold voltage of the drive transistor T1, is applied to the gate electrode of the drive transistor T1.

[0080] The driving voltage ELVDD and the compensation voltage are applied to both ends of the first capacitor Cst, and a charge corresponding to the voltage difference between both ends of the first capacitor Cst can be stored in the first capacitor Cst.

[0081] Thereafter, during the light-emitting period, the light-emitting control signal EM supplied from the light-emitting control line EML changes from high to low, turning on the operation control transistor T5 and the light-emitting control transistor T6, thereby generating a driving current due to the voltage difference between the gate electrode voltage of the driving transistor T1 and the driving voltage ELVDD, and the driving current is supplied to the light-emitting diode LED via the light-emitting control transistor T6, causing the light to emit.

[0082] The characteristics of the light emitting diodes LED that emit different light and / or the characteristics of the driving transistors T1 of each pixel circuit PC may be different. In particular, the color coordinate of the display device 1 may change (e.g., reddish) when driven at a high frequency. However, according to the present invention, the voltage of the source electrode of the driving transistor T1 can be controlled via the bias voltage Vobs through the bias transistor T8. This allows the driving current to be controlled, thereby improving the brightness deviation (current deviation) and color coordinate deviation for each sub-pixel. Therefore, a display device with improved display quality can be provided.

[0083] FIG. 4 is a cross-sectional view showing a part of the display area DA of the display device 1 according to one embodiment of the present invention.

[0084] Referring to FIG. 4, pixel circuits PC may be disposed on a substrate 100, and light emitting diodes LED may be disposed on the pixel circuits PC.

[0085] The substrate 100 may include glass, metal, or a polymer resin. In one embodiment, the substrate 100 may be flexible or bendable. If the substrate 100 is flexible or bendable, the substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0086] The substrate 100 may have a single-layer or multi-layer structure of the above materials, and in the case of a multi-layer structure, may further include an inorganic layer. For example, the substrate 100 may include a first organic base layer, a first inorganic barrier layer, a second organic base layer, and a second inorganic barrier layer. The first organic base layer and the second organic base layer may each include a polymer resin. The first inorganic barrier layer and the second inorganic barrier layer are barrier layers that prevent the penetration of external foreign substances and may be single-layer or multi-layer structures including inorganic insulators such as silicon nitride and / or silicon oxide.

[0087] A lower metal layer BML may be disposed on the substrate 100. The lower metal layer BML may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In some embodiments, the lower metal layer BML may be a single layer of molybdenum, a bilayer structure in which a molybdenum layer and a titanium layer are stacked, or a trilayer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked.

[0088] The lower metal layer BML may have a constant voltage level. For example, the lower metal layer BML may be electrically connected to the driving voltage line PL described with reference to FIG. 3 and have the same voltage level (e.g., driving voltage ELVDD, FIG. 3) as the driving voltage line PL. The lower metal layer BML may prevent negative charges from accumulating under the semiconductor layer (hereinafter referred to as driving semiconductor layer A1) of the driving transistor T1, thereby preventing or minimizing the problem of image retention due to negative charges. When viewed from a direction perpendicular to the top surface of the substrate 100, the lower metal layer BML may entirely overlap the channel region C1 of the driving semiconductor layer A1 of the driving transistor T1.

[0089] The buffer layer 111 may be disposed on the lower metal layer BML. The buffer layer 111 may be an inorganic insulating layer containing an inorganic insulating material such as silicon nitride and / or silicon oxide, and may have a single-layer or multi-layer structure containing the aforementioned materials.

[0090] A transistor including a silicon semiconductor layer may be disposed on the buffer layer 111. In this regard, Figure 4 illustrates a driving semiconductor layer A1 of the driving transistor T1, which corresponds to a part of the first silicon semiconductor pattern 1110. The driving semiconductor layer A1 includes a channel region C1 and impurity regions doped with impurities disposed on both sides of the channel region C1. In this regard, Figure 4 illustrates a first region B1, which is one of the impurity regions disposed on one side of the channel region C1.

[0091] The first gate insulating layer 112 may be disposed on the first silicon semiconductor pattern 1110, for example, the driving semiconductor layer A1. The first gate insulating layer 112 may be an inorganic insulating layer including an inorganic insulator such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0092] The first conductive pattern 1210 may be disposed on the first gate insulating layer 112. The first conductive pattern 1210 may include a driving gate electrode G1 and / or a bottom electrode CE1 of the first capacitor Cst. The driving gate electrode G1 of the first conductive pattern 1210 may function as the bottom electrode CE1, or the bottom electrode CE1 may function as the driving gate electrode G1. In other words, the driving gate electrode G1 may be integrally formed with the bottom electrode CE1.

[0093] The first conductive pattern 1210, e.g., the driving gate electrode G1 and / or the lower electrode CE1 of the first capacitor Cst, may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed of a single layer or multiple layers including the above-mentioned materials. In some embodiments, the driving gate electrode G1 and / or the lower electrode CE1 of the first capacitor Cst may include a single layer of molybdenum.

[0094] The second gate insulating layer 113 may be disposed on the driving gate electrode G1 and / or the lower electrode CE1 of the first capacitor Cst. The second gate insulating layer 113 may be an inorganic insulating layer including an inorganic insulator such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0095] Another conductive pattern (hereinafter referred to as a third conductive pattern 1310) may be disposed on the second gate insulating layer 113. The third conductive pattern 1310 may include an upper electrode CE2 of the first capacitor Cst. The third conductive pattern 1310, for example, the upper electrode CE2 of the first capacitor Cst, may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed of a single layer or multiple layers including the above-mentioned materials. In some embodiments, the upper electrode CE2 may include the same material as the lower electrode CE1 and / or the lower metal layer BML.

[0096] The upper electrode CE2 may overlap the drive gate electrode G1 and / or the lower electrode CE1. The upper electrode CE2 may include an opening 1310OP so that a first connection electrode 1630, which electrically connects the drive gate electrode G1 of the drive transistor T1 and the compensation semiconductor layer A3 of the compensation transistor T3, is connected to the drive gate electrode G1. The opening 1310OP may overlap a portion of the drive gate electrode G1.

[0097] The first interlayer insulating layer 114 may be disposed on the upper electrode CE2. The first interlayer insulating layer 114 may be an inorganic insulating layer including an inorganic insulator such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0098] An oxide semiconductor pattern 1410 may be disposed on the first interlayer insulating layer 114. In this regard, Figure 4 illustrates a compensation semiconductor layer A3 of the compensation transistor T3, which corresponds to a part of the oxide semiconductor pattern 1410. The oxide semiconductor pattern 1410 may include an oxide semiconductor material.

[0099] The compensation semiconductor layer A3 includes a channel region C3 and conductive regions disposed on both sides of the channel region C3, and FIG. 4 illustrates one region B3 of the conductive regions disposed on one side of the channel region C3. The compensation semiconductor layer A3 and the driving semiconductor layer A1 may be disposed on different layers. For example, the driving semiconductor layer A1 may be disposed on the buffer layer 111, and the compensation semiconductor layer A3 may be disposed on the first interlayer insulating layer 114. In other words, the vertical distance from the substrate 100 to the compensation semiconductor layer A3 may be greater than the vertical distance from the substrate 100 to the driving semiconductor layer A1.

[0100] The third gate electrode G3 may be disposed below and / or above the compensation semiconductor layer A3. In one embodiment, FIG. 4 illustrates the third gate electrode G3 including a lower compensation gate electrode G3a disposed below the compensation semiconductor layer A3 and an upper compensation gate electrode G3b disposed on the compensation semiconductor layer A3. In other embodiments, either the lower compensation gate electrode G3a or the upper compensation gate electrode G3b may be omitted.

[0101] The lower compensation gate electrode G3a may include the same material as the upper electrode CE2 and may be located on the same layer (e.g., the second gate insulating layer 113). The upper compensation gate electrode G3b may be disposed on the compensation semiconductor layer A3 with the third gate insulating layer 115 sandwiched therebetween. The upper compensation gate electrode G3b may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed of a single layer or multiple layers including the above-mentioned materials.

[0102] 4 illustrates that the third gate insulating layer 115 is disposed only between the upper compensation gate electrode G3b and the compensation semiconductor layer A3, but the present invention is not limited thereto. In another embodiment, the third gate insulating layer 115 may be formed to entirely cover the substrate 100, similar to other insulating layers, for example, the first gate insulating layer 112. The third gate insulating layer 115 may also be an inorganic insulating layer containing an inorganic insulator such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure containing the aforementioned materials.

[0103] The second interlayer insulating layer 116 may be disposed on the upper compensation gate electrode G3b. The second interlayer insulating layer 116 may be an inorganic insulating layer including an inorganic insulator such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0104] The first connection electrode 1630 and the compensation scan line GCL may be disposed on the second interlayer insulating layer 116. The first connection electrode 1630 and the compensation scan line GCL may be formed of a single layer or multiple layers including aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu). In one embodiment, the first connection electrode 1630 and the compensation scan line GCL may have an aluminum / titanium / aluminum three-layer structure. The compensation scan line GCL may be electrically connected to the upper compensation gate electrode G3b through a contact hole penetrating the second interlayer insulating layer 116.

[0105] The first via insulating layer 121 may be disposed on the first connection electrodes 1630 and the compensation scan lines GCL. The first via insulating layer 121 may cover the first connection electrodes 1630 and the compensation scan lines GCL and may be disposed on the second interlayer insulating layer 116. The first via insulating layer 121 may be referred to as a first planarization layer that provides a flat upper surface.

[0106] The first via insulating layer 121 may include an organic insulating material, such as photoresist, BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), Polymethylmethacrylate (PMMA), polystyrene, a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a mixture thereof.

[0107] The driving voltage line PL may be disposed on the first via insulating layer 121. The driving voltage line PL may overlap the driving transistor T1 and the first capacitor Cst. In some embodiments, the driving voltage line PL may overlap the compensation transistor T3. The driving voltage line PL may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-mentioned materials. In one embodiment, the driving voltage line PL may have a three-layer structure of aluminum layer / titanium layer / aluminum layer.

[0108] The second via insulating layer 123 may be disposed on the driving voltage line PL. The second via insulating layer 123 may cover the driving voltage line PL and be disposed on the first via insulating layer 121. The second via insulating layer 123 is also referred to as a second planarization layer that provides a flat upper surface.

[0109] The second via insulating layer 123 may include an organic insulating material, such as photoresist, BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), Polymethylmethacrylate (PMMA), polystyrene, a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a mixture thereof.

[0110] The light emitting diode LED may be disposed on the second via insulating layer 123. The light emitting diode LED may include a pixel electrode 210, an intermediate layer 220, and a counter electrode 230 on the second via insulating layer 123.

[0111] The pixel electrode 210 may be a (semi-)transparent electrode or a reflective electrode. For example, the pixel electrode 210 may include a reflective layer containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof, and a transparent or semi-transparent electrode layer disposed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). For example, the pixel electrode 210 may have a three-layer structure of ITO / Ag / ITO.

[0112] The edge of the pixel electrode 210 is covered by the bank layer 130, and the inner portion of the pixel electrode 210 can overlap the intermediate layer 220 through the pixel opening 130OP of the bank layer 130. That is, the bank layer 130 can cover the edge of the pixel electrode 210 and define the pixel opening 130OP that exposes a part of the pixel electrode 210. The pixel opening 130OP of the bank layer 130 can define the light-emitting area EA of the light-emitting diode LED.

[0113] The pixel electrode 210 may be formed for each light emitting diode LED, whereas the counter electrode 230 may be formed for multiple light emitting diodes LED. In other words, multiple light emitting diodes LED share the counter electrode 230, and the stacked structure of the pixel electrode 210, the intermediate layer 220, and the counter electrode 230 may correspond to the light emitting diode LED.

[0114] An intermediate layer 220 may be disposed on the pixel electrode 210. The intermediate layer 220 may include an emitting layer 222, a first functional layer 221 disposed under the emitting layer 222, and a second functional layer 223 disposed on the emitting layer 222. The emitting layer 222 may have a patterned shape corresponding to the pixel electrode 210. For example, the first emitting layer (not shown) may be patterned to correspond to a first pixel electrode (210a, see FIG. 17) described below, the second emitting layer (222b, see FIG. 20A) may be patterned to correspond to the second pixel electrode (210b, see FIG. 17), and the third emitting layer (222c, see FIG. 17) may be patterned to correspond to the third pixel electrode (210c, see FIG. 20A). The first light-emitting layer, the second light-emitting layer (222b, see FIG. 20A), and the light-emitting layer (222c, see FIG. 20A) may each include a polymer or small molecule organic material that emits light of a predetermined color. The first functional layer 221 may be a hole transport layer. Alternatively, the first functional layer 221 may include a hole injection layer and a hole transport layer. The second functional layer 223 may include an electron transport layer and / or an electron injection layer. The first functional layer 221 and the second functional layer 223 may be integrally formed to accommodate a plurality of light-emitting diodes (LEDs). In other embodiments, the first functional layer 221 or the second functional layer 223 may be omitted.

[0115] In one embodiment, the intermediate layer 220 may include two or more sequentially stacked light-emitting units and a charge generation layer disposed between the two light-emitting units. When the intermediate layer 220 includes two or more light-emitting units and a charge generation layer, the light-emitting diode LED may be a tandem light-emitting device. The light-emitting diode LED has a stacked structure of multiple light-emitting units, which can improve color purity and luminous efficiency.

[0116] One light-emitting unit may include a light-emitting layer 222 and a first functional layer 221 and a second functional layer 223 below and above the light-emitting layer 222, respectively. The charge generation layer may include a negative charge generation layer and a positive charge generation layer. The negative charge generation layer and the positive charge generation layer may further increase the luminous efficiency of the light-emitting diode (LED), which is a tandem light-emitting element having multiple light-emitting layers 222.

[0117] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer can supply electrons. The negative charge generation layer can include a host and a dopant. The host can include an organic material. The dopant can include a metal material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer can supply holes. The positive charge generation layer can include a host and a dopant. The host can include an organic material. The dopant can include a metal material.

[0118] A counter electrode 230 may be disposed on the intermediate layer 220. The counter electrode 230 may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The counter electrode 230 may include, for example, lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), silver-ytterbium (Ag-Yb), indium tin oxide (ITO), indium zinc oxide (IZO), or any combination thereof. The counter electrode 230 may be integrally formed to accommodate multiple light-emitting diodes (LEDs).

[0119] An encapsulation layer 300 may be disposed on the light-emitting diode LED. The encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 4 illustrates one embodiment in which the encapsulation layer 300 includes a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330.

[0120] The first inorganic sealing layer 310 and the second inorganic sealing layer 330 are made of silicon oxide (SiO2), silicon nitride (SiN X The first inorganic sealing layer 310 and the second inorganic sealing layer 330 may have a single layer or multi-layer structure including the inorganic insulating material.

[0121] The organic encapsulation layer 320 can relieve internal stress in the first inorganic encapsulation layer 310 and / or the second inorganic encapsulation layer 330. The organic encapsulation layer 320 can include a polymer-based material. The polymer-based material can include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.), or any combination thereof.

[0122] The organic encapsulation layer 320 may be formed by applying a flowable material containing a monomer and then reacting the monomer with heat or light such as ultraviolet light to bond the monomer into a polymer, or by applying a polymer material.

[0123] 5 is a plan view schematically illustrating a portion of wiring arranged in a display area DA of a display device (1, see FIG. 1) according to one embodiment of the present invention. The pixel circuits PC may be arranged in the display area DA along a first direction (e.g., ±y direction) and a second direction (e.g., ±x direction), and FIG. 5 illustrates pixel circuits PC electrically connected to pixels arranged in the same row, e.g., the i-th row.

[0124] The pixel circuits PC may be electrically connected to the light emitting diodes (LEDs, see FIG. 3) of the plurality of subpixels, respectively. For example, the first pixel circuit PC1 may be electrically connected to the first light emitting diode of the first subpixel, the second pixel circuit PC2 may be electrically connected to the second light emitting diode of the second subpixel, and the third pixel circuit PC3 may be electrically connected to the third light emitting diode of the third subpixel. For convenience of explanation, the pixel circuits PC electrically connected to the first light emitting diode, the second light emitting diode, and the third light emitting diode, which emit light of different colors, respectively, will be referred to as the first to third pixel circuits PC1, PC2, and PC3.

[0125] 5, the first to third pixel circuits PC1, PC2, and PC3 may be repeatedly arranged along a second direction (e.g., ±x direction). The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 may be arranged in this order along the second direction (e.g., ±x direction), and the distance between the second pixel circuit PC2 and the third pixel circuit PC3 may be greater than the distance between the second pixel circuit PC2 and the first pixel circuit PC1.

[0126] The display device (1, see FIG. 1) may include lines arranged in the display area DA and electrically connected to the pixel circuits PC, such as first conductive lines (hereinafter referred to as horizontal conductive lines) extending along a second direction (e.g., ±x direction) and second conductive lines (hereinafter referred to as vertical conductive lines) extending along a first direction (e.g., ±y direction).

[0127] The horizontal conductive lines extending along the second direction (e.g., ±x direction) may include a horizontal voltage line HVTL, a first initialization control line GIL, a scan line GWL, a compensation scan line GCL, an emission control line EML, a repair line RL, a second initialization control line GBL, and a bias voltage line VOL. The horizontal voltage line HVTL may be a wiring electrically connected to a vertical voltage line VVTL, which will be described later. The horizontal voltage line HVTL may include a first initialization horizontal voltage line HVIL and a second initialization horizontal voltage line HVAL. The second initialization horizontal voltage line HVAL may include a 2-1st initialization horizontal voltage line HVAL(R) and a 2-2nd initialization horizontal voltage line HVAL(GB). In one embodiment, the first initialization horizontal voltage line HVIL, the 2-1st initialization horizontal voltage line HVAL(R), and the 2-2nd initialization horizontal voltage line HVAL(GB) may be arranged on different layers.

[0128] Vertical conductive lines extending along a first direction (e.g., ±y direction) may include a vertical voltage line VVTL, a first data line DL1, a second data line DL2, and a third data line DL3. The vertical voltage line VVTL may include a first initialization vertical voltage line VVIL, a common voltage line VSL providing a common voltage (ELVSS, see FIG. 3), and a second initialization vertical voltage line VVAL. The second initialization vertical voltage line VVAL may include a 2-1 initialization vertical voltage line VVAL(R) and a 2-2 initialization vertical voltage line VVAL(GB).

[0129] The first initialization vertical voltage line VVIL and the first initialization horizontal voltage line HVIL, which provide the first initialization voltage Vint, may be electrically connected in the display area DA. The second-first initialization horizontal voltage line HVAL(R) and the second-first initialization vertical voltage line VVAL(R), which provide the second-first initialization voltage Vaint(R) to the first pixel circuit PC1, may be electrically connected in the display area DA. The second-second initialization vertical voltage line VVAL(GB) and the second-second initialization horizontal voltage line HVAL(GB), which provide the second-second initialization voltage Vaint(GB) to the second pixel circuit PC2 and the third pixel circuit PC3, respectively, may be electrically connected in the display area DA.

[0130] 5 illustrates that the second pixel circuit PC2 and the third pixel circuit PC3 are electrically connected to the same voltage line, for example, the 2-2 initialization vertical voltage line VVAL(GB) and / or the 2-2 initialization horizontal voltage line HVAL(GB), but the present invention is not limited thereto. In another embodiment, the horizontal and vertical voltage lines for applying the second initialization voltage to the second pixel circuit PC2 and the horizontal and vertical voltage lines for applying the second initialization voltage to the third pixel circuit PC3 may exist independently.

[0131] The first data line DL1, the second data line DL2, and the third data line DL3 may be electrically connected to the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3, respectively. The first, second, and third data lines DL1, DL2, and DL3 may transmit data signals (Dm, see FIG. 3) to the first, second, and third pixel circuits PC1, PC2, and PC3, respectively.

[0132] Fig. 6 is a plan view schematically showing the arrangement of wirings and light-emitting regions of a plurality of pixels P arranged in a display area DA of a display device (1, see Fig. 1) according to one embodiment of the present invention. Fig. 7 is an enlarged view showing a partial area of ​​Fig. 6. Fig. 7 is an enlarged view showing four adjacent pixels Pa, Pb, Pc, and Pd, i.e., first to fourth pixels Pa, Pb, Pc, and Pd, among the plurality of pixels P shown in Fig. 6. Fig. 6 illustrates the arrangement of some horizontal and vertical conductive lines among the plurality of wirings described with reference to Fig. 5.

[0133] 6 and 7, each of the pixels P may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3. The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may emit light of different colors through a first light emitting diode (not shown), a second light emitting diode (LED2, see FIG. 20A), and a third light emitting diode (LED3, see FIG. 20A), respectively. For example, the first subpixel SP1 may be a red subpixel that emits red light, the second subpixel SP2 may be a green subpixel that emits green light, and the third subpixel SP3 may be a blue subpixel that emits blue light.

[0134] The pixels P may be arranged along a first direction (e.g., y direction) and a second direction (e.g., x direction). For example, the pixels P may be arranged in a matrix including a plurality of pixel columns extending in the first direction (e.g., ±y directions) and a plurality of pixel rows extending in the second direction (e.g., ±x directions).

[0135] For example, the plurality of pixels P may include a first pixel Pa, a second pixel Pb, a third pixel Pc, and a fourth pixel Pd, as shown in FIG. 7. The first pixel Pa and the second pixel Pb may be arranged along a first direction, and the third pixel Pc and the fourth pixel Pd may be arranged along the first direction in a column different from the first pixel Pa and the second pixel Pb. The first pixel Pa and the third pixel Pc may be arranged along a second direction, and the second pixel Pb and the fourth pixel Pd may be arranged along a row different from the first pixel Pa and the third pixel Pc. The second pixel Pb may be adjacent to the first pixel Pa in the first direction, the third pixel Pc may be adjacent to the first pixel Pa in the second direction, and the fourth pixel Pd may be adjacent to the third pixel Pc in the first direction and adjacent to the second pixel Pb in the second direction.

[0136] In each column, the first light-emitting region EA1 of the first subpixel SP1 and the second light-emitting region EA2 of the second subpixel SP2 may be alternately and repeatedly arranged along the first direction. For example, the second light-emitting region EA2 of the second subpixel SP2a of the first pixel Pa, the first light-emitting region EA1 of the first subpixel SP1a of the first pixel Pa, the second light-emitting region EA2 of the second subpixel SP2b of the second pixel Pb, and the first light-emitting region EA1 of the first subpixel SP1b of the second pixel Pb may be sequentially arranged along the first direction. For example, the second light-emitting region EA2 of the second subpixel SP2c of the third pixel Pc, the first light-emitting region EA1 of the first subpixel SP1c of the third pixel Pc, the second light-emitting region EA2 of the second subpixel SP2d of the fourth pixel Pd, and the first light-emitting region EA1 of the first subpixel SP1d of the fourth pixel Pd may be sequentially arranged along the first direction.

[0137] In each column, the third light-emitting regions EA3 of the third subpixels SP3 may be repeatedly arranged along the first direction. For example, the third light-emitting region EA3 of the third subpixel SP3a of the first pixel Pa and the third light-emitting region EA3 of the third subpixel SP3b of the second pixel Pb may be sequentially arranged along the first direction. For example, the third light-emitting region EA3 of the third subpixel SP3c of the third pixel Pc and the third light-emitting region EA3 of the fourth subpixel SP4d of the fourth pixel Pd may be sequentially arranged along the first direction.

[0138] The third light-emitting regions EA3 arranged in the same row in two adjacent columns may be shifted relative to each other. For example, the third light-emitting region EA3 of the pixel P arranged in the i-th row and j-th column and the third light-emitting region EA3 of the pixel P arranged in the i-th row and (j+1)-th column may be arranged diagonally rather than in a straight line along the second direction.

[0139] In each column, the third light-emitting regions EA3 are not equally spaced from one another. In one embodiment, the third light-emitting regions EA3 in each column may be alternately spaced at a relatively short first distance D1 and a longer second distance D2. For example, when the distance between a pair of adjacent third light-emitting regions EA3 is the first distance D1, the distance between the adjacent third light-emitting region EA3 in the first direction from one of the pair of third light-emitting regions EA3 may be the second distance D2.

[0140] 7, the third light-emitting regions EA3 arranged in the same row in two adjacent columns are shifted relative to each other, so that the distance between two third light-emitting regions EA3 arranged in one column may be different from the distance between two third light-emitting regions EA3 arranged in another adjacent column in the four third light-emitting regions EA3 arranged in two adjacent rows and two adjacent columns. For example, as shown in FIG. 7, the first distance D1 between the third light-emitting region EA3 of the third sub-pixel SP3a of the first pixel Pa and the third light-emitting region EA3 of the third sub-pixel SP3b of the second pixel Pb is shorter than the second distance D2 between the third light-emitting region EA3 of the third sub-pixel SP3c of the third pixel Pc and the third light-emitting region EA3 of the third sub-pixel SP3d of the fourth pixel Pd.

[0141] Although the shapes of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 are illustrated as squares with rounded corners (apexes), the shapes of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be variously modified, such as polygons including triangles and squares, circles, or ellipses.

[0142] The first light-emitting region EA1 of the first subpixel SP1, the second light-emitting region EA2 of the second subpixel SP2, and the third light-emitting region EA3 of the third subpixel SP3 may have different areas (sizes). In one embodiment, the third light-emitting region EA3 of the third subpixel SP3 may have a larger area than the first light-emitting region EA1 of the first subpixel SP1. Also, the third light-emitting region EA3 of the third subpixel SP3 may have a larger area than the second light-emitting region EA2 of the second subpixel SP2. In one embodiment, the second light-emitting region EA2 of the second subpixel SP2 may have a larger area than the first light-emitting region EA1 of the first subpixel SP1. In another embodiment, the first light-emitting region EA1 of the first subpixel SP1 may have the same area as the second light-emitting region EA2 of the second subpixel SP2.

[0143] The vertical voltage lines VVTL may be spaced apart from one another in the second direction and arranged in different columns. The first initialization vertical voltage line VVIL, the common voltage line VSL, the 2-1st initialization vertical voltage line VVAL(R), and the 2-2nd initialization vertical voltage line VVAL(GB) may be spaced apart from one another and arranged in different columns. In one embodiment, the first initialization vertical voltage line VVIL, the common voltage line VSL, the 2-1st initialization vertical voltage line VVAL(R), the 2-2nd initialization vertical voltage line VVAL(GB), and the common voltage line VSL may be spaced apart from one another in the second direction. For example, the first initialization vertical voltage line VVIL may be arranged in the jth column (j is a natural number), the common voltage line VSL may be arranged in the (j+1)th column, the 2-1st initialization vertical voltage line VVAL(R) may be arranged in the (j+2)th column, the 2-2nd initialization vertical voltage line VVAL(GB) may be arranged in the (j+3)th column, and the common voltage line VSL may be arranged in the (j+4)th column. However, this is merely an example, and the arrangement order of the vertical voltage lines VVTL may be changed in various ways.

[0144] The display device (1, see FIG. 1) may further include connecting conductive patterns CP arranged in the display area DA. In FIGS. 6 and 7, the connecting conductive patterns CP are illustrated as being located between the light-emitting areas and spaced apart from each light-emitting area, but this is not limiting. For example, at least a portion of each connecting conductive pattern CP may be located between the light-emitting areas and include a contact portion located between the light-emitting areas. For example, a portion of each connecting conductive pattern CP may be located between the light-emitting areas, and the remaining portion may overlap at least one of the light-emitting areas.

[0145] The horizontal voltage line HVTL may be electrically connected to the vertical voltage line VVTL by a connecting conductive pattern CP. In each row, the horizontal voltage line HVTL may include a first initialization horizontal voltage line HVIL, a 2-1st initialization horizontal voltage line HVAL(R), and a 2-2nd initialization horizontal voltage line HVAL(GB). For example, the horizontal voltage line HVTL may include the 2-1st initialization horizontal voltage line HVAL(R), the first initialization horizontal voltage line HVIL, and the 2-2nd initialization horizontal voltage line HVAL(GB) located in the i-th row, and the 2-1st initialization horizontal voltage line HVAL(R), the first initialization horizontal voltage line HVIL, and the 2-2nd initialization horizontal voltage line HVAL(GB) located in the (i+1)-th row. Since the horizontal voltage lines HVTL arranged in each row are electrically connected to the vertical voltage line VVTL, a voltage may be transmitted to each of the plurality of pixels P arranged in a matrix via the vertical voltage line VVTL.

[0146] The vertical conductive lines (e.g., the first to third data lines DL1, DL2, and DL3 and the vertical voltage line VVTL) may be electrically connected to the connection conductive pattern CP through the contact hole CNT. In one embodiment, the vertical conductive lines may be disposed on the same layer (e.g., the first via insulating layer 121) as the driving voltage line PL described with reference to FIG. 4. In one embodiment, the connection conductive pattern CP may be disposed on the same layer (e.g., the second interlayer insulating layer 116) as the compensating scan line GCL described with reference to FIG. 4. The first via insulating layer 121 described with reference to FIG. 4 may be disposed between the connection conductive pattern CP and the vertical conductive lines, and the contact hole CNT may be defined in the first via insulating layer 121. The contact hole CNT may electrically connect the connection conductive pattern CP and the vertical voltage line VVTL to through holes penetrating the first via insulating layer 121. Each vertical conductive line includes a contact portion that is connected (or in contact with) the connecting conductive pattern CP within the contact hole CNT, and the description of the contact hole CNT in this specification can be understood in the same way as the description of the contact portion of each vertical conductive line.

[0147] The connecting conductive pattern CP may include a voltage connecting pattern VCP electrically connected to the vertical voltage line VVTL and a data connecting pattern DCP electrically connected to the first to third data lines DL1, DL2, and DL3. The data connecting pattern DCP may include first data connecting patterns DCP1a and DCP1b electrically connected to the first data line DL1, second data connecting patterns DCP2a and DCP2b electrically connected to the second data line DL2, and third data connecting patterns DCP3a and DCP3b electrically connected to the third data line DL3.

[0148] In one embodiment, the vertical voltage line VVTL is electrically connected to the horizontal voltage line HVTL through the voltage connection pattern VCP to transmit a constant voltage (e.g., a first initialization voltage, a 2-1 initialization voltage, or a 2-2 initialization voltage) to each of the pixels P. For example, if the vertical voltage line VVTL is the first initialization vertical voltage line VVIL, it may be electrically connected to the first initialization horizontal voltage line HVIL through the voltage connection pattern VCP. For example, if the vertical voltage line VVTL is the 2-1 initialization vertical voltage line VVAL(R), it may be electrically connected to the 2-1 initialization horizontal voltage line HVAL(R) through the voltage connection pattern VCP. For example, if the vertical voltage line VVTL is the 2-2 initialization vertical voltage line VVAL(GB), it may be electrically connected to the 2-2 initialization horizontal voltage line HVAL(GB) through the voltage connection pattern VCP. In one embodiment, if the vertical voltage line VVTL is the common voltage line VSL, it is electrically connected to the voltage connection pattern VCP through the contact hole CNT but is not connected to the horizontal conductive line arranged in the display area DA. However, even in this case, the common voltage line VSL can be electrically connected to the counter electrode (230, see FIG. 4) to transmit a common voltage to each of the pixels P. In another embodiment, the common voltage line VSL can be electrically connected to a horizontal conductive line extending in the second direction through the voltage connection pattern VCP and the contact hole CNT.

[0149] In a plan view, at least some of the contact holes CNT connecting the vertical voltage line VVTL and the connection conductive pattern CP may be arranged between the third light-emitting regions EA3 spaced apart by a relatively short first distance D1. The remaining parts of the contact holes CNT connecting the vertical voltage line VVTL and the connection conductive pattern CP may be arranged in line along the second direction with the contact holes CNT arranged between the third light-emitting regions EA3 spaced apart by the short first distance D1. The contact holes CNT connecting the vertical voltage line VVTL and the connection conductive pattern CP do not overlap with the first to third light-emitting regions EA1, EA2, and EA3. That is, in a plan view, the contact holes CNT connecting the vertical voltage line VVTL and the connection conductive pattern CP may be spaced apart from the first to third light-emitting regions EA1, EA2, and EA3.

[0150] In this specification, the expression that a contact hole CNT connects (or electrically connects) A and B means that A and B are connected (or electrically connected) by the contact hole CNT. Alternatively, the expression that a contact hole CNT connects (or electrically connects) A and B can mean that A and B are electrically connected (or electrically connected) by the contact portion of A or B arranged in the contact hole CNT.

[0151] 7, a contact hole CNT electrically connecting the second-1 data line DL2a and the second-1 data connection pattern DCP2a may be located between the third light-emitting region EA3 of the third subpixel SP3a of the first pixel Pa and the third light-emitting region EA3 of the third subpixel SP3b of the second pixel Pb. In this case, the second-1 data line DL2a extends in the first direction to overlap the third light-emitting region EA3 of the third subpixel SP3a of the first pixel Pa and the third light-emitting region EA3 of the third subpixel SP3b of the second pixel Pb, and may transmit a data voltage to the second subpixel SP2a of the first pixel Pa and the second subpixel SP2b of the second pixel Pb. In addition, the second-1 data connection pattern DCP2a may be electrically connected to the second subpixel SP2b of the second pixel Pb.

[0152] The contact holes CNT electrically connecting the 2-2 data line DL2b and the 2-2 data connection pattern DCP2b may be aligned in the second direction with the contact holes CNT electrically connecting the 2-1 data line DL2a and the 2-1 data connection pattern DCP2a. The 2-2 data line DL2b extends in the first direction to overlap the third light-emitting area EA3 of the third subpixel SP3c of the third pixel Pc and the third light-emitting area EA3 of the third subpixel SP3d of the fourth pixel Pd, and may transmit data voltages to the second subpixel SP2c of the third pixel Pc and the second subpixel SP2d of the fourth pixel Pd. The 2-2 data connection pattern DCP2b may also be electrically connected to the second subpixel SP2d of the fourth pixel Pd. A contact hole CNT electrically connecting the 2-2 data line DL2b and the 2-2 data connection pattern DCP2b may be located between the third light-emitting area EA3 of the third sub-pixel SP3c of the third pixel Pc and the third light-emitting area EA3 of the third sub-pixel SP3d of the fourth pixel Pd.

[0153] The contact holes CNT electrically connecting the 1-1 data line DL1a and the 1-1 data connection pattern DCP1a may be aligned in the second direction with the contact holes CNT connecting the 2-1 data line DL2a and the 2-1 data connection pattern DCP2a. The 1-1 data line DL1a may transmit a data voltage to the first subpixel SP1a of the first pixel Pa and the first subpixel SP1b of the second pixel Pb. The 1-1 data connection pattern DCP1a may be electrically connected to the first subpixel SP1b of the second pixel Pb.

[0154] The contact holes CNT electrically connecting the 3-1 data line DL3a and the 3-1 data connection pattern DCP3a may be aligned in the second direction with the contact holes CNT connecting the 2-1 data line DL2a and the 2-1 data connection pattern DCP2a. The 3-1 data line DL3a may transmit a data voltage to the third subpixel SP3a of the first pixel Pa and the third subpixel SP3b of the second pixel Pb. The 3-1 data connection pattern DCP3a may be electrically connected to the third subpixel SP3b of the second pixel Pb.

[0155] Similarly, the contact hole CNT electrically connecting the 1-2 data line DL1b and the 1-2 data connection pattern DCP1b and the contact hole CNT electrically connecting the 3-2 data line DL3b and the 3-2 data connection pattern DCP3b may be aligned in the second direction with the contact hole CNT connecting the 2-1 data line DL2a and the 2-1 data connection pattern DCP2a. The 1-2 data line DL1b may transmit a data voltage to the first subpixel SP1c of the 3rd pixel Pc and the first subpixel SP1d of the 4th pixel Pd, and the 3-2 data line DL3b may transmit a data voltage to the third subpixel SP3c of the 3rd pixel Pc and the third subpixel SP3d of the 4th pixel Pd. The 1-2 data connection pattern DCP1b may be electrically connected to the first subpixel SP1d of the 4th pixel Pd, and the 3-2 data connection pattern DCP3b may be electrically connected to the third subpixel SP3d of the 4th pixel Pd.

[0156] A contact hole CNT electrically connecting the first vertical voltage line VVTLa and the first voltage connection pattern VCPa may be located between the third light-emitting region EA3 of the third subpixel SP3a of the first pixel Pa and the third light-emitting region EA3 of the third subpixel SP3b of the second pixel Pb. In this case, the first vertical voltage line VVTLa may extend in the first direction to overlap the third light-emitting region EA3 of the third subpixel SP3a of the first pixel Pa and the third light-emitting region EA3 of the third subpixel SP3b of the second pixel Pb. The contact hole CNT electrically connecting the first vertical voltage line VVTLa and the first voltage connection pattern VCPa may be aligned with the contact holes CNT electrically connecting the data lines and the data connection patterns DCP. For example, the contact hole CNT electrically connecting the first vertical voltage line VVTLa and the first voltage connection pattern VCPa may be aligned with the contact hole CNT electrically connecting the 2-1st data line DL2a and the 2-1st data connection pattern DCP2a in the second direction. In one embodiment, the first vertical voltage line VVTLa may be disposed between the second-first data line DL2a and the third-first data line DL3a.

[0157] The contact holes CNT electrically connecting the second vertical voltage line VVTLb and the second voltage connection pattern VCPb may be aligned in the second direction with the contact holes CNT electrically connecting the first vertical voltage line VVTLa and the first voltage connection pattern VCPa. In this case, the second vertical voltage line VVTLb may extend in the first direction to overlap the third light-emitting area EA3 of the third subpixel SP3c of the third pixel Pc and the third light-emitting area EA3 of the third subpixel SP3d of the fourth pixel Pd. The contact holes CNT electrically connecting the second vertical voltage line VVTLb and the second voltage connection pattern VCPb may be aligned in the second direction with the contact holes CNT electrically connecting the data lines and the data connection patterns DCP. For example, the contact holes CNT electrically connecting the second vertical voltage line VVTLb and the second voltage connection pattern VCPb may be aligned in the second direction with the contact holes CNT electrically connecting the 2-1 data line DL2a and the 2-1 data connection pattern DCP2a. In one embodiment, the second vertical voltage line VVTLb may be disposed between the second-second data line DL2b and the third-second data line DL3b.

[0158] The first vertical voltage line VVTLa and the second vertical voltage line VVTLb may be vertical voltage lines VVTL arranged in two adjacent columns, respectively. The first vertical voltage line VVTLa and the second vertical voltage line VVTLb may be different types of vertical voltage lines. For example, the first vertical voltage line VVTLa may transmit a first voltage, which is a constant voltage, to the first to fourth pixels Pa, Pb, Pc, and Pd, and the second vertical voltage line VVTLb may transmit a second voltage, which is also a constant voltage, to the first to fourth pixels Pa, Pb, Pc, and Pd. For example, the first vertical voltage line VVTLa may be any one of the first initialization vertical voltage line VVIL, the common voltage line VSL, the 2-1st initialization vertical voltage line VVAL(R), and the 2-2nd initialization vertical voltage line VVAL(GB), and the second vertical voltage line VVTLb may be any other one of the first initialization vertical voltage line VVIL, the common voltage line VSL, the 2-1st initialization vertical voltage line VVAL(R), and the 2-2nd initialization vertical voltage line VVAL(GB).

[0159] Although the connection between the first voltage connection pattern VCPa and the horizontal voltage line HVTL is omitted in FIG. 7, the first vertical voltage line VVTLa may be electrically connected to one of the horizontal voltage lines HVTL as shown in FIG. 6. For example, the first vertical voltage line VVTLa may be electrically connected to a first horizontal voltage line (e.g., one of the first initialization horizontal voltage line HVIL, the 2-1st initialization horizontal voltage line HVAL(R), and the 2-2nd initialization horizontal voltage line (HVAL(GB))) by the first voltage connection pattern VCPa. Although the connection between the second voltage connection pattern VCPb and the horizontal voltage line HVTL is omitted in FIG. 7, the second vertical voltage line VVTLb may be electrically connected to one of the horizontal voltage lines HVTL as shown in FIG. 6. For example, the second vertical voltage line VVTLb may be electrically connected to a second horizontal voltage line (e.g., one of the first initialization horizontal voltage line HVIL, the 2-1st initialization horizontal voltage line HVAL(R)) by the second voltage connection pattern VCPb. ) and the 2-2nd initialization horizontal voltage line HVAL(GB). The first horizontal voltage line and the second horizontal voltage line may be different wirings arranged on different layers. For example, the first vertical voltage line VVTLa may be electrically connected to the first horizontal voltage lines arranged in a plurality of rows, respectively, to transmit a first voltage to each of the plurality of pixels P including the first to fourth pixels Pa, Pb, Pc, and Pd. For example, the second vertical voltage line VVTLb may be electrically connected to the second horizontal voltage lines arranged in a plurality of rows, respectively, to transmit a second voltage to each of the plurality of pixels P including the first to fourth pixels Pa, Pb, Pc, and Pd.

[0160] In one embodiment, when the light emitting diodes (LEDs, see FIG. 4) of the plurality of pixels P are tandem light emitting elements, the functional layer included in the intermediate layer 220 may have relatively high electrical conductivity. In one embodiment, the display device (1, see FIG. 1) may further include separators SEP for reducing leakage current between adjacent light emitting diodes LED. In a plan view, the separators SEP may include a separator surrounding the first light emitting region EA1, a separator surrounding the second light emitting region EA2, and a separator surrounding the pair of third light emitting regions EA3. The distance between the pair of third light emitting regions EA3 surrounded by one separator may be a first distance D1. For example, as shown in FIG. 7, one of the plurality of separators may surround the third light emitting region EA3 of the third subpixel SP3a of the first pixel Pa and the third light emitting region EA3 of the third subpixel SP3b of the second pixel Pb. However, since the separator SEP does not completely surround each of the first light-emitting area EA1, the second light-emitting area EA2, and the pair of third light-emitting areas EA3, the opposing electrodes (230, see FIG. 4) may be connected to each other and integrally provided in the display area DA.

[0161] In one embodiment, the display device (1, see FIG. 1) may further include a spacer SPC. In a plan view, the spacer SPC may be located between a pair of third light-emitting regions EA3 and another pair of third light-emitting regions EA3, each surrounded by a separator SEP. For example, in a plan view, the spacer SPC may be located between a pair of third light-emitting regions EA3 surrounded by a separator SEP and the third light-emitting regions EA3 spaced apart by a second distance D2 along the first direction. For example, as shown in FIG. 7, the spacer SPC may be located between the third light-emitting region EA3 of the third sub-pixel SP3c of the third pixel Pc and the third light-emitting region EA3 of the third sub-pixel SP3d of the fourth pixel Pd.

[0162] In one embodiment, the spacer SPC may overlap a contact hole CNT electrically connecting the vertical voltage line VVTL and the connection conductive pattern CP located between the third light-emitting areas EA3, which are spaced apart by the second distance D2. For example, as shown in FIG. 7, the contact hole CNT connecting the second-second data connection pattern DCP2b and the second-second data line DL2b and / or the contact hole CNT connecting the second voltage connection pattern VCPb and the second vertical voltage line VVTLb, which are located between the third light-emitting area EA3 of the third sub-pixel SP3c of the third pixel Pc and the third light-emitting area EA3 of the third sub-pixel SP3d of the fourth pixel Pd, may overlap the spacer SPC.

[0163] The spacers SPC may be disposed on the bank layer 130 described with reference to FIG. 4. The spacers SPC may include the same material as the bank layer (130, see FIG. 4). In this case, the bank layer (130, see FIG. 4) and the spacers SPC are formed together using a process using a halftone mask or the like, and the spacers SPC may have island shapes protruding at predetermined intervals in the z direction from the bank layer (130, see FIG. 4). In another embodiment, the spacers SPC may include a different material from the bank layer (130, see FIG. 4). In this case, the spacers SPC may be island-shaped insulating patterns arranged at predetermined intervals on top of the bank layer (130, see FIG. 4).

[0164] 8 is a plan view illustrating first to third pixel circuits PC1, PC2, and PC3 of a display device 1 according to an embodiment of the present invention. The first pixel circuit PC1, second pixel circuit PC2, and third pixel circuit PC3 illustrated in FIG. 8 may be electrically connected to first to third subpixels (SP1, SP2, SP3, see FIG. 6) of a pixel (P, see FIG. 6) arranged in the ith row and jth column, respectively. The first pixel circuit PC1, second pixel circuit PC2, and third pixel circuit PC3 may be arranged along a second direction.

[0165] 8, the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 may each include a plurality of transistors and capacitors. In some embodiments, FIG. 8 illustrates that the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 each include the eight transistors T1, T2, T3, T4, T5, T6, T7, and T8 and the first capacitor Cst described with reference to FIG.

[0166] The driving transistor T1 may overlap the first capacitor Cst. The switching transistors (e.g., T2, T3, T4, T5, T6, T7, and T8) may be arranged above and / or below the driving transistor T1 and / or the first capacitor Cst in a planar view. In one embodiment, FIG. 8 illustrates that the data write transistor T2, the compensation transistor T3, and the first initialization transistor T4 are arranged above (e.g., in the +y direction) the driving transistor T1 and / or the first capacitor Cst in a planar view. The operation control transistor T5, the light-emitting control transistor T6, the second initialization transistor T7, and the bias transistor T8 may be arranged below (e.g., in the -y direction) the driving transistor T1 and / or the first capacitor Cst in a planar view.

[0167] The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 are arranged along the second direction, and a first separation distance between the second pixel circuit PC2 and the third pixel circuit PC3 may be greater than a second separation distance between the first pixel circuit PC1 and the second pixel circuit PC2. A vertical voltage line VVTL may be disposed in a space (hereinafter referred to as a separation space, IVA) between the second pixel circuit PC2 and the third pixel circuit PC3, which are separated by the first separation distance. The vertical voltage line VVTL shown in FIG. 8 may be the first initialization vertical voltage line VVIL, the common voltage line VSL, the 2-1st initialization vertical voltage line VVAL(R), and / or the 2-2nd initialization vertical voltage line VVAL(GB) described with reference to FIGS. 5 and 6.

[0168] Figure 8 shows the first to third pixel electrodes (210a, 210b, 210c, see Figure 17) in areas corresponding to the first light-emitting region EA1 of the first organic light-emitting diode electrically connected to the first pixel circuit PC1, the second light-emitting region EA2 of the second organic light-emitting diode electrically connected to the second pixel circuit PC2, and the third light-emitting region EA3 of the third organic light-emitting diode electrically connected to the third pixel circuit PC3, and the bank layer 130 shown with reference to Figure 18 is omitted.

[0169] 9 to 18 are plan views showing steps of forming the first to third pixel circuits PC1, PC2, and PC3 shown in FIG.

[0170] Referring to FIG. 9, a lower metal layer BML may be disposed on a substrate (100, see FIG. 4). The lower metal layer BML may include main portions BMLc corresponding to the first to third pixel circuits PC1, PC2, and PC3, respectively. The lower metal layer BML may include first branch portions BMLa connecting the main portions BMLc along the second direction (e.g., ±x direction) and second branch portions BMLb connecting the main portions BMLc disposed in pixel circuits electrically connected to pixels disposed in different rows along the first direction (e.g., ±y direction). The main portions BMLc, the first branch portion BMLa, and the second branch portion BMLb may be connected together.

[0171] The lower metal layer BML is electrically connected to the driving voltage line (PL, see FIG. 4) and can have the same voltage level as the driving voltage line (PL, see FIG. 4).

[0172] The lower metal layer BML may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In some embodiments, the lower metal layer BML may be a single layer of molybdenum, a bilayer structure in which a molybdenum layer and a titanium layer are stacked, or a trilayer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked.

[0173] 9 and 10, a buffer layer (111, see FIG. 4) may be disposed on the lower metal layer BML, and a first semiconductor layer may be disposed on the buffer layer (111, see FIG. 4). The first semiconductor layer may include a first silicon semiconductor pattern 1110 and a second silicon semiconductor pattern 1120. The first silicon semiconductor pattern 1110 and the second silicon semiconductor pattern 1120 may be disposed on the same layer (e.g., the buffer layer 111).

[0174] The first silicon semiconductor patterns 1110 and the second silicon semiconductor patterns 1120 may be arranged corresponding to the first to third pixel circuits PC1, PC3, and PC3, respectively. The first silicon semiconductor patterns 1110 arranged in the first to third pixel circuits PC1, PC3, and PC3, respectively, may be separated and spaced apart from each other. The first silicon semiconductor patterns 1110 and the second silicon semiconductor patterns 1120 corresponding to the same pixel circuit may also be spaced apart from each other, but the present invention is not limited thereto. As another embodiment, the first silicon semiconductor patterns 1110 and the second silicon semiconductor patterns 1120 corresponding to the same pixel circuit may be connected together.

[0175] The first silicon semiconductor pattern 1110 may include a driving semiconductor layer A1 of the driving transistor (T1, see FIG. 8) described with reference to FIG. 8, a semiconductor layer of the data write transistor (T2, see FIG. 8) (hereinafter referred to as a data write semiconductor layer, A2), a semiconductor layer of the operation control transistor (T5, see FIG. 8) (hereinafter referred to as an operation control semiconductor layer, A5), a semiconductor layer of the light-emitting control transistor (T6, see FIG. 8) (hereinafter referred to as a light-emitting control semiconductor layer, A6), and a semiconductor layer of the second initialization transistor (T7, see FIG. 8) (hereinafter referred to as a second initialization semiconductor layer, A7). The second silicon semiconductor pattern 1120 may include a semiconductor layer of the bias transistor (T8, see FIG. 8) (hereinafter referred to as a bias semiconductor layer, A8).

[0176] The first silicon semiconductor pattern 1110 and the second silicon semiconductor pattern 1120 may include amorphous silicon or polysilicon. For example, the first silicon semiconductor pattern 1110 and the second silicon semiconductor pattern 1120 may include polysilicon crystallized at a low temperature.

[0177] 10 and 11, a first gate insulating layer (112, see FIG. 4) may be disposed on the first silicon semiconductor pattern 1110 and the second silicon semiconductor pattern 1120, and a first conductive layer (or first gate layer) may be disposed on the first gate insulating layer (112, see FIG. 4). The first conductive layer (or first gate layer) may include a first conductive pattern 1210, a second conductive pattern 1220, an emission control line EML, a second initialization control line GBL, and a 2-2nd initialization horizontal voltage line HVAL(GB). The first conductive pattern 1210, the second conductive pattern 1220, the emission control line EML, the second initialization control line GBL, and the 2-2nd initialization horizontal voltage line HVAL(GB) may be disposed on the same layer (e.g., the first gate insulating layer (112, see FIG. 4)).

[0178] The first conductive pattern 1210, the second conductive pattern 1220, the light emitting control line EML, the second initialization control line GBL, and the 2-2nd initialization horizontal voltage line HVAL(GB) may include the same material. The first conductive pattern 1210, the second conductive pattern 1220, the light emitting control line EML, the second initialization control line GBL, and the 2-2nd initialization horizontal voltage line HVAL(GB) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-mentioned materials.

[0179] The first conductive pattern 1210, the second conductive pattern 1220, the emission control line EML, and the second initialization control line GBL may each include a gate electrode overlapping the first silicon semiconductor pattern 1110 and / or the second silicon semiconductor pattern 1120.

[0180] The first conductive pattern 1210 may be disposed in each of the first to third pixel circuits PC1, PC2, and CP3 and may have an isolated shape. The first conductive pattern 1210 may include a driving gate electrode G1 of the driving transistor T1. The driving semiconductor layer A1 may include a channel region overlapping the first conductive pattern 1210, which is the driving gate electrode G1, and source and drain regions disposed on both sides of the channel region. Referring to FIGS. 9 and 10, the channel region of the driving semiconductor layer A1 may overlap a portion (e.g., a main portion, BMLc) of the lower metal layer BML. The channel region of the driving semiconductor layer A1 of each of the first and second pixel circuits (PC1 and PC2) may have a shape formed by multiple bends (e.g., an omega shape). In consideration of the efficiency of a third light emitting diode electrically connected to the third pixel circuit PC3, the channel region of the driving semiconductor layer A1 of the third pixel circuit PC3 may have a linear shape.

[0181] The fact that the separation distance between the second pixel circuit PC2 and the third pixel circuit PC3 is greater than the separation distance between the second pixel circuit PC2 and the first pixel circuit PC1 can be confirmed by the fact that the separation distance between the drive transistor T1 of the second pixel circuit PC2 and the drive transistor T1 of the third pixel circuit PC3 is greater than the separation distance between the drive transistor T1 of the second pixel circuit PC2 and the drive transistor T1 of the first pixel circuit PC1. For example, this can be confirmed by the fact that the first separation distance DS1 between the channel region of the drive transistor T1 of the second pixel circuit PC2 and the channel region of the drive transistor T1 of the third pixel circuit PC3, measured along the second direction (e.g., the ±x direction), is longer than the second separation distance DS2 between the channel region of the drive transistor T1 of the second pixel circuit PC2 and the channel region of the drive transistor T1 of the first pixel circuit PC1. In other words, this can be confirmed by the fact that the first separation distance DS1 between the drive gate electrode G1 of the drive transistor T1 of the second pixel circuit PC2 and the drive gate electrode G1 of the drive transistor T1 of the third pixel circuit PC3 measured along the second direction (e.g., the ±x direction) is longer than the second separation distance DS2 between the drive gate electrode G1 of the drive transistor T1 of the second pixel circuit PC2 and the drive gate electrode G1 of the drive transistor T1 of the first pixel circuit PC1.

[0182] In some embodiments, the first conductive pattern 1210 may include a bottom electrode CE1 of the first capacitor Cst, and may be the driving gate electrode G1 and / or the bottom electrode CE1 of the first capacitor Cst.

[0183] The second conductive patterns 1220 may be arranged in the first to third pixel circuits PC1, PC2, and CP3, respectively, and may have an isolated shape. The second conductive patterns 1220 may include the second gate electrode G2 of the data write transistor T2. The data write semiconductor layer a2 may include a channel region overlapping the second gate electrode G2 of the data write transistor T2, and source and drain regions arranged on both sides of the channel region.

[0184] The emission control line EML may extend along the second direction (e.g., ±x direction) to pass through the first to third pixel circuits PC1, PC2, and CP3. The emission control line EML may include an operation control gate electrode G5 of the operation control transistor T5 and an emission control gate electrode G6 of the emission control transistor T6. The operation control semiconductor layer A5 may include a channel region overlapping the operation control gate electrode G5, and source and drain regions disposed on both sides of the channel region. The emission control semiconductor layer A6 may include a channel region overlapping the emission control gate electrode G6, and source and drain regions disposed on both sides of the channel region.

[0185] The second initialization control line GBL may extend along a second direction (e.g., ±x direction) to pass through the first to third pixel circuits PC1, PC2, and CP3. The second initialization control line GBL may include a second initialization gate electrode G7 of the second initialization transistor T7 and a bias gate electrode G8 of the bias transistor T8. The second initialization semiconductor layer A7 may include a channel region overlapping the second initialization gate electrode G7, and source and drain regions disposed on both sides of the channel region. The bias semiconductor layer A8 may include a channel region overlapping the bias gate electrode G8, and source and drain regions disposed on both sides of the channel region.

[0186] 11 and 12, a second gate insulating layer (113, see FIG. 4) may be disposed on the first conductive pattern 1210, the second conductive pattern 1220, the emission control line EML, the second initialization control line GBL, and the 2-2 initialization horizontal voltage line HVAL (GB), and a second conductive layer may be disposed on the second gate insulating layer (113, see FIG. 4). The second conductive layer may include a third conductive pattern 1310, a fourth conductive pattern 1320, a fifth conductive pattern 1330, and a bridge pattern 1340. The third conductive pattern 1310, the fourth conductive pattern 1320, the fifth conductive pattern 1330, and the bridge pattern 1340 may be disposed on the same layer (e.g., the second gate insulating layer (113, see FIG. 4)).

[0187] The third conductive pattern 1310, the fourth conductive pattern 1320, the fifth conductive pattern 1330, and the bridge pattern 1340 may include the same material. The third conductive pattern 1310, the fourth conductive pattern 1320, the fifth conductive pattern 1330, and the bridge pattern 1340 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-mentioned materials.

[0188] The third conductive pattern 1310 may be disposed to overlap the first conductive pattern 1210. The third conductive pattern 1310 may be a horizontal driving voltage line having a voltage level of a driving voltage, and may extend along the second direction (e.g., ±x direction) to pass through the first to third pixel circuits PC1, PC2, and CP3.

[0189] In one embodiment, the third conductive pattern 1310 may include a first portion 1311 overlapping the first conductive pattern 1210 arranged in each of the first to third pixel circuits PC1, PC2, and PC3, and a second portion 1312 extending along the second direction (e.g., the x-direction) to connect the first portions 1311 arranged in each of the first to third pixel circuits PC1, PC2, and PC3.

[0190] The first conductive patterns 1210 arranged in the first to third pixel circuits PC1, PC2, and PC3 may correspond to the lower electrodes CE1 of the first capacitors Cst. The first portions 1311 of the third conductive patterns 1310 arranged in the first to third pixel circuits PC1, PC2, and PC3 may correspond to the upper electrodes CE2 of the first capacitors Cst.

[0191] 9 and 12, a first portion 1311 of the third conductive pattern 1310 may overlap a main portion BMLc of the lower metal layer BML, and a second portion 1312 of the third conductive pattern 1310 may overlap a first branch portion BMLa of the lower metal layer BML.

[0192] By arranging the third conductive pattern 1310 and the lower metal layer BML, which have the same voltage level, to overlap each other, coupling between the driving transistor T1 and its surrounding components (wiring or electrodes) can be prevented, and the transistors, voltage lines, and signal lines of the first to third pixel circuits PC1, PC2, and PC3 can be efficiently arranged in a limited space, thereby improving space efficiency (e.g., improving integration). The third conductive pattern 1310 may have an opening 1310OP in a closed state.

[0193] The fourth conductive pattern 1320 and the fifth conductive pattern 1330 may be disposed in the first to third pixel circuits PC1, PC2, and PC3, respectively. The fourth conductive pattern 1320 and the fifth conductive pattern 1330 may have an isolated shape.

[0194] The fourth conductive pattern 1320 may correspond to a lower compensation gate electrode G3a of a compensation transistor T3, which will be described later, and the fifth conductive pattern 1330 may correspond to a lower first initialization gate electrode G4a of a first initialization transistor T4, which will be described later.

[0195] The bridge pattern 1340 may be disposed in a separation space IVA between the second pixel circuit PC2 and the third pixel circuit PC3.

[0196] 12 and 13, a first interlayer insulating layer (114, see FIG. 4) may be disposed on the third conductive pattern 1310, the fourth conductive pattern 1320, the fifth conductive pattern 1330, and the bridge pattern 1340, and a second semiconductor layer may be disposed on the first interlayer insulating layer (114, see FIG. 4). The second semiconductor layer may include an oxide semiconductor pattern 1410.

[0197] The oxide semiconductor pattern 1410 may have a folded shape. For example, the oxide semiconductor pattern 1410 may include a portion corresponding to the compensation semiconductor layer A3 extending along the second direction (e.g., ±x direction) to overlap with the fourth conductive pattern 1320, and a portion corresponding to the first initialization semiconductor layer A4 extending along the first direction (e.g., ±y direction) to overlap with the fifth conductive pattern 1330.

[0198] The oxide semiconductor pattern 1410 may include an oxide semiconductor material. For example, the oxide semiconductor pattern 1410 may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the oxide semiconductor pattern 1410 may include ITZO (InSnZnO), IGZO (InGaZnO), etc. Oxide semiconductors have a wide band gap (approximately 3.1 eV), high carrier mobility, and low leakage current, so that voltage drop is not significant even with long operating times and brightness change due to voltage drop is not significant even with low-frequency operation.

[0199] 13 and 14, a third conductive layer may be disposed on the oxide semiconductor pattern 1410. The third conductive layer may include a sixth conductive pattern 1510, a seventh conductive pattern 1520, a repair line RL, and a 2-1 st initialization horizontal voltage line HVAL(R).

[0200] The sixth conductive pattern 1510, the seventh conductive pattern 1520, the repair line RL, and the 2-1st initialization horizontal voltage line HVAL(R) may include the same material. The sixth conductive pattern 1510, the seventh conductive pattern 1520, the repair line RL, and the 2-1st initialization horizontal voltage line HVAL(R) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-mentioned materials. In one embodiment, the sixth conductive pattern 1510, the seventh conductive pattern 1520, the repair line RL, and the 2-1 initialization horizontal voltage line HVAL(R) may have a three-layer structure of aluminum layer / titanium layer / aluminum layer.

[0201] The sixth conductive pattern 1510 and the seventh conductive pattern 1520 may be disposed in the first to third pixel circuits PC1, PC2, and PC3, respectively. The sixth conductive pattern 1510 and the seventh conductive pattern 1520 may have an isolated shape.

[0202] The sixth conductive pattern 1510 and the seventh conductive pattern 1520 may each include a gate electrode overlapping the oxide semiconductor pattern 1410. The sixth conductive pattern 1510 may include an upper compensation gate electrode G3b overlapping a portion of the oxide semiconductor pattern 1410, for example, the compensation semiconductor layer A3. The seventh conductive pattern 1520 may include an upper first initialization gate electrode G4b overlapping a portion of the oxide semiconductor pattern 1410, for example, the first initialization semiconductor layer A4.

[0203] The compensation semiconductor layer A3 disposed in each of the first to third pixel circuits PC1, PC2, and PC3 may include a channel region overlapping the fourth conductive pattern 1320 disposed below the compensation semiconductor layer A3 and the sixth conductive pattern 1510 disposed on the compensation semiconductor layer A3, and source and drain regions disposed on both sides of the channel region. The first initialization semiconductor layer A4 disposed in each of the first to third pixel circuits PC1, PC2, and PC3 may include a channel region overlapping the fifth conductive pattern 1330 disposed below the first initialization semiconductor layer A4 and the seventh conductive pattern 1520 disposed on the first initialization semiconductor layer A4, and source and drain regions disposed on both sides of the channel region.

[0204] The fourth conductive pattern 1320 and the sixth conductive pattern 1510 may correspond to the lower compensation gate electrode G3a and the upper compensation gate electrode G3b of the compensation transistor T3, respectively. The fifth conductive pattern 1330 and the seventh conductive pattern 1520 may correspond to the lower first initialization gate electrode G4a and the upper first initialization gate electrode G4b of the first initialization transistor T4, respectively.

[0205] 14 illustrates that the compensation transistor T3 includes a dual gate electrode of a lower compensation gate electrode G3a and an upper compensation gate electrode G3b, and that the first initialization transistor T4 includes a dual gate electrode of a lower first initialization gate electrode G4a and an upper first initialization gate electrode G4b, but the present invention is not limited thereto. In another embodiment, the compensation transistor T3 may include one of the lower compensation gate electrode G3a and the upper compensation gate electrode G3b, and one of the lower first initialization gate electrode G4a and the upper first initialization gate electrode G4b of the first initialization transistor T4.

[0206] The 2-1st initialization horizontal voltage line HVAL(R) may be arranged on the same layer as the sixth conductive pattern 1510 which is the gate electrode of the compensation transistor T3 (e.g., the upper compensation gate electrode G3b), the seventh conductive pattern 1520 which is the gate electrode of the first initialization transistor T4 (e.g., the upper first initialization gate electrode G4b), and the repair line RL. For example, the 2-1st initialization horizontal voltage line HVAL(R), the sixth conductive pattern 1510, the seventh conductive pattern 1520, and the repair line RL may each be arranged on the second gate insulating layer (115, see FIG. 4).

[0207] 4, the second gate insulating layers (115, see FIG. 4) disposed below the sixth conductive pattern 1510, the seventh conductive pattern 1520, the repair line RL, and the 2-1st initialization horizontal voltage line HVAL(R) may be separated from one another, but the present invention is not limited thereto. In another embodiment, the second gate insulating layers (115, see FIG. 4) disposed below the sixth conductive pattern 1510, the seventh conductive pattern 1520, the repair line RL, and the 2-1st initialization horizontal voltage line HVAL(R) may be integrally connected.

[0208] The 2-1st initialization horizontal voltage line HVAL(R) and the 2-2nd initialization horizontal voltage line HVAL(GB) may overlap each other. The 2-2nd initialization horizontal voltage line HVAL(GB) and the 2-1st initialization horizontal voltage line HVAL(R) may have a constant voltage level. For example, the 2-2nd initialization horizontal voltage line HVAL(GB) and the 2-1st initialization horizontal voltage line HVAL(R) may have the same or similar voltage levels. By overlapping the 2-2nd initialization horizontal voltage line HVAL(GB) and the 2-1st initialization horizontal voltage line HVAL(R) having the same or similar voltage levels, the 2-2nd initialization horizontal voltage line HVAL(GB) and the 2-1st initialization horizontal voltage line HVAL(R) can be arranged to minimize the occurrence of parasitic capacitance between the electrodes, voltage lines, and / or signal lines of the transistors of the first to third pixel circuits PC1, PC2, and PC3 in a limited space, and the space can be efficiently utilized (e.g., the integration density can be improved).

[0209] As shown in FIG. 14, each of the 2-1st initialization horizontal voltage line HVAL(R) and the 2-2nd initialization horizontal voltage line HVAL(GB) can cross the second branch portion BMLb of the lower metal layer BML in plan view.

[0210] 14 illustrates that the 2-1st initialization horizontal voltage line HVAL(R) is disposed on the same layer and includes the same material as the sixth conductive pattern 1510, which is the upper compensation gate electrode G3b of the compensation transistor T3, and / or the seventh conductive pattern 1520, which is the upper first initialization gate electrode G4b of the first initialization transistor T4, but the present invention is not limited thereto. In another embodiment, the 2-1st initialization horizontal voltage line HVAL(R) may be disposed on the same layer and include the same material as the fourth conductive pattern 1320, which is the lower compensation gate electrode G3a of the compensation transistor T3, and / or the fifth conductive pattern 1330, which is the lower first initialization gate electrode G4a of the first initialization transistor T4.

[0211] 14 and 15, a second interlayer insulating layer (116, see FIG. 4) may be disposed on the sixth conductive pattern 1510, the seventh conductive pattern 1520, the repair line RL, and the 2-1st initialization horizontal voltage line HVAL(R), and a fourth conductive layer (or a connection conductive layer) may be disposed on the second interlayer insulating layer (116, see FIG. 4). The fourth conductive layer may include a voltage transmission line 1610, a first pixel connecting electrode 1620, a first connecting electrode 1630, a second connecting electrode 1640, a third connecting electrode 1650, a fourth connecting electrode 1660, a fifth connecting electrode 1670, a sixth connecting electrode 1680, a first initialization horizontal voltage line HVIL, a first initialization control line GIL, a scan line GWL, a compensation scan line GCL, and a bias voltage line VOL. The voltage transmission wiring 1610, the first pixel connection electrode 1620, the first connection electrode 1630, the second connection electrode 1640, the third connection electrode 1650, the fourth connection electrode 1660, the fifth connection electrode 1670, the sixth connection electrode 1680, the first initialization horizontal voltage line HVIL, the first initialization control line GIL, the scan line GWL, the compensation scan line GCL, and the bias voltage line VOL may be arranged on the same layer (e.g., the second interlayer insulating layer (116, see FIG. 4)).

[0212] The voltage transmission line 1610, the first pixel connection electrode 1620, the first connection electrode 1630, the second connection electrode 1640, the third connection electrode 1650, the fourth connection electrode 1660, the fifth connection electrode 1670, the sixth connection electrode 1680, the first initialization horizontal voltage line HVIL, the first initialization control line GIL, the scan line GWL, the compensation scan line GCL, and the bias voltage line VOL may include the same material. The voltage transmission line 1610, the first pixel connecting electrode 1620, the first connecting electrode 1630, the second connecting electrode 1640, the third connecting electrode 1650, the fourth connecting electrode 1660, the fifth connecting electrode 1670, the sixth connecting electrode 1680, the first initialization horizontal voltage line HVIL, the first initialization control line GIL, the scan line GWL, the compensation scan line GCL, and the bias voltage line VOL may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0213] The voltage transmission line 1610 may extend in a second direction (for example, the ±x direction). The voltage transmission line 1610 passes through each of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3.

[0214] In one embodiment, the voltage transmission wiring 1610 may have a voltage level of a driving voltage (ELVDD, FIG. 3). In one embodiment, the voltage transmission wiring 1610 may be electrically connected to a driving voltage line PL, which will be described later, and may have a voltage level of the driving voltage (ELVDD, FIG. 3).

[0215] The voltage transmission wiring 1610 may be electrically connected to the lower metal layer (BML, see FIG. 9) through the first-1 contact hole CNT1a. The voltage transmission wiring 1610 may be electrically connected to the third conductive pattern (1310, see FIG. 14) through the first-2 contact hole CNT1b. The voltage transmission wiring 1610 may be electrically connected to the first silicon semiconductor pattern (1110, see FIG. 10) through the first-3 contact hole CNT1c. The lower metal layer (BML, see FIG. 9) may have a voltage level of the driving voltage ELVDD through the connection structure between the voltage transmission wiring 1610 and the lower metal layer (BML, see FIG. 9) through the first-1 contact hole CNT1a. The voltage transmission wiring 1610 can provide the driving voltage ELVDD to the upper electrode (CE2, see FIG. 14) of the first capacitor Cst and the operation control semiconductor layer (A5, see FIG. 10) of the operation control transistor T5 through the first-second contact hole CNT1b and the first-third contact hole CNT1c.

[0216] The first pixel connecting electrode 1620 may be spaced apart from the voltage transmission line 1610. The first pixel connecting electrode 1620 may be electrically insulated from the voltage transmission line 1610.

[0217] The first pixel connecting electrode 1620 may be arranged in the same layer as the voltage transmission line 1610. The first pixel connecting electrode 1620 may include a 1-1 pixel connecting electrode 1620a, a 1-2 pixel connecting electrode 1620b, and a 1-3 pixel connecting electrode 1620c arranged in the first to third pixel circuits PC1, PC2, and PC3, respectively. The 1-1 pixel connecting electrode 1620a, the 1-2 pixel connecting electrode 1620b, and the 1-3 pixel connecting electrode 1620c may be arranged apart from the voltage transmission line 1610.

[0218] The first pixel connecting electrode 1620 may be electrically connected to the first silicon semiconductor pattern 1110 through the second contact hole CNT2. For example, the 1-1 pixel connecting electrode 1620a may be electrically connected to the first silicon semiconductor pattern (1110, see FIG. 11) corresponding to the first pixel circuit PC1 through the second contact hole CNT2. The first pixel connecting electrode 1620 may be electrically connected to an emission control semiconductor layer (A6, see FIG. 11) of the emission control transistor (T6, see FIG. 11) formed along the first silicon semiconductor pattern 1110 and / or a second initialization semiconductor layer (A7, see FIG. 11) of the second initialization transistor T7.

[0219] The first connection electrode 1630, the second connection electrode 1640, the third connection electrode 1650, the fourth connection electrode 1660, and the fifth connection electrode 1670 may each have an isolated shape. The first connection electrode 1630, the second connection electrode 1640, the third connection electrode 1650, the fourth connection electrode 1660, and the fifth connection electrode 1670 may be disposed in the first to third pixel circuits PC1, PC2, and PC3, respectively.

[0220] The first connection electrode 1630 may electrically connect the first conductive pattern (1210, see FIG. 11) and the oxide semiconductor pattern (1410, see FIG. 13). The first connection electrode 1630 may be electrically connected to the first conductive pattern (1210, see FIG. 11) through the 3-1 contact hole CNT3a. The first connection electrode 1630 may be electrically connected to the oxide semiconductor pattern (1410, for example, the compensation semiconductor layer A3 of the compensation transistor T3, see FIG. 13) through the 3-2 contact hole CNT3b. The first connection electrode 1630 may electrically connect the driving gate electrode (G1, see FIG. 11) of the driving transistor T1 and the compensation semiconductor layer (A3, see FIG. 13) of the compensation transistor T3. The first connection electrode 1630 may electrically connect the first capacitor Cst and the compensation transistor T3.

[0221] The first connection electrode 1630 may overlap a portion of the lower metal layer (BML, see FIG. 9), for example, the second branch portion BMLb.

[0222] The second connection electrode 1640 may electrically connect the first silicon semiconductor pattern (1110, see FIG. 11) and the oxide semiconductor pattern (1410, see FIG. 14). The second connection electrode 1640 may be electrically connected to the first silicon semiconductor pattern (1110, see FIG. 11) through the 4-1 contact hole CNT4a. The second connection electrode 1640 may be electrically connected to the oxide semiconductor pattern (1410, see FIG. 14) through the 4-2 contact hole CNT4b. The second connection electrode 1640 may electrically connect the driving semiconductor layer (A1, see FIG. 11) of the driving transistor T1 and the compensation semiconductor layer (A3, see FIG. 14) of the compensation transistor T3. The second connection electrode 1640 may electrically connect the emission control semiconductor layer (A6, see FIG. 11) of the emission control transistor T6 and the compensation semiconductor layer (A3, see FIG. 14) of the compensation transistor T3.

[0223] The third connection electrode 1650 may be electrically connected to the first silicon semiconductor pattern (1110, see FIG. 11) through the fifth contact hole CNT5. For example, the third connection electrode 1650 corresponding to the first pixel circuit PC1 may be electrically connected to the first data line DL1, which will be described later with reference to FIG. 16. That is, the third connection electrode 1650 corresponding to the first pixel circuit PC1 may transmit a data signal applied to the first data line DL1 to the data write semiconductor layer (A2, see FIG. 11) of the data write transistor T2. For example, the third connection electrode 1650 corresponding to the second pixel circuit PC2 may be electrically connected to the second data line DL2, which will be described later with reference to FIG. 16. For example, the third connection electrode 1650 corresponding to the third pixel circuit PC3 may be electrically connected to the third data line DL3, which will be described later with reference to FIG. 16. The third connection electrode 1650 may correspond to the data connection pattern DCP described with reference to FIGS. 6 and 7. For example, the third connection electrode 1650 electrically connected to the first data line DL1 is also referred to as the first data connection pattern, the third connection electrode 1650 electrically connected to the second data line DL2 is also referred to as the second data connection pattern, and the third connection electrode 1650 electrically connected to the third data line DL3 is also referred to as the third data connection pattern.

[0224] The fourth connection electrode 1660 may electrically connect the first silicon semiconductor pattern (1110, see FIG. 11) and the second silicon semiconductor pattern (1120, see FIG. 11). The fourth connection electrode 1660 may be electrically connected to the first silicon semiconductor pattern (1110, see FIG. 11) through the 6-1 contact hole CNT6a. The fourth connection electrode 1660 may be electrically connected to the second silicon semiconductor pattern (1120, see FIG. 11) through the 6-2 contact hole CNT6b. The fourth connection electrode 1660 may electrically connect the operation control semiconductor layer (A5, see FIG. 11) of the operation control transistor T5 formed along the first silicon semiconductor pattern (1110, see FIG. 11) and the bias semiconductor layer (A8, see FIG. 11) of the bias transistor T8 formed along the second silicon semiconductor pattern (1120, see FIG. 11).

[0225] The fifth connection electrode 1670 corresponding to the first pixel circuit PC1 may electrically connect the first silicon semiconductor pattern (1110, see FIG. 11) corresponding to the first pixel circuit PC1 and the 2-1st initialization horizontal voltage line HVAL(R). The fifth connection electrode 1670 corresponding to the first pixel circuit PC1 may electrically connect the second initialization semiconductor layer (A7, see FIG. 11) of the second initialization transistor T7 formed along the first silicon semiconductor pattern (1110, see FIG. 11) and the 2-1st initialization horizontal voltage line HVAL(R).

[0226] The fifth connecting electrode 1670 corresponding to the first pixel circuit PC1 may be electrically connected to the second initialization semiconductor layer (A7, see FIG. 11) of the second initialization transistor T7 corresponding to the first pixel circuit PC1 through the 7-1 contact hole CNT7a and may be electrically connected to the 2-1 initialization horizontal voltage line HVAL(R) through the 7-2 contact hole CNT7b. The 2-1 initialization horizontal voltage line HVAL(R) may transmit the 2-1 initialization voltage to the second initialization transistor T7 of the first pixel circuit PC1 through the fifth connecting electrode 1670.

[0227] The fifth connecting electrode 1670 corresponding to the second pixel circuit PC2 and the third pixel circuit PC3, respectively, can electrically connect the first silicon semiconductor pattern (1110, see FIG. 11) and the 2-2 initialization horizontal voltage line HVAL(GB) corresponding to the second pixel circuit PC2 and the third pixel circuit PC3, respectively. The fifth connecting electrode 1670 corresponding to the second pixel circuit PC2 and the third pixel circuit PC3, respectively, can electrically connect the second initialization semiconductor layer (A7, see FIG. 11) of the second initialization transistor T7 and the 2-2 initialization horizontal voltage line HVAL(GB) corresponding to the second pixel circuit PC2 and the third pixel circuit PC3, respectively.

[0228] The fifth connection electrodes 1670 corresponding to the second pixel circuit PC2 and the third pixel circuit PC3 are electrically connected to the second initialization semiconductor layers (A7, see FIG. 9) of the second initialization transistors T7 corresponding to the second pixel circuit PC2 and the third pixel circuit PC3, respectively, through the 7-1 contact holes CNT7a. The fifth connection electrodes 1670 corresponding to the second pixel circuit PC2 and the third pixel circuit PC3, respectively, may be electrically connected to the 2-2 initialization horizontal voltage line HVAL(GB) through the 7-2 contact holes CNT7b. The 2-2 initialization horizontal voltage line HVAL(GB) may transmit the 2-2 initialization voltage to the second initialization transistors (T7, see FIG. 11) corresponding to the second pixel circuit PC2 and the third pixel circuit PC3, respectively, through the fifth connection electrodes 1670 disposed in the second pixel circuit PC2 and the third pixel circuit PC3, respectively. In some embodiments, the 2-1 initialization voltage and the 2-2 initialization voltage may have the same voltage level.

[0229] The sixth connection electrode 1680 may have an isolated shape. At least a portion of the sixth connection electrode 1680 may be disposed in the isolation space IVA in which the vertical voltage line (VVTL, see FIG. 8) is disposed. The sixth connection electrode 1680 may correspond to the voltage connection pattern VCP described with reference to FIGS. 6 and 7. The sixth connection electrode 1680 may be electrically connected to the vertical voltage line (VVTL, see FIG. 8). In one embodiment, the sixth connection electrode 1680 may be electrically connected to the bridge pattern (1340, see FIG. 12) through a contact hole CNT_VC2.

[0230] The first initialization control line GIL, the scan line GWL, the compensation scan line GCL, the bias voltage line VOL, and the first initialization horizontal voltage line HVIL may extend in a second direction (eg, ±x direction).

[0231] The first initialization control line GIL may be electrically connected to the fifth conductive pattern (1330, see FIG. 14) and the seventh conductive pattern (1520, see FIG. 14) of each of the first to third pixel circuits PC1, PC2, and PC3. The first initialization control line GIL may be electrically connected to the fifth conductive pattern (1330, see FIG. 14) of each of the first to third pixel circuits PC1, PC2, and PC3 through the 8-1 contact hole CNT8a. The first initialization control line GIL may be electrically connected to the seventh conductive pattern (1520, see FIG. 14) of each of the first to third pixel circuits PC1, PC2, and PC3 through the 8-2 contact hole CNT8b. The first initialization control line GIL can provide a first initialization control signal (GI, see FIG. 3) to each of the fifth conductive pattern (1330, see FIG. 14) which is the lower first initialization gate electrode G4a of the first initialization transistor T4 and the seventh conductive pattern (1520, see FIG. 14) which is the upper first initialization gate electrode G4b.

[0232] The scan line GWL may be electrically connected to the second conductive pattern (1220, see FIG. 11) of each of the first to third pixel circuits PC1, PC2, and PC3 through the ninth contact hole (CNT9). The scan line GWL may provide a scan signal (GW, see FIG. 3) to the second conductive pattern (1220, see FIG. 11), which is the second gate electrode (G2, see FIG. 11) of the data write transistor T2 of each of the first to third pixel circuits PC1, PC2, and PC3.

[0233] The compensation scan line GCL may be electrically connected to the fourth conductive pattern (1320, see FIG. 14) and the sixth conductive pattern (1510, see FIG. 14) of each of the first to third pixel circuits PC1, PC2, and PC3. The compensation scan line GCL may be electrically connected to the fourth conductive pattern (1320, see FIG. 14) of each of the first to third pixel circuits PC1, PC2, and PC3 through the 10-1 contact hole CNT10a. The compensation scan line GCL may be electrically connected to the sixth conductive pattern (1510, see FIG. 14) of each of the first to third pixel circuits PC1, PC2, and PC3 through the 10-2 contact hole CNT10b. The compensation scan line GCL may provide a compensation scan signal (GC, see FIG. 3) to the fourth conductive pattern (1320, see FIG. 12), which is the lower compensation gate electrode G3a of the compensation transistor T3, and the sixth conductive pattern 1510, which is the upper compensation gate electrode G3b.

[0234] The bias voltage line VOL may be electrically connected to the second silicon semiconductor pattern (1120, see FIG. 11) of each of the first to third pixel circuits PC1, PC2, and PC3 through the eleventh contact hole CNT11. The bias voltage line VOL may provide a bias voltage (Vobs, see FIG. 3) to the bias semiconductor layer (A8, see FIG. 11) of the bias transistor T8 of each of the first to third pixel circuits PC1, PC2, and PC3.

[0235] The first initialization horizontal voltage line HVIL may be electrically connected to the oxide semiconductor patterns (1410, FIG. 13) of the first to third pixel circuits PC1, PC2, and PC3 through the twelfth contact holes CNT12. That is, the first initialization voltage (Vint, see FIG. 3) may be provided to the first initialization transistor T4 formed along the oxide semiconductor patterns (1410, FIG. 13).

[0236] 15 and 16, a first via insulating layer (121, see FIG. 4) may be disposed on the voltage transmission line 1610, the first pixel connecting electrode 1620, the first connecting electrode 1630, the second connecting electrode 1640, the third connecting electrode 1650, the fourth connecting electrode 1660, the fifth connecting electrode 1670, the sixth connecting electrode 1680, the first initialization horizontal voltage line HVIL, the first initialization control line GIL, the scan line GWL, the compensation scan line GCL, and the bias voltage line VOL, and a fifth conductive layer (or vertical conductive layer) may be disposed on the first via insulating layer (121, see FIG. 4). The fifth conductive layer may include the second pixel connecting electrode 1710, the driving voltage line PL, the first data line DL1, the second data line DL2, the third data line DL3, and the vertical voltage line VVTL. The second pixel connecting electrode 1710, the driving voltage line PL, the first data line DL1, the second data line DL2, the third data line DL3, and the vertical voltage line VVTL may be disposed on the same layer (for example, the first via insulating layer 121).

[0237] The driving voltage line PL, the first data line DL1, the second data line DL2, the third data line DL3, and the vertical voltage line VVTL extend along a first direction (e.g., the ±y direction). The driving voltage line PL, the first data line DL1, the second data line DL2, the third data line DL3, the vertical voltage line VVTL, and the second pixel connecting electrode 1710 may include the same material.

[0238] The driving voltage line PL, the first data line DL1, the second data line DL2, the third data line DL3, the vertical voltage line VVTL, and the second pixel connecting electrode 1710 may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0239] The driving voltage lines PL may be disposed in the first to third pixel circuits PC1, PC2, and PC3, respectively. The driving voltage line PL corresponding to any one of the first to third pixel circuits PC1, PC2, and PC3 may be electrically connected to a voltage transmission line (1610, see FIG. 15) through a fourteenth contact hole CNT14. The shapes and areas of the driving voltage lines PL disposed in the first to third pixel circuits PC1, PC2, and PC3 are different from each other.

[0240] The driving voltage line PL disposed in each of the first to third pixel circuits PC1, PC2, and PC3 may overlap the gate electrodes of the compensation transistors T3 of the first to third pixel circuits PC1, PC2, and PC3, for example, the lower compensation gate electrode G3a and the upper compensation gate electrode G3b in FIG. 14, and may also overlap the first connection electrode 1630 corresponding to each of the first to third pixel circuits PC1, PC2, and PC3. Here, the first connection electrode 1630 may connect the compensation semiconductor layer A3 of the compensation transistor T3 to the driving gate electrode G1 of the driving transistor T1. This overlapping structure may prevent unwanted parasitic capacitance from affecting the compensation transistor T3 and the first connection electrode 1630. As shown in FIG. 16, in a plan view, the first connection electrode 1630 overlaps the second branch portion BMLb of the lower metal layer (BML, see FIG. 9) and the driving voltage line PL, which have the same constant voltage level (e.g., the driving voltage ELVDD level). This may more effectively prevent the occurrence of the parasitic capacitance.

[0241] The first data line DL1, the second data line DL2, and the third data line DL3 may be electrically connected to the data write transistors (T2, see FIG. 11) of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3, respectively. The first to third data lines DL1, DL2, and DL3 may transmit data signals (Dm, see FIG. 3) to the first to third pixel circuits PC1, PC2, and PC3, respectively.

[0242] The first data line DL1 may be electrically connected to the third connection electrode (1650, see FIG. 15) corresponding to the first pixel circuit PC1 through the first data contact hole DCNT1. Similarly, the second data line DL2 may be electrically connected to the third connection electrode 1650 corresponding to the second pixel circuit PC2 through the second data contact hole DCNT2, and the third data line DL3 may be electrically connected to the third connection electrode 1650 corresponding to the third pixel circuit PC3 through the third data contact hole DCNT3. The third connection electrode 1650 corresponding to each of the first to third pixel circuits PC1, PC2, and PC3 is electrically connected to the first silicon semiconductor pattern (1110, see FIG. 10) of the corresponding pixel circuit, and thus can provide a data signal (Dm, see FIG. 3) to the data write transistor T2 formed along the first silicon semiconductor pattern (1110, see FIG. 10).

[0243] The shapes of the first data line DL1, the second data line DL2, and the third data line DL3 may be different from each other in a plan view. For example, the first data line DL1 and the second data line DL2 may have different planar shapes when passing through the region corresponding to the second pixel circuit PC2. For example, the first data line DL1 and the second data line DL2 may be asymmetric about an imaginary line extending in the first direction (e.g., the ±y direction) between the first data line DL1 and the second data line DL2. The planar shape of the third data line DL3 may be different from the planar shapes of the first data line DL1 and the second data line DL2.

[0244] The first data line DL1, the second data line DL2, and the third data line DL3 can cross the 2-1st initialization horizontal voltage line HVAL(R) and the 2-2nd initialization horizontal voltage line HVAL(GB) in plan view.

[0245] The vertical voltage line VVTL may be disposed in the separation space IVA between the second pixel circuit PC2 and the third pixel circuit PC3. For example, the vertical voltage line VVTL may be disposed between the second data line DL2 and the driving voltage line PL of the third pixel circuit PC3.

[0246] The vertical voltage line VVTL may be electrically connected to voltage lines extending in the second direction (e.g., ±x direction). In one embodiment, Figure 16 illustrates a state in which the vertical voltage line VVTL is connected to the sixth connection electrode 1680 through a contact hole CNT_VC1, the sixth connection electrode 1680 is connected to the bridge pattern 1340 disposed directly below through a contact hole CNT_VC2, and the bridge pattern 1340 is electrically connected to the first initialization horizontal voltage line HVIL through a contact hole CNT_VC3. That is, the vertical voltage line VVTL illustrated in Figure 16 may be the first initialization vertical voltage line (VVIL, see Figure 5).

[0247] The second pixel connecting electrode 1710 may be electrically connected to the first pixel connecting electrode (1620, see FIG. 15). For example, the 2-1 pixel connecting electrode 1710a may be electrically connected to the 1-1 pixel connecting electrode (1620a, see FIG. 15) through the 13-1 contact hole CNT13a. For example, the 2-2 pixel connecting electrode 1710b may be electrically connected to the 1-2 pixel connecting electrode (1620b, see FIG. 15) through the 13-2 contact hole CNT13b. For example, the 2-3 pixel connecting electrode 1710c may be electrically connected to the 1-3 pixel connecting electrode (1620c, see FIG. 15) through the 13-3 contact hole CNT13c.

[0248] As shown in region "A," in a plan view, the first data contact hole DCNT1, the second data contact hole DCNT2, and the third data contact hole DCNT3 may be arranged in a line along the second direction (e.g., the ±x direction). Also, in a plan view, the first data contact hole DCNT1, the second data contact hole DCNT2, and the third data contact hole DCNT3 may be arranged in a line along the second direction (e.g., the ±x direction) together with the contact hole CNT_VC1 that electrically connects the vertical voltage line VVTL and the sixth connection electrode 1680. For example, the first data contact hole DCNT1, the second data contact hole DCNT2, the third data contact hole DCNT3, and the contact hole CNT_VC1 that electrically connects the vertical voltage line VVTL and the sixth connection electrode 1680 may be arranged on an imaginary straight line LL extending along the second direction (e.g., the ±x direction).

[0249] 16 and 17, a second via insulating layer (123, see FIG. 4) may be disposed on the second pixel connecting electrode 1710, the driving voltage line PL, the first data line DL1, the second data line DL2, the third data line DL3, and the vertical voltage line VVTL, and the first to third pixel electrodes 210a, 210b, and 210c may be disposed on the second via insulating layer (123, see FIG. 4).

[0250] A first pixel electrode 210a electrically connected to the first pixel circuit PC1, a second pixel electrode 210b electrically connected to the second pixel circuit PC2, and a third pixel electrode 210c electrically connected to the third pixel circuit PC3 may be spaced apart from each other. In one embodiment, the first pixel electrode 210a and the second pixel electrode 210b may be arranged in the same column along a first direction (e.g., the y direction) and may be arranged alternately. The third pixel electrode 210c may be arranged in a column adjacent to the column in which the first pixel electrode 210a and the second pixel electrode 210b are arranged.

[0251] The pixel electrodes may be electrically connected to the first to third pixel circuits PC1, PC2, and PC3, respectively, via the second pixel connecting electrode (1710, see FIG. 16) and the first pixel connecting electrode (1620, see FIG. 15). The first pixel electrode 210a may be connected to the 2-1 pixel connecting electrode (1710a, see FIG. 16) via the 16-1 contact hole CNT16a, and the 2-1 pixel connecting electrode 1710a may be electrically connected to the 1-1 pixel connecting electrode (1620a, see FIG. 15) via the 13-1 contact hole (CNT13a, see FIG. 16). The second pixel electrode 210b may be electrically connected to the 2-2 pixel connecting electrode (1710b, see FIG. 16) through the 16-2 contact hole CNT16b, and the 2-2 pixel connecting electrode 1710b may be electrically connected to the 1-2 pixel connecting electrode (1620b, see FIG. 15) through the 13-2 contact hole (CNT13b, see FIG. 16). The third pixel electrode 210c may be electrically connected to the 2-3 pixel connecting electrode (1710c, see FIG. 16) through the 16-3 contact hole CNT16c, and the 2-3 pixel connecting electrode 1710c may be electrically connected to the 1-3 pixel connecting electrode (1620c, see FIG. 15) through the 13-3 contact hole (CNT13c, see FIG. 16).

[0252] 17 and 18, a bank layer 130 may be disposed on the first to third pixel electrodes 210a, 210b, and 210c. A pixel opening 130OP defined in the bank layer 130 may expose portions of the first to third pixel electrodes 210a, 210b, and 210c. For example, the bank layer 130 may include a first pixel opening 130OP1 that covers an edge of the first pixel electrode 210a and exposes a portion of the first pixel electrode 210a. For example, the bank layer 130 may include a second pixel opening 130OP2 that covers an edge of the second pixel electrode 210b and exposes a portion of the second pixel electrode 210b. For example, the bank layer 130 may include a third pixel opening 130OP3 that covers an edge of the third pixel electrode 210c and exposes a portion of the third pixel electrode 210c. The first pixel opening 130OP1, the second pixel opening 130OP2, and the third pixel opening 130OP3 can respectively define a first light-emitting area EA1 of the first light-emitting diode, a second light-emitting area EA2 of the second light-emitting diode, and a third light-emitting area EA3 of the third light-emitting diode.

[0253] The bank layer 130 increases the distance between the edge of the first pixel electrode 210a and the opposing electrode (230, see Figure 4), the distance between the edge of the second pixel electrode (210b, see Figure 4) and the opposing electrode (230, see Figure 4), and the distance between the third pixel electrode 210c and the opposing electrode (230, see Figure 4), thereby preventing arcs and the like from occurring at the edges of the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c.

[0254] 8 and 18, the contact hole CNT_VC1 and the second data contact hole DCNT2 electrically connecting the vertical voltage line VVTL and the sixth connection electrode (1680, see FIG. 15) are located between adjacent third light-emitting regions EA3, and the first data contact hole DCNT1, the second data contact hole DCNT2, the third data contact hole DCNT3, and the contact hole CNT_VC1 electrically connecting the vertical voltage line VVTL and the sixth connection electrode (1680, see FIG. 15) may be arranged in a line along the second direction (e.g., ±x direction). For example, the first data contact hole DCNT1, the second data contact hole DCNT2, the third data contact hole DCNT3, and the contact hole CNT_VC1 electrically connecting the vertical voltage line VVTL and the sixth connection electrode (1680, see FIG. 15) may be located between adjacent third light-emitting regions EA3 and on an imaginary straight line LL extending along the second direction (e.g., ±x direction).

[0255] 16 and 18, in a plan view, the 13-1 contact hole CNT13a, which connects the 2-1 pixel connecting electrode 1710a and the 1-1 pixel connecting electrode (1620a, see FIG. 15) and penetrates the first via insulating layer (121, see FIG. 4), may be separated from the pixel opening 130OP (e.g., the light-emitting region). Similarly, the 13-2 contact hole CNT13b and the 13-3 contact hole CNT13c may be separated from the pixel opening 130OP (e.g., the light-emitting region) in a plan view. In addition, the 14 contact hole CNT14, which connects the driving voltage line PL and the voltage transmission line (1610, see FIG. 15) and penetrates the first via insulating layer (121, see FIG. 4), may be separated from the pixel opening 130OP (e.g., the light-emitting region).

[0256] In an embodiment of the present invention, the contact hole penetrating the first via insulating layer 121 may be separated from the light emitting region in a plan view.

[0257] Hereinafter, the same reference numerals as those used above will be used to omit redundant explanations.

[0258] FIG. 19 is a cross-sectional view taken along line II' in FIG.

[0259] Referring to Figures 8 to 19, the contact holes that connect the first to third pixel electrodes 210a, 210b, 210c to the vertical voltage lines VVTL arranged in the layer that is closest to them in the direction toward the top surface of the substrate 100 (e.g., the -z direction) and the connecting conductive pattern (CP, see Figure 6) arranged below the vertical voltage lines VVTL and that penetrate the first via insulating layer 121 overlap the bank layer 130 but do not overlap the pixel opening 130OP (or the light-emitting area EA) of the bank layer 130.

[0260] 19, the first initialization vertical voltage line VVIL, which is the vertical voltage line VVTL arranged in the layer closest to the third pixel electrode 210c in the direction toward the top surface of the substrate 100, is connected to a sixth connection electrode 1680 corresponding to a connection conductive pattern (CP, see FIG. 6) by a contact hole CNT_VC1 penetrating the first via insulating layer 121. The contact hole CNT_VC1 overlaps the bank layer 130 but does not overlap the third pixel opening OP3 (or the third light-emitting region EA3). That is, the contact hole CNT_VC1 may be separated from the third light-emitting region EA3 in a plan view.

[0261] FIG. 19 illustrates the first initialization vertical voltage line VVIL of the vertical voltage lines VVTL as an example, but the 2-1 initialization vertical voltage line VVAL(R), the 2-2 initialization vertical voltage line VVAL(GB), and the common voltage line VSL are also connected to the connection conductive pattern (CP, see FIG. 6) by a contact hole penetrating the first via insulating layer 121, and the contact hole penetrating the first via insulating layer 121 overlaps the bank layer 130 but does not overlap the pixel opening 130OP (or the light-emitting area EA).

[0262] According to one embodiment of the present invention, the light emitting area (EA, see FIG. 4) of the light emitting diode (LED, see FIG. 4) does not overlap with the contact hole penetrating the first via insulating layer 121, so that the second via insulating layer 123 does not curve and can provide a substantially flat upper surface in the overlapping area of ​​the pixel opening 130OP. As a result, the first to third pixel electrodes 210a, 210b, 210c disposed on the second via insulating layer 123 are formed substantially flat, and color shift or image quality shift due to the viewing angle of the display device (1, see FIG. 1) can be reduced or prevented.

[0263] In one embodiment, the vertical voltage line VVTL arranged in the layer closest to the first to third pixel electrodes 210a, 210b, and 210c in a direction toward the top surface of the substrate 100 (e.g., the -z direction) is arranged on the first via insulating layer 121, and the through-hole penetrating the first via insulating layer 121 does not overlap with the light-emitting area (EA, see FIG. 4), but this is not limited thereto. In another embodiment, the display device (1, see FIG. 1) further includes a sixth conductive layer on the second via insulating layer 123 and a third via insulating layer on the sixth conductive layer, and when the first to third pixel electrodes 210a, 210b, and 210c are arranged on the third via insulating layer, the conductive pattern of the sixth conductive layer and the conductive layer arranged below the sixth conductive layer are electrically connected, and the contact hole penetrating the second via insulating layer 123 does not overlap with the light-emitting area, similar to the contact hole penetrating the first via insulating layer 121 described herein.

[0264] Figures 20A and 20B are cross-sectional views taken along line II-II' in Figure 18. Figures 20A and 20B show separators SEP according to different embodiments.

[0265] 18 and 20A , in one embodiment, the bank layer 130 defines auxiliary openings OPs surrounding a portion of the first pixel opening 130OP1, a portion of the second pixel opening 130OP2, and a portion of a pair of adjacent third pixel openings 130OP3. In this case, the auxiliary openings OPs may function as separators SEP. The auxiliary openings OPs may be spaced apart from the first pixel opening 130OP1, the second pixel opening 130OP2, and the third pixel opening 130OP3. As shown in FIG. 20A , the side surfaces of the auxiliary openings OPs may have an inverse tapered shape. That is, the side surfaces of the bank layer 130 defining the auxiliary openings OPs may have an undercut structure.

[0266] Common layers integrally formed corresponding to a plurality of light-emitting diodes (LEDs, see FIG. 4), such as the first functional layer 221, the second functional layer 223, and the counter electrode 230, may be separated by separators SEP or may have discontinuous portions that are thinner than the surrounding regions. For example, the first functional layer 221, the second functional layer 223, and the counter electrode 230 disposed on the upper surface of the bank layer 130 may be separated and spaced apart from the dummy layer dm disposed in the auxiliary openings OPs. However, because the separators SEP do not completely surround each of the first pixel opening 130OP1, the second pixel opening 130OP2, and the third pixel opening 130OP3, the counter electrodes 230 may be integrally formed and connected to each other in the display area (DA, see FIG. 1).

[0267] 18 and 20B, a separator SEP may be disposed on the bank layer 130. In an embodiment, the separator SEP may be formed of the same material as the bank layer 130, but is not limited to such. In another embodiment, the separator SEP may be formed of a different material from the bank layer 130. The separator SEP may have an inverted tapered shape. The separator SEP may include a separator surrounding a portion of the first pixel opening 130OP1, a separator surrounding a portion of the second pixel opening 130OP2, and a separator surrounding a pair of adjacent third pixel openings 130OP3. A dummy layer dm formed by separating the first functional layer 221, the second functional layer 223, and the counter electrode 230 may be disposed between the separators SEP surrounding adjacent pixel openings. In an embodiment, a dummy layer dm may be disposed on the upper surface of the separator SEP.

[0268] 21 is a plan view showing a portion of the electrical connection of four adjacent pixels according to an embodiment of the present invention. Fig. 21 shows a portion of the electrical connection of four pixels arranged in the i-th row, the (i+1)-th row, the (j+2)-th column, and the (j+3)-th column. Fig. 21 shows the electrical connection between the 2-1st initialization horizontal voltage line HVAL(R) and the 2-1st initialization vertical voltage line VVAL(R) and the electrical connection between the 2-2nd initialization horizontal voltage line HVAL(GB) and the 2-2nd initialization vertical voltage line VVAL(GB) of a display device 1 according to an embodiment of the present invention.

[0269] Referring to Figure 21, in the (j+2)th column, the distance between adjacent third light-emitting regions EA3 in the first direction is smaller than the distance between adjacent third light-emitting regions EA3 in the (j+3)th column, which is the column adjacent to the (j+2)th column.

[0270] The 2-1 initialization horizontal voltage line HVAL(R) passes through the first to third pixel circuits PC1, PC2, and PC3 arranged in the (i)th row, but may be electrically connected to the 2-1 initialization vertical voltage line VVAL(R) which passes through the separation space IVA between the second pixel circuit PC2 and the third pixel circuit PC3 arranged in the (j+2)th column.

[0271] The 2-1st initialization horizontal voltage line HVAL(R) may include a bridge portion HVAL(R)-B extending toward the (i+1)th row along a first direction (e.g., ±y direction). The bridge portion HVAL(R)-B may be integrally formed using the same material as the 2-1st initialization horizontal voltage line HVAL(R). The bridge portion HVAL(R)-B may be located in a separation space IVA between the second pixel circuit PC2 and the third pixel circuit PC3 arranged in the (i+1)th row and the (j+2)th column, respectively.

[0272] The 2-1st initialization vertical voltage line VVAL(R) may be electrically connected to the bridge portion HVAL(R)-B of the 2-1st initialization horizontal voltage line HVAL(R). For example, the 2-1st initialization vertical voltage line VVAL(R) and the bridge portion HVAL(R)-B of the 2-1st initialization horizontal voltage line HVAL(R) may be electrically connected to each other through a first connecting conductive pattern 1680a overlapping a portion of the bridge portion HVAL(R)-B of the 2-1st initialization horizontal voltage line HVAL(R) and a portion of the 2-1st initialization vertical voltage line VVAL(R) in the separation space IVA. For example, the 2-1st initialization vertical voltage line VVAL(R) may be connected to the first connecting conductive pattern 1680a through a contact hole CNT-VA1a, and the first connecting conductive pattern 1680a may be connected to the bridge portion HVAL(R)-B through a contact hole CNT-VA2a.

[0273] The 2-2 initialization horizontal voltage line HVAL(GB) passes through the first to third pixel circuits PC1, PC2, and PC3 arranged in the (i)th row, but can be electrically connected to the 2-2 initialization vertical voltage line VVAL(GB) which passes through the separation space IVA between the second pixel circuit PC2 and the third pixel circuit PC3 arranged in the (j+3)th column.

[0274] The 2-2nd initialization horizontal voltage line HVAL(GB) may include a bridge portion HVAL(GB)-B extending toward the (i+1)th row along the first direction (e.g., the ±y direction). The bridge portion HVAL(GB)-B may be integrally formed using the same material as the 2-2nd initialization horizontal voltage line HVAL(GB). The bridge portion HVAL(GB)-B may be located in a separation space IVA between the second pixel circuit PC2 and the third pixel circuit PC3 arranged in the (i+1)th row and the (j+3)th column, respectively.

[0275] The second-second initialization vertical voltage line VVAL(GB) may be electrically connected to the bridge portion HVAL(GB)-B of the second-second initialization horizontal voltage line HVAL(GB). For example, the second-second initialization vertical voltage line VVAL(GB) and the bridge portion HVAL(GB)-B of the second-second initialization horizontal voltage line HVAL(GB) may be electrically connected to each other through a second connecting conductive pattern 1680b overlapping a portion of the bridge portion HVAL(GB)-B of the second-second initialization horizontal voltage line HVAL(GB) and a portion of the second-second initialization vertical voltage line VVAL(GB) in the separation space IVA. For example, the second-second initialization vertical voltage line VVAL(GB) may be connected to the second connecting conductive pattern 1680b through a contact hole CNT-VA1b, and the second connecting conductive pattern 1680b may be connected to the bridge portion HVAL(GB)-B through a contact hole CNT-VA2b.

[0276] The first to third data lines DL1, DL2, and DL3 arranged in the (j+2)th column may be electrically connected to the third connection electrode (or data connection pattern) 1650 through data contact holes DCNT1a, DCNT2a, and DCNT3a, respectively. The first to third data lines DL1, DL2, and DL3 arranged in the (j+3)th column may be electrically connected to the third connection electrode (or data connection pattern) 1650 through data contact holes DCNT1b, DCNT2b, and DCNT3b, respectively.

[0277] As shown in region “B,” in plan view, data contact holes DCNT1a, DCNT2a, and DCNT3a located in the (j+2)th column and data contact holes DCNT1b, DCNT2b, and DCNT3b located in the (j+3)th column may be aligned in a line along the second direction (e.g., ±x direction). Contact hole CNT-VA1a electrically connecting the 2-1st initialization vertical voltage line VVAL(R) to the first voltage connection pattern 1680a and contact hole CNT-VA1b electrically connecting the 2-2nd initialization vertical voltage line VVAL(GB) to the second voltage connection pattern 1680b may be aligned in a line along the second direction (e.g., ±x direction). In addition, in plan view, the data contact holes DCNT1a, DCNT2a, DCNT3a located in the (j+2)th column and the contact hole CNT-VA1a electrically connecting the 2-1st initialization vertical voltage line VVAL(R) to the first voltage connection pattern 1680a may be arranged in a line along the second direction (e.g., ±x direction). In addition, in plan view, the data contact holes DCNT1b, DCNT2b, DCNT3b located in the (j+3)th column and the contact hole CNT-VA1b electrically connecting the 2-2nd initialization vertical voltage line VVAL(GB) to the second voltage connection pattern 1680b may be arranged in a line along the second direction (e.g., ±x direction).

[0278] FIG. 21 shows that the 2-1 initialization vertical voltage line VVAL(R) and the 2-2 initialization vertical voltage line VVAL(GB) are arranged in two adjacent columns, respectively, but this is merely an example, and the types of vertical voltage lines in the two adjacent columns may be changed.

[0279] While the present invention has been described above based on one embodiment shown in the drawings, it will be understood that this is merely an example, and that various modifications and variations of the embodiment are possible by those skilled in the art. Therefore, the true technical scope of protection of the present invention should be determined by the technical spirit of the claims. [Explanation of symbols]

[0280] GWL Scanline GCL Compensation Scan Line GIL First initialization control line GBL Second initialization control line EML Light Emission Control Line HVTL Horizontal Voltage Line VVTL Vertical Voltage Line HVIL First initialization horizontal voltage line HVAL Second initialization horizontal voltage line HVAL(R) 2nd-1st Initialization Horizontal Voltage Line HVAL(GB) 2nd-2nd initialization horizontal voltage line VVIL First initialization vertical voltage line VVAL Second initialization vertical voltage line VVAL(G) 2nd-1st initialization vertical voltage line VVAL(RB) 2nd-2nd initialization vertical voltage line CP connection conductive pattern VCP voltage connection pattern DCP Data Connection Pattern

Claims

1. a plurality of pixels including a first pixel, a second pixel adjacent to the first pixel in a first direction, a third pixel adjacent to the first pixel in a second direction perpendicular to the first direction, and a fourth pixel adjacent to the third pixel in the first direction and adjacent to the second pixel in the second direction, wherein each of the first to fourth pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors; a first data line extending in the first direction and transmitting a data voltage to the second sub-pixel of the first pixel and the second sub-pixel of the second pixel; a second data line extending in the first direction and transmitting a data voltage to the second sub-pixel of the third pixel and the second sub-pixel of the fourth pixel; a first data connection pattern electrically connected to the first data line through a first contact hole and electrically connected to the second sub-pixel of the second pixel; a second data connection pattern electrically connected to the second data line through a second contact hole and electrically connected to the second sub-pixel of the fourth pixel; a distance between a light-emitting region of the third subpixel of the first pixel and a light-emitting region of the third subpixel of the second pixel is smaller than a distance between a light-emitting region of the third subpixel of the third pixel and a light-emitting region of the third subpixel of the fourth pixel in a plan view; the first contact hole is located between the light-emitting region of the third sub-pixel of the first pixel and the light-emitting region of the third sub-pixel of the second pixel in a plan view; In a plan view, the first contact holes and the second contact holes are arranged in a line along the second direction.

2. The display device according to claim 1 , wherein the first contact hole is spaced apart from the light-emitting region of the third sub-pixel of the first pixel and the light-emitting region of the third sub-pixel of the second pixel in a plan view.

3. 2 . The display device according to claim 1 , wherein, in a plan view, the second contact hole is located between the light-emitting region of the third sub-pixel of the third pixel and the light-emitting region of the third sub-pixel of the fourth pixel.

4. a third data line extending in the first direction and transmitting a data voltage to the first sub-pixel of the first pixel and the first sub-pixel of the second pixel; a third data connection pattern electrically connected to the third data line through a third contact hole and electrically connected to the first sub-pixel of the second pixel; The display device according to claim 1 , wherein, in a plan view, the third contact holes are arranged in a line with the first contact holes and the second contact holes along the second direction.

5. a fourth data line extending in the first direction and transmitting a data voltage to the third sub-pixel of the first pixel and the third sub-pixel of the second pixel; a fourth data connection pattern electrically connected to the fourth data line through a fourth contact hole and electrically connected to the third sub-pixel of the second pixel; The display device according to claim 4 , wherein, in a plan view, the fourth contact hole is arranged in a line with the first contact hole, the second contact hole, and the third contact hole along the second direction.

6. a first vertical voltage line extending in the first direction and transmitting a first voltage, which is a constant voltage, to each of the first pixel, the second pixel, the third pixel, and the fourth pixel; a first voltage connection pattern electrically connected to the first vertical voltage line through a fifth contact hole; The display device according to claim 1 , wherein, in a plan view, the fifth contact hole is arranged in a line with the first contact hole and the second contact hole along the second direction.

7. a second vertical voltage line extending in the first direction and transmitting a second voltage, which is a constant voltage, to each of the first pixel, the second pixel, the third pixel, and the fourth pixel; a second voltage connection pattern electrically connected to the second vertical voltage line through a sixth contact hole; The display device according to claim 6 , wherein, in a plan view, the sixth contact hole is arranged in a line with the first contact hole, the second contact hole, and the fifth contact hole along the second direction.

8. 8. The display device according to claim 7, wherein, in a plan view, the fifth contact hole is located between the light-emitting region of the third sub-pixel of the first pixel and the light-emitting region of the third sub-pixel of the second pixel, and the sixth contact hole is located between the light-emitting region of the third sub-pixel of the third pixel and the light-emitting region of the third sub-pixel of the fourth pixel.

9. The display device of claim 7 , wherein the first data line, the second data line, the first vertical voltage line, and the second vertical voltage line are arranged on the same layer.

10. The display device of claim 7 , wherein the first data connection pattern, the second data connection pattern, the first voltage connection pattern, and the second voltage connection pattern are disposed on the same layer.

11. The display device of claim 7 , further comprising a first horizontal voltage line extending in the second direction and electrically connected to the first voltage connection pattern.

12. The display device of claim 11 , further comprising a second horizontal voltage line disposed on a different layer from the first horizontal voltage line, extending in the second direction, and electrically connected to the second voltage connection pattern.

13. further comprising a plurality of separators; 2 . The display device according to claim 1 , wherein one separator of the plurality of separators surrounds the light-emitting region of the third subpixel of the first pixel and the light-emitting region of the third subpixel of the second pixel in a plan view.

14. The display device of claim 1 , wherein the third subpixel emits blue light.

15. The display device of claim 1 , wherein an area of ​​the light-emitting region of the third subpixel is larger than an area of ​​the light-emitting region of the first subpixel and an area of ​​the light-emitting region of the second subpixel.

16. a plurality of pixels each including a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors; a data line extending in a first direction and transmitting a data voltage to at least one pixel among the plurality of pixels; a first vertical voltage line extending in the first direction and transmitting a first voltage, which is a constant voltage, to the plurality of pixels; a data connection pattern electrically connected to the data line through a first contact hole; a first voltage connection pattern electrically connected to the first vertical voltage line through a second contact hole; In a plan view, the first contact holes and the second contact holes are arranged in a line along a second direction perpendicular to the first direction.

17. the plurality of pixels include a first pixel, a second pixel adjacent to the first pixel in a first direction, a third pixel adjacent to the first pixel in a second direction perpendicular to the first direction, and a fourth pixel adjacent to the third pixel in the first direction and adjacent to the second pixel in the second direction, a distance between a light-emitting region of the third subpixel of the first pixel and a light-emitting region of the third subpixel of the second pixel is smaller than a distance between a light-emitting region of the third subpixel of the third pixel and a light-emitting region of the third subpixel of the fourth pixel in a plan view; 17 . The display device according to claim 16 , wherein, in a plan view, the second contact hole is located between the light-emitting region of the third sub-pixel of the first pixel and the light-emitting region of the third sub-pixel of the second pixel.

18. a second vertical voltage line extending in the first direction and transmitting a second voltage, which is a constant voltage, to the plurality of pixels; a second voltage connection pattern electrically connected to the second vertical voltage line through a third contact hole, The display device according to claim 17 , wherein, in a plan view, the third contact holes are arranged in a line with the first contact holes and the second contact holes along the second direction.

19. 19 . The display device according to claim 18 , wherein, in a plan view, the third contact hole is located between the light-emitting region of the third sub-pixel of the third pixel and the light-emitting region of the third sub-pixel of the fourth pixel.

20. The display device of claim 18 , further comprising a first horizontal voltage line extending in the second direction and electrically connected to the first voltage connection pattern.

21. 21. The display device of claim 20, further comprising a second horizontal voltage line disposed on a different layer from the first horizontal voltage line, extending in the second direction, and electrically connected to the second voltage connection pattern.

22. The display device of claim 18 , wherein the third subpixel emits blue light.

23. a substrate including a display area and a peripheral area disposed outside the display area; a plurality of pixels arranged in the display region, each of which includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, each of which emits light of a different color; a first semiconductor layer disposed on the substrate and including a silicon semiconductor; a first conductive layer disposed on the first semiconductor layer; a second conductive layer disposed on the first conductive layer; a second semiconductor layer disposed on the second conductive layer and including an oxide semiconductor; a third conductive layer disposed on the second semiconductor layer; a fourth conductive layer disposed on the third conductive layer and including a plurality of connecting conductive patterns; a fifth conductive layer disposed on the fourth conductive layer, the fifth conductive layer including a plurality of vertical conductive lines electrically connected to the plurality of connecting conductive patterns, each extending in a first direction; a via insulating layer disposed between the fourth conductive layer and the fifth conductive layer, in which a plurality of contact holes are defined that electrically connect the plurality of connecting conductive patterns and the plurality of vertical conductive lines, respectively; In a plan view, the plurality of contact holes of the via insulating layer are separated from the light-emitting regions of the first to third sub-pixels.

24. the plurality of pixels include a first pixel, a second pixel adjacent to the first pixel in a first direction, a third pixel adjacent to the first pixel in a second direction perpendicular to the first direction, and a fourth pixel adjacent to the third pixel in the first direction and adjacent to the second pixel in the second direction, a distance between a light-emitting region of the third subpixel of the first pixel and a light-emitting region of the third subpixel of the second pixel is smaller than a distance between a light-emitting region of the third subpixel of the third pixel and a light-emitting region of the third subpixel of the fourth pixel in a plan view; 24. The display device according to claim 23, wherein, in a plan view, a first contact hole among the plurality of contact holes is located between the light-emitting region of the third sub-pixel of the first pixel and the light-emitting region of the third sub-pixel of the second pixel.

25. 25. The display device according to claim 24, wherein, in a plan view, a second contact hole among the plurality of contact holes is located between the light-emitting region of the third sub-pixel of the first pixel and the light-emitting region of the third sub-pixel of the second pixel.

26. The display device of claim 25, wherein the first contact holes and the second contact holes are arranged in a line along the second direction.

27. a plurality of pixels including a first pixel, a second pixel adjacent to the first pixel in a first direction, a third pixel adjacent to the first pixel in a second direction perpendicular to the first direction, and a fourth pixel adjacent to the third pixel in the first direction and adjacent to the second pixel in the second direction, wherein the first to fourth pixels each include a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors; a first data line extending in the first direction and transmitting a data voltage to the second sub-pixel of the first pixel and the second sub-pixel of the second pixel; a second data line extending in the first direction and transmitting a data voltage to the second sub-pixel of the third pixel and the second sub-pixel of the fourth pixel; a first data connection pattern electrically connected to the first data line through a first contact hole and electrically connected to the second sub-pixel of the second pixel; a second data connection pattern electrically connected to the second data line through a second contact hole and electrically connected to the second sub-pixel of the fourth pixel; a distance between a light-emitting region of the third subpixel of the first pixel and a light-emitting region of the third subpixel of the second pixel is smaller than a distance between a light-emitting region of the third subpixel of the third pixel and a light-emitting region of the third subpixel of the fourth pixel in a plan view; the first contact hole is located between the light-emitting region of the third sub-pixel of the first pixel and the light-emitting region of the third sub-pixel of the second pixel in a plan view; An electronic device including a display device, wherein, in a plan view, the first contact holes and the second contact holes are arranged in a line along the second direction.

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