Display device

Abstract

To provide a display device having a large area that can provide a uniform driving voltage to pixels.SOLUTION: A display device comprises: a detection line disposed in a non-display area; a first power supply line connected to pixels to provide a first driving voltage; and a second power supply line that provides a second driving voltage to the pixels. The detection line includes: extension lines spaced apart from each other by a display area; a bridge line connected to the first power supply line; and connection lines connecting one of the extension lines and one end of the bridge line as well as another one of the extension lines and another end of the bridge line. The second power supply line intersects the connection lines in a plan view.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to a display device, and more particularly to a display device with improved display quality. [Background technology]

[0002] Generally, electronic devices that provide images to users, such as smartphones, digital cameras, laptops, navigation systems, and smart televisions, include a display device for displaying the images. The display device generates images and provides the generated images to users via a display screen.

[0003] The display device includes a plurality of pixels for generating an image and a plurality of lines connected to the pixels, and the pixels are driven by receiving driving signals through the lines.

[0004] In large-sized display devices with large screens, such as tablets and smart TVs, there may be a difference between the driving voltage provided from the bottom and the driving voltage transmitted to the top, and a design to compensate for this difference is required. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device that can provide a uniform driving voltage to pixels in a large-area display device. [Means for solving the problem]

[0006] a first line disposed in the display area and connected to the pixels, a second line connected to the first line and disposed in the non-display area; a second power line provided with a second driving voltage lower than the first driving voltage; and detection lines disposed in the non-display area and surrounding at least a portion of the display area, the detection lines each extending in the second direction and including extension lines spaced apart along the first direction with the display area therebetween; bridge lines extending in the first direction and connected to the first power line; and connecting lines connecting one end of one of the extension lines to one end of the bridge line and another of the extension lines to the other end of the bridge line, the second lines intersecting the connecting lines in a plane.

[0007] The extension line may be farther away from the display area than the second line, and the bridge line may be closer to the display area than the second line.

[0008] Each of the extension lines may include a sensing pattern and a power pattern disposed on and connected to the sensing pattern.

[0009] The display device may further include an outer dam disposed in the non-display area and surrounding at least a portion of the display area, and an inner dam disposed between the outer dam and the display area, wherein the outer dam includes first to fourth dam patterns sequentially stacked on the insulating layer, and the inner dam includes fifth and sixth dam patterns sequentially stacked on the insulating layer.

[0010] The sensing pattern may be covered by the first dam pattern, the power supply pattern may be disposed on the first dam pattern and covered by the second dam pattern, and the power supply pattern may be connected to the sensing pattern through at least one contact hole penetrating the first dam pattern.

[0011] The sensing pattern and the power supply pattern may each include first to third conductive patterns stacked in sequence, the first and third conductive patterns may include titanium, the second conductive pattern may include aluminum, and a side surface of the second conductive pattern may be recessed inward relative to a side surface of each of the first and third conductive patterns.

[0012] The first and second dam patterns may include an organic material, the first dam pattern may cover a side surface of each of the first to third conductive patterns of the sensing pattern, and the second dam pattern may cover a side surface of each of the conductive patterns of the power supply pattern.

[0013] The second line may extend from the inside of the inner dam to the inside of the outer dam, and the second line may include a first pattern including the same material as the sensing pattern and a second pattern including the same material as the power supply pattern.

[0014] The first pattern and the second pattern may be in contact with each other inside the inner dam and may be spaced apart from each other inside the outer dam with the first dam pattern therebetween.

[0015] Each of the pixels may include an anode, a cathode disposed on the anode, and an emitting layer disposed between the anode and the cathode, and the cathode may extend into the non-display area and contact the second pattern.

[0016] Each of the pixels may include a lower metal layer disposed on the substrate, a first semiconductor layer overlapping the lower metal layer, a first gate electrode overlapping the first semiconductor layer, a dummy electrode overlapping the first gate electrode, a second semiconductor layer separated from the first semiconductor layer, and a second gate electrode overlapping the second semiconductor layer, and may further include a first connecting electrode connected to the first semiconductor layer, and a second connecting electrode connecting the first connecting electrode to the anode.

[0017] the insulating layers may include a buffer layer disposed on the substrate and covering the lower metal layer; a first insulating layer disposed on the buffer layer and covering the first semiconductor layer; a second insulating layer disposed on the first insulating layer and covering the first gate electrode; a third insulating layer disposed on the second insulating layer and covering the dummy electrode; a fourth insulating layer disposed on the third insulating layer and covering the second semiconductor layer; a fifth insulating layer disposed on the fourth insulating layer and covering the second gate electrode; a sixth insulating layer disposed on the fifth insulating layer and covering the first connecting electrode, the sixth insulating layer including an organic material; and a seventh insulating layer disposed on the sixth insulating layer and covering the second connecting electrode, the seventh insulating layer including an organic material. The first connecting electrode may be connected to the first semiconductor layer through a first contact hole penetrating the first to fifth insulating layers, the second connecting electrode may be connected to the first connecting electrode through a second contact hole penetrating the sixth insulating layer, and the anode may be connected to the second connecting electrode through a third contact hole penetrating the seventh insulating layer.

[0018] The pixel defining layer may further include a pixel defining layer including an organic material, the pixel defining layer being disposed on the seventh insulating layer and defining a first opening exposing at least a portion of each of the anodes, and a spacer including an organic material, the pixel defining layer being disposed on the pixel defining layer and defining a second opening overlapping the first opening.

[0019] The first dam pattern may include the same material as the sixth insulating layer, the second dam pattern may include the same material as the seventh insulating layer, the third dam pattern and the fifth dam pattern may include the same material as the pixel defining layer, and the fourth dam pattern and the sixth dam pattern may include the same material as the spacer.

[0020] The sensing pattern may include the same material as the first connecting electrode, and the power supply pattern may include the same material as the second connecting electrode.

[0021] The connection line may be disposed on the first insulating layer and covered by the second insulating layer, and may include the same material as the first gate electrode, and the power supply pattern may be connected to the connection line through a contact hole penetrating the second to fifth insulating layers.

[0022] The bridge line may be disposed on the first insulating layer and covered by the second insulating layer, and the connecting line and the bridge line may be an integral pattern.

[0023] The bridge line may be disposed on the second insulating layer, covered by the third insulating layer, and may include the same material as the dummy electrode, and may be connected to the connection line through a contact hole penetrating the second insulating layer.

[0024] The bridge line may be disposed on the fourth insulating layer, covered by the fifth insulating layer, and may include the same material as the second gate electrode, and may be connected to the connection line through a contact hole penetrating the second to fourth insulating layers.

[0025] The bridge line may be disposed on the first insulating layer, covered by the second insulating layer, and made of the same material as the first gate electrode; the connection line may be disposed on the second insulating layer, covered by the third insulating layer, and made of the same material as the dummy electrode; the power supply pattern may be connected to one end of the bridge line through a first contact hole penetrating the third to fifth insulating layers, and the other end of the connection line may be connected to the bridge line through a second contact hole penetrating the second insulating layer.

[0026] The bridge line may be disposed on the first insulating layer, covered by the second insulating layer, and made of the same material as the first gate electrode; the connection line may be disposed on the fourth insulating layer, covered by the fifth insulating layer, and made of the same material as the second gate electrode; the power supply pattern may be connected to one end of the connection line through a first contact hole penetrating the fifth insulating layer, and the other end of the connection line may be connected to the bridge line through a second contact hole penetrating the second and third insulating layers.

[0027] The second line may have a width greater than the width of the extension line on a plane. [Effects of the Invention]

[0028] According to an embodiment of the present invention, a constant driving voltage can be provided regardless of the size / area of ​​the display region, thereby providing a display device with improved reliability. [Brief explanation of the drawings]

[0029] [Figure 1] 1 is a perspective view of a display device according to an embodiment of the present invention; [Figure 2] 2 is a diagram illustrating an example of a cross section of the display device shown in FIG. [Figure 3] 3 is a diagram illustrating an example of a cross section of the display panel shown in FIG. 2. FIG. [Figure 4]FIG. 2 is a block diagram of the display device shown in FIG. [Figure 5] FIG. 5 is a diagram showing an equivalent circuit of one of the pixels shown in FIG. [Figure 6] 6 is a timing chart of a scanning signal and a light emitting signal for explaining the operation of the pixel shown in FIG. 5. FIG. [Figure 7] 6 is a diagram illustrating an example of a cross section of a light emitting element, a first transistor, a fourth transistor, and a sixth transistor of the pixel illustrated in FIG. 5. FIG. [Figure 8] 1 is a plan view of a display panel according to an embodiment of the present invention; [Figure 9] FIG. 9 is a cross-sectional view taken along II' in FIG. 8. [Figure 10] FIG. 9 is a cross-sectional view taken along line II-II' in FIG. 8. [Figure 11] FIG. 9 is a cross-sectional view taken along the line III-III' in FIG. 8. [Figure 12] FIG. 12 is a cross-sectional view of the area corresponding to FIG. 11. [Figure 13] FIG. 12 is a cross-sectional view of the area corresponding to FIG. 11. [Figure 14] FIG. 12 is a cross-sectional view of the area corresponding to FIG. 11. [Figure 15] FIG. 12 is a cross-sectional view of the area corresponding to FIG. 11. [Figure 16] FIG. 12 is a cross-sectional view of the area corresponding to FIG. 11. [Figure 17] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0030] As used herein, when a component (or region, layer, portion, etc.) is referred to as being "on," "connected," or "coupled" to another component, it means that it may be directly disposed on, coupled, or connected to the other component, or that a third component may be disposed therebetween.

[0031] The same reference numerals refer to the same elements. In the drawings, the thickness, proportions, and dimensions of the elements are exaggerated for the purpose of effectively explaining the technical content. "And / or" includes all combinations of one or more elements defined by the associated elements.

[0032] Terms such as "first," "second," etc. are used to describe various components, but the components are not limited to these terms. These terms are used only to distinguish one component from another. For example, a first component may be designated as a "second component," and similarly, a second component may be designated as a "first component" without departing from the scope of the present invention. A singular expression includes a plural expression unless the context clearly dictates otherwise.

[0033] Furthermore, terms such as "under," "below," "on," and "above" are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0034] It should be understood that the terms "comprise" or "have" and the like specify the presence of any feature, number, step, operation, component, part, or combination thereof set forth above in the specification, but do not preclude the presence or possible addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the present invention belongs. Furthermore, terms that are the same as those defined in commonly used dictionaries should be interpreted to have a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted in an overly ideal or formal sense unless explicitly defined herein.

[0036] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0037] FIG. 1 is a perspective view of a display device according to one embodiment of the present invention.

[0038] 1, a display device DD according to an embodiment of the present invention may have long sides extending parallel to a first direction DR1 and short sides extending parallel to a second direction DR2 intersecting the first direction DR1. Corners of the display device DD connecting the long and short sides may be curved. Corners of the display device DD having a curved shape may be defined as rounded corners. The shape of such a display device DD may be defined as a rounded rectangle.

[0039] Hereinafter, a direction substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In addition, in this specification, the meaning of when viewed from a plane is defined as a state viewed from the third direction DR3.

[0040] The front surface of the display device DD may be defined as a display surface DS, which may have a plane defined by a first direction DR1 and a second direction DR2. An image IM generated by the display device DD may be presented to a user via the display surface DS.

[0041] The display surface DS includes a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image, while the non-display area NDA may not display an image. The non-display area NDA may surround the display area DA and define a frame for the display device DD that is printed in a predetermined color.

[0042] The display area DA may have a rectangular shape with rounded corners depending on the shape of the display device DD. For example, the display area DA may include rectangular sides extending in a first direction DR1 and a second direction DR2, and rounded corners connecting the sides. The four sides extending in the first direction DR1 may be defined as long sides, and the four sides extending in the second direction DR2 may be defined as short sides.

[0043] The display device DD can sense inputs applied from outside the display device DD. For example, the display device DD can sense a first input by a touch pen PEN and a second input by a touch TC. The touch pen PEN can be defined as an input device.

[0044] The touch pen PEN may be an active pen that outputs a signal. The second input by the touch TC may include various forms of external input such as a part of the user's body, light, heat, or pressure.

[0045] The display device DD and the touch pen PEN can communicate bidirectionally. The display device DD can provide an upward signal to the touch pen PEN. For example, the upward signal can include, but is not limited to, information such as panel information and protocol version.

[0046] The touch pen PEN may provide a downward signal to the display device DD. The downward signal may include a synchronization signal or status information of the touch pen PEN. For example, the downward signal may include, but is not limited to, coordinate information of the touch pen PEN, battery information of the touch pen PEN, gradient information of the touch pen PEN, and / or various information stored in the touch pen PEN.

[0047] The display device DD may be used in large electronic devices such as televisions, monitors, or external advertising boards. The display device DD may also be used in small to medium-sized devices such as personal computers, laptops, personal digital assistants, car navigation systems, game consoles, smartphones, tablets, or cameras. However, these are merely exemplary embodiments, and the display device DD may also be used in other electronic devices without departing from the concept of the present invention.

[0048] FIG. 2 is a diagram illustrating an example of a cross section of the display device shown in FIG.

[0049] For example, FIG. 2 shows a cross section of the display device DD as viewed in a second direction DR2.

[0050] Referring to FIG. 2, the display device DD may include a display panel DP, an input sensing ISP, an anti-reflection layer RPL, a window WIN, a panel protection film PPF, and first and second adhesive layers AL1 and AL2.

[0051] According to an embodiment of the present invention, the display panel DP may be an emissive display panel. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of an inorganic light-emitting display panel may include quantum dots, quantum rods, or the like. Hereinafter, the display panel DP will be referred to as an organic light-emitting display panel.

[0052] The input sensing unit ISP may be disposed on the display panel DP. The input sensing unit ISP may include a plurality of sensing units (not shown) for sensing external inputs using a capacitive method. The input sensing unit ISP may be directly manufactured on the display panel DP when manufacturing the display device DD. However, the input sensing unit ISP is not limited thereto, and may be manufactured as a separate panel from the display panel DP and attached to the display panel DP by an adhesive layer.

[0053] The anti-reflection layer RPL may be disposed on the input sensing unit ISP. The anti-reflection layer RPL may be directly manufactured on the input sensing unit ISP when manufacturing the display device DD. However, the anti-reflection layer RPL is not limited thereto, and may be manufactured as a separate display panel and attached to the input sensing unit ISP by an adhesive layer.

[0054] The anti-reflection layer RPL can be defined as an external light anti-reflection film. The anti-reflection layer RPL can reduce the reflectance of external light incident from above the display device DD toward the display panel DP. The anti-reflection layer RPL may prevent the external light from being visible to the user.

[0055] If external light traveling toward the display panel DP is reflected by the display panel DP and provided to an external user, the user may view the external light as if it were a mirror. To prevent this phenomenon, for example, the anti-reflection layer RPL may include a plurality of color filters that display the same colors as the pixels of the display panel DP.

[0056] The color filter may filter external light to the same color as the pixel. In such a case, the external light may not be visible to the user. However, the anti-reflection layer RPL may include a retarder and / or a polarizer to reduce the reflectance of external light.

[0057] The window WIN may be disposed on the anti-reflection layer RPL, and may protect the display panel DP, the input sensing unit ISP, and the anti-reflection layer RPL from external scratches and impacts.

[0058] The panel protection film PPF may be disposed below the display panel DP. The panel protection film PPF may protect the lower part of the display panel DP. The panel protection film PPF may include a flexible plastic material such as polyethylene terephthalate (PET).

[0059] The first adhesive layer AL1 is disposed between the display panel DP and the panel protective film PPF, and the first adhesive layer AL1 bonds the display panel DP and the panel protective film PPF together. The second adhesive layer AL2 is disposed between the window WIN and the anti-reflection layer RPL, and the second adhesive layer AL2 bonds the window WIN and the anti-reflection layer RPL together.

[0060] FIG. 3 is a diagram illustrating an example of a cross section of the display panel shown in FIG.

[0061] For example, FIG. 3 shows a cross section of the display panel DP as viewed from the second direction DR2.

[0062] Referring to Figure 3, the display panel DP may include a substrate SUB, a circuit element layer DP-CL arranged on the substrate SUB, a display element layer DP-OLED arranged on the circuit element layer DP-CL, and a thin-film encapsulation layer TFE arranged on the display element layer DP-OLED.

[0063] The substrate SUB may include a display area DA and a non-display area NDA surrounding the display area DA. The substrate SUB may include glass or a flexible plastic material such as polyimide (PI). The display element layer DP-OLED may be disposed on the display area DA.

[0064] A plurality of pixels may be disposed on the circuit element layer DP-CL and the display element layer DP-OLED, and each pixel may include a transistor disposed on the circuit element layer DP-CL and a light-emitting element disposed on the display element layer DP-OLED and connected to the transistor.

[0065] The thin film encapsulation layer TFE may be disposed on the circuit element layer DP-CL so as to cover the display element layer DP-OLED, and protects the pixels from moisture, oxygen, and external foreign substances.

[0066] FIG. 4 is a block diagram of the display device shown in FIG.

[0067] Referring to FIG. 4, the display device DD may include a display panel DP, a timing controller TC, a scan driver SDV, a data driver DDV, an emission driver EDV, and a voltage generator VG.

[0068] The display panel DP may include a plurality of scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm, a plurality of light emitting lines EML1 to EMLm, a plurality of data lines DL1 to DLn, and a plurality of pixels PX, where m and n are natural numbers.

[0069] The pixels PX may be electrically connected to the scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm, the light emitting lines EML1 to EMLm, and the data lines DL1 to DLn, respectively. Each pixel PX may be electrically connected to four corresponding scan lines, one corresponding data line, and one corresponding light emitting line.

[0070] The scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm may include a plurality of initialization scan lines GIL1 to GILm, a plurality of compensation scan lines GCL1 to GCLm, a plurality of write scan lines GWL1 to GWLm, and a plurality of bias scan lines GBL1 to GBLm.

[0071] Each of the pixels PX may be connected to a corresponding one of the initialization scan lines GIL1 to GILm, a corresponding one of the compensation scan lines GCL1 to GCLm, a corresponding one of the write scan lines GWL1 to GWLm, and a corresponding one of the bias scan lines GBL1 to GBLm.

[0072] The scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm are connected to the scan driver SDV, extended in a first direction DR1, and arranged in a second direction DR2. The light emitting lines EML1 to EMLm are connected to the light emitting driver EDV, extended in the first direction DR1, and arranged in the second direction DR2. The data lines DL1 to DLn are connected to the data driver DDV, extended in the second direction DR2, and arranged in the first direction DR1.

[0073] The scan driver SDV, the light emitting driver EDV, and the data driver DDV may be substantially arranged on the display panel DP, and such a configuration is illustrated in FIG. 8 below.

[0074] The timing controller TC receives the video signal RGB and the control signal CTRL. The timing controller TC converts the data format of the video signal RGB to conform to the interface specifications with the data driver DDV and generates a video data signal DAS. The timing controller TC outputs a scan control signal SCS, a data control signal DCS, and a light emission control signal ECS in response to the control signal CTRL.

[0075] The voltage generator VG generates voltages necessary for the operation of the display panel DP. The voltage generator VG generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage VAINT. The first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT, and the second initialization voltage VAINT can be applied to the pixels PX.

[0076] The scan driver SDV may receive a scan control signal SCS from the timing controller TC. In response to the scan control signal SCS, the scan driver SDV may output scan signals to the scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm. The scan signals may be applied to the pixels PX via the scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm.

[0077] The data driver DDV may receive a data control signal DCS and a video data signal DAS from the timing controller TC. The data driver DDV may convert the video data signal DAS into a data signal and output the converted data signal. The data signal may be defined as an analog voltage corresponding to the gray level of the video data signal DAS. The data signal may be applied to the pixels PX via the data lines DL1 to DLn.

[0078] The light emitting driver EDV may receive a light emitting control signal ECS from the timing controller TC. In response to the light emitting control signal ECS, the light emitting driver EDV may output a light emitting signal to the light emitting lines EML1 to EMLm. The light emitting signal may be applied to the pixels PX via the light emitting lines EML1 to EMLm.

[0079] The pixel PX can be provided with a data voltage in response to a scan signal, and can emit light of a brightness corresponding to the data voltage in response to a light emitting signal to display an image.

[0080] FIG. 5 is a diagram showing an equivalent circuit of one of the pixels shown in FIG.

[0081] 5 exemplarily shows a pixel PXij connected to the jth data line DLj, the ith scan lines GWLi, GCLi, GILi, GBLi, and the ith emission line EMLi, where i and j are natural numbers.

[0082] 5, the pixel PXij may include a pixel circuit PC and a light-emitting element OLEDC coupled to the pixel circuit PC. The pixel circuit light-emitting element PC may drive the light-emitting element OLED.

[0083] The pixel circuit PC may include a plurality of transistors T1 to T8 and a capacitor CST. The transistors T1 to T8 and the capacitor CST may control the amount of current flowing to the light emitting element OLED. The light emitting element OLED may generate light having a predetermined brightness depending on the amount of current provided.

[0084] The i-th write scan line GWLi may receive the i-th write scan signal GWi, the i-th compensation scan line CGLi may receive the i-th compensation scan signal GCi, the i-th initialization scan line GILi may receive the i-th initialization scan signal GIi, the i-th bias scan line CBLi may receive the i-th bias scan signal GBi, and the i-th emission line EMLi may receive the i-th emission signal EMi.

[0085] The pixel PXij may be connected to the jth data line DLj, the ith write scan line GWi, the ith compensation scan line GCi, the ith initialization scan line GIi, the ith bias scan line GBi, the ith emission line EMLi, the first initialization line VIL1, the second initialization line VIL2, the bias line VBL, and the first and second power supply lines PL1 and PL2.

[0086] The first initialization line VIL1 may receive the first initialization voltage VINT, the second initialization line VIL2 may receive the second initialization voltage VAINT, the bias line VBL may receive the bias voltage VBIAS, the first power supply line PL1 may receive the first driving voltage ELVDD, and the second power supply line PL2 may receive the eleventh driving voltage ELVSS.

[0087] Each of the transistors T1 to T8 may include a source electrode, a drain electrode, and a gate electrode. Hereinafter, in FIG. 5, for convenience, one of the source electrode and the drain electrode is defined as a first electrode, and the other is defined as a second electrode. Furthermore, the gate electrode is defined as a control electrode.

[0088] The transistors T1 to T8 may include first to eighth transistors T1 to T8. The first, second, fifth to eighth transistors T1, T2, T5 to T8 may be PMOS transistors. The third and fourth transistors T3 and T4 may be NMOS transistors.

[0089] The first transistor T1 may be defined as a driving transistor, the second transistor T2 may be defined as a switching transistor, the third transistor T3 may be defined as a compensation transistor, the fourth transistor T4 and the seventh transistor T7 may be defined as initialization transistors, the fifth transistor T5 and the sixth transistor T6 may be defined as light-emitting control transistors, and the eighth transistor T8 may be defined as a bias transistor.

[0090] The light-emitting element OLED may be defined as an organic light-emitting element. The light-emitting element OLED may include an anode AE ​​and a cathode CE. The anode AE ​​may receive a first driving voltage ELVDD via the sixth, first, and fifth transistors T6, T1, and T5. The first driving voltage ELVDD may be applied to the pixel circuit PC via a first power line PL1.

[0091] The cathode CE may receive a second driving voltage ELVSS having a level lower than the first driving voltage ELVDD, and the second driving voltage ELVSS may be applied to the pixel circuit PC via a second power line PL2.

[0092] The first transistor T1 may be disposed between the fifth transistor T5 and the sixth transistor T6 and may be coupled to the fifth transistor T5 and the sixth transistor T6. The first transistor T1 may be coupled to the first power line PL1 via the fifth transistor T5 and to the anode AE ​​via the sixth transistor T6.

[0093] The first transistor T1 may include a first electrode connected to the first power line PL1 via the fifth transistor T5, a second electrode connected to the anode AE ​​via the sixth transistor T6, and a control electrode connected to the first node N1.

[0094] A first electrode of the first transistor T1 may be connected to the fifth transistor T5, and a second electrode of the first transistor T1 may be connected to the sixth transistor T6. The first transistor T1 may control the amount of current flowing through the light emitting element OLED according to a voltage of a first node N1 applied to a control electrode of the first transistor T1.

[0095] The second transistor T2 may be disposed between the first transistor T1 and the j-th data line DLj and may be coupled to the first transistor T1 and the j-th data line DLj. The second transistor T2 may include a first electrode coupled to the j-th data line DLj, a second electrode coupled to the first electrode of the first transistor T1, and a control electrode coupled to the ith write scan line GWLi.

[0096] The second transistor T2 may be turned on by an i-th write scan signal GWi applied via an i-th write scan line GWLi to electrically connect the j-th data line DLj to the first electrode of the first transistor T1, and may perform a switching operation to provide the data voltage VD (corresponding to the data signal described above) applied via the j-th data line DLj to the first electrode of the first transistor T1.

[0097] The third transistor T3 may be coupled to the second electrode of the first transistor T1 and the first node N1, and may include a first electrode coupled to the second electrode of the first transistor T1, a second electrode coupled to the first node N1, and a control electrode coupled to the i-th compensation scan line GCLi.

[0098] The third transistor T3 may be turned on by an i-th compensation scan signal GCi applied through an i-th compensation scan line GCLi to electrically connect the second electrode of the first transistor T1 to the control electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 and the third transistor T3 may be connected in a diode configuration.

[0099] The fourth transistor T4 may be coupled to the first node N1. The fourth transistor T4 may include a first electrode coupled to the first node N1, a second electrode coupled to the first initialization line VIL1, and a control electrode coupled to the i-th initialization scan line GILi. The fourth transistor T4 may be turned on by the i-th initialization scan signal GIi applied via the i-th initialization scan line GILi to provide the first initialization voltage VINT applied via the first initialization line VIL1 to the first node N1.

[0100] The fifth transistor T5 may include a first electrode coupled to the first power line PL1, a second electrode coupled to the first electrode of the first transistor T1, and a control electrode coupled to the i-th light-emitting line EMLi.

[0101] The sixth transistor T6 may include a first electrode coupled to the second electrode of the first transistor T1, a second electrode coupled to the anode AE, and a control electrode coupled to the i-th light-emitting line EMLi.

[0102] The fifth transistor T5 and the sixth transistor T6 may be turned on by the i-th light-emitting signal EMLi applied through the i-th light-emitting line ELi. The turned-on fifth transistor T5 and the sixth transistor T6 may provide the first driving voltage ELVDD to the light-emitting element OLED, causing a driving current to flow through the light-emitting element OLED. As a result, the light-emitting element OLED may emit light.

[0103] The seventh transistor T7 may include a first electrode connected to the anode AE, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the i-th bias scan line GBLi. The seventh transistor T7 may be turned on in response to the i-th bias scan signal GBi applied via the i-th bias scan line GBLi to provide the second initialization voltage VAINT received via the second initialization line VIL2 to the anode AE ​​of the light emitting element OLED.

[0104] In the embodiment of the present invention, the second initialization voltage VAINT may have a different level from the first initialization voltage VINT, but is not limited thereto, and may have the same level as the first initialization voltage VINT.

[0105] The seventh transistor T7 may improve the black expression capability of the pixel PXij. When the seventh transistor T7 is turned on, a parasitic capacitor (not shown) of the light emitting element OLED may be discharged. Therefore, when black brightness is realized, the light emitting element OLED does not emit light due to the leakage current of the first transistor T1, thereby improving the black expression capability.

[0106] The capacitor CST may include a first electrode coupled to the first power line PL1 and a second electrode coupled to the first node N1. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 may be determined by the voltage stored in the capacitor CST.

[0107] The eighth transistor T8 may include a first electrode coupled to the bias line VBL, a second electrode coupled to the first electrode of the first transistor T1, and a control electrode coupled to the i-th bias scan line GBLi.

[0108] The eighth transistor T8 may be turned on by the i-th bias scan signal GBi to provide the bias voltage VBIAS applied via the bias line VBL to the first electrode of the first transistor T1.

[0109] FIG. 6 is a timing diagram of scanning signals and light emitting signals for explaining the operation of the pixel shown in FIG.

[0110] Referring to FIGS. 5 and 6, the i-th light emitting signal EMi may have a high level during a non-light emitting period NLP and a low level during a light emitting period LP.

[0111] The activation intervals of the i-th write scanning signal GWi and the i-th bias scanning signal GBi may be defined as the low levels of the i-th write scanning signal GWi and the i-th bias scanning signal GBi.

[0112] The activation intervals of the i-th compensation input scanning signal GCi and the i-th initialization scanning signal GIi may be defined as the high levels of the i-th compensation input scanning signal GCi and the i-th initialization scanning signal GIi.

[0113] After the i-th initialization scan signal GIi is activated, the i-th compensation input scan signal GCi and the i-th write scan signal GWi may be activated, and then the i-th bias scan signal GBi may be activated.

[0114] During the non-light emitting period NLP, the activated i-th initialization scanning signal GIi, the i-th compensation input scanning signal GCi, the i-th write scanning signal GWi, and the i-th bias scanning signal GBi may be applied to the pixel PXij.

[0115] The i-th initialization scan signal GIi may be applied to the fourth transistor T4 to turn on the fourth transistor T4. The fourth transistor T4 may provide a first initialization voltage VINT to the node N1. Thus, the first initialization voltage VINT may be applied to the control electrode of the first transistor T1, and the first transistor T1 may be initialized by the first initialization voltage VINT. This operation may be defined as an initialization operation.

[0116] The i-th write scanning signal GWi may be applied to the second transistor T2 to turn on the second transistor T2, and the i-th compensation scanning signal GCi may be applied to the third transistor T3 to turn on the third transistor T3.

[0117] The first transistor T1 and the third transistor T3 may be connected to each other in the form of a diode. In this case, a compensation voltage Vd-Vth, which is a data voltage VD supplied via the data line DLj minus a threshold voltage Vth of the first transistor T1, may be applied to the control electrode of the first transistor T1. This operation may be defined as a write operation (or programming operation) and a compensation operation.

[0118] A first driving voltage ELVDD and a compensation voltage Vd-Vth may be applied to a first electrode and a second electrode of the capacitor CST, respectively, and a charge corresponding to a difference between the voltage of the first electrode of the capacitor CST and the voltage of the second electrode of the capacitor CST may be stored in the capacitor CST.

[0119] Next, the i-th bias scan signal GBi may be applied to the seventh and eighth transistors T7 and T8 to turn on the seventh and eighth transistors T7 and T8. The second initialization voltage VAINT may be provided to the anode AE ​​via the seventh transistor T7 to initialize the anode AE ​​to the second initialization voltage VAINT. The bias voltage VBIAS may be applied to the first electrode of the first transistor T1 via the eighth transistor T8.

[0120] Next, during the light-emitting period LP, the i-th light-emitting signal EMi is applied to the fifth transistor T5 and the sixth transistor T6 via the i-th light-emitting line EMLi, turning on the fifth transistor T5 and the sixth transistor T6. In this case, a driving current Id corresponding to a voltage difference between the voltage of the control electrode of the first transistor T1 and the first driving voltage ELVDD may be generated. The driving current Id is provided to the light-emitting element OLED via the sixth transistor T6, causing the light-emitting element OLED to emit light.

[0121] FIG. 7 is a diagram illustrating an example of a cross section of the light emitting element, the first transistor, the fourth transistor, and the sixth transistor of the pixel illustrated in FIG.

[0122] 7, the light-emitting element OLED may include a first electrode AE, a second electrode CE, a hole control layer HCL, an electron control layer ECL, and an emitting layer EML. The first electrode AE ​​may be the anode AE ​​shown in FIG. 5, and the second electrode CE may be the cathode CE shown in FIG. 5. The second electrode CE may be disposed on the first electrode AE, and the hole control layer HCL, the electron control layer ECL, and the emitting layer EML may be disposed between the first electrode AE ​​and the second electrode CE.

[0123] The first, fourth, and sixth transistors T1, T4, and T6 and the light-emitting element OLED may be disposed on a substrate SUB. The display area DA may include a light-emitting area LEA corresponding to the pixel PXij and a non-light-emitting area NLEA adjacent to the light-emitting area LEA. The light-emitting element OLED may be disposed in the light-emitting area LEA.

[0124] A lower metal layer BML may be disposed on the substrate SUB. The lower metal layer BML may overlap the first transistor T1. Although not shown, a constant voltage may be applied to the lower metal layer BML. When the constant voltage is applied to the lower metal layer BML, the threshold voltage Vth value of the first transistor T1 disposed on the lower metal layer BML may be maintained unchanged.

[0125] The lower metal layer BML may block light incident on the first transistor T1 from below the lower metal layer BML. The lower metal layer BML may include a reflective metal. The lower metal layer BML may be omitted.

[0126] A buffer layer BFL may be disposed on the substrate SUB, and the buffer layer BFL may be an inorganic layer. The buffer layer BFL may cover the lower metal layer BML. The semiconductor layers S1, A1, and Dr1 of the first transistor T1 and the semiconductor layers S6, A6, and Dr6 of the sixth transistor T6 may be disposed on the buffer layer BFL. The semiconductor layers S1, A1, Dr1, S6, A6, and Dr6 may include polysilicon. However, the semiconductor layers S1, A1, Dr1, S6, A6, and Dr6 may include amorphous silicon.

[0127] The semiconductor layers S1, A1, Dr1, S6, A6, and Dr6 may be doped with an N-type dopant or a P-type dopant. The semiconductor layers S1, A1, Dr1, S6, A6, and Dr6 may include highly doped regions and lightly doped regions. The highly doped regions have greater conductivity than the lightly doped regions and may substantially serve as source and drain electrodes of the first and sixth transistors T1 and T6. The lightly doped regions may substantially correspond to the active regions (or channels) of the first and sixth transistors T1 and T6.

[0128] The first source region S1, the first channel region A1, and the first drain region Dr1 of the first transistor T1 may be composed of semiconductor layers S1, A1, and Dr1. The sixth source region S6, the sixth channel region A6, and the sixth drain region Dr6 of the sixth transistor T6 may be composed of semiconductor layers S6, A6, and Dr6. The first channel region A1 may be disposed between the first source region S1 and the first drain region Dr1. The sixth channel region A6 may be disposed between the sixth source region S6 and the sixth drain region Dr6.

[0129] A first insulating layer INS1 may be disposed on the buffer layer BFL to cover the semiconductor layers S1, A1, Dr1, S6, A6, and Dr6. A first gate electrode G1 (or control electrode) of the first transistor T1 and a sixth gate electrode G6 (or control electrode) of the sixth transistor T6 may be disposed on the first insulating layer INS1. When viewed from above, the first gate electrode G1 may overlap the first channel region A1, and the sixth gate electrode G6 may overlap the sixth channel region A6.

[0130] Although not shown, the structures of the source region, channel region, drain region, and gate electrode of each of the second, fifth, and seventh transistors T2, T5, and T7 may be substantially the same as those of the first and sixth transistors T1, T6.

[0131] A second insulating layer INS2 may be disposed on the first insulating layer INS1 so as to cover the first and sixth gate electrodes G1 and G6. A dummy electrode DME may be disposed on the second insulating layer INS2. The dummy electrode DME may be disposed on the first gate electrode G1 and may overlap the first gate electrode G1 when viewed from above. The dummy electrode DME may form the above-mentioned capacitor CST together with the first gate electrode G1.

[0132] A third insulating layer INS3 may be disposed on the second insulating layer INS2 so as to cover the dummy electrode DME. Semiconductor layers S4, A4, and Dr4 of the fourth transistor T4 may be disposed on the third insulating layer INS3. The semiconductor layers S4, A4, and Dr4 may include an oxide semiconductor made of a metal oxide. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor.

[0133] The semiconductor layers S4, A4, and Dr4 may include multiple regions that are distinguished by whether the metal oxide is reduced or not. The regions where the metal oxide is reduced (hereinafter referred to as reduced regions) may have higher conductivity than regions where the metal oxide is not reduced (hereinafter referred to as non-reduced regions). The reduced regions may essentially function as the source or drain electrodes of the fourth transistor T4. The non-reduced regions may essentially correspond to the active (or channel) of the fourth transistor T4.

[0134] The fourth source region S4, the fourth channel region A4, and the fourth drain region Dr4 of the fourth transistor T4 may be formed of semiconductor layers S4, D4, and Dr4, and the fourth channel region A4 may be disposed between the fourth source region S4 and the fourth drain region Dr4.

[0135] A fourth insulating layer INS4 may be disposed on the third insulating layer INS3 to cover the semiconductor layers S4, A4, and Dr4. A fourth gate electrode G4 of the fourth transistor T4 may be disposed on the fourth insulating layer INS4. When viewed from above, the fourth gate electrode G4 may overlap the fourth channel region A4.

[0136] A fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 to cover the fourth gate electrode G4. Although not shown, the source region, channel region, drain region, and gate electrode of the third transistor T3 may have substantially the same structures as those of the fourth transistor T4.

[0137] The buffer layer BFL and the first to fifth insulating layers INS1 to INS5 may include inorganic layers. Exemplarily, the buffer layer BFL, the first insulating layer INS1, and the fourth insulating layer INS4 may include silicon oxide layers, and the second insulating layer INS2 may include a silicon nitride layer.

[0138] The third and fifth insulating layers INS3 and INS5 may comprise multiple inorganic insulating layers that are made of different materials and stacked on top of each other. For example, the third insulating layer INS3 may comprise a silicon nitride layer and a silicon oxide layer that are stacked sequentially, and the fifth insulating layer INS5 may comprise a silicon oxide layer and a silicon nitride layer that are stacked sequentially. The thicknesses of the third and fifth insulating layers INS3 and INS5 may be greater than the thicknesses of the buffer layer BFL and the first, second, and fourth insulating layers INS1, INS2, and INS4, respectively.

[0139] A connecting electrode CNE may be disposed between the sixth transistor T6 and the light emitting element OLED. The connecting electrode CNE may electrically connect the sixth transistor T6 and the light emitting element OLED. The connecting electrode CNE may include a first connecting electrode CNE1 and a second connecting electrode CNE2 disposed on the first connecting electrode CNE1.

[0140] The first connecting electrode CNE1 may be disposed on the fifth insulating layer INS5 and may be connected to the sixth drain region Dr6 through a first contact hole CH1 defined in the first to fifth insulating layers INS1 to INS5. A sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 to cover the first electrode CNE1.

[0141] The second connecting electrode CNE1 may be disposed on the sixth insulating layer INS6. The second electrode CNE2 may be connected to the first connecting electrode CNE1 through a second contact hole CH2 defined in the sixth insulating layer INS6.

[0142] A seventh insulating layer INS7 may be disposed on the sixth insulating layer INS6 so as to cover the second electrode CNE2. The sixth to seventh insulating layers INS6 and INS7 may include inorganic layers or organic layers.

[0143] A first electrode AE ​​may be disposed on the seventh insulating layer INS7 and may be electrically connected to the second connecting electrode CNE2 through a third contact hole CH3 defined in the seventh insulating layer INS7.

[0144] A pixel defining layer PDL exposing a predetermined portion of the first electrode AE ​​may be disposed on the first electrode AE ​​and the seventh insulating layer INS7, and a first opening PDL_OP exposing a predetermined portion of the first electrode AE ​​may be defined in the pixel defining layer PDL.

[0145] A spacer SDL may be disposed on the pixel defining layer PDL. The spacer SDL may include an organic material and may support a mask used in a process of depositing the emitting layer EML. A second opening PX_OP overlapping the first opening PDL_OP may be defined in the spacer SDL.

[0146] The hole control layer HCL may be disposed on the first electrode AE ​​and the spacer SDL. The hole control layer HCL may be disposed in common in the light-emitting area LEA and the non-light-emitting area NLEA. The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0147] The emitting layer EML may be disposed on the hole controlling layer HCL. The emitting layer EML may be disposed in a region corresponding to the opening PX_OP. The emitting layer EML may include an organic material and / or an inorganic material. The emitting layer EML may generate any one of red, green, and blue light.

[0148] The electron control layer ECL may be disposed on the light-emitting layer EML and the hole control layer HCL. The electron control layer ECL may be disposed in common in the light-emitting area LEA and the non-light-emitting area NLEA. The electron control layer ECL may include an electron transport layer and an electron injection layer.

[0149] The second electrode CE may be disposed on the electronic control layer ECL. The second electrode CE may be disposed in common to the pixels PX. That is, the second electrode CE may be disposed in common on the emitting layer EML of the pixels PX.

[0150] The layers from the buffer layer BFL to the seventh insulating layer INS7 may be defined as a circuit element layer DP-CL. The layer in which the light-emitting element OLED is disposed may be defined as a display element layer DP_OLED.

[0151] A thin-film encapsulation layer TFE may be disposed on the light-emitting element OLED. The thin-film encapsulation layer TFE may include a first inorganic layer LIL, an organic layer OL, and a second inorganic layer IL2 stacked in sequence. The inorganic layers LIL and UIL may include inorganic materials and protect the pixel from moisture / oxygen. The organic layer OL may include an organic material and protect the pixel PX from foreign matter such as dust particles.

[0152] A first voltage ELVDD may be applied to the first electrode AE, and a second voltage ELVSS may be applied to the second electrode CE. Holes and electrons injected into the emitting layer EML may combine to form excitons, and the excitons may transition to a ground state, causing the light emitting element OLED to emit light. As the light emitting element OLED emits light, an image may be displayed.

[0153] Figure 8 is a plan view of a display panel according to an embodiment of the present invention. Figure 9 is a cross-sectional view taken along line I-I' in Figure 8. Figure 10 is a cross-sectional view taken along line II-II' in Figure 8. Figure 11 is a cross-sectional view taken along line III-III' in Figure 8. The same or similar reference numerals are used for the same or similar components as in Figures 1 to 7, and redundant descriptions will be omitted.

[0154] Referring to FIG. 8, the display panel DP may include pixels PX, a plurality of data drivers DDV, a plurality of pads PD, a scan driver SDV (see FIG. 5), and an emission driver EDV (see FIG. 5).

[0155] The display panel DP may include a display area DA and a non-display area NDA that is disposed around and surrounds the display area DA. The display area DA may have a rectangular shape with rounded corners that corresponds to the shape of the display panel DP.

[0156] The display panel DP may include a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of light emitting lines EML1 to EMLm, a plurality of first power lines PL1-1, PL1-n, and a second power line PL2. The pixels PX may be arranged in a display area DA. The pixels PX may be connected to the scan lines SL1 to SLm, the data lines DL1 to DLn, and the light emitting lines EML1 to EMLm.

[0157] The scan lines SL1 to SLm may include the scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBL shown in Fig. 4. For example, the i-th scan line among the scan lines SL1 to SLm may include the i-th write scan line GWLi, the i-th compensation scan line GCLi, the i-th initialization scan line GILi, and the i-th bias scan line GBLi. Therefore, the above-mentioned scan signals may be applied to the pixels PX via the scan lines SL1 to SLm.

[0158] The data lines DL1 to DLn, the first power supply lines PL1-1, PL1-n, the second power supply line PL2, and the light emitting lines EML1 to EMLm may be the same as the data lines DL1 to DLn, the first power supply line PL1, the second power supply line PL2, and the light emitting lines EML1 to EMLm shown in FIG.

[0159] Although the scan driver SDV (see FIG. 5) and the emission driver EDV (see FIG. 5) are omitted in FIG. 8, the scan driver SDV (see FIG. 5) and the emission driver EDV (see FIG. 5) may be arranged in adjacent non-display areas NDA on both sides of the display panel DP opposite each other in the first direction DR1, with the display area DA sandwiched between them.

[0160] The data drivers DDV may be disposed at the bottom of the non-display area NDA and spaced apart from each other along the first direction DR1.

[0161] The first power lines PL1-1 to PL1-n may be extended in a first direction DR1 within the display area DA and connected to the pixels PX. Although not shown, one end of each of the first power lines PL1-1 to PL1n may be connected to a pad PD, and the other end of each of the first power lines PL1-1 to PL1n may be connected to a bridge line EL-B.

[0162] The second power supply line PL2 may include first lines PL2-1 to PL2-e and second lines PL2-S. The first lines PL2-1 to PL2-e may extend in the first direction DR1 and be connected to the pixels PX. The second lines PL2-S may be disposed in the non-display area NDA and surround at least a portion of the display area DA. The first lines PL2-1 to PL2-e may extend from the display area DA to the non-display area NDA and be connected to the second lines PL2-S. One end and the other end of the second lines PL2-S may be connected to the pads PD.

[0163] The scan lines SL1 to SLm may be extended in a first direction DR1 and connected to the pixels PX and the scan driver SDV (see FIG. 5). The data lines DL1 to DLn may be extended in a second direction DR2 and connected to the pixels PX and the data driver DDV. The light emitting lines EML1 to EMLm may be extended in the first direction DR1 and connected to the pixels PX and the light emitting driver EDV (see FIG. 5).

[0164] The data drivers DDV may be spaced apart from each other in a first direction DR1. A predetermined number of data lines may be connected to each data driver DDV. Although two data drivers DDV are shown as an example, the number of data drivers DDV is not limited to this. For example, the number of data drivers DDV may increase as the left and right areas of the display panel DP increase.

[0165] The pads PD are disposed in the non-display area NDA adjacent to the lower end of the display panel DP and may be closer to the lower end of the display panel DP than the data driver DDV. The data driver DDV may be connected to the pads PD. The data lines DL1 to DLn may be connected to the data driver DDV, and the data driver DDV may be connected to the pads PD corresponding to the data lines DL1 to DLn.

[0166] The timing controller TC and voltage generator VG shown in FIG. 4 may be mounted on a printed circuit board and connected to the pads PD via the printed circuit board.

[0167] The display panel DP according to the present invention may include a sensing line EL-T, which may include an extension line EL-D, a connecting line EL-C, and a bridging line EL-B.

[0168] The detection line EL-T may measure a dropped voltage by sensing a difference between a first driving voltage ELVDD (see FIG. 5) delivered to a pixel PX arranged at the bottom of the display area DA adjacent to the pad PD and a first driving voltage ELVDD (see FIG. 5) delivered to a pixel PX arranged at the top of the display area DA among pixels PX arranged in the same column along the second direction DR2. For example, one end of the first power line PL1 may be connected to the pad PD, and the other end of the first power line PL1 may be connected to a bridge line EL-B. The bridge line EL-B may be connected to one end of an extension line EL-D via a connection line EL-C, and the other end of the connection line EL-C may be connected to the pad PD. The materials, line widths, and thicknesses of the extension line EL-D, the bridge line EL-B, and the connection line EL-C may be controlled, so that the resistance values ​​of the lines may be known in advance.

[0169] The difference between the initial driving voltage value provided to the pixel PX arranged at the bottom of the display area DA and the reduced driving voltage value provided to the pixel PX arranged at the top is sensed via the detection line EL-T, the voltage reduced by the resistance value of the detection line EL-T is detected, and a compensated first driving voltage ELVDD (see FIG. 5) can be provided by the voltage generator VG (see FIG. 4). As a result, the display device DD according to the present invention can provide a constant first driving voltage ELVDD (see FIG. 5) regardless of the size / area of ​​the display area DA, thereby providing a display device DD with improved reliability.

[0170] The lower the resistance of the lines included in the sensing line EL-T, the more accurately the dropped voltage can be measured and compensated for. Therefore, it is desirable to reduce the resistance of the lines included in the sensing line EL-T.

[0171] The detection line EL-T may include an extension line EL-D, a connecting line EL-C, and a bridge line EL-B.

[0172] A "portion" of the extension line EL-D may extend along the second direction DR2 and be spaced apart along the first direction DR1 across the display area DA. Another portion of the extension line EL-D may extend along the first direction DR1, with one end connected to the portion and the other end connected to the pad PD.

[0173] The bridge line EL-B may extend along the first direction DR1 and be disposed above the display area DA. The first power lines PL1-1 to PL1-n may be connected to the bridge line EL-B.

[0174] The extension line EL-D and the bridge line EL-B may be disposed on different layers or on the same layer and spaced apart from each other.

[0175] The connecting line EL-C may connect the extension line EL-D and the bridge line EL-B. The connecting line EL-D disposed on the upper left side of the display area DA may be connected to one end of one of the extension lines EL-D and one end of the bridge line EL-B. The other end of one of the extension lines EL-D may be connected to the pad PD.

[0176] The connecting line EL-D disposed on the upper right side of the display area DA may be connected to one end of another extension line EL-D and the other end of the bridge line EL-B, and the other end of the other extension line EL-D may be connected to the pad PD.

[0177] According to this embodiment, the second line PL2-S may cross the connecting line EL-C on a plane, and thus the second line PL2-S may be disposed on a different layer from the connecting line EL-C.

[0178] The connecting line EL-C may be spaced further from the display area DA than the second line PL2-S, so that the second line PL2-S may be disposed between the connecting line EL-C and the display area DA.

[0179] The bridge line EL-B may be closer to the display area DA than the second line PL2-S, and thus may be disposed between the second direction PL2-S and the display area DA.

[0180] 9, the non-display area NDA of the display panel DP according to an embodiment may include a base substrate SUB, a plurality of insulating layers BFL to INS7, and a sealing layer TFE. The display panel DP according to an embodiment may include outer and inner dams DMP-O and DMP-I arranged along the non-display area NDA and surrounding at least a portion of the display area DA.

[0181] The outer dam DMP-O may surround at least a portion of the inner dam DMP-I, and the inner dam DMP-I may surround at least a portion of the display area DA. Thus, the outer dam DMP-O may be spaced further away from the display area DA than the inner dam DMP-I.

[0182] The outer dam DMP-O may include first to fourth dam patterns D1, D2, D3, and D4 sequentially stacked on the fifth insulating layer ISN5. The first dam pattern D1 may be formed and patterned in the same process as the sixth insulating layer ISN6 described in FIG. 7 and may include the same material as the sixth insulating layer ISN6. The first dam pattern D1 may include an organic material.

[0183] The second dam pattern D2 may be disposed on the first dam pattern D1. The second dam pattern D2 covers the side surfaces of the first dam pattern D1. The second dam pattern D2 may be formed and patterned in the same process as the seventh insulating layer ISN7 described in FIG. 7 and may include the same material as the seventh insulating layer ISN7. The second dam pattern D2 may include an organic material.

[0184] The third dam pattern D3 may be disposed on the second dam pattern D2. The third dam pattern D3 may cover the side surfaces of the second dam pattern D2. The third dam pattern D3 may be formed and patterned in the same process as the pixel defining layer PDL described in FIG. 7 and may include the same material as the pixel defining layer PDL. The third dam pattern D3 may include an organic material.

[0185] The fourth dam pattern D4 may be disposed on the third dam pattern D3. The fourth dam pattern D4 may be formed and patterned in the same process as the spacer SDL described in FIG. 7 and may include the same material as the spacer SDL. The fourth dam pattern D4 may include an organic material.

[0186] The inner dam DMP-I may include fifth and sixth dam patterns D5 and Dr6 sequentially stacked on the fifth insulating layer ISN5.

[0187] The fifth dam pattern D5 may be disposed on the fifth insulating layer ISN5. The fifth dam pattern D5 may be formed and patterned in the same process as the pixel defining layer PDL described in FIG. 7 and may include the same material as the pixel defining layer PDL. Therefore, the fifth dam pattern D5 may be formed in the same process as the third dam pattern D3.

[0188] The sixth dam pattern D6 may be disposed on the fifth dam pattern D5. The sixth dam pattern D6 may be formed and patterned in the same process as the spacer SDL described in FIG. 7 and may include the same material as the spacer SDL. Therefore, the sixth dam pattern D6 may be formed in the same process as the fourth dam pattern D4.

[0189] At least one of the outer dam DMP-O and the inner dam DMP-I may define a boundary of the organic layer OL in the non-display area NDA so that the organic layer OL does not overflow outside the base substrate SUB during the formation of the organic layer OL of the encapsulation layer TFE. While FIG. 9 illustrates that the organic layer OL is formed up to the side surface of the outer dam DMP-O, the boundary of the organic layer OL may be defined by the inner dam DMP-I.

[0190] According to the present invention, the extension line EL-D may include a sensing pattern ES and a power supply pattern EV. That is, the extension line EL-D included in the detection line EL-T may have a double wiring structure. The sensing pattern ES and the power supply pattern EV may be disposed inside the outer dam DMP-O. The description of the extension line EL-D shown in FIG. 9 may also be applied to the extension line EL-D disposed on the right side in FIG. 8, and redundant description will be omitted.

[0191] The sensing pattern ES may be disposed on the fifth insulating layer ISN5. In this embodiment, the sensing pattern ES may be formed and patterned by the same process as the first connecting electrode CNE1 described in FIG. 7. Therefore, the sensing pattern ES may include the same material as the first connecting electrode CNNE1. The sensing pattern ES may be covered by the first dam pattern D1.

[0192] The power supply pattern EV may be disposed on the first dam pattern D1 and covered by the second dam pattern D2. In this embodiment, the power supply pattern EV may be formed and patterned using the same process as the first connecting electrode CNE1 described in FIG. 7. Therefore, the sensing pattern ES may include the same material as the first connecting electrode CNE1. The sensing pattern ES may be covered by the first dam pattern D1. According to the present invention, the extension line EL-D, which measures a voltage value dropped from an initial driving voltage, has a double wiring structure, thereby providing a low-resistance sensing line EL-T.

[0193] 10, the power supply pattern EV may be connected to the sensing pattern ES through a contact hole CNT-E penetrating a first dam pattern D1 in a non-display area NDA adjacent to a lower end of the display area DA, and one end of the power supply pattern EV may be connected to a pad PD.

[0194] 8 may include a first portion P1 and a second portion P2. The first portion P1 may be disposed on the fifth insulating layer ISN5. The second portion P2 may be disposed on the sixth insulating layer ISN6 and may be disposed in a hole penetrating the sixth insulating layer ISN6 and connected to the first portion P1. According to one embodiment, the power supply pattern EV and the second portion P2 may be an integral pattern connected to each other.

[0195] 9, according to one embodiment, the second line PL2-S of the second power line PL2 (see FIG. 7) may include a first pattern P2-1 and a second pattern P2-2. The first pattern P2-1 and the second pattern P2-2 may extend from the interior of the inner dam DMP-I to the interior of the outer dam DMP-O. The first pattern P2-1 and the second pattern P2-2 may contact each other within the inner dam DMP-I and be spaced apart within the outer dam DMP-O with the first dam pattern D1 sandwiched therebetween. Within the outer dam DMP-O, the first pattern P2-1 may be disposed between the fifth insulating layer ISN5 and the first dam pattern D1, and the second pattern P2-2 may be disposed between the first dam pattern D1 and the second dam pattern D2.

[0196] The second line PL2-S may contact the second electrode CE extending from the display area DA to the non-display area NDA. The second electrode CE may be disposed directly on the second pattern P2-2. Inside the outer dam DMP-O, the second electrode CE may be separated from the second pattern P2-2 with the second dam pattern D2 interposed therebetween. According to this embodiment, the line width of the second line PL2-S may be greater than the line width of the extension line EL-D in a plan view.

[0197] 11, the power supply pattern EV may be connected to the sensing pattern ES through a contact hole CNT-E penetrating a first dam pattern D1 in a non-display area NDA adjacent to the top of the display area DA (see FIG. 7). As described with reference to FIGS. 10 and 11, the power supply pattern EV and the sensing pattern ES may be connected through the contact hole CNT-E at the bottom and top of the non-display area NDA, sandwiching the display area DA therebetween. However, the position where the power supply pattern EV and the sensing pattern ES are connected through the contact hole CNT-E is not limited to any one embodiment, as long as the extension line EL-D is disposed.

[0198] According to the present invention, the second line PL2-S of the second power supply line PL2 (see FIG. 7) may cross the connecting line EL-C, i.e., the second line PL2-S may be disposed on a different layer from the connecting line EL-C and may overlap each other.

[0199] According to this embodiment, the connection line EL-C may be disposed on the first insulating layer ISN1 and covered by the second insulating layer ISN2. The connection line EL-C may be formed and patterned in the same process as the first gate electrode G1 described in FIG. 7 and may include the same material as the first gate electrode G1.

[0200] One end of the sensing pattern ES may be connected to one end of the connecting line EL-C via a contact hole CNT-C penetrating the second to fifth insulating layers ISN2 to ISN5.

[0201] In this embodiment, the bridging line EL-B may be disposed on the second insulating layer ISN2 and covered by the third insulating layer ISN3. The bridging line EL-B may be formed and patterned in the same process as the first gate electrode G1 described in FIG. 7 and may include the same material as the first gate electrode G1. In this embodiment, the connecting line EL-C and the bridging line EL-B may be formed in the same process and disposed on the same layer. Therefore, the connecting line EL-C and the bridging line EL-B may be an integrated pattern.

[0202] According to this embodiment, a double wiring structure is formed to reduce the resistance of the extension line EL-D, and the power supply pattern EV and the sensing pattern ES included in the extension line EL-D are formed in the same layer as the first pattern P2-1 and the second pattern P2-2 included in the second line PL2-S. Therefore, to prevent the extension line EL-D and the second line PL2-S from crossing each other, the extension line EL-D and the bridge line EL-B may be connected via the connecting line EL-C. Therefore, the connecting line EL-C and the second line PL2-S may be characterized as being arranged on different layers and crossing each other.

[0203] Figures 12 to 16 are cross-sectional views of the area corresponding to Figure 11. The same or similar reference numerals are used for the same or similar components as in Figures 1 to 11, and duplicated descriptions will be omitted.

[0204] 12, the non-display area NDA of the display panel DP1 according to an embodiment may include a base substrate SUB, a plurality of insulating layers BFL-INS7, first and second inorganic layers LIL and UIL, an outer dam DMP-O, an inner dam DMP-I, a sensing line EL-T, and a second line PL2-S of the second power line PL2 (see FIG. 7). The sensing line EL-T may include an extension line EL-D, a connection line EL-C, and a bridging line EL-B1, and the extension line EL-D may include a sensing pattern ES and a power pattern EV. The second line PL2-S may include a first pattern P2-1 and a second pattern P2-2.

[0205] The power supply pattern EV may be connected to the sensing pattern ES through a contact hole CNT-E penetrating the first dam pattern D1 in the non-display area NDA adjacent to the top end of the display area DA (see FIG. 7).

[0206] The connecting line EL-C may be disposed on the first insulating layer ISN1 and covered by the second insulating layer ISN2. The connecting line EL-C may be formed and patterned in the same process as the first gate electrode G1 described in FIG. 7 and may include the same material as the first gate electrode G1.

[0207] One end of the sensing pattern ES may be connected to one end of the connecting line EL-C via a contact hole CNT-C penetrating the second to fifth insulating layers ISN2 to ISN5.

[0208] In this embodiment, the bridge line EL-B1 may be disposed on the second insulating layer ISN2 and covered by the third insulating layer ISN3. The bridge line EL-B1 may be formed and patterned in the same process as the dummy electrode DME described in FIG. 7 and may include the same material as the dummy electrode DME. In this embodiment, the bridge line EL-B1 may be connected to the other end of the connecting line EL-C through a contact hole CNT-B penetrating the second insulating layer ISN2.

[0209] 13, the non-display area NDA of the display panel DP2 according to an embodiment may include a base substrate SUB, a plurality of insulating layers BFL-INS7, first and second inorganic layers LIL and UIL, an outer dam DMP-O, an inner dam DMP-I, a sensing line EL-T, and a second line PL2-S of the second power line PL2 (see FIG. 7). The sensing line EL-T may include an extension line EL-D, a connecting line EL-C, and a bridging line EL-B2, and the extension line EL-D may include a sensing pattern ES and a power pattern EV. The second line PL2-S may include a first pattern P2-1 and a second pattern P2-2.

[0210] The power supply pattern EV may be connected to the sensing pattern ES through a contact hole CNT-E penetrating the first dam pattern D1 in the non-display area NDA adjacent to the top end of the display area DA (see FIG. 7).

[0211] The connecting line EL-C may be disposed on the first insulating layer ISN1 and covered by the second insulating layer ISN2. The connecting line EL-C may be formed and patterned in the same process as the first gate electrode G1 described in FIG. 7 and may include the same material as the first gate electrode G1.

[0212] One end of the sensing pattern ES may be connected to one end of the connecting line EL-C via a contact hole CNT-C penetrating the second to fifth insulating layers ISN2 to ISN5.

[0213] In this embodiment, the bridge line EL-B2 may be disposed on the fourth insulating layer ISN4 and covered by the fifth insulating layer ISN5. The bridge line EL-B2 may be formed and patterned in the same process as the fourth gate electrode G4 (the second gate electrode in the claims) described in FIG. 7 and may include the same material as the fourth gate electrode G4. In this embodiment, the bridge line EL-B2 may be connected to the other end of the connecting line EL-C through a contact hole CNT-B that penetrates the second and third insulating layers ISN2 and ISN3.

[0214] 14, the non-display area NDA of the display panel DP3 according to an embodiment may include a base substrate SUB, a plurality of insulating layers BFL-INS7, first and second inorganic layers LIL and UIL, an outer dam DMP-O, an inner dam DMP-I, a sensing line EL-T, and a second line PL2-S of the second power line PL2 (see FIG. 7). The sensing line EL-T may include an extension line EL-D, a connecting line EL-C, and a bridging line EL-B3, and the extension line EL-D may include a sensing pattern ES and a power pattern EV. The second line PL2-S may include a first pattern P2-1 and a second pattern P2-2.

[0215] The power supply pattern EV may be connected to the sensing pattern ES through a contact hole CNT-E penetrating the first dam pattern D1 in the non-display area NDA adjacent to the top end of the display area DA (see FIG. 7).

[0216] The connecting line EL-C may be disposed on the first insulating layer ISN1 and covered by the second insulating layer ISN2. The connecting line EL-C may be formed and patterned in the same process as the first gate electrode G1 described in FIG. 7 and may include the same material as the first gate electrode G1.

[0217] One end of the sensing pattern ES may be connected to one end of the connecting line EL-C via a contact hole CNT-C penetrating the second to fifth insulating layers ISN2 to ISN5.

[0218] In this embodiment, the bridging line EL-B3 may be disposed on the fifth insulating layer ISN5 and covered by the sixth insulating layer ISN6. The bridging line EL-B3 may be formed and patterned in the same process as the first connecting electrode CNE1 described in FIG. 7 and may include the same material as the first connecting electrode CNE1. In this embodiment, the bridging line EL-B3 may be connected to the other end of the connecting line EL-C through a contact hole CNT-B that penetrates the second to fourth insulating layers ISN2 to ISN4.

[0219] 15, the non-display area NDA of the display panel DP4 according to an embodiment may include a base substrate SUB, a plurality of insulating layers BFL-INS7, first and second inorganic layers LIL and UIL, an outer dam DMP-O, an inner dam DMP-I, a sensing line EL-T, and a second line PL2-S of the second power line PL2 (see FIG. 7). The sensing line EL-T may include an extension line EL-D, a connecting line EL-C1, and a bridging line EL-B, and the extension line EL-D may include a sensing pattern ES and a power pattern EV. The second line PL2-S may include a first pattern P2-1 and a second pattern P2-2.

[0220] The power supply pattern EV may be connected to the sensing pattern ES through a contact hole CNT-E penetrating the first dam pattern D1 in the non-display area NDA adjacent to the top end of the display area DA (see FIG. 7).

[0221] In this embodiment, the connecting line EL-C1 may be disposed on the second insulating layer ISN2 and covered by the third insulating layer ISN3. The connecting line EL-C1 may be formed and patterned in the same process as the dummy electrode DME described in FIG. 7 and may include the same material as the dummy electrode DME.

[0222] One end of the sensing pattern ES may be connected to one end of the connecting line EL-C1 through a contact hole CNT-C penetrating the third to fifth insulating layers ISN3 to ISN5.

[0223] In this embodiment, the bridge line EL-B may be disposed on the first insulating layer ISN1 and covered by the second insulating layer ISN2. The bridge line EL-B may be formed and patterned in the same process as the first gate electrode G1 described in FIG. 7 and may include the same material as the first gate electrode G1. In this embodiment, the other end of the connecting line EL-C1 may be connected to the bridge line EL-B through a contact hole CNT-B penetrating the second insulating layer ISN2.

[0224] 16, the non-display area NDA of the display panel DP5 according to an embodiment may include a base substrate SUB, a plurality of insulating layers BFL-INS7, first and second inorganic layers LIL and UIL, an outer dam DMP-O, an inner dam DMP-I, a sensing line EL-T, and a second line PL2-S of the second power line PL2 (see FIG. 7). The sensing line EL-T may include an extension line EL-D, a connecting line EL-C2, and a bridging line EL-B, and the extension line EL-D may include a sensing pattern ES and a power pattern EV. The second line PL2-S may include a first pattern P2-1 and a second pattern P2-2.

[0225] The power supply pattern EV may be connected to the sensing pattern ES through a contact hole CNT-E penetrating the first dam pattern D1 in the non-display area NDA adjacent to the top end of the display area DA (see FIG. 7).

[0226] In this embodiment, the connection line EL-C2 may be disposed on the fourth insulating layer ISN4 and covered by the fifth insulating layer ISN5. The connection line EL-C2 may be formed and patterned in the same process as the fourth gate electrode G4 (the second gate electrode in the claims) described in FIG. 7 and may include the same material as the fourth gate electrode G4.

[0227] One end of the sensing pattern ES may be connected to one end of the connecting line EL-C2 through a contact hole CNT-C penetrating the fifth insulating layer ISN5.

[0228] In this embodiment, the bridge line EL-B may be disposed on the first insulating layer ISN1 and covered by the second insulating layer ISN2. The bridge line EL-B may be formed and patterned in the same process as the first gate electrode G1 described in FIG. 7 and may include the same material as the first gate electrode G1. In this embodiment, the other end of the connecting line EL-C2 may be connected to the bridge line EL-B through a contact hole CNT-B penetrating the second to fourth insulating layers ISN2 to ISN4.

[0229] 17 is a cross-sectional view of a display panel according to an embodiment of the present invention, in which the same or similar reference numerals as in FIGS. 1 to 11 are used for the same or similar components, and redundant descriptions will be omitted.

[0230] The extension line EL-D according to the present invention may include a sensing pattern ES and a power supply pattern EV. The sensing pattern ES and the power supply pattern EV may be disposed inside an outer dam DMP-O. The outer dam DMP-O may include first to fourth dam patterns D1, D2, D3, and D4 containing organic materials.

[0231] The sensing pattern ES may include first to third conductive patterns C1 to C3 stacked sequentially on the fifth insulating layer ISN5, and the power supply pattern EV may include first to third conductive patterns F1 to F3 stacked sequentially on the first dam pattern D1.

[0232] The first and third conductive patterns C1 and C3 may include titanium, and the second conductive pattern C2 may include aluminum. The thickness of the second conductive pattern C2 may be greater than the thicknesses of the first and third conductive patterns C1 and C3. According to one embodiment, the side surface CS of the second conductive pattern C2 is recessed toward the inside of the sensing pattern ES more than the side surfaces of the first and third conductive patterns C1 and C3. This may be due to a difference in etching rate of the first to third conductive patterns C1 to C3 with respect to the etching solution.

[0233] The first and third conductive patterns F1 and F3 may include titanium, and the second conductive pattern F2 may include aluminum. The thickness of the second conductive pattern F2 may be greater than the thickness of the first and third conductive patterns F1 and F3. According to one embodiment, the side surface FS of the second conductive pattern F2 is recessed toward the inside of the power pattern EV more than the side surfaces of the first and third conductive patterns F1 and F3. This may be due to a difference in etching rate of the first to third conductive patterns F1 to F3 with respect to the etching solution.

[0234] According to this embodiment, the side surfaces CS and FS of the second conductive patterns C2 and F2 may be covered with an insulating layer containing an organic material. For example, the side surface CS of the second conductive pattern C2 may be covered with a first dam pattern D1, and the side surface FS of the second conductive pattern F2 may be covered with a second dam pattern D2. This may prevent the side surfaces CS and FS of the second conductive patterns C2 and F2 from being oxidized. This may provide a sign panel DP6 including an extension line EL-D with improved reliability.

[0235] Although the present invention has been described above with reference to preferred embodiments, it will be understood by those skilled in the art or those with ordinary knowledge in the art that various modifications and changes can be made to the present invention without departing from the spirit and technical scope of the present invention as set forth in the claims below.

[0236] Therefore, the technical scope of the present invention should be determined by the claims, not by the contents described in the detailed description of the specification. [Explanation of symbols]

[0237] DD: Display device DP: Display panel DA: Display area NDA: Hidden area DMP-O: Outer dam DMP-I: Inner dam EL-T: Detection line EL-D: Extension line EL-C: Connecting line EL-B: Bridge line PL1: First power line PL2: Second power line ES: Sensing pattern EV: Power supply pattern

Claims

1. a substrate including a display area and a non-display area surrounding the display area; an insulating layer disposed over the substrate; pixels arranged in the display area; First power lines are arranged along a first direction, extend along a second direction intersecting the first direction, and are connected to the pixels to provide a first driving voltage; a first line disposed in the display area and connected to the pixel, a second line connected to the first line and disposed in the non-display area, and a second power line providing a second driving voltage having a level lower than the first driving voltage; a detection line disposed in the non-display area and surrounding at least a portion of the display area; The detection line is extension lines each extending along the second direction and spaced apart along the first direction with the display area therebetween; a bridge line extending along the first direction and connected to the first power line; a connecting line connecting one of the extension lines to one end of the bridge line and another of the extension lines to the other end of the bridge line, In a display device, the second line intersects with the connecting line on a plane.

2. the extension line is farther from the display area than the second line; The display device according to claim 1 , wherein the bridge line is closer to the display area than the second line.

3. Each of the extension lines is The display device of claim 1 , comprising: a sensing pattern; and a power pattern disposed on and connected to the sensing pattern.

4. an outer dam disposed in the non-display area and surrounding at least a portion of the display area; and an inner dam disposed between the outer dam and the display area; the outer dam includes first to fourth dam patterns sequentially stacked on the insulating layer, The display device of claim 3 , wherein the inner dam includes fifth and sixth dam patterns sequentially stacked on the insulating layer.

5. the sensing pattern is covered by the first dam pattern, and the power supply pattern is disposed on the first dam pattern and covered by the second dam pattern; The display device of claim 4 , wherein the power supply pattern is connected to the sensing pattern through at least one contact hole that penetrates the first dam pattern.

6. the sensing pattern and the power supply pattern each include first to third conductive patterns that are sequentially stacked, the first and third conductive patterns include titanium, and the second conductive pattern includes aluminum; The display device according to claim 5 , wherein the side surfaces of the second conductive pattern are recessed inward from the side surfaces of the first and third conductive patterns.

7. the first and second dam patterns include an organic material; the first dam pattern covers each side of the first to third conductive patterns of the sensing pattern; The display device according to claim 6 , wherein the second dam pattern covers each side of the conductive pattern of the power supply pattern.

8. the second line extends from the interior of the inner dam to the interior of the outer dam; The display device of claim 4 , wherein the second line includes a first pattern including the same material as the sensing pattern and a second pattern including the same material as the power supply pattern.

9. the first pattern and the second pattern contact each other inside the inner dam; The display device of claim 8 , wherein the first dam pattern is sandwiched between the first dam pattern and the second dam pattern.

10. each of the pixels includes an anode, a cathode disposed on the anode, and a light-emitting layer disposed between the anode and the cathode; The display device of claim 9 , wherein the cathode extends into the non-display area and contacts the second pattern.

11. Each of the pixels is a lower metal layer disposed over the substrate; a first semiconductor layer overlapping the lower metal layer; a first gate electrode overlapping the first semiconductor layer; a dummy electrode overlapping the first gate electrode; a second semiconductor layer spaced apart from the first semiconductor layer; a second gate electrode overlapping the second semiconductor layer; The display device of claim 10 , further comprising: a first connecting electrode connected to the first semiconductor layer; and a second connecting electrode connecting the first connecting electrode to the anode.

12. The insulating layer is a buffer layer disposed on the substrate and covering the lower metal layer; a first insulating layer disposed on the buffer layer and covering the first semiconductor layer; a second insulating layer disposed on the first insulating layer and covering the first gate electrode; a third insulating layer disposed on the second insulating layer and covering the dummy electrode; a fourth insulating layer disposed on the third insulating layer and covering the second semiconductor layer; a fifth insulating layer disposed on the fourth insulating layer and covering the second gate electrode; a sixth insulating layer disposed on the fifth insulating layer to cover the first connecting electrode, the sixth insulating layer including an organic material; a seventh insulating layer disposed on the sixth insulating layer to cover the second connecting electrode, the seventh insulating layer including an organic material; the first connecting electrode is connected to the first semiconductor layer through a first contact hole penetrating the first to fifth insulating layers; the second connecting electrode is connected to the first connecting electrode through a second contact hole penetrating the sixth insulating layer; The display device of claim 11, wherein the anode is connected to the second connecting electrode through a third contact hole that penetrates the seventh insulating layer.

13. a pixel defining layer disposed on the seventh insulating layer, the pixel defining layer defining a first opening exposing at least a portion of each of the anodes, the pixel defining layer including an organic material; The display device of claim 12 , further comprising: a spacer disposed on the pixel defining layer, defining a second opening overlapping the first opening, the spacer including an organic material.

14. the first dam pattern includes the same material as the sixth insulating layer; the second dam pattern includes the same material as the seventh insulating layer; the third dam pattern and the fifth dam pattern include the same material as the pixel defining layer; The display device of claim 13 , wherein the fourth dam pattern and the sixth dam pattern include the same material as the spacers.

15. the sensing pattern includes the same material as the first connecting electrode; The display device of claim 12 , wherein the power supply pattern includes the same material as the second connecting electrode.

16. the connection line is disposed on the first insulating layer and covered by the second insulating layer, and includes the same material as the first gate electrode; 16. The display device of claim 15, wherein the power supply pattern is connected to the connection line through a contact hole that penetrates the second to fifth insulating layers.

17. The display device of claim 15, wherein the bridge line is disposed on the first insulating layer and covered by the second insulating layer, and the connecting line and the bridge line are an integral pattern.

18. the bridge line is disposed on the second insulating layer and covered by the third insulating layer, and includes the same material as the dummy electrode; The display device of claim 15, wherein the bridge line is connected to the connection line through a contact hole that penetrates the second insulating layer.

19. the bridge line is disposed on the fourth insulating layer and covered by the fifth insulating layer, and includes the same material as the second gate electrode; 16. The display device of claim 15, wherein the bridge line is connected to the connection line through a contact hole that penetrates the second to fourth insulating layers.

20. the bridge line is disposed on the first insulating layer and covered by the second insulating layer, and includes the same material as the first gate electrode; the connection line is disposed on the second insulating layer and covered by the third insulating layer, and includes the same material as the dummy electrode; 16. The display device of claim 15, wherein the power supply pattern is connected to one end of the bridge line through a first contact hole that penetrates the third to fifth insulating layers, and the other end of the connection line is connected to the bridge line through a second contact hole that penetrates the second insulating layer.

21. the bridge line is disposed on the first insulating layer and covered by the second insulating layer, and includes the same material as the first gate electrode; the connection line is disposed on the fourth insulating layer and covered by the fifth insulating layer, and includes the same material as the second gate electrode; 16. The display device of claim 15, wherein the power supply pattern is connected to one end of the connection line through a first contact hole that penetrates the fifth insulating layer, and the other end of the connection line is connected to the bridge line through a second contact hole that penetrates the second and third insulating layers.

22. The display device according to claim 1 , wherein the second line has a width greater than the extension line on a plane.

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