Plasma excitation with ion energy control

Abstract

To provide plasma processing and biasing methods that are able to provide desirable plasma-assisted etching process results.SOLUTION: In a processing system, a waveform generator 500 for generating a waveform for substrate plasma processing includes a main voltage source 502 selectively coupled to an output node 504. The output node 504 is coupled to an electrode disposed within a processing chamber 100 and is selectively coupled to a ground node 508. The waveform generator 500 also includes a radio frequency (RF) signal generator 506 and a high-pass filter 546 coupled between the RF signal generator and the output node.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to systems used in semiconductor device manufacturing, and more particularly to plasma processing systems used to process substrates. [Background technology]

[0002] Reliably producing high aspect ratio features is one of the major technological challenges for next generation semiconductor devices. One method of forming high aspect ratio features uses a plasma-assisted etching process in which a plasma is formed in a processing chamber and ions from the plasma are accelerated toward the surface of the substrate to form openings in a layer of material disposed beneath a mask layer formed on the surface of the substrate.

[0003] In a typical plasma-assisted etching process, a substrate is placed on a substrate support disposed in a processing chamber, a plasma is formed above the substrate, and ions are accelerated from the plasma toward the substrate across a plasma sheath, i.e., an electron-depleted region, formed between the plasma and the surface of the substrate.

[0004] Conventional RF plasma-assisted etching processes, which simply supply a sinusoidal waveform containing an RF signal to one or more electrodes in a plasma processing chamber, have been found to not adequately or desirably control sheath characteristics and generated ion energy, which can lead to undesirable plasma processing results, which can include excessive sputtering of mask layers and the creation of sidewall defects in high aspect ratio features.

[0005] Therefore, there is a need in the art for plasma treatment and biasing methods that can provide desirable plasma-assisted etch process results. Summary of the Invention

[0006] SUMMARY OF THE INVENTION The embodiments provided herein generally include an apparatus, plasma processing system, and method for generating a waveform for plasma processing of a substrate in a processing chamber.

[0007] One embodiment of the present disclosure is directed to a waveform generator for plasma processing. The waveform generator generally includes a voltage source selectively coupled to an output node, the output node configured to be coupled to an electrode disposed within a processing chamber, the output node selectively coupled to a ground node, a radio frequency (RF) signal generator, and a first filter coupled between the RF signal generator and the output node.

[0008] One embodiment of the present disclosure is directed to a method for waveform generation that generally includes coupling a voltage source to an output node during a first phase of a waveform, the output node being coupled to an electrode disposed within a process chamber, and coupling a ground node to the output node during a second phase of the waveform, the RF signal generator being coupled to the output node through a filter.

[0009] One embodiment of the present disclosure is directed to an apparatus for waveform generation. The apparatus generally includes a memory and one or more processors coupled to the memory. The memory and the one or more processors are configured to: couple a voltage source to an output node during a first phase of a waveform, the output node being coupled to an electrode disposed in a process chamber; and couple a ground node to the output node during a second phase of the waveform, the RF signal generator being coupled to the output node through a filter.

[0010] So that the above-recited features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above can be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings depict only exemplary embodiments and therefore should not be considered limiting of its scope, as other equally effective embodiments may be recognized. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a schematic cross-sectional view of a processing system, according to one or more embodiments, configured to practice the methods described herein. [Figure 2A] FIG. 2 illustrates a voltage waveform that may be applied to electrodes of a processing chamber according to one or more embodiments. [Figure 2B] FIG. 2 illustrates a voltage waveform established on a substrate by a voltage waveform applied to an electrode of a processing chamber. [Figure 3A] FIG. 1 illustrates a typical ion energy distribution (IED) when using a single frequency excitation waveform. [Figure 3B] 1 is a graph illustrating an IED function (IEDF), according to some embodiments of the present disclosure. [Figure 4] 1A-1C illustrate waveforms generated using a waveform generator in accordance with some embodiments of the present disclosure. [Figure 5] FIG. 1 illustrates one exemplary implementation of a waveform generator for biasing a substrate to achieve IED control, in accordance with some aspects of the present disclosure. [Figure 6] 1A-1C illustrate exemplary filter topologies in accordance with some embodiments of the present disclosure. [Figure 7] 6 is a timing diagram illustrating the states of the switches of the waveform generator of FIG. 5 in accordance with some aspects of the present disclosure. [Figure 8] FIG. 1 is a process flow diagram illustrating a method for waveform generation. DETAILED DESCRIPTION OF THE INVENTION

[0012] As technology nodes progress toward 2 nm, the fabrication of smaller features with larger aspect ratios requires atomic precision for plasma processing. In etching processes where plasma ions play a key role, ion energy control is a challenge for the semiconductor equipment industry. Traditionally, RF bias techniques use sinusoidal waves to excite the plasma and accelerate ions.

[0013] Some embodiments of the present disclosure are generally directed to techniques for generating waveforms to control ion energy distribution (IED). For example, a pulsed voltage waveform and a radio frequency (RF) waveform may be applied to the same node in a plasma chamber to implement low-energy and high-energy peaks in an IED function with few intermediate energies between the low-energy and high-energy peaks, as described in more detail herein. Ions associated with the high-energy peak have energy and directionality that allow them to reach the bottom of a high-aspect ratio feature being etched and enable the etching reaction. Although ions with low energy cannot reach the bottom of the feature during etching, low-energy ions are still important to the etching process. Ions with intermediate energy are not beneficial to the etching process because they do not have the desired directionality and will strike the sidewall of the feature being etched, often resulting in undesirable bowing of the sidewall in the etched feature. Some embodiments are directed to techniques for generating waveforms with high-energy and low-energy peaks with few intermediate-energy ions.

[0014] Plasma processing system example 1 is a schematic cross-sectional view of a processing system 10 configured to perform one or more of the plasma processing methods described herein. In some embodiments, the processing system 10 is configured for a plasma-assisted etching process, such as a reactive ion etching (RIE) plasma process. However, it should be noted that the embodiments described herein may also be used with processing systems configured for use in other plasma-assisted processes, such as a plasma deposition process, e.g., a plasma-enhanced chemical vapor deposition (PECVD) process, a plasma-enhanced physical vapor deposition (PEPVD) process, a plasma-enhanced atomic layer deposition (PEALD) process, a plasma treatment process, or a plasma-based ion implantation process, e.g., a plasma doping (PLAD) process.

[0015] As shown, the processing system 10 is configured to form a capacitively coupled plasma (CCP), where the processing chamber 100 includes an upper electrode (e.g., a chamber lid 123) disposed in a processing volume 129, the upper electrode facing a lower electrode (e.g., a substrate support assembly 136) also disposed in the processing volume 129. In a typical capacitively coupled plasma (CCP) processing system, a radio frequency (RF) source is electrically coupled to one of the upper or lower electrodes and provides an RF signal, which is capacitively coupled to each of the upper and lower electrodes and configured to ignite and sustain a plasma (e.g., plasma 101) disposed in a processing region between the upper and lower electrodes. Typically, the opposing one of the upper or lower electrodes is coupled to ground or to a second RF power source for additional plasma excitation. As shown, the processing system 10 includes the processing chamber 100, the support assembly 136, and a system controller 126.

[0016] The processing chamber 100 generally includes a chamber body 113 including a chamber lid 123, one or more sidewalls 122, and a chamber base 124 that collectively define a processing volume 129. The one or more sidewalls 122 and the chamber base 124 generally comprise a material sized and shaped to provide structural support for the elements of the processing chamber 100 and are configured to withstand pressure and added energy applied to the one or more sidewalls 122 and the chamber base 124 while a plasma 101 is generated within a vacuum environment maintained in the processing volume 129 of the processing chamber 100 during processing. In one example, the one or more sidewalls 122 and the chamber base 124 are formed from a metal, such as aluminum, an aluminum alloy, or a stainless steel alloy.

[0017] A gas inlet 128 disposed through the chamber lid 123 is used to supply one or more process gases to the process volume 129 from a process gas source 119 that is fluidly connected to the process volume 129. The substrate 103 is loaded into and removed from the process volume 129 through an opening (not shown) in one of the one or more sidewalls 122, which is sealed with a slit valve (not shown) during plasma processing of the substrate 103.

[0018] In some embodiments, a plurality of lift pins 20 movably disposed through openings formed in the substrate support assembly 136 are used to facilitate substrate transfer to and from the substrate support surface 105A. In some embodiments, the plurality of lift pins 20 are disposed above, coupled to, and / or engageable with a lift pin hoop (not shown) disposed in the processing volume 129. The lift pin hoop may be coupled to a shaft (not shown) that sealingly extends through the chamber base 124. The shaft may be coupled to an actuator (not shown) used to raise and lower the lift pin hoop. When the lift pin hoop is in the raised position, the lift pin hoop engages the plurality of lift pins 20 to raise the upper surfaces of the lift pins above the substrate support surface 105A, lifting the substrate 103 from the substrate support surface 105A and allowing a robotic handler (not shown) to access the inactive (backside) surface of the substrate 103. When the lift pin hoop is in the lowered position, the plurality of lift pins 20 are flush with or recessed below the substrate support surface 105A and the substrate 103 rests on the substrate support surface 105A.

[0019] The system controller 126, also referred to herein as a processing chamber controller, includes a central processing unit (CPU) 133, memory 134, and support circuits 135. The system controller 126 is used to control the process sequence used to process the substrate 103, including the substrate bias method described herein. The CPU 133 is a general-purpose computer processor configured for use in an industrial setting to control the processing chamber and its associated sub-processors. The memory 134, described herein as generally non-volatile memory, may include random access memory, read-only memory, floppy or hard disk drives, or other suitable forms of local or remote digital storage. The support circuits 135 are conventionally coupled to the CPU 133 and include cache, clock circuits, input / output subsystems, power supplies, etc., or combinations thereof. Software instructions (programs) and data may be coded and stored in the memory 134 to instruct the processor in the CPU 133. Software programs (or computer instructions) readable by the CPU 133 in the system controller 126 determine which tasks are performable by the components in the processing system 10.

[0020] Generally, a program readable by the CPU 133 in the system controller 126 includes code that, when executed by the processor (CPU 133), performs tasks related to the plasma processing regimes described herein. The program may include instructions used to control various hardware and electrical components within the processing system 10 to perform various process tasks and sequences used to implement the methods described herein. In one embodiment, the program includes instructions used to perform one or more of the operations described below with respect to FIG. 8.

[0021] The plasma control system generally includes a first source assembly 196 for establishing at least a first pulsed voltage (PV) waveform at the bias electrode 104 and a second source assembly 197 for establishing at least a second PV waveform at the edge control electrode 115. The first PV waveform or the second PV waveform may be generated using one or more components in a waveform generator assembly 150, which may correspond to the waveform generators described in more detail herein with respect to FIGS. 4 and 5. In some embodiments, the waveform generator supplies an RF signal to the support base 107 (e.g., a powered electrode or cathode) or the bias electrode 104, which may be used to generate (sustain and / or ignite) the plasma 101 in a processing region disposed between the substrate support assembly 136 and the chamber lid 123.

[0022] In some embodiments, an RF signal is used to ignite and sustain the processing plasma 101 using a process gas disposed in the processing volume 129 and an electric field generated by RF power (RF signal) supplied to the support base 107 and / or bias electrode 104. In some aspects, the RF signal may be generated by a waveform generator assembly 150. The processing volume 129 is fluidly coupled to one or more dedicated vacuum pumps through a vacuum outlet 120, which maintain the processing volume 129 at subatmospheric conditions and evacuate the processing gas and / or other gases from the processing volume 129. In some embodiments, a substrate support assembly 136 disposed in the processing volume 129 is grounded and disposed on a support shaft 138 that extends through the chamber base 124. The waveform generator assembly 150 may include an RF generator 506, as shown in FIG. 5. As shown in FIG. 5, the RF generator 506 may, in some embodiments, be implemented using an RF signal source 580 and an RF matching network 582. In some embodiments, as described further below, the RF generator 506 is configured to provide an RF signal having a frequency greater than 40 MHz, such as between about 40 MHz and about 200 MHz.

[0023] The substrate support assembly 136, briefly described above, generally includes a substrate support 105 (e.g., an ESC substrate support) and a support base 107. In some embodiments, the substrate support assembly 136 may further include an insulator plate 111 and a grounded plate 112, as described further below. The support base 107 is electrically insulated from the chamber base 124 by the insulator plate 111, and the grounded plate 112 is interposed between the insulator plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to and disposed on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105 and the substrate 103 disposed on the substrate support 105 during substrate processing. In some embodiments, the support base 107 includes one or more cooling channels (not shown) disposed therein, the one or more cooling channels being fluidly coupled to and in fluid communication with a coolant source (not shown), such as a refrigerant source or a water source having a relatively high electrical resistance. In some embodiments, the substrate support 105 includes a heater (not shown), such as a resistive heating element embedded in the dielectric material of the substrate support 105. Herein, the support base 107 is formed from a corrosion-resistant, thermally conductive material, such as a corrosion-resistant metal, e.g., aluminum, an aluminum alloy, or stainless steel, and is coupled to the substrate support with an adhesive or by mechanical means.

[0024] Typically, the substrate support 105 is formed from a dielectric material, such as a corrosion-resistant metal oxide or metal nitride material, e.g., aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (YO3), mixtures thereof, or combinations thereof, or a bulk-sintered ceramic material. In embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded in the dielectric material of the substrate support 105.

[0025] In one configuration, the bias electrode 104 is a chucking pole used to secure (i.e., chuck) the substrate 103 to the substrate support surface 105A of the substrate support 105 and to bias the substrate 103 with respect to the processing plasma 101 using one or more of the pulsed voltage biasing schemes described herein. Generally, the bias electrode 104 is formed from one or more conductive portions, such as one or more metal meshes, foils, plates, or combinations thereof.

[0026] In some embodiments, bias electrode 104 is electrically coupled to a clamping network that uses an electrical conductor, such as a coaxial power supply line 106 (e.g., a coaxial cable), to provide a chucking voltage to bias electrode 104, such as a static DC voltage between about −5000 V and about 5000 V. As described further below, the clamping network includes a DC power supply 155 (e.g., a high-voltage DC (HVDC) power supply) and a filter 151 (e.g., a low-pass filter).

[0027] The substrate support assembly 136 may further include an edge control electrode 115, which is disposed below the edge ring 114, surrounds the bias electrode 104, and / or is disposed a distance from the center of the bias electrode 104. Generally, for a processing chamber 100 configured to process a circular substrate, the edge control electrode 115 is annular in shape, made of a conductive material, and configured to surround at least a portion of the bias electrode 104. In some embodiments, such as that shown in FIG. 1, the edge control electrode 115 is disposed within the region of the substrate support 105. In some embodiments, as shown in FIG. 1, the edge control electrode 115 comprises a conductive mesh, foil, and / or plate disposed a similar distance (i.e., in the Z direction) from the substrate support surface 105A of the substrate support 105 as the bias electrode 104.

[0028] The edge control electrode 115 may be biased through the use of a waveform generator assembly that is different from the waveform generator assembly 150 used to bias the bias electrode 104. In some embodiments, the edge control electrode 115 may be biased through the use of a waveform generator assembly 150 that is also used to bias the bias electrode 104 by splitting a portion of the power to the edge control electrode 115. In one configuration, a first waveform generator assembly 150 of the first source assembly 196 is configured to bias the bias electrode 104, and a second waveform generator assembly 150 of the second source assembly 197 is configured to bias the edge control electrode 115.

[0029] A power supply line 157 electrically connects the output of the waveform generator assembly 150 of the first source assembly 196 to the bias electrode 104. The following description primarily describes the power supply line 157 of the first source assembly 196, which is used to couple the waveform generator assembly 150 to the bias electrode 104, although the power supply line 158 of the second source assembly 197, which couples the waveform generator assembly 150 to the edge control electrode 115, will include the same or similar components. The electrical conductor(s) in the various portions of the power supply line 157 may include one or a combination of: (a) coaxial cables, such as a flexible coaxial cable connected in series with a rigid coaxial cable; (b) insulated high-voltage corona-resistant hook-up wire; (c) bare wire; (d) metal rods; (e) electrical connectors; or (f) any combination of the electrical elements in (a)-(e).

[0030] In some embodiments, the processing chamber 100 further includes a quartz pipe 110 or collar that at least partially circumscribes portions of the substrate support assembly 136 to prevent the substrate support 105 and / or support base 107 from contacting corrosive process gases or plasma, cleaning gases or plasma, or their by-products. Generally, the quartz pipe 110, insulator plate 111, and ground plate 112 are circumscribed by a liner 108. In some embodiments, a plasma screen 109 is disposed between the cathode liner 108 and the sidewall 122 to prevent plasma from forming in a volume below the plasma screen 109 between the liner 108 and one or more sidewalls 122.

[0031] FIG. 2A shows a voltage waveform that can be established at an electrode in a processing chamber. FIG. 2B shows an example of a different type of voltage waveform 225 and a voltage waveform 230 established at a substrate by different voltage waveforms similar to those shown in FIG. 2A, which are separately established at electrodes in a processing chamber. The waveforms include two stages, an ion current stage and a sheath collapse stage, as shown. At the beginning of the ion current stage, a drop in the substrate voltage creates a high-voltage sheath above the substrate, accelerating positive ions toward the substrate. Positive ions bombarding the surface of the substrate during the ion current stage deposit positive charge on the substrate surface, which, if uncompensated, causes the substrate voltage to gradually increase positive during the ion current stage, as shown by voltage waveform 225 in FIG. 2B. However, uncontrolled accumulation of positive charge on the substrate surface undesirably gradually discharges the sheath capacitor and chuck capacitor, slowly decreasing the sheath voltage drop and bringing the substrate potential closer to zero, as shown by voltage waveform 225. The accumulation of positive charge causes a voltage droop in the voltage waveform established at the substrate (FIG. 2B). However, as shown in FIG. 2A, a voltage waveform established at the electrode with a negative slope during the ion current stage can be generated to establish a square region (e.g., a near-zero slope) for the established substrate voltage waveform, as shown by curve 230 in FIG. 2B. Implementing a slope in the waveform established at the electrode during the ion current stage is sometimes referred to as current compensation. The voltage difference between the beginning and end of the ion current phase determines the ion energy distribution function (IEDF) width. The larger the voltage difference, the wider the IEDF width. To achieve monoenergetic ions and a narrower IEDF width, an operation is performed to flatten the substrate voltage waveform in the ion current phase using current compensation. In some embodiments of the present disclosure, an RF signal is overlaid on the voltage waveform shown in FIG. 2A.

[0032] Generation techniques for waveform generation Some present embodiments are generally directed to techniques for waveform generation that facilitate plasma processing of substrates using simultaneous plasma generation and ion energy distribution (IED) control while reducing undesirable IED bowing profiles formed in etched high aspect ratio features. For example, a pulsed voltage (PV) waveform may be generated with an RF signal overlaid on the PV waveform. In some embodiments, the generated waveform may also include a ramp signal to facilitate current compensation, as described herein.

[0033] FIG. 3A illustrates a typical IED when using a single RF frequency excitation waveform. As shown, the IED has a bimodal shape, with a high-energy peak 306, a low-energy peak 302, and intermediate-energy ions (e.g., associated with an intermediate-energy region 304). From the perspective of the plasma etching process, only ions at or near the high-energy peak have the energy and directionality to overcome ion-generated charging effects created in the material being etched, reach the bottom of the feature, and enable the etching reaction. Ions with intermediate energies are not beneficial to the etching process because they lack directionality and tend to strike the sidewalls of the feature, often resulting in an undesirable IED bowing profile. Ions with low energies are important to the etching process because they clean the mask surface, maintain the shape of the mask layer, and prevent hole clogging. Some embodiments of the present disclosure are directed to creating an energy profile with a high-energy peak and a low-energy peak, with little intermediate energy between the high-energy peak and the low-energy peak.

[0034] FIG. 3B is a graph illustrating an IED function (IEDF) in accordance with some embodiments of the present disclosure. As shown, the IEDF includes a low-energy peak 301 and a high-energy peak 303. The energy associated with the low-energy peak can be less than a few hundred eV (e.g., less than 1K eV), while the energy associated with the high-energy peak can be from a few hundred eV to tens of thousands of eV, depending on the aspect ratio of the feature to be formed in the substrate. For example, in some cases, the energy associated with the high-energy peak can be between 4K eV and 10K eV. As shown, there are no ions (or at least fewer than in conventional implementations) between the low-energy peak 301 and the high-energy peak 303. Some embodiments are directed to techniques for implementing the ion energy distribution shown in FIG. 3B using waveform adjustment techniques, as described in more detail herein.

[0035] 4 illustrates a waveform 400 generated using a waveform generator in accordance with some embodiments of the present disclosure. As shown, waveform 400 includes waveform region 401 and waveform region 405. Waveform region 401 includes a direct current (DC) signal overlaid with RF signal 404, and waveform region 405 includes a voltage ramp (e.g., for current compensation) overlaid with RF signal 404.

[0036] The RF signal 404 sustains the plasma in the chamber, creating the low-energy peak 301 described with reference to FIG. 3B . In some embodiments, the RF signal 404 may have a frequency between 40 MHz and 200 MHz. The frequency of the RF signal 404 may be higher than the ion sheath transit frequency. In this case, the average ion transit time across the sheath thickness is longer than the period of the RF signal 404, causing ions to experience multiple cycles of the RF signal 404 and acquire the average energy associated with the multiple cycles, creating the low-energy peak 301. Thus, ions are accelerated by the average sheath potential induced by the RF signal 404, thus achieving a single ion energy peak. High-frequency RF excitation creates ions with a mono-energy peak. In other words, ions traveling across the sheath experience the average sheath potential driven by the RF signal 404, creating a single ion energy peak rather than a continuous energy distribution.

[0037] During a portion of the pulse waveform cycle, plasma bulk electrons are attracted to the surface of the substrate (e.g., substrate 103) by the rising edge 402 of the pulse step. However, the plasma bulk electrons may not be able to establish a negative DC sheath potential to create the higher energy peak 303. The substrate surface and the electrode (e.g., support base 107) are connected to the electrostatic chuck capacitor (C esc)), which in some embodiments comprises a dielectric material layer of the substrate support 105 disposed between the bias electrode 104 and the substrate support surface 105A, as shown in FIG. 1. There is an equal amount of positive charge on the electrode (e.g., compared to the negative charge on the substrate) to cancel the electric field generated by the plasma bulk electrons. At the trailing edge 403 of the waveform 400, ions are neutralized by electrons due to the application of the waveform to the electrode. Thus, a negative DC sheath potential is established on the substrate surface. This is the origin of the higher energy peak 303. The DC sheath potential (Vdc), or higher ion energy, is determined by the magnitude (ΔV) of the trailing edge and the esc and sheath capacitance (C sheath ) and based on the following equation: TIFF2025157283000002.tif14170 Thus, waveform region 401 serves to sustain a plasma in the chamber (eg, while creating lower energy peak 301) and establish a DC sheath potential for higher energy peak 303.

[0038] As the incoming ions neutralize electrons on the substrate surface, the DC sheath potential will decrease in the absence of a means of compensation. Thus, the ions incident on the substrate are no longer monoenergetic. In some embodiments, a voltage ramp is implemented during the waveform region 405 to provide an increasing amount of electrons to the electrodes to counteract the otherwise increasing electric field caused by the positive charge from the incoming ions, thereby maintaining a constant sheath potential (monoenergetic peak). The DC supply current to implement the ramp can be controlled to equalize and compensate for the ion current provided during the ion current stage. The ion current (I ion ) is calibrated by using ion energy diagnostics or calculated by sampling the electrode voltage (V) and sheath potential values ​​(e.g., to calculate the time derivative of V), based on the following equation: As shown in TIFF2025157283000003.tif14170, an RF signal 404 may also be overlaid on the ramp signal in region 405 to continue to sustain a plasma in the chamber (e.g., while creating the lower energy peak 301) and establish a DC sheath potential for the higher energy peak 303.

[0039] 5 illustrates an exemplary implementation of a waveform generator 500 for biasing a substrate to achieve IED control, according to some embodiments of the present disclosure. The waveform generator 500 may be used to implement the waveform generator assembly 150, as described with respect to FIG. 1. As shown, the waveform generator 500 may generate the waveform 400 described with respect to FIG. 4.

[0040] The waveform generator 500 includes a main voltage source 502 (e.g., a DC voltage source) for implementing a positive voltage during the waveform region 401, a current source 505 for implementing a ramp voltage during the waveform region 405, and an RF generator 506 (also referred to as an RF signal generator) for providing an RF signal 404. The waveform generator 500 generates the waveform 400 at an output node 504. The output node 504 may be coupled to a bias electrode 104 or a support base 107 in a substrate support 105 (e.g., a ceramic puck). When the output node 504 is coupled to the support base 107, the total capacitance (e.g., 1 / C total =1 / C esc +1 / C SB where C SB is the capacitance of a dielectric layer disposed between the support base 107 and the bias electrode 104) is esc ) is larger than the capacitance C esc This can result in a lower voltage drop across the sheath and a higher voltage drop on the sheath.

[0041] As shown, a switch 520 (e.g., a high-voltage solid-state relay) may be coupled between a main voltage source 502 and an output node 504, and a switch 522 (e.g., a high-voltage solid-state relay) may be coupled between a ground node 508 and the output node 504. As shown, an RF filter 540 may be implemented in a path between the voltage source 502 and the switch 520, an RF filter 542 may be implemented in a path between the ground node 508 and the switch 522, and an RF filter 544 may be implemented between the current source 505 and the output node 504. RF filters 540, 542, 544 may be implemented as low-pass filters configured to block RF signal(s) provided from an RF generator 506. The voltage source 502 and the current source 505 are protected from the output of the RF generator 506 by the respective RF filters 540, 544. In other words, the RF filters 540, 544 are configured to block high-frequency RF signals provided from the RF generator 506. The ground node 508 is isolated from the RF generator 506 by an RF filter 542 (e.g., a low-pass filter) when the switch 522 is closed. In some embodiments, each of the RF filters 540, 542, 544 may be implemented as a parallel LC topology, as shown in FIG.

[0042] 6 shows a parallel LC filter topology 600 having a capacitive element 602 and an inductive element 604. As shown, the capacitive element 602 may be coupled in parallel with the inductive element 604 and between a node 610 and a node 612. Each of the RF filters 540, 542, 544 may be implemented using the parallel LC filter topology 600. For example, for the RF filter 542, the node 610 may be coupled to the ground node 508, and the node 612 may be coupled to the switch 522. As an example, for a 40 MHz RF signal, the capacitive element 602 may be 100 picofarads (pF) and the inductive element 604 may be 158 nanohenries (nH) to block the 40 MHz RF signal. In other words, the LC filter topology 600 is a resonant circuit that effectively acts as an open circuit for the 40 MHz signal, isolating the voltage source 502, the ground node 508, or the current source 505 from the 40 MHz RF signal.

[0043] FIG. 7 is a timing diagram 700 illustrating the states of switch 520 (labeled “S1”) and switch 522 (labeled “S2”) according to some embodiments of the present disclosure. As shown, switch 520 and switch 522 are not closed simultaneously to avoid electrically shorting voltage source 502 to ground node 508. In some embodiments, during phase 1 of a waveform cycle (e.g., a cycle of waveform 400), switch 520 may be closed to create rising edge 402 as shown in FIG. 4. Switch 520 may be closed for a period ranging from 20 ns to 2000 ns to allow a sufficient number of electrons to collect at the substrate surface. After a period associated with waveform region 401, switch 520 may be opened and switch 522 may be closed to create falling edge 403 during phase 2 of the waveform cycle. After opening switch S1, switch S2 may be closed for a time period ranging from 10 ns to 100 ns.

[0044] In some embodiments, during phase 1 while switch S1 is closed, positive charge accumulates on substrate 103 shown in FIG. 1 . The voltage on substrate 103 cannot change instantaneously due to capacitive effects. Therefore, during phase 2, when switch S1 is opened and switch S2 is closed, the voltage at output node 504 (e.g., at electrode 104 shown in FIG. 1 ) drops from a positive voltage to a negative voltage, as shown in FIG. 4 . The drop from a positive voltage to a negative voltage is believed to be due to negative charge forming on electrode 104, offsetting the positive charge on substrate 104. In other words, the positive charge on substrate 103 attracts electrons to electrode 104, causing output node 504 to drop to a negative voltage when switch S2 is closed.

[0045] 5, RF generator 506 and current source 505 may always be connected to output node 504 (e.g., to the chamber). In some embodiments, a high-pass filter 546 may be coupled between RF generator 506 and output node 504. High-pass filter 546 isolates the RF generator from DC components at output node 504 (e.g., caused by current source 505 when switch 520 is closed, voltage source 502, or ground node 508 when switch 522 is closed). High-pass filter 546 may, in some embodiments, be implemented as an alternating current (AC) blocking capacitor.

[0046] In some embodiments, impedance 570 may be coupled between the output of current source 505 and the ground node to shunt the output current from current source 505 when switch 520 is closed. In other words, an abrupt impedance change may occur due to the coupling of voltage source 502 to output node 504. Impedance 570 provides a flow path for current from current source 505 to ground when switch 520 is closed, allowing for a gradual decrease in current from current source 505 after rising edge 402. As shown, impedance 570 may be implemented using an inductor-resistor (RL) circuit having inductive element 574 and resistive element 572. When using a 40 MHz RF signal, the impedance of the inductive element may be 2 microhenries (μH), and the resistance of resistive element 572 may be 100 ohms.

[0047] Embodiments of the present disclosure provide a process-friendly dual-peak IED and a method for achieving such an IED on a substrate surface for a plasma processing chamber with simultaneous plasma excitation and sustainment. One advantage of embodiments of the present disclosure compared to traditional ion energy control techniques is simultaneous plasma generation and IED control. After one PV waveform cycle is completed, multiple additional PV waveform cycles will be repeated multiple times consecutively, as shown in FIG. 4 by the partial view of the repeating second voltage waveform cycle. In some embodiments, the voltage waveform established at the electrodes is determined by the ion current time period (e.g., the length of the waveform region 405) and the waveform period T P (e.g., the length of waveform region 401 plus the length of waveform region 405), and has an on-time greater than 50% or greater than 70%, such as between 80% and 95%. In some embodiments, the period T Pis continuously repeated in a PV waveform burst, with a burst period being between about 100 microseconds (μs) and about 10 milliseconds (ms). The PV waveform burst can have a burst duty cycle that is between about 5% and 100%, such as between about 50% and about 95%, where the duty cycle is the ratio of the burst period divided by the burst period plus the non-burst period (i.e., no PV waveform is generated) that separates the burst periods.

[0048] 8 is a process flow diagram illustrating a method 800 for waveform generation. Method 800 may be performed by a waveform generation system including a waveform generator, such as waveform generator 500, and / or a system controller, such as system controller 126.

[0049] At activity 802, the waveform generation system couples a voltage source (e.g., voltage source 502) to an output node (e.g., output node 504) (e.g., by closing switch 520) during a first phase (e.g., phase 1 shown in FIG. 7) of a waveform (e.g., waveform 400). The output node may be coupled to an electrode disposed within a processing chamber (e.g., processing chamber 100). For example, the output node may be coupled to electrode 104 or support base 107.

[0050] At activity 804, the waveform generation system couples a ground node (e.g., ground node 508) to the output node (e.g., by closing switch 522) during the second phase of the waveform (e.g., phase 2 shown in FIG. 7). In some embodiments, an RF signal generator (e.g., RF generator 506) is coupled to the output node through a filter (e.g., filter 546) during the first phase. The RF signal generator may be coupled to the output node during the first, second, and third phases of the waveform (e.g., phase 3 shown in FIG. 7). The voltage source and ground node are decoupled from the output node (e.g., by opening switches 520, 522) during the third phase. In some embodiments, the voltage source is coupled to the output node through a filter (e.g., filter 540) and the ground node is coupled to the output node through a filter (e.g., filter 542).

[0051] In some embodiments, a current source (e.g., current source 505) is coupled to the output node during the third phase of the waveform, and the voltage source and ground node are decoupled from the output node during the third phase. The current source may be coupled to the output node through a filter (e.g., filter 544).

[0052] The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object A physically contacts object B, and object B contacts object C, then objects A and C may still be considered coupled to one another even though objects A and C are not in direct physical contact with one another. For example, a first object may be coupled to a second object even though the first object is never in direct physical contact with the second object.

[0053] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, which scope is determined by the following claims.

Claims

1. 1. A waveform generator for plasma processing, comprising: a voltage source selectively coupled to the output node, the output node is configured to be coupled to an electrode disposed within a processing chamber; the output node is selectively coupled to a ground node; a voltage source; a radio frequency (RF) signal generator; a first filter coupled between the RF signal generator and the output node; A waveform generator comprising:

2. 10. The waveform generator of claim 1, wherein the waveform generator is configured to generate a pulsed voltage signal by selectively coupling the voltage source and the ground node to the output node, and the RF signal generator is configured to generate an RF signal overlaid on the pulsed voltage signal.

3. The waveform generator of claim 1 , wherein the first filter comprises a high-pass filter.

4. 2. The waveform generator of claim 1, wherein the voltage source is selectively coupled to the output node through a switch.

5. 2. The waveform generator of claim 1, wherein the ground node is selectively coupled to the output node through a switch.

6. 10. The waveform generator of claim 1, further comprising a second filter coupled between the voltage source and the output node.

7. The waveform generator of claim 1 further comprising a second filter coupled between the ground node and the output node.

8. The waveform generator of claim 7 , wherein the second filter comprises a low pass filter.

9. 9. The waveform generator of claim 8, wherein the low pass filter comprises a capacitive element in parallel with an inductive element.

10. a current source coupled to the output node; a second filter coupled between the current source and the output node; 10. The waveform generator of claim 1 further comprising:

11. a first switch configured to couple the voltage source to the output node during a first phase; a second switch configured to couple the output node to the ground node during a second phase; and 11. The waveform generator of claim 10, further comprising: the first switch and the second switch further configured to decouple the voltage supply and the ground node from the output node during a third phase; and the RF signal generator is coupled to the output node during the third phase.

12. 11. The waveform generator of claim 10, further comprising an impedance coupled between the current source and the ground node.

13. The waveform generator of claim 12 , wherein the impedance comprises an inductive element and a resistive element.

14. 1. An apparatus for waveform generation, comprising: Memory and one or more processors coupled to the memory; wherein the memory and the one or more processors: coupling a voltage source to an output node during a first phase of the waveform, the output node being coupled to an electrode disposed within the processing chamber; coupling a ground node to the output node during a second phase of the waveform; a radio frequency (RF) signal generator coupled to the output node through a filter during the first phase; Device.

15. 15. The apparatus of claim 14, wherein a current source is coupled to the output node during a third phase of the waveform, and the voltage source and the ground node are decoupled from the output node during the third phase.

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