Semiconductor device

Abstract

To provide a circuit technique which enables reduction in power consumption and higher definition of a display device.SOLUTION: A switch controlled by a start signal is provided on a gate electrode of a transistor, which is connected to a gate electrode of a bootstrap transistor. When the start signal is input, a potential is supplied to the gate electrode of the transistor through the switch, and the transistor is turned off. The transistor is turned off, so that leakage of a charge from the gate electrode of the bootstrap transistor can be prevented. Accordingly, the time for storing a charge in the gate electrode of the bootstrap transistor can be shortened, and high-speed operation can be performed.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a display device having a circuit configured using transistors. Display devices that use electro-optical elements such as light-emitting elements or light-emitting elements as display media, and and a driving method thereof. [Background technology]

[0002] In recent years, the development of display devices has been actively promoted due to the increase in large display devices such as LCD TVs. In particular, non-crystalline semiconductor (hereinafter referred to as amorphous silicon) is used on an insulating substrate. A driving circuit including a pixel circuit and a shift register is formed by using a transistor configured as above. The technology of forming an integrated circuit (hereinafter referred to as internal circuit) has contributed greatly to reducing power consumption and costs. The internal circuit formed on the insulating substrate is Controller I via C (Flexible Printed Circuit) C (hereinafter also referred to as an external circuit) and its operation is controlled.

[0003] Among the internal circuits shown above, transistors made of amorphous semiconductors (hereinafter referred to as A shift register using amorphous silicon transistors (also known as amorphous silicon transistors) has been devised. The flip-flop configuration of a conventional shift register is shown in Figure 100(A) (Patent Reference 1). The flip-flop in Figure 100(A) is a transistor 11 (bootstrap transistor), transistor 12, transistor 13, transistor 14, transistor a signal line 21, a signal line 22, a transistor 15, a transistor 16, and a transistor 17; The signal line 21 is connected to the wiring 23, the signal line 24, the power supply line 25, and the power supply line 26. 22, signal line 24, power supply line 25, and power supply line 26 are respectively connected to a start signal and a reset signal. , a clock signal, a power supply potential VDD, and a power supply potential VSS are input. The operation period of the flip-flop is as shown in the timing chart of Figure 100(B). It is divided into a period, a selection period, a reset period, and a non-selection period.

[0004] During the set period, an H signal is input from the signal line 21, and the potential of the node 41 is set to VDD-V th15 (Vth15: threshold voltage of transistor 15) The transistor 11 is turned on, and the node 41 is left floating. When an H signal is input from the line 21, the transistor is turned on, and the gate electrode is connected to the node 41. By turning on the transistor 14 connected to the node 42 and setting the potential of the node 42 to the L level, the transistor In other words, after the H signal is input to the signal line 21, the transistor 16 is turned off. During the period until the transistor 16 is turned off, charge leaks from the gate electrode of the transistor 11. .

[0005] Here, a signal whose potential is VDD is called an H signal, and a signal whose potential is VSS is called an L signal. Moreover, the L level means that the potential of the L signal is VSS.

[0006] The display devices of Non-Patent Document 1 and Non-Patent Document 2 use amorphous silicon transistors. The shift register configured as a scanning line driver circuit is used to drive the R, G, and B sub-pixels. By inputting the video signal from a single signal line, the number of signal lines is reduced to one-third. In this way, the display devices of Non-Patent Document 1 and Non-Patent Document 2 are Reducing the number of connections. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-157508 [Non-patent literature]

[0008] [Non-Patent Document 1] Jin Young Choi, et al., “A Compact and Cost-efficient TFT-LCD through the Triple-Gate Pixel Structure”, SOCIETY FOR INFORMATION DISPLAY 2006 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVII, p.274-276 [Non-patent document 2] Yong Soon Lee, et al., “Advanced TFT-LCD Data Line Reduction Method”, SOCIETY FOR INFORMATION DISPLAY 2006 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVII, p.1083-1086 Summary of the Invention [Problem to be solved by the invention]

[0009] According to the conventional technology, the bootstrap transistor is turned on while the bootstrap is turned on. However, in the conventional technology, the gate electrode of the top transistor is in a floating state. , while the bootstrap transistor is turned on, It takes time to make the gate electrode floating, so it cannot operate at high speed. Furthermore, when amorphous silicon is used as the semiconductor layer of a transistor, In this case, there is a problem that the threshold voltage of the transistor shifts. It is proposed to reduce the number of contacts between the display panel and the driver IC by one-third. However, in practice, the number of contacts on the driver IC should be reduced. There is a need to further reduce emissions.

[0010] That is, the problem that cannot be solved by the conventional technology is that the shift register can operate at high speed. Circuit technology, including suppressing fluctuations in the threshold voltage of transistors, remains an issue. In addition, we are developing a technology to reduce the number of contacts on the driver IC mounted on the display panel, Other issues that remain are increasing power consumption and increasing the size or resolution of display devices. [Means for solving the problem]

[0011] The display device of this specification is a transistor connected to the gate electrode of the bootstrap transistor. A switch controlled by a start signal is provided at the gate electrode of the transistor. When a start signal is input, a potential is supplied to the gate electrode of the transistor via the switch. When the transistor is turned off, the bootstrap This can prevent leakage of electric charges from the gate electrode of the wrap transistor. This shortens the time required to charge the gate electrode of the bootstrap transistor. Therefore, high speed operation is possible.

[0012] The switches shown in this document (such as the specification, claims or drawings) may be of various types. Examples include electrical switches and mechanical switches. In other words, anything that can control the flow of current is acceptable, and is not limited to a specific type. For example, a transistor (e.g., bipolar transistor, MOS transistor) can be used as a switch. diodes (e.g., PN diodes, PIN diodes, Schottky diodes, etc.), Diode, MIM (Metal Insulator Metal) diode, MIS (Metal Insulator Semiconductor) Diode A thyristor or the like can be used. Combinatorial logic circuits can be used as switches.

[0013] When a transistor is used as a switch, the transistor acts as a simple switch. However, the polarity (conductivity type) of the transistor is not particularly limited. To suppress this, it is desirable to use a transistor with a polarity that has a smaller off-state current. Transistors with low leakage current include transistors with LDD regions and multi-gate There are also transistors that operate as switches. The device operates with the source terminal potential close to the low-potential power supply (Vss, GND, 0V, etc.). In this case, it is desirable to use an N-channel transistor. However, when operating near the high-potential power supply (such as Vdd), a P-channel transistor It is desirable to use a capacitor because the source terminal of the N-channel transistor is at a low potential. When operating close to the power supply, or when the source terminal of the P-channel transistor is at a high voltage, When operating close to the power supply on the top side, the absolute value of the gate-source voltage can be increased, This is because it makes it easier to switch the switch on or off. Since follower operation is rare, the output voltage becomes smaller. This is because there are few such cases.

[0014] CMOS type transistors are used to form a CMOS transistor. A CMOS switch can be used as a switch. If either the N-channel or N-channel transistor is conductive, For example, the input signal to the switch is Whether the voltage is high or low, the voltage can be output appropriately. The voltage amplitude of the signal used to turn the switch on and off can be reduced, reducing power consumption. The power consumption can also be reduced.

[0015] When a transistor is used as a switch, the switch is connected to the input terminal (source terminal and The output terminal (the other of the source and drain terminals) and the output terminal (the other of the source and drain terminals) are connected together. The gate terminal controls the diode. In some cases, the switch may not have a terminal that controls conduction. Using a diode as a switch rather than a resistor reduces the amount of wiring required to control the terminal. It can be made easier.

[0016] In this specification, when it is explicitly stated that A and B are connected, it means that A and B are connected by electricity. When A and B are electrically connected, when A and B are functionally connected, and when A and B are directly connected, Here, A and B are objects (e.g., devices, elements) (electrodes, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). In the configuration disclosed in the present application, a predetermined connection relationship, for example, a connection relationship shown in a drawing or a sentence, It is not limited to this and includes connections other than those shown in the drawings or text.

[0017] For example, if A and B are electrically connected, then the elements (e.g., switches, transistors, capacitors, inductors, resistors, diodes) One or more elements (such as a code) may be placed between A and B. Alternatively, A and B may be functionally When A and B are connected to each other, a circuit (e.g., a logic circuit) that allows the functional connection of A and B is created. circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (booster circuit, buck circuit (e.g., level shifter circuits that change the potential level of signals), voltage sources, current sources, switching Circuits, amplifier circuits (circuits that can increase signal amplitude or current, etc.), operational amplifiers, differential amplifiers circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc. One or more of these may be placed between A and B. Alternatively, A and B may be directly connected. In this case, A and B are directly connected without any other elements or circuits between them. It may be possible.

[0018] If you explicitly state that A and B are directly connected, then A and B are directly connected. (i.e., when A and B are connected without any other elements or circuits in between) When A and B are electrically connected (i.e., when there is another element or another circuit between A and B), (When connected by sandwiching) and

[0019] If it is explicitly stated that A and B are electrically connected, then it means that A and B are electrically connected. (i.e., when another element or circuit is interposed between A and B) ) and when A and B are functionally connected (i.e., when another circuit is inserted between A and B, the A and B are directly connected (i.e., the connection between A and B is functionally connected) and B is directly connected (i.e., the connection between A and B is functionally connected). (When connected to a power supply without any other element or circuit in between) When explicitly stating that something is electrically connected, it should simply be stated that it is connected. shall be the same as if explicitly stated.

[0020] Display element, display device which is a device having a display element, light emitting element, device having a light emitting element A light emitting device can be used in a variety of forms and can have a variety of elements. For example, the display element, display device, light emitting element or light emitting device may be an EL element ( Organic EL elements, inorganic EL elements, or EL elements containing organic and inorganic materials), electron-emitting elements , liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLV), plastics Zuma Display (PDP), Digital Micromirror Device (DMD), Piezoelectric Ceramic displays, carbon nanotubes, etc., are subject to electromagnetic effects, It is possible to use a display medium whose brightness, reflectance, transmittance, etc. change. The display device used was an EL display, and the display device using an electron-emitting device was a filter. Field Emission Displays (FED) and SED Flat Panel Displays (SED: Surface-conduction Electron-emitter Disp As a display device using liquid crystal elements, there are liquid crystal displays (transmissive liquid crystal displays) and Ray, transflective LCD, reflective LCD, direct-view LCD, Projection type liquid crystal display), and display devices using electronic ink or electrophoretic elements include electronic pens. There is a par.

[0021] As the transistor described in this document (specification, claims, drawings, etc.), Various types of transistors can be used. There is no limitation on the type. For example, amorphous silicon, polycrystalline silicon, microcrystalline A thin film with a non-single-crystal semiconductor film, typically silicon (also called amorphous or semi-amorphous) Thin-film transistors (TFTs) can be used. For example, it can be manufactured at a lower temperature than single crystal silicon, This allows for cost reduction and the need for larger manufacturing equipment. Transistors can be fabricated on large substrates, resulting in low-cost, simultaneous production of large numbers of displays. Furthermore, since the manufacturing temperature is low, substrates with low heat resistance can be used. Therefore, transistors can be fabricated on transparent substrates. Transistors can be used to control the transmission of light through the display element. Because the film thickness of the transistor is thin, some of the films that make up the transistor can transmit light. As a result, the aperture ratio can be improved.

[0022] When producing polycrystalline silicon, a catalyst (such as nickel) is used to improve the crystallinity. This further improves the electrical characteristics of the transistors, making it possible to manufacture transistors with excellent electrical characteristics. , gate driver circuits (scanning line driver circuits), source driver circuits (signal line driver circuits), Signal processing circuits (signal generation circuits, gamma correction circuits, DA conversion circuits, etc.) are integrated on the board. It is possible.

[0023] When manufacturing microcrystalline silicon, the crystallinity is improved by using a catalyst (such as nickel). This further improves the electrical characteristics of the transistors. The crystallinity can be improved by simply applying heat treatment without using a laser. , gate driver circuits (scanning line driving circuits) and part of the source driver circuits (analog switches Furthermore, if a laser is not used for crystallization, This can reduce unevenness in the crystallinity of silicon, resulting in an image with improved quality. It can be shown.

[0024] However, polycrystalline silicon and microcrystalline silicon can be produced without using a catalyst (such as nickel). It is possible to do so.

[0025] A transistor can be formed using a semiconductor substrate, an SOI substrate, or the like. , MOS type transistors, junction type transistors, bipolar transistors, etc. These can be used as transistors described in To manufacture small-sized transistors with little variation in shape, high current supply capacity, By using these transistors, it is possible to reduce the power consumption of the circuit or High integration can be achieved.

[0026] The transistors that can be used are zinc oxide (ZnO), amorphous oxide (a-In GaZnO), silicon germanium (SiGe), gallium arsenide (GaAs), indium Chemicals such as indium zinc oxide (IZO), indium tin oxide (ITO), and tin oxide (SnO) Transistors having compound semiconductors or oxide semiconductors, and further, transistors having these compound semiconductors These include thin-film transistors made of thin-film semiconductors such as silicon or oxide semiconductors. This allows the temperature to be lowered, making it possible to fabricate transistors at room temperature, for example. Forming transistors directly on a substrate with low thermal resistance, such as a plastic substrate or film substrate These compound semiconductors or oxide semiconductors can be used as the transistor chips. It can be used not only for the channel part but also for other purposes. The compound semiconductor or oxide semiconductor can be used as a resistance element, a pixel electrode, or a transparent electrode. Furthermore, they can be deposited or formed simultaneously with the transistors, reducing costs. It can be reduced.

[0027] Usable transistors include transistors formed using inkjet or printing methods. These allow transistors to be manufactured at room temperature, in low vacuum, or on a large scale. It can be manufactured on a substrate without using a mask (reticle). This allows for easy changes to the transistor layout. Since there is no need to use resist, material costs are reduced and the number of processes can be reduced. In order to apply the film only to the necessary parts, rather than the method of forming a film over the entire surface and then etching it, This means that no materials are wasted and costs can be kept low.

[0028] Transistors that can be used include organic semiconductors and transistors with carbon nanotubes. These make it possible to form transistors on flexible substrates. Therefore, transistors with organic semiconductors and carbon nanotubes can be The device used can be shock resistant.

[0029] In addition, various other transistors can be used.

[0030] The type of substrate on which the transistor is formed can be various, and in particular The substrate on which the transistor is formed is not limited to a specific one. Crystal substrate, SOI substrate, glass substrate, quartz substrate, plastic substrate, paper substrate, cellophane Substrate, stone substrate, wood substrate, fabric substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyester) polyurethane, polyester) or recycled fiber (acetate, cupra, rayon, recycled polyester), leather substrate, rubber substrate, stainless steel substrate, stainless steel Alternatively, a substrate with a steel foil or the like can be used. The skin (skin epidermis, dermis) or subcutaneous tissue may be used as a substrate. The transistor may be formed on a substrate and then transferred to another substrate. Substrates to be transposed include single crystal substrates, SOI substrates, glass substrates, quartz substrates, and plastic substrates. Black board, paper board, cellophane board, stone board, wood board, cloth board (natural fiber (silk, cotton, hemp) ), synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate , cupra, rayon, recycled polyester), leather substrate, rubber substrate, stainless steel A substrate with a stainless steel foil or a substrate with a stainless steel foil can be used. Alternatively, a transistor may be placed on the skin (skin surface, dermis) or subcutaneous tissue of an animal such as a human. By using these substrates, transistors with good characteristics can be manufactured. Formation of low-power transistors, fabrication of durable devices, and heat resistance Or, weight reduction can be achieved.

[0031] The transistor configuration can take many forms and is not limited to a specific configuration. For example, a multi-gate structure having two or more gate electrodes may be used. When the transistor is connected in series, the channel regions are connected in series. The multi-gate structure reduces the off-current and improves the breakdown voltage of the transistor. Alternatively, the multi-gate structure can be used to reduce the operation time in the saturation region. When operating, even if the drain-source voltage changes, the drain-source current does not change much. It is possible to obtain voltage-current characteristics with a flat slope without any distortion. By utilizing the voltage-current characteristics of the As a result, it is possible to realize differential circuits and current mirror circuits with good characteristics. Alternatively, a structure in which gate electrodes are disposed above and below the channel may be used. By using a structure in which gate electrodes are placed above and below the channel, the channel area is increased. Therefore, it is necessary to increase the current value or reduce the S value by making it easier for a depletion layer to form. When gate electrodes are placed above and below the channel, multiple transistors can be connected in parallel. This results in a connected configuration.

[0032] Alternatively, a gate electrode may be disposed on the channel region. Alternatively, a gate electrode may be disposed under the gate electrode region. A tag structure may be used, or the channel region may be divided into a plurality of regions. may be connected in parallel, or the channel regions may be connected in series. The channel region (or a part thereof) may be overlapped with a source electrode or a drain electrode. A structure in which the source electrode and drain electrode overlap the channel region (or part of it). This prevents charge from accumulating in part of the channel region, causing instability in operation. Furthermore, an LDD region may be provided. By providing the LDD region, the off-current can be reduced. Alternatively, the reliability can be improved by increasing the breakdown voltage of the transistor. By providing an LDD region, the drain-source voltage is changed when operating in the saturation region. Even if the gate voltage is increased, the drain-source current does not change much, and the slope of the voltage-current characteristic is flat. It can be made to have a property that

[0033] The transistors in this specification can be of various types, and various Therefore, the circuitry required to achieve a desired function can be formed on the substrate. All of them may be formed on the same substrate. All of the circuits are on glass substrates, plastic substrates, single crystal substrates, or SOI substrates. The substrate may be formed on a substrate other than the substrate. All of the circuits required to achieve this functionality are formed on the same substrate, Reducing the number of points reduces costs, and reducing the number of connections to circuit components improves reliability. Alternatively, some of the circuits required to achieve a specific function can be mounted on a certain substrate. Another part of the circuitry required to realize a given function is formed on a separate substrate. In other words, all of the circuits required to realize a predetermined function may be formed in the same It does not have to be formed on a substrate. For example, the circuitry required to realize a predetermined function may be Some of them are formed using transistors on a glass substrate, and are required to realize a specific function. Another part of the essential circuit is formed on the single crystal substrate and is composed of transistors on the single crystal substrate. The IC chip is connected to the glass substrate by COG (Chip On Glass). The IC chip may be placed on a glass substrate. Alternatively, the IC chip may be attached to a TAB (Tape). It is bonded to the glass substrate using a PC board or automated bonding. In this way, since part of the circuit is formed on the same substrate, Reducing the number of points reduces costs, and reducing the number of connections to circuit components improves reliability. In addition, circuits with high drive voltages or high drive frequencies consume a lot of power. Therefore, the circuits for such parts are not formed on the same substrate. The circuit for that part is formed on a single crystal substrate, and an IC chip consisting of that circuit is used. In this way, an increase in power consumption can be prevented.

[0034] In this specification, one pixel refers to one element whose brightness can be controlled. For example, one pixel refers to one color element, and the brightness is expressed by that one color element. Therefore, in the case of a color display device consisting of R (red), G (green), and B (blue) color elements, In this example, the smallest unit of an image is composed of three pixels: an R pixel, a G pixel, and a B pixel. The color elements are not limited to three colors, and more than three colors may be used, or colors other than RGB may be used. Color may also be used. For example, W (white) may be added to make it RGBW. Add one or more colors, such as yellow, cyan, magenta, emerald green, or vermilion. Also, for example, a color similar to at least one color in RGB may be added to RGB. For example, R, G, B1, B2 may be used. B1 and B2 are both blue. However, the frequencies are slightly different. Similarly, R1, R2, G, and B may be used. By using color elements like these, it is possible to display more realistic images and reduce power consumption. Another example is to use multiple regions for one color element to reduce the brightness. When controlling the brightness, one area may be regarded as one pixel. If you have sub-pixels, you can set the brightness for each color element. There are multiple areas to control, and the gradation is expressed as a whole, but one of the areas to control the brightness In this case, one color element is made up of multiple pixels. Or, even if there are multiple areas that control brightness within one color element, they can be grouped together and used as one One color element may be one pixel. In this case, one color element is composed of one pixel. In addition, when controlling the brightness of one color element using multiple regions, The size of the area that contributes to the display may differ depending on the pixel. In the brightness control area, which has multiple color elements, the signal supplied to each is slightly In other words, for one color element, multiple The potentials of the pixel electrodes in each region may be different. The voltage applied to each pixel electrode is different, which makes it possible to widen the viewing angle. .

[0035] When explicitly describing one pixel (three colors), it refers to the three pixels of R, G, and B as one pixel. When explicitly describing one pixel (one color), for one color element, When there are multiple regions, they are all considered to be one pixel.

[0036] In this document, pixels may be arranged (arranged) in a matrix. The pixels are arranged in a matrix, which means that the pixels are arranged vertically or horizontally. This includes cases where elements are arranged in a straight line or in a jagged line. For example, when displaying full color using three color elements (e.g., RGB), the stripe arrangement This also includes cases where the dots of the three color elements are arranged in delta. This includes cases where the color elements are arranged in a Bayer pattern. Note that the number of color elements is not limited to three, and may be more than three. For example, RGBW (W is white) or RGB plus yellow, cyan, magenta, etc. There are also ones that add more than two colors. Also, the size of the display area for each dot of the color element is different. This can reduce power consumption or extend the life of the display element. can.

[0037] In this document, the term "active matrix type" refers to a type in which pixels have active elements, or A passive matrix system that does not have active elements can be used.

[0038] In the active matrix system, the active element (active element, nonlinear element) is a transistor. By using not only transistors but also various active elements (active elements, nonlinear elements), For example, MIM (Metal Insulator Metal) and TFD It is also possible to use a thin film diode (Thin Film Diode). Since the number of manufacturing steps is small, it is possible to reduce manufacturing costs and improve yields. Furthermore, the small size of the element allows for an improved aperture ratio, which in turn allows for lower power consumption and higher image quality. Brightness can be increased.

[0039] Other than the active matrix type, active elements (active elements, nonlinear elements) It is also possible to use a passive matrix type that does not use active elements (active elements). Since it does not use any nonlinear elements, the manufacturing process is reduced, reducing manufacturing costs and improving yield. In addition, it is possible to improve the performance without using active elements (active elements, non-linear elements). Therefore, the aperture ratio can be improved, and low power consumption and high brightness can be achieved.

[0040] A transistor is a device that has at least three terminals, including a gate, a drain, and a source. The element has a channel region between a drain region and a source region, and the drain A current can be passed through the gate region, the channel region, and the source region, where: The source and drain will change depending on the transistor structure and operating conditions, so Therefore, in this specification, it is difficult to define whether the In this case, the regions that function as source and drain are not called source or drain. In this case, they may be referred to as the first terminal and the second terminal, respectively. These may be referred to as the first electrode and the second electrode, respectively. This may be referred to as the rain area.

[0041] A transistor has at least three terminals including a base, an emitter, and a collector. In this case, the emitter and the collector may be connected to the first terminal and the second terminal. It may be written as two terminals.

[0042] The gate is a gate electrode and a gate wiring (gate line, gate signal line, scanning line, scanning signal The term "gate electrode" refers to the entire structure including the gate electrode (also called a gate line, etc.) or a part of the gate electrode. The term "gate insulating film" refers to a semiconductor that forms a channel region and overlaps it via a gate insulating film. The part of the gate electrode is called LDD (Lightly Doped). ped Drain) region, source region or drain region and the on-chip gate insulating film. The gate wiring is the wiring between the gate electrodes of each transistor. Wiring for connecting the gate electrodes of each pixel, or wiring for connecting the gate electrodes of each pixel This refers to wiring that connects a terminal electrode to another wiring.

[0043] However, there are areas (regions, conductive films) that function as both gate electrodes and gate wiring. Such parts (regions, conductive films, wiring, etc.) are also present. In other words, the gate electrode and the gate wiring are There are also areas that cannot be clearly distinguished. For example, there are areas where the gate wiring is extended and If the channel regions overlap, the overlapping areas (regions, conductive films, wiring, etc.) It functions as a gate wiring, but also as a gate electrode. The part (region, conductive film, wiring, etc.) may be called a gate electrode or a gate wiring. Good too.

[0044] It is made of the same material as the gate electrode and forms the same island as the gate electrode. The part (region, conductive film, wiring, etc.) that is connected to the gate electrode may also be called a gate electrode. It is made of the same material as the gate wiring and forms the same island as the gate wiring. The part (region, conductive film, wiring, etc.) that is connected to the gate may also be called the gate wiring. In the strict sense, the area (region, conductive film, wiring, etc.) does not overlap with the channel region. However, there are cases where the gate electrode does not have a function to connect to another gate electrode. It is formed of the same material as the gate electrode or gate wiring, and is the same material as the gate electrode or gate wiring. There are also parts (areas, conductive films, wiring, etc.) that are connected to form islands. Therefore, such parts (regions, conductive films, wiring, etc.) are also called gate electrodes or gate wiring. That's fine too.

[0045] For example, in a multi-gate transistor, one gate electrode and another gate electrode In many cases, the gate electrode is connected to the gate electrode through a conductive film made of the same material. The components (regions, conductive films, wiring, etc.) are parts for connecting gate electrodes. Since it is a component (region, conductive film, wiring, etc.), it can be called gate wiring, but multi-gate Since the transistors can be considered as one transistor, they can be called gate electrodes. That is, the gate electrode or the gate wiring is formed of the same material, and the gate electrode or the gate wiring is formed of the same material. The part (area, conductive film, wiring, etc.) that forms the same island as the port wiring and is connected The gate electrode and the gate wiring may be called gate electrodes or gate wirings. The conductive film of the portion connecting the gate electrode and the gate wiring is made of a material different from that of the gate electrode or the gate wiring. The conductive film formed by the above process may also be called a gate electrode or a gate wiring.

[0046] The gate terminal is the part of the gate electrode (region, conductive film, wiring, etc.) or the gate electrode and A part of an electrically connected area (area, conductive film, wiring, etc.) say.

[0047] When wiring is called a gate wiring, gate line, gate signal line, scanning line, scanning signal line, etc., In some cases, the gate of a transistor is not connected to the wiring. The gate lines, gate signal lines, scanning lines, and scanning signal lines are formed in the same layer as the transistor gates. wiring made of the same material as the gate of a transistor, or wiring made of the same material as the gate of a transistor It may refer to wiring formed at the same time as the gate. Examples include wiring for storage capacitors, These include power supply lines and reference potential supply wiring.

[0048] The source includes a source region, a source electrode, and a source wiring (source line, source signal line, The whole or part of the data line, data signal line, etc. The source region is formed by doping P-type impurities (such as boron or gallium) or N-type impurities (such as phosphorus or gallium). Therefore, it is a semiconductor region that contains a small amount of P-type impurities and N The region containing type impurities, so-called LDD (Lightly Doped Drain) The source electrode is made of a material different from that of the source region. The conductive layer is a portion of the conductive layer that is electrically connected to the source region. The source electrode may also be called the source electrode, including the source region. Wiring for connecting the source electrodes of each transistor, and wiring between the source electrodes of each pixel or a wiring for connecting a source electrode to another wiring. This refers to

[0049] However, there is a portion (region, Such parts (regions, conductive films, wiring, etc.) are also present. It can be called an electrode or a source wiring. However, there are also areas that cannot be clearly distinguished. For example, one of the source wirings that is arranged in an extended manner If the source region overlaps with the source region, the overlapping region (region, conductive film, wiring, etc.) It functions as a source wiring, but also as a source electrode. Such a portion (region, conductive film, wiring, etc.) may be called a source electrode, or It may also be called wiring.

[0050] It is made of the same material as the source electrode and is connected to the source electrode by forming an island. The part where the source electrode is connected to the source electrode (region, conductive film, wiring, etc.) The source electrode (region, conductive film, wiring, etc.) may also be called the source electrode. The burlapped portion can also be called the source electrode. The area that is connected to the source wiring and forms the same island is also called the source wiring. Such parts (areas, conductive films, wiring, etc.) are, in the strict sense, However, the source electrode or is made of the same material as the source wiring and is connected to the source electrode or source wiring. (area, conductive film, wiring, etc.) Therefore, such parts (area, conductive film, wiring, etc.) ) may also be called a source electrode or source wiring.

[0051] For example, the conductive film in the portion connecting the source electrode and the source wiring is Alternatively, a conductive film formed of a material different from the source wiring may also be called a source electrode. This may also be called a source wiring.

[0052] The source terminal is a region of the source region, a source electrode, or a region electrically connected to the source electrode. This refers to a part of a part (such as an area, conductive film, or wiring) that is being processed.

[0053] The wiring may be called a source wiring, a source line, a source signal line, a data line, a data signal line, etc. In this case, the source (drain) of the transistor may not be connected to the wiring. , source wiring, source line, source signal line, data line, data signal line are transistor solenoids. Wiring formed in the same layer as the source (drain) of the transistor Wiring formed from a material or wiring formed at the same time as the source (drain) of a transistor Examples include storage capacitor wiring, power supply wiring, and reference potential supply wiring. etc.

[0054] The drain is the same as the source.

[0055] A semiconductor device is a circuit that includes semiconductor elements (transistors, diodes, thyristors, etc.). Furthermore, it refers to any device that can function by utilizing the properties of semiconductors. It may also be called a semiconductor device.

[0056] Display elements include optical modulation elements, liquid crystal elements, light-emitting elements, EL elements (organic EL elements, inorganic EL elements), EL elements or EL elements containing organic and inorganic materials), electron emission elements, electrophoretic elements, discharge This refers to elements, optical reflecting elements, optical diffraction elements, DMDs, etc. However, it is not limited to these. do not have.

[0057] The display device refers to a device having a display element. A plurality of pixels including the pixel array and a peripheral driving circuit for driving the pixel array are formed on the same substrate. The display device is made of a material that is bonded to the display panel by wire bonding or bumps. Therefore, the peripheral drive circuits arranged on the substrate, the so-called IC chips connected by COG, Alternatively, the display device may include an IC chip connected by a tab or the like. FPC with C chips, resistors, capacitors, inductors, transistors, etc. Furthermore, the display device may be connected via an FPC or the like, and may include an IC chip, a resistor, A printed circuit board (P Furthermore, the display device may include an optical sheet such as a polarizing plate or a retardation plate. Furthermore, the display device may include a lighting device, a housing, an audio input / output device, an optical sensor, and the like. Here, the lighting device such as the backlight unit may include a light guide plate , prism sheet, diffusion sheet, reflective sheet, light source (LED, cold cathode fluorescent lamp, etc.), cooling device (Water-cooled, air-cooled) etc.

[0058] The lighting device includes a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflective sheet, and A device that has a port, light source (LED, cold cathode fluorescent lamp, hot cathode fluorescent lamp, etc.), cooling device, etc. This refers to

[0059] A light-emitting device refers to a device that has a light-emitting element or the like.

[0060] The reflecting device is a device that has a light reflecting element, a light diffracting element, a light reflecting electrode, etc. cormorant.

[0061] A liquid crystal display device is a display device that has a liquid crystal element. There are projection type, transmissive type, reflective type, semi-transmissive type, etc.

[0062] A driving device is a device that has semiconductor elements, electric circuits, and electronic circuits. For example, A transistor that controls the input of a signal from a source signal line into a pixel (selection transistor, (sometimes called switching transistors, etc.), which supplies voltage or current to the pixel electrode The transistors that supply voltage or current to the light-emitting element and the like are used in the driving device. Furthermore, a circuit for supplying signals to the gate signal lines (gate drivers, gate lines a circuit that supplies signals to the source signal lines (source driver , a source line driver circuit, etc.) is an example of a driver device.

[0063] Display devices, semiconductor devices, lighting devices, cooling devices, light-emitting devices, reflecting devices, driving devices, etc. Some devices overlap with each other. For example, a display device may have a semiconductor device and a light-emitting device. Alternatively, when the semiconductor device has a display device and a driving device, There is.

[0064] In this document, B is formed on A, or B is formed on A. When explicitly stating "A", it is not limited to B being formed directly on A. This also includes cases where there is no direct contact, i.e., when another object is between A and B. Here, A and B are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductors, etc.). (film, layer, etc.).

[0065] For example, it is explicitly stated that layer B is formed on top of layer A (or on top of layer A). In this case, layer B is formed directly on top of layer A, and layer B is formed directly on top of layer A. Layer B is formed on top of another layer (such as layer C or layer D). The other layer (for example, layer C or layer D) may be a single layer or , and may be multi-layered.

[0066] Furthermore, the same applies to cases where it is explicitly stated that B is formed above A. It is not limited to B being directly on A, and there is another object between A and B. For example, layer B is formed above layer A. In this case, layer B is formed directly on top of layer A, and layer B is formed directly on top of layer A. There are cases where a layer (such as layer C or layer D) is formed and layer B is formed on top of it, and The other layers (such as layers C and D) may be single or multi-layered. Good too.

[0067] When explicitly stating that B is formed directly on A, it is This only includes cases where B is formed by A and B, and does not include cases where another object is interposed between A and B. It shall be deemed not to exist.

[0068] The same applies to the case where B is below A, or B is below A. [Effects of the Invention]

[0069] The configuration described in this specification allows the shift register to operate at high speed. Even if amorphous silicon is used as the semiconductor layer of the shift register, Therefore, the shift register can be used in semiconductor devices such as liquid crystal displays. The body device can be operated at high speed, and can be easily made larger or have higher definition. [Brief explanation of the drawings]

[0070] [Figure 1] 1A to 1C illustrate a structure of a flip-flop described in Embodiment 1. [Figure 2] 2 is a timing chart illustrating the operation of the flip-flop shown in FIG. 1; [Figure 3] FIG. 2 is a diagram for explaining the operation of the flip-flop shown in FIG. [Figure 4] 1A to 1C illustrate a structure of a flip-flop described in Embodiment 1. [Figure 5] 1A to 1C illustrate a structure of a flip-flop described in Embodiment 1. [Figure 6] 4 is a timing chart illustrating the operation of the flip-flop shown in Embodiment 1. [Figure 7] FIG. 2 illustrates a structure of a shift register described in Embodiment 1. [Figure 8] 8 is a timing chart illustrating the operation of the shift register shown in FIG. 7. [Figure 9] 8 is a timing chart illustrating the operation of the shift register shown in FIG. 7. [Figure 10] FIG. 2 illustrates a structure of a shift register described in Embodiment 1. [Figure 11] 1A to 1C illustrate a structure of a display device described in Embodiment 1. [Figure 12] 12 is a timing chart illustrating a writing operation of the display device shown in FIG. [Figure 13] 1A to 1C illustrate a structure of a display device described in Embodiment 1. [Figure 14] 1A to 1C illustrate a structure of a display device described in Embodiment 1. [Figure 15] 15 is a timing chart illustrating a writing operation of the display device shown in FIG. 14. [Figure 16] 10 is a timing chart illustrating the operation of the flip-flop shown in Embodiment 2. [Figure 17] 10 is a timing chart illustrating the operation of the flip-flop shown in Embodiment 2. [Figure 18] 10A and 10B illustrate a structure of a shift register described in Embodiment 2. [Figure 19] 19 is a timing chart illustrating the operation of the shift register shown in FIG. 18. [Figure 20] 19 is a timing chart illustrating the operation of the shift register shown in FIG. 18. [Figure 21] 10A to 10C illustrate a structure of a display device described in Embodiment 2. [Figure 22] FIG. 1 illustrates a structure of a display device described in Embodiment 2. [Figure 23] 10A to 10C illustrate a structure of a flip-flop described in Embodiment 3. [Figure 24] 24 is a timing chart illustrating the operation of the flip-flop shown in FIG. 23. [Figure 25] 10A and 10B illustrate a structure of a shift register described in Embodiment 3. [Figure 26] 26 is a timing chart illustrating the operation of the shift register shown in FIG. 25. [Figure 27] 10A to 10C illustrate a structure of a flip-flop described in Embodiment 4. [Figure 28] 28 is a timing chart illustrating the operation of the flip-flop shown in FIG. 27. [Figure 29] FIG. 5B is a top view of the flip-flop shown in FIG. [Figure 30] FIG. 11 is a diagram for explaining the configuration of the buffer shown in FIG. 10. [Figure 31] 10 illustrates a configuration of a signal line driver circuit described in Embodiment 5. [Figure 32] 32 is a timing chart illustrating the operation of the signal line driver circuit shown in FIG. 31. [Figure 33] 10 illustrates a configuration of a signal line driver circuit described in Embodiment 5. [Figure 34] 34 is a timing chart illustrating the operation of the signal line driver circuit shown in FIG. 33. [Figure 35] 10 illustrates a configuration of a signal line driver circuit described in Embodiment 5. [Figure 36] 10A and 10B illustrate a structure of a protection diode described in Embodiment 6. [Figure 37] 10A and 10B illustrate a structure of a protection diode described in Embodiment 6. [Figure 38] 10A and 10B illustrate a structure of a protection diode described in Embodiment 6. [Figure 39] 10A to 10C illustrate a structure of a display device described in Embodiment 7. [Figure 40] 1A to 1C are diagrams illustrating a process for manufacturing a semiconductor device according to the present invention. [Figure 41] 1A to 1C are diagrams illustrating a structure of a semiconductor device according to the present invention. [Figure 42] 1A to 1C are diagrams illustrating a structure of a semiconductor device according to the present invention. [Figure 43] 1A to 1C are diagrams illustrating a structure of a semiconductor device according to the present invention. [Figure 44] 1A to 1C are diagrams illustrating a structure of a semiconductor device according to the present invention. [Figure 45] 1A to 1C are diagrams illustrating a method for driving a semiconductor device according to the present invention. [Figure 46]1A to 1C are diagrams illustrating a method for driving a semiconductor device according to the present invention. [Figure 47] 1A and 1B are diagrams illustrating a structure of a display device of a semiconductor device according to the present invention. [Figure 48] FIG. 2 is a diagram illustrating a peripheral circuit configuration of a semiconductor device according to the present invention. [Figure 49] 2A to 2C are diagrams illustrating peripheral components of a semiconductor device according to the present invention; [Figure 50] 2A to 2C are diagrams illustrating peripheral components of a semiconductor device according to the present invention; [Figure 51] 2A to 2C are diagrams illustrating peripheral components of a semiconductor device according to the present invention; [Figure 52] FIG. 2 is a diagram illustrating a peripheral circuit configuration of a semiconductor device according to the present invention. [Figure 53] 2A to 2C are diagrams illustrating peripheral components of a semiconductor device according to the present invention; [Figure 54] 1A and 1B are diagrams illustrating a panel circuit configuration of a semiconductor device according to the present invention. [Figure 55] 1A and 1B are diagrams illustrating a panel circuit configuration of a semiconductor device according to the present invention. [Figure 56] 1A and 1B are diagrams illustrating a panel circuit configuration of a semiconductor device according to the present invention. [Figure 57] 1 is a cross-sectional view of a display element of a semiconductor device according to the present invention. [Figure 58] 1 is a cross-sectional view of a display element of a semiconductor device according to the present invention. [Figure 59] 1 is a cross-sectional view of a display element of a semiconductor device according to the present invention. [Figure 60] 1 is a cross-sectional view of a display element of a semiconductor device according to the present invention. [Figure 61] 1 is a top view of a pixel of a semiconductor device according to the present invention; [Figure 62] 1 is a top view of a pixel of a semiconductor device according to the present invention; [Figure 63] 1 is a top view of a pixel of a semiconductor device according to the present invention; [Figure 64] 1 shows an example of a pixel layout of a semiconductor device according to the present invention. [Figure 65] 1 shows an example of a pixel layout of a semiconductor device according to the present invention. [Figure 66]1 shows an example of a pixel layout of a semiconductor device according to the present invention. [Figure 67] 1A to 1C are diagrams illustrating a method for driving a semiconductor device according to the present invention. [Figure 68] 1A to 1C are diagrams illustrating a method for driving a semiconductor device according to the present invention. [Figure 69] 1A and 1B are diagrams illustrating a pixel configuration of a semiconductor device according to the present invention; [Figure 70] 1A and 1B are diagrams illustrating a pixel configuration of a semiconductor device according to the present invention; [Figure 71] 1A and 1B are diagrams illustrating a pixel configuration of a semiconductor device according to the present invention; [Figure 72] 1A and 1B are cross-sectional views showing an example of a pixel layout of a semiconductor device according to the present invention; [Figure 73] 1 is a cross-sectional view of a display element of a semiconductor device according to the present invention. [Figure 74] 1 is a cross-sectional view of a display element of a semiconductor device according to the present invention. [Figure 75] 1 is a cross-sectional view of a display element of a semiconductor device according to the present invention. [Figure 76] 1A to 1C are diagrams illustrating a structure of a semiconductor device according to the present invention. [Figure 77] 1A to 1C are diagrams illustrating a structure of a semiconductor device according to the present invention. [Figure 78] 1A to 1C are diagrams illustrating a structure of a semiconductor device according to the present invention. [Figure 79] 1A to 1C are diagrams illustrating a structure of a semiconductor device according to the present invention. [Figure 80] 1A to 1C are diagrams illustrating a structure of a semiconductor device according to the present invention. [Figure 81] 1A to 1C are diagrams illustrating a structure of a semiconductor device according to the present invention. [Figure 82] 1A to 1C are diagrams illustrating a method for driving a semiconductor device according to the present invention. [Figure 83] 1A to 1C are diagrams illustrating a method for driving a semiconductor device according to the present invention. [Figure 84] 1A to 1C are diagrams illustrating a method for driving a semiconductor device according to the present invention. [Figure 85] 1A to 1C are diagrams illustrating a method for driving a semiconductor device according to the present invention. [Figure 86] 1A to 1C are diagrams illustrating a structure of a semiconductor device according to the present invention. [Figure 87] 1A to 1C are diagrams illustrating electronic devices using a semiconductor device according to the present invention. [Figure 88] 1A to 1C are diagrams illustrating a structure of a semiconductor device according to the present invention. [Figure 89] 1A to 1C are diagrams illustrating electronic devices using a semiconductor device according to the present invention. [Figure 90] 1A to 1C are diagrams illustrating electronic devices using a semiconductor device according to the present invention. [Figure 91] 1A to 1C are diagrams illustrating electronic devices using a semiconductor device according to the present invention. [Figure 92] 1A to 1C are diagrams illustrating electronic devices using a semiconductor device according to the present invention. [Figure 93] 1A to 1C are diagrams illustrating electronic devices using a semiconductor device according to the present invention. [Figure 94] 1A to 1C are diagrams illustrating electronic devices using a semiconductor device according to the present invention. [Figure 95] 1A to 1C are diagrams illustrating electronic devices using a semiconductor device according to the present invention. [Figure 96] 1A to 1C are diagrams illustrating electronic devices using a semiconductor device according to the present invention. [Figure 97] 1A to 1C are diagrams illustrating electronic devices using a semiconductor device according to the present invention. [Figure 98] 1A to 1C are diagrams illustrating electronic devices using a semiconductor device according to the present invention. [Figure 99] FIG. 11 is a diagram for explaining the configuration of the buffer shown in FIG. 10. [Figure 100] FIG. 1 is a diagram for explaining the configuration and timing of a flip-flop according to the prior art; DETAILED DESCRIPTION OF THE INVENTION

[0071] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the embodiments described herein, and the scope of the present invention is not to be limited to the embodiments described herein. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the following description of the embodiments. In the configuration of the present invention, the same parts or parts having similar functions are denoted by the same reference numerals. The same applies to the drawings, and the repeated explanations thereof will be omitted.

[0072] (Embodiment 1) In this embodiment, a flip-flop, a driver circuit including the flip-flop, and The configuration and driving method of a display device having the driving circuit will be described.

[0073] A basic structure of a flip-flop of this embodiment mode will be described with reference to FIG. The flip-flop shown in FIG. 1A includes a first transistor 101, a second transistor a third transistor 102, a fourth transistor 103, a fifth transistor 105, a sixth transistor 106, a seventh transistor 107 and an eighth transistor In this embodiment, the first transistor 101, the second transistor a third transistor 102, a fourth transistor 103, a fifth transistor 104, a sixth transistor 105, a seventh transistor 106, a seventh transistor 107 and an eighth transistor The transistor 108 is an N-channel transistor, and the gate-source voltage (Vgs) is a threshold. When the voltage exceeds a certain threshold voltage (Vth), the transistor is in a conductive state.

[0074] The flip-flop of this embodiment includes a first transistor 101 to an eighth transistor 108 are all made up of N-channel transistors. The flip-flop of the embodiment uses amorphous silicon as the semiconductor layer of the transistor. This allows for the simplification of the manufacturing process, reduction of manufacturing costs, and improvement of yield. However, the semiconductor layer of the transistor is made of polysilicon or single crystal. Even when crystalline silicon is used, the manufacturing process can be simplified.

[0075] The connection relationship of the flip-flop in FIG. 1A will be described. The first electrode (one of the source electrode and the drain electrode) of the first transistor is connected to the fifth wiring 125. The second electrode (the other of the source electrode and the drain electrode) of the first transistor 101 is connected to the The first electrode of the second transistor 102 is connected to the fourth wiring 123. 4, and the second electrode of the second transistor 102 is connected to the third wiring 123. A first electrode of the third transistor 103 is connected to a sixth wiring 126. The second electrode of the third transistor 103 is connected to the gate electrode of the second transistor 102. The gate electrode of the transistor 103 is connected to the sixth wiring 126. The first electrode of the fourth transistor 104 is connected to the eighth wiring 128, and the second electrode of the fourth transistor 104 is connected to the eighth wiring 128. The electrode is connected to the gate electrode of the second transistor 102 and the electrode of the fourth transistor 104 The gate electrode of the fifth transistor is connected to the gate electrode of the first transistor 101. The first electrode of the fifth transistor 105 is connected to the seventh wiring 127, and the second electrode of the fifth transistor 105 is connected to the seventh wiring 127. The electrode is connected to the gate electrode of the first transistor 101, and the electrode of the fifth transistor 105 The gate electrode of the sixth transistor 106 is connected to the first wiring 121. The second electrode of the sixth transistor 106 is connected to the tenth wiring 130, and the second electrode of the sixth transistor 106 is connected to the first wiring 130. The gate electrode of the sixth transistor 106 is connected to the gate electrode of the second transistor 101. The first electrode of the seventh transistor 107 is connected to the gate electrode of the seventh transistor 102. The second electrode of the seventh transistor 107 is connected to the eleventh wiring 131, and the second electrode of the seventh transistor 107 is connected to the The gate electrode of the seventh transistor 107 is connected to the gate electrode of the second transistor 108. The first electrode of the eighth transistor 108 is connected to the ninth wiring 129. the second electrode of the eighth transistor 108 is connected to the gate of the second transistor 102. The gate electrode of the eighth transistor 108 is connected to the first wiring 121. can be.

[0076] The gate electrode of the first transistor 101, the gate electrode of the fourth transistor 104, the second electrode of the fifth transistor 105, the second electrode of the sixth transistor 106, and The connection point of the second electrodes of the transistors 107 of the second transistor 107 is a node 141. the gate electrode of the third transistor 102, the second electrode of the third transistor 103, the fourth electrode of the fourth transistor the second electrode of the sixth transistor 104, the gate electrode of the eighth transistor 106, The connection point of the second electrode of 108 is designated as node 142 .

[0077] The first wiring 121, the second wiring 122, the third wiring 123 and the fifth wiring 125 are They may be called the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. In addition, the fourth wiring 124, the sixth wiring 126, the seventh wiring 127, the eighth wiring 128, the ninth wiring 129, The first wiring 129, the tenth wiring 130 and the eleventh wiring 131 are respectively connected to the first power supply line. , the second power line, the third power line, the fourth power line, the fifth power line, the sixth power line, the seventh power line It may also be called a source line.

[0078] Next, the operation of the flip-flop shown in Figure 1(A) is compared with the timing chart in Figure 2. 3. Furthermore, the timing chart of FIG. 2 is a set period, a selection period, and a The explanation will be divided into the selection period, reset period, and non-selection period. The period and non-selection period are sometimes collectively referred to as the non-selection period.

[0079] The sixth wiring 126 and the seventh wiring 127 are supplied with a potential of V1. 124, the eighth wiring 128, the ninth wiring 129, the tenth wiring 130 and the eleventh wiring 131 is supplied with a potential of V2, where V1>V2. A signal is called an H signal, and a signal with a potential of V2 is called an L signal.

[0080] The first wiring 121, the fifth wiring 125, and the second wiring 122 are connected to the signal lines shown in FIG. The third wiring 123 is connected to the input terminals 221, 225, and 222. 2 is output. Here, signals 221, 225, 222 and The signal 223 has a potential of V1 (hereinafter also referred to as H level) for the H signal and a potential of V2 ( In the following, the signal 221, the signal 225, and the signal 226 are digital signals. The signal 222 and the signal 223 are respectively a start signal, a clock signal, a reset signal, and an output signal. It may also be called a force signal.

[0081] However, the first wiring 121, the second wiring 122, the fourth wiring 124 to the eleventh wiring 13 1 may be input with various signals, potentials and currents.

[0082] During the set period shown in FIG. 2(A) and FIG. 3(A), the signal 221 becomes H level. , the fifth transistor 105 and the eighth transistor 108 are turned on. Since the signal 22 is at the L level, the seventh transistor 107 is turned off. The potential (potential 241) is generated when the second electrode of the fifth transistor 105 serves as the source electrode. The potential of the seventh wiring 127 is the potential obtained by subtracting the threshold voltage of the fifth transistor 105. Therefore, V1-Vth105 (Vth105: threshold voltage of the fifth transistor 105) Therefore, the first transistor 101 and the fourth transistor 104 are turned on, The fifth transistor 105 is turned off. At this time, the potential of the node 142 (potential 242) is The potential difference (V1-) between the potential (V2) of the eighth wiring 128 and the potential (V1) of the sixth wiring 126 V2) is connected to the third transistor 103, the fourth transistor 104 and the eighth transistor The voltage is divided by the resistor 108 to become V2+β (β: any positive number). <Vt h102 (Vth102: threshold voltage of the second transistor 102) and β <Vth 106 (threshold voltage of the sixth transistor 106). The sixth transistor 102 and the sixth transistor 106 are turned off. The third wiring 123 is electrically connected to the fifth wiring 125 to which the L signal is input. The potential of the wiring 123 becomes V2. Therefore, an L signal is output from the third wiring 123. Furthermore, the node 141 is in a floating state while maintaining the potential at V1-Vth105.

[0083] The third transistor 103 and the fourth transistor 104 connect the input terminal to node 14 1, an inverter is configured with the output terminal being the node 142. The flip-flop in this state functions as an inverter between the node 141 and the node 142. It is sufficient that a circuit for this purpose is arranged.

[0084] In the flip-flop of this embodiment, the node 142 is connected to the eighth transistor 108. This supplies V2, and advances the timing at which the sixth transistor 106 turns off. Therefore, the time during which the potential of the node 142 becomes V1-Vth105 can be shortened. The flip-flop of this embodiment is capable of high-speed operation and is suitable for larger display devices or This can be applied to higher resolution display devices.

[0085] As shown in FIG. 4B, the flip-flop of this embodiment includes a fifth transistor 1 Even if the first electrode of the first electrode 05 is connected to the first wiring 121, the same period as the set period described above is As a result, the flip-flop in FIG. 4B does not need the seventh wiring 127. Therefore, the yield can be improved. This allows the layout area to be reduced.

[0086] In order to set the potential of the node 142 to V2+β, the channel width of the fourth transistor 104 is The value of the ratio W / L of W to the channel length L of the third transistor 103 is It is preferable to set the value at least 10 times or more. The transistor size (W×L) becomes large. The value of the channel length L of the third transistor is set to be larger than the value of the channel length L of the fourth transistor 104, More preferably, it is set to 2 to 3 times. Since the register size can be reduced, the layout area can be reduced.

[0087] During the selection period shown in FIG. 2(B) and FIG. 3(B), the signal 221 is at L level, and the fifth The first transistor 105 and the eighth transistor 108 are turned off. Since the signal remains at the L level, the seventh transistor 107 remains off. 141 maintains the potential at V1-Vth 105. Therefore, the first transistor 10 The first and fourth transistors 104 remain on. Therefore, the second transistor 102 and the sixth transistor The transistor 106 remains off. Here, an H signal is input to the fifth wiring 125. Therefore, the potential of the third wiring 123 starts to rise. The strap operation increases from V1-Vth105 to V1+Vth101+α(Vt h101: threshold voltage of the first transistor 101, α: any positive number). Therefore, the potential of the third wiring 123 is the same as the potential of the fifth wiring 125, that is, V1. In this manner, during the selection period, the third wiring 123 is connected to the fifth wiring 125 to which the H signal is input. Therefore, the potential of the third wiring 123 becomes V1. It is output from 23.

[0088] This bootstrap operation occurs when the gate electrode of the first transistor 101 and the second electrode As shown in FIG. 1(B), the capacitance of the first transistor is By disposing the capacitor element 151 between the gate electrode and the second electrode of the transistor 101, A bootstrap operation can be performed, and the parasitic capacitance of the first transistor 101 can be reduced. The capacitor 151 uses a gate insulating film as an insulating layer, a gate electrode layer and a Alternatively, a gate insulating film may be used as the insulating layer, and a gate insulating film may be used as the conductive layer. An electrode layer and a semiconductor layer doped with impurities may be used. Alternatively, an interlayer may be used as an insulating layer. A film (insulating film) may be used, and a wiring layer and a transparent electrode layer may be used as the conductive layer. 151, when a gate electrode layer and a wiring layer are used as the conductive film, the gate electrode layer is The gate electrode of the first transistor 101 is connected to the wiring layer. It is preferable to connect the gate electrode layer and the wiring layer as the conductive film. In this case, the gate electrode layer is directly connected to the gate electrode of the first transistor 101, and the wiring layer is It is preferable to directly connect the second electrode of the first transistor 101. This is because the increase in layout area of ​​the flip-flop due to the placement of 1 is small.

[0089] As shown in FIG. 1C, a transistor 152 may be used as the capacitor 151. The transistor 152 has a gate electrode connected to the node 141, a first electrode and a second electrode. When the electrode is connected to the third wiring 123, the electrode functions as a capacitor having a large capacitance component. However, the transistor 152 can be connected to either the first electrode or the second electrode. Even if either one of them is in a floating state, it can still function as a capacitance element.

[0090] The first transistor 101 must supply an H signal to the third wiring 123 . Therefore, in order to shorten the fall and rise times of the signal 223, The W / L value of the transistor 101 is the same as that of the first to eighth transistors 101 to 108. It is desirable to have the maximum W / L value among the 108 values.

[0091] During the set period, the fifth transistor 105 The potential of the gate electrode of the transistor 101 must be V1-Vth105. The value of W / L of the fifth transistor 105 is larger than the value of W / L of the first transistor 101. It is recommended to set the ratio to 1 / 2 to 1 / 5, and more preferably 1 / 3 to 1 / 4.

[0092] During the reset period shown in FIG. 2(C) and FIG. 3(C), the signal 221 remains at the L level. Therefore, the fifth transistor 105 and the eighth transistor 108 remain off. Furthermore, since the signal 222 is at H level, the seventh transistor 107 is turned on. The potential of the node 141 is the potential (V2) of the eleventh wiring 131. 7, it becomes V2. Therefore, the first transistor 101 and the fourth The transistor 104 is turned off. At this time, the potential of the node 142 is The second electrode of the capacitor 103 serves as a source electrode, and the potential (V1) of the sixth wiring 126 is connected to the third Since the value is obtained by subtracting the threshold voltage of the transistor 103 from the value of V1-Vth103 (Vt h103: the threshold voltage of the third transistor 103). The sixth transistor 102 and the sixth transistor 106 are turned on. Since the third wiring 123 and the fourth wiring 124 to which V2 is supplied are electrically connected, Therefore, the potential of the third wiring 123 becomes V2. can be.

[0093] By delaying the timing when the seventh transistor 107 turns on, the rising edge of the signal 223 The fall time can be shortened because the L signal input to the fifth wiring 125 is This is because the voltage is supplied to the third wiring 123 via the first transistor 101, which has a large value of be.

[0094] The value of W / L of the seventh transistor 107 is reduced so that the potential of the node 141 becomes V2. Even if the fall time until the signal 223 falls is increased, the fall time of the signal 223 can be shortened. In this case, the value of W / L of the seventh transistor 107 is set to W / L of the first transistor 101. It is preferable to set the value to 1 / 10 to 1 / 40 times, more preferably 1 / 20 to 1 / 30 times, of the value.

[0095] As shown in FIG. 4A, a resistor element 401 is used instead of the third transistor 103. Therefore, the potential of the node 142 can be set to V1. In addition, the sixth transistor 106 can be easily turned on, and the operating efficiency can be improved. In addition, as shown in FIG. 4C, a transistor 4 is connected in parallel to the third transistor 103. 02 may also be connected.

[0096] During the non-selection periods shown in FIG. 2(D) and FIG. 3(D), the signal 221 remains at the L level. Therefore, the fifth transistor 105 and the eighth transistor 108 remain off. Furthermore, the signal 222 goes low, turning off the seventh transistor 107. At this time, the potential of the node 142 is maintained at V1-Vth103. The sixth transistor 102 and the sixth transistor 106 remain on. The potential of the node 141 is supplied with V2 through the sixth transistor 106. Therefore, the first transistor 101 and the fourth transistor 104 remain ON. In this way, during the non-selection period, the third wiring 123 and the V2 are supplied. Since the fourth wiring 124 connected to the third wiring 123 is conductive, the potential of the third wiring 123 remains at V2. Therefore, the L signal is output from the third wiring 123.

[0097] When the potential supplied to the sixth wiring 126 is set lower than V1, the potential of the node 142 is Therefore, the second transistor 102 and the sixth transistor 10 Therefore, the flip-flop of this embodiment can suppress the threshold voltage shift of As a semiconductor layer of a transistor, degradation of characteristics (shift in threshold voltage) is evident. Even when rufous silicon is used, deterioration of the transistor characteristics can be suppressed.

[0098] From the above, in the flip-flop of this embodiment, the node 14 The rise time of the potential of 1 can be shortened, enabling high-speed operation and the use of larger display devices. The present invention can be applied to display devices with higher resolution.

[0099] Here, the functions of the first transistor 101 to the eighth transistor 108 will be described. The first transistor 101 supplies the potential of the fifth wiring 125 to the third wiring 123. The potential of the node 141 is also controlled by the bootstrap function. It has the function of boosting the voltage by operation and functions as a bootstrap transistor. The second transistor 102 supplies the potential of the fourth wiring 124 to the third wiring 123. It has the function of selecting the timing and functions as a switching transistor. The transistor 103 divides the potential of the sixth wiring 126 and the potential of the eighth wiring 128. The fourth transistor has a function of having a resistance component or functions as a resistance element. The inverter 104 selects the timing at which the potential of the eighth wiring 128 is supplied to the node 142. The fifth transistor 105 has a function of switching the transistor. a function of selecting timing for supplying the potential of the seventh wiring 127 to the node 141; The sixth transistor 106 functions as an input transistor. The potential of the switching transistor 141 is supplied to the node 141. The seventh transistor 107 functions as a transistor. The switching transistor has a function of selecting the timing of supplying the voltage to the node 141. The eighth transistor 108 connects the potential of the ninth wiring 129 to the node 142 It has the function of selecting the timing to supply to .

[0100] However, the first transistor 101 to the eighth transistor 108 have the functions described above. As long as it has the above characteristics, it is not limited to a transistor. For example, a switching transistor The second transistor 102, the fourth transistor 104, and the sixth transistor 106 function as The seventh transistor 106, the seventh transistor 107 and the eighth transistor 108 are switching Any functional element, such as a diode, a CMOS analog switch, or various logic Furthermore, a fifth transistor that functions as an input transistor may be applied. The resistor 105 has the function of increasing the potential of the node 141 and selecting the timing to turn it off. If so, apply a PN junction diode or a diode-connected transistor. That's fine.

[0101] If it operates in the same way as Figure 1, the layout and number of transistors are limited to Figure 1. As can be seen from FIG. 3, which explains the operation of the flip-flop in FIG. 1(A), In this embodiment, the set period, the selection period, the reset period, and the non-selection period are shown in FIG. ) to 3(D) as shown by the solid line. If it is possible to place transistors and other elements in the (resistive elements, capacitive elements, etc.), diodes, switches, various logic circuits, etc. It may be placed.

[0102] Furthermore, if it operates in the same manner as in FIG. 1, the driving of the flip-flop of this embodiment The timing is not limited to the timing chart of FIG.

[0103] For example, as shown in the timing chart of FIG. 6, the first wiring 121 and the second wiring 12 2. The period during which the H signal is input to the fifth wiring 125 may be shortened. Compared with the timing chart, the timing when the signal switches from L level to H level is within the period T The signal is delayed by a1, and the timing at which the signal switches from H level to L level is Ta2. Therefore, the flip-flop to which the timing chart in Figure 6 is applied is ,The instantaneous current of each wiring becomes small, which leads to power saving, suppression of malfunctions, and improvement of operating efficiency. Furthermore, the flip-flop to which the timing chart of FIG. 6 is applied can be In the reset period, the fall time of the signal output from the third wiring 123 can be shortened. This is because the timing at which the potential of the node 141 becomes L level is within the period Ta1+. Since the delay is Ta2, the L signal input to the fifth wiring 125 is delayed by a large current capacity. The voltage is supplied to the third wiring 123 via the first transistor 101 having a large channel width. Note that the same symbols are used for the parts that are common to the timing chart in FIG. Therefore, the explanation will be omitted.

[0104] The relationship between the periods Ta1, Ta2, and Tb is ((Ta1+Tb) / (Ta1+T a2+Tb))×100<10[%] is desirable. More desirable is ((Ta It is desirable that Ta1 + Ta2 + Tb) / (Ta1 + Ta2 + Tb) × 100 < 5%. Furthermore, it is desirable that the period Ta1 is approximately equal to the period Ta2.

[0105] If it operates in the same way as in FIG. 1, the first wiring 121 to the eleventh wiring 131 can be freely For example, as shown in FIG. 5A, the second transistor 102 a first electrode of the fourth transistor 104; a first electrode of the sixth transistor 106; the first electrode of the seventh transistor 107 and the second electrode of the eighth transistor 108 The first electrode of the fifth transistor 105 may be connected to a sixth wiring 506. a first electrode of the third transistor 103 and a first electrode of the third transistor 103 The gate electrode may be connected to a fifth wiring 505. , the first electrode of the third transistor 103 and the gate electrode of the third transistor 103 may be connected to the seventh wiring 507. Here, the first wiring 501, the second wiring 50 The second, third wiring 503 and fourth wiring 504 are the same as the first wiring 121 and the second wiring 122 in FIG. These correspond to the first wiring 122, the third wiring 123 and the fifth wiring 125.

[0106] The flip-flops in Figures 5(A) and (B) can reduce the number of wires, improving yield. Furthermore, the flip-flops shown in Figs. 5(A) and (B) can be used to reduce the layout area. The flop can improve reliability and operational efficiency. In the flip-flop of B), the potential supplied to the sixth wiring 506 can be reduced. The shift in the threshold voltage of the first transistor 102 and the sixth transistor 106 can be suppressed. Cut.

[0107] An example of a top view of the flip-flop shown in FIG. 5(A) is shown in FIG. 29. The wiring 2951 includes a portion that functions as a first electrode of the first transistor 101. The conductive layer 2902 is connected to the fourth wiring 504 through the first transistor 101. The second electrode is connected to the third wiring 503 via the wiring 2952. The conductive layer 2903 is a gate electrode of the first transistor 101 and a gate electrode of the fourth transistor 102. The conductive layer 2904 includes a portion that functions as the gate electrode of the second transistor 104. a first electrode of the sixth transistor 102, a first electrode of the sixth transistor 106, a first electrode of the fourth transistor 104 and the portion serving as the first electrode of the eighth transistor 108. and is connected to the sixth wiring 506. The conductive layer 2905 is connected to the second transistor 102. The second electrode is connected to the third wiring 503 via the wiring 2954. The conductive layer 2906 is connected to the gate electrode of the second transistor 102 and the gate electrode of the sixth transistor 103. The conductive layer 2907 includes a portion that functions as the gate electrode of the third transistor 106. The fifth wiring 2955 includes a portion that functions as the first electrode of the resistor 103. The conductive layer 2908 is connected to the second electrode of the third transistor 103 and and a portion serving as the second electrode of the fourth transistor 104, and The conductive layer 2909 is connected to the gate of the third transistor 103. The fifth wiring 505 is connected to the second wiring 2955. The conductive layer 2910 includes a portion that functions as a first electrode of the fifth transistor 105. The conductive layer 2911 is connected to the fifth wiring 505 via a wiring 2959. The second electrode of the seventh transistor 105 and the second electrode of the seventh transistor 107. The conductive layer 2912 includes a portion where the conductive layer 2912 is connected to the conductive layer 2903 through a wiring 2958. , including a portion that functions as the gate electrode of the fifth transistor 105, and The conductive layer 2913 is connected to the first wiring 501. The second electrode is connected to the conductive layer 2903 via a wiring 2957. The conductive layer 2914 includes a portion that functions as the gate electrode of the seventh transistor 107. , and is connected to the second wiring 502 via a wiring 2962. The conductive layer 2915 is The conductive layer 2 includes a portion that functions as a gate electrode of the transistor 108 and is connected to the conductive layer 2 via a wiring 2961. The conductive layer 2916 is connected to the second electrode of the eighth transistor 108. It includes a functional portion and is connected to the conductive layer 2906 via a wiring 2953 .

[0108] Here, the wiring 2962 is a wiring 2951, a wiring 2952, a wiring 2953, a wiring 2954, Wiring 2955, Wiring 2956, Wiring 2957, Wiring 2958, Wiring 2959, Wiring 296 0 or the width of the wiring is smaller than the wiring 2961. In other words, the resistance value of the wiring 2962 is increased. By doing so, the potential of the conductive layer 2914 becomes H level during the reset period. Therefore, the timing of the seventh transaction can be delayed during the reset period. Since the timing at which the resistor 107 is turned on can be delayed, the third wiring 503 The signal can be set to L level early because the time when node 141 becomes L level During the delay, the L signal is input to the third This is because it is supplied to the wiring 503.

[0109] In addition, wiring 2951, wiring 2952, wiring 2953, wiring 2954, wiring 2955, wiring 2956, wiring 2957, wiring 2958, wiring 2959, wiring 2960, wiring 2961 and The wiring 2962 is similar to a pixel electrode (also called a transparent electrode or a reflective electrode). and are made by similar processes and materials.

[0110] The gate electrode, the first electrode, and the second electrode of the first transistor 101 The portions are formed by overlapping the conductive layer including each and the semiconductor layer 2981. The portions functioning as the gate electrode, the first electrode, and the second electrode of the second transistor 102 The portions are formed by overlapping the conductive layer including each of them with the semiconductor layer 2982. Portions that function as the gate electrode, the first electrode, and the second electrode of the third transistor 103 The fourth conductive layer and the semiconductor layer 2983 overlap each other. The portions that function as the gate electrode, the first electrode, and the second electrode of the transistor 104 are , and the conductive layer including the semiconductor layer 2984 overlap with each other. Portions that function as the gate electrode, the first electrode, and the second electrode of the transistor 105 are: The conductive layer including each of these and the semiconductor layer 2985 are overlapped with each other. The portions of the transistor 106 that function as the gate electrode, the first electrode, and the second electrode are The seventh transistor is formed by overlapping the conductive layer including the seventh transistor and the semiconductor layer 2986. The portions that function as the gate electrode, the first electrode, and the second electrode of the transistor 107 are This is a portion where the conductive layer including these and the semiconductor layer 2987 overlap. The portions of the transistor 108 that function as the gate electrode, the first electrode, and the second electrode are This is a portion where the conductive layer including this and the semiconductor layer 2988 overlap with each other.

[0111] Next, the configuration of the shift register having the flip-flop of the present embodiment and The driving method will be explained.

[0112] The configuration of the shift register of this embodiment will be described with reference to FIG. The register consists of n flip-flops (flip-flop 701_1 to flip-flop 701_n).

[0113] The connection relationship of the shift register in Figure 7 will be explained. The flip-flop 701_i in the i-th stage (flip-flop 701_1 to flip-flop 701_n) indicates that the first wiring 121 shown in FIG. 1(A) is connected to the seventh wiring The second wiring 122 shown in FIG. 1A is connected to the seventh wiring 71 7_i+1. The third wiring 123 shown in FIG. 1A is connected to the seventh wiring 717_ The fourth wiring 124, the eighth wiring 128, and the ninth wiring 129 shown in FIG. 129, the tenth wiring 130 and the eleventh wiring 131 are connected to the fifth wiring 715. The fifth wiring 125 shown in FIG. 1A is connected to the second wiring in the odd-numbered flip-flops. The flip-flops in the even-numbered stages are connected to the third wiring 712 , and the flip-flops in the even-numbered stages are connected to the third wiring 713 . The sixth wiring 126 and the seventh wiring 127 shown in FIG. 1A are connected to the fourth wiring 714. The first wiring 121 of the first stage flip-flop 701_1 shown in FIG. , is connected to the first wiring 711. Also, the n-th stage flip-flop 701_n in FIG. The second wiring 122 shown in A) is connected to the sixth wiring 716 .

[0114] The first wiring 711, the second wiring 712, the third wiring 713, and the sixth wiring 716 are These may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. The fourth wiring 714 and the fifth wiring 715 are called the first power supply line and the second power supply line, respectively. That's fine too.

[0115] Next, the operation of the shift register shown in FIG. 10 will be explained with reference to the timing chart of FIG. The timing chart of FIG. 8 is a timing chart showing the scanning period. The scanning period is divided into a period during which the selection signal is output from the seventh wiring 717_1 and a blanking period. This is the period from when the output of the selection signal from the seventh wiring 717_n starts until when the output of the selection signal from the seventh wiring 717_n ends. In the blanking period, the output of the selection signal from the seventh wiring 717_n is completed, and the seventh wiring 7 This is the period until the output of the selection signal from 17_1 starts.

[0116] A potential of V1 is supplied to the fourth wiring 714, and a potential of V2 is supplied to the fifth wiring 715. will be done.

[0117] The first wiring 711, the second wiring 712, the third wiring 713 and the sixth wiring 716 are 8 are inputted, respectively. Here, the signals 811, 812, 813, and 816 are the signals that are generated when the potential of the H signal is The potential of the V1 and L signals is V2. The signal 813 and the signal 816 are respectively a start signal, a first clock signal, and a second clock signal. These signals may also be called a clock signal (inverted clock signal) and a reset signal.

[0118] However, the first wiring 711 to the sixth wiring 716 are connected to various signals, potentials, and and current may be input.

[0119] The seventh wirings 717_1 to 717_n output the potentials of the H signals V1 and V2, respectively. The digital signals 817_1 to 817_n are output with the potential of the L signal being V2. As shown in FIG. 10, the seventh wiring 717_1 to the seventh wiring 717_n are connected to the buffers. The signal may be output via the buffers 1001_1 to 1001_n. The shift register divides the output signal of the shift register and the transfer signal of each flip-flop. So it's easy to make it work.

[0120] The buffers 1001_1 to 1001_n included in the shift register shown in FIG. An example will be described with reference to Figures 99(A) and 99(B). The buffer 8000 includes an inverter 8001a and an inverter 8002b between the wiring 8011 and the wiring 8012. By connecting inverter 8001b and inverter 8001c, the input to wiring 8011 is The inverted signal of the signal input to the line 8011 is output from the line 8012. There is no limit to the number of inverters connected between the wiring 8011 and the wiring 801. When an even number of inverters are connected between the two, the same signal as that input to the wiring 8011 is A signal of the polarity is output from the wiring 8012. Furthermore, the buffer 8100 in FIG. As shown, inverter 8002a, inverter 8002b, and inverter 8002c are connected in series. inverter 8002c, inverter 8003a, inverter 8003b, and inverter 8003c arranged in series. 99(B) and inverter 8003c may be connected in parallel. 0 is output from the wiring 8012 because it can average out the variations in the transistor characteristics. The delay and distortion of the signal can be reduced. The output of 8003a, and the outputs of inverter 8002b and inverter 8003b are , may be connected.

[0121] In FIG. 99(A), the W<inverter W of the transistor in inverter 8001b < W of the transistor in inverter 8001c , because the W of the transistor included in the inverter 8001a is The small size of the transistors reduces the driving capacity of the flip-flop (specifically, the transistor 10 in Figure 1(A)). Since the value of W / L in the shift register of the present invention can be reduced, the layout area of ​​the shift register of the present invention can be reduced. Similarly, in FIG. 99(B), the transistor of the inverter 8002a W of the transistor < W of the transistor of the inverter 8002b < inverter 8002 It is preferable that c is W of the transistor. Similarly, in FIG. 99(B), The W of the transistor in the inverter 8003a is less than the W of the transistor in the inverter 8003b. It is preferable that the W of the transistor included in the inverter 8003c is smaller than the W of the transistor included in the inverter 8003c. Furthermore, the W of the transistor in the inverter 8002a is equal to the W of the transistor in the inverter 8003a. The W of the transistor in inverter 8002b is equal to the W of the transistor in inverter 8002a. W of the transistor in inverter 8003b, W of the transistor in inverter 8002c = It is preferable that the W of the transistor included in the inverter 8003c is used.

[0122] The inverters shown in Figures 99(A) and 99(B) are designed to invert the input signal. There is no particular limitation as long as it can be outputted. For example, as shown in FIG. 99(C), The first transistor 8201 and the second transistor 8202 constitute an inverter. Furthermore, a signal is input to the first wiring 8211, and a signal is output from the second wiring 8212. A signal is output from the third wiring 8213, V1 is supplied to the third wiring 8214, and V 99C, the inverter inputs an H signal to the first wiring 8211. V1-V2 is divided by the first transistor 8201 and the second transistor 8202. potential (W / L of the first transistor 8201<W / L of the second transistor 8202) , and output from the second wiring 8212. Furthermore, the inverter in FIG. 99(C) When an L signal is input to 8211, V1-Vth8201 (Vth8201: the first transistor) The threshold voltage of the first transistor 8201 is output from the second wiring 8212. The transistor 8201 may be a PN junction diode, as long as it is an element having a resistance component. It may simply be a resistive element.

[0123] As shown in FIG. 99(D), the first transistor 8301 and the second transistor 830 2. The third transistor 8303 and the fourth transistor 8304 form an inverter. A signal is input to the first wiring 8311, and a signal is output from the second wiring 8312. A signal is output, V1 is supplied to the third wiring 8313 and the fifth wiring 8315, and V2 is supplied to the fourth wiring 8314 and the sixth wiring 8316. When an H signal is input to the first wiring 8311, the inverter outputs V2 from the second wiring 8312. At this time, the potential of the node 8341 is set to L level, and the first transistor 8 99(D) is turned off. When V is input, V1 is output from the second wiring 8312. At this time, the voltage of the node 8341 The value is V1-Vth8303 (Vth8303: threshold voltage of the third transistor 8303). When the potential of the node 8341 becomes By the bootstrap operation, V1+Vth8301 (Vth8301: the first transistor Since the voltage Vout becomes higher than the threshold voltage of the first transistor 8301, the first transistor 8301 is turned on. Furthermore, the first transistor 8301 is used as a bootstrap transistor. To function as a capacitor, a capacitive element may be disposed between the second electrode and the gate electrode.

[0124] As shown in FIG. 30A, a first transistor 8401 and a second transistor 840 2, an inverter is formed by a third transistor 8403 and a fourth transistor 8404 The inverter in FIG. 30(A) is a two-input inverter, and the A signal is input to the first wiring 8411, and a signal is input to the second wiring 84 An inverted signal is input to the third wiring 8412, and a signal is output from the third wiring 8413. V1 is supplied to the fifth wiring 8415 and the seventh wiring 8416. The inverter in FIG. 30A is connected to the first wiring 841 When an L signal is input to 1 and an H signal is input to the second wiring 8412, V2 is output from the third wiring 8413. At this time, the potential of the node 8441 becomes V2, and the first transistor 84 30A. Furthermore, the inverter in FIG. 30A applies a H signal to the first wiring 8411, When an L signal is input to the second wiring 8412, V1 is output from the third wiring 8413. At this time, the potential of the node 8441 is V1-Vth8403 (Vth8403: the third transistor When the voltage drops below the threshold voltage of the resistor 8403, the node 8441 is in a floating state. , the potential of the node 8441 becomes V1+Vth8401 (Vt h8401: the threshold voltage of the first transistor 8401) becomes higher, The transistor 8401 is turned on. Furthermore, the first transistor 8401 is turned on. To function as a trap transistor, a capacitance element is disposed between the second electrode and the gate electrode. Furthermore, one of the first wiring 8411 and the second wiring 8412 may be 1A, the third wiring 123 shown in FIG. 1A is connected to the other side, and the node 142 shown in FIG. It is recommended to connect

[0125] As shown in FIG. 30B, the first transistor 8501 and the second transistor 850 The second and third transistors 8502 may form an inverter. The inverter in B) is a two-input inverter and is capable of bootstrap operation. A signal is input to the first wiring 8511, and an inverted signal is input to the second wiring 8512. A signal is output from the third wiring 8513. A signal is output from the fourth wiring 8514 and the sixth wiring 8515. V1 is supplied to the fifth wiring 8516, and V2 is supplied to the fifth wiring 8515. When an L signal is input to the first wiring 8511 and an H signal is input to the second wiring 8512, the inverter , V2 is output from the third wiring 8513. At this time, the potential of the node 8541 becomes V2. Therefore, the first transistor 8501 is turned off. When an H signal is input to the first wiring 8511 and an L signal is input to the second wiring 8512, V1 is set to the third At this time, the potential of the node 8541 is V1-Vth8503 (Vth8503: threshold voltage of the third transistor 8503), the node 85 As a result, the potential of the node 8541 is V1+Vth8501 (Vth8501: threshold voltage of the first transistor 8501) Since the voltage becomes higher than the voltage (voltage), the first transistor 8501 is turned on. The transistor 8501 functions as a bootstrap transistor, so the second electrode A capacitor may be disposed between the first wiring 8511 and the gate electrode. One of the second wirings 8512 is connected to the third wiring 123 shown in FIG. The node 142 shown in FIG. 1(A) may be connected to the

[0126] As shown in FIG. 30C, the first transistor 8601 and the second transistor 860 2, the third transistor 8603 and the fourth transistor 8604 The inverter in FIG. 30(C) is a two-input inverter, Furthermore, a signal is input to the first wiring 8611, and a signal is input to the second wiring 8621. An inverted signal is input to the first wiring 8612 and a signal is output from the third wiring 8613 . The fourth wiring 8614 is supplied with V1, and the fifth wiring 8615 and the sixth wiring 8616 are supplied with V2. The inverter in FIG. 30C is supplied with an L signal to the first wiring 8611 and a V signal to the second wiring 8622. When an H signal is input to the second wiring 8612, V2 is output from the third wiring 8613. At this time, the potential of the node 8641 becomes V2, and the first transistor 8601 is turned off. 30(C) 。 Furthermore, the inverter of FIG. 30(C) is connected to the first wiring 8611 with an H signal and the second wiring 86 When an L signal is input to node 12, V1 is output from the third wiring 8613. The potential of 8641 is V1-Vth8603 (Vth8603: the third transistor 8603 When the voltage drops to the threshold voltage of the node 8641, the node 8641 is in a floating state. The voltage of 1 is V1+Vth8601 (Vth8601: Since the threshold voltage of the first transistor 8601 is higher than that of the first transistor 8602, The first transistor 8601 is a bootstrap transistor. A capacitance element may be disposed between the second electrode and the gate electrode to function as a capacitance element. One of the first wiring 8611 and the second wiring 8612 is connected to the third wiring 8611 shown in FIG. The other end of the wiring 123 is preferably connected to the node 142 shown in FIG.

[0127] In FIG. 7, the seventh wiring 717 is used as a start signal for the flip-flop 701_i. The signal output from the seventh wiring 717_i+1 is used as a reset signal. The start signal of the flip-flop 701_1 is a signal output from the first wiring The reset signal of the flip-flop 701_n is input from the sixth distribution The signal is input from a line 716. However, the reset signal for the flip-flop 701_n is A signal output from the seventh wiring 717_1 may be used, or a signal output from the seventh wiring 717_2 may be used. Alternatively, a dummy flip-flop can be newly placed to Alternatively, the output signal of a dummy flip-flop may be used. The number of signals can be reduced.

[0128] As shown in FIG. 9, for example, when the flip-flop 701_i is in the selected period, the seventh An H signal (selection signal) is output from the wiring 717_i. At this time, the flip-flop 70 1_i+1 is the set period. After that, the flip-flop 701_i is in the reset period. As a result, an L signal is output from the seventh wiring 717_i. The period 701_i+1 is the selected period. After that, the flip-flop 701_i is in the non-selected period. As a result, the L signal continues to be output from the seventh wiring 717_i. The flop 701_i+1 is in the reset period.

[0129] In this way, the shift register of FIG. 7 transmits the selection signal from the seventh wiring 717_1 to the seventh wiring 717_2 in order. In other words, the shift register of FIG. The first to seventh wirings 717_n can be scanned.

[0130] The shift register to which the flip-flop of this embodiment is applied is capable of high-speed operation. This embodiment can be applied to a higher resolution display device or a larger display device. The shift register using flip-flops in this state simplifies the process, reduces manufacturing costs, and This can improve productivity and yield.

[0131] Next, the structure and driving of a display device having the shift register of the present embodiment described above will be described. However, the display device of this embodiment has at least the method of this embodiment. It is sufficient to have a flip-flop.

[0132] The structure of the display device of this embodiment will be described with reference to FIG. The device has a signal line driver circuit 1101, a scanning line driver circuit 1102, and a pixel portion 1104. The pixel portion 1104 includes a plurality of signal lines extending from the signal line driver circuit 1101 in the column direction. Scanning lines S1 to Sm are a plurality of scanning lines extending in the row direction from the scanning line driving circuit 1102. G1 to Gn, and signal lines S1 to Sm and scanning lines G1 to Gn. Each pixel 1103 is connected to a signal line Sj (signal Scanning line Gi (one of scanning lines G1 to Gn) and is connected.

[0133] The shift register of this embodiment mode can be applied to the scanning line driver circuit 1102. Of course, the shift register of this embodiment mode may also be used in the signal line driver circuit 1101. stomach.

[0134] The scanning lines G1 to Gn correspond to the seventh wiring 717_1 to the seventh wiring 717_2 shown in FIGS. It is connected to 17_n.

[0135] The signal lines and the scanning lines may be simply called wirings. The scanning line driver circuit 1102 and the scanning line driver circuit 1103 may be referred to as driver circuits.

[0136] The pixel 1103 includes at least one switching element, one capacitance element, and a pixel electrode. However, the pixel 1103 has a plurality of switching elements or a plurality of capacitance elements. Furthermore, the capacitance element is not necessarily required. The pixel 1103 may have a transistor that operates in the sum region. The switching element may include a transistor and a display element such as an L element. However, a transistor and a PN junction diode can be used as a switching element. When using a transistor, it is desirable that the transistor operates in the linear region. When the scan line driver circuit 1102 is composed of only N-channel transistors, It is desirable to use an N-channel transistor as the switching element. When the switching circuit 1102 is composed of only P-channel transistors, It is desirable to use a P-channel transistor as the element.

[0137] The scanning line driver circuit 1102 and the pixel portion 1104 are formed on an insulating substrate 1105. The signal line driver circuit 1101 is not formed on the insulating substrate 1105. is formed on a single crystal substrate, an SOI substrate, or an insulating substrate other than the insulating substrate 1105. The signal line driver circuit 1101 transmits the signal via a printed circuit board such as an FPC. The signal line driver circuit 1101 is formed on an insulating substrate 1105. Alternatively, a circuit constituting a part of the signal line driving circuit 1101 may be formed on the insulating substrate 110. 5.

[0138] The signal line driver circuit 1101 inputs a voltage or a current as a video signal to the signal lines S1 to Sm. However, the video signal may be a digital signal or an analog signal. The video signal may be inverted between positive and negative polarities every frame (frame inversion drive). , the positive and negative polarities may be inverted for each row (gate line inversion drive). The signal may be inverted between positive and negative polarities for each column (source line inversion drive), or may be inverted for each row and The positive and negative polarities may be inverted for each column (dot inversion drive). The signals may be input to the signal lines S1 to Sm in a dot sequential driving manner or in a line sequential driving manner. Furthermore, the signal line driver circuit 1101 receives not only a video signal but also a precharge voltage and other signals. A constant voltage such as a precharge voltage may be input to the signal lines S1 to Sm. It is recommended to input the time for each route selection period and for each frame.

[0139] The scanning line driving circuit 1102 inputs signals to the scanning lines G1 to Gn, and drives the scanning lines G1 to Gn in a single drive mode. The scanning line driver circuit 1102 selects (hereinafter also referred to as scanning) the pixels in order from the th row. , selects a plurality of pixels 1103 connected to the selected scan line. The period during which the scanning line is selected is called one gate selection period, and the period during which the scanning line is not selected is called one gate selection period. Furthermore, the signal output from the scanning line driver circuit 1102 to the scanning line is called a non-selection period. Furthermore, the maximum value of the scanning signal is higher than the maximum value of the video signal or the maximum voltage of the signal line. and the minimum value of the scanning signal is smaller than the minimum value of the video signal or the minimum voltage of the signal line. It is characterized by its small size.

[0140] When the pixel 1103 is selected, a signal is sent from the signal line driver circuit 1101 via a signal line. When the pixel 1103 is not selected, a video signal is input to the pixel 1103. In this case, the pixel 1103 receives the video signal (potential corresponding to the video signal) input during the selection period. ) is held.

[0141] Although not shown, the signal line driver circuit 1101 and the scanning line driver circuit 1102 have a plurality of A potential and a number of signals are provided.

[0142] Next, the operation of the display device shown in FIG. 11 will be described with reference to the timing chart of FIG. In FIG. 12, one frame period corresponds to the period for displaying one screenful of image. There is no particular limit to the length of one frame period, but it is important to consider whether the person viewing the image notices flicker. It is preferable to set it to 1 / 60 seconds or less so that it is not noticeable.

[0143] In the timing chart of FIG. 12, the first scanning line G1, the i-th scanning line Gi, and the i+1 The timings at which the scanning line Gi+1 of the nth row and the scanning line Gn of the nth row are selected are shown. are.

[0144] In FIG. 12, for example, the i-th row of the scanning line Gi is selected, and a plurality of Then, the pixels 1103 connected to the scanning line Gi are selected as follows: A video signal is input to each pixel, and the pixel holds a potential corresponding to the video signal. The scanning line Gi is deselected, the scanning line Gi+1 on the i+1th row is selected, and the scanning line Gi+1 Then, a plurality of pixels 1103 connected to the scanning line Gi+1 are selected. Each of the pixels 1103 receives a video signal and holds a potential corresponding to the video signal. In this way, scanning lines G1 to Gn are selected in order during one frame period. Then, the pixels 1103 connected to each scanning line are selected in turn. A video signal is input to each of the plurality of pixels 1103 connected to the optical fiber 1101, and a voltage corresponding to the video signal is generated. Hold the position.

[0145] A display device using the shift register of this embodiment as a scanning line driver circuit 1102 has the following features: High-speed operation is possible, and therefore higher resolution or larger size can be achieved. The display device of this embodiment simplifies the manufacturing process, reduces manufacturing costs, and improves yield. This can be achieved.

[0146] The display device of FIG. 11 includes a signal line driver circuit 1101 that requires high-speed operation and a scanning line driver circuit 1102. The scanning line driver circuit 102 and the pixel portion 1104 are formed on separate substrates. The semiconductor layer of the transistor included in the pixel 1102 and the semiconductor layer of the transistor included in the pixel 1103 Amorphous silicon can be used as the semiconductor layer, resulting in a simplified manufacturing process. This allows for simplification, which in turn reduces manufacturing costs and improves yield. Therefore, the display device of this embodiment can be enlarged. Even if polysilicon or single crystal silicon is used as the conductor layer, the manufacturing process can be simplified. can be done.

[0147] The signal line driver circuit 1101, the scanning line driver circuit 1102, and the pixel portion 1104 are all mounted on the same substrate. In the case where the gate electrode is formed on a substrate, the semiconductor layer of the transistor included in the scanning line driver circuit 1102 and The semiconductor layer of the transistor in the pixel 1103 is made of polysilicon or single crystal silicon. It is recommended to use a recon.

[0148] If we could select pixels and write video signals to them independently, as shown in Figure 11, The number and arrangement of the driving circuits are not limited to those shown in FIG.

[0149] For example, as shown in FIG. 13, the scanning lines G1 to Gn are connected to the first scanning line driving circuit 130. The first scanning line driver 1302a and the second scanning line driver 1302b may be used for scanning. The scanning line driving circuit 1302a and the second driving circuit 1302b are the same as the scanning line driving circuit 1 shown in FIG. It has the same configuration as 102, and scans the scanning lines G1 to Gn at the same timing. The first scanning line driver circuit 1302a and the second driver circuit 1302b are connected to the first scanning line driver circuit 1302a and the second scanning line driver circuit 1302b, respectively. These may also be called the first drive circuit and the second drive circuit.

[0150] The display device of FIG. 13 includes a first scanning line driving circuit 1302a and a second scanning line driving circuit 1302b. Even if a defect occurs in one of the scanning line driving circuits 1302a and 302b, the scanning line driving circuit 1302a and the second scanning line driving circuit 302b can be maintained. The other of the driving circuits 1302b can scan the scanning lines G1 to Gn, providing redundancy. Furthermore, the display device of FIG. 13 has a load ( The wiring resistance of the scanning line and the parasitic capacitance of the scanning line and the load of the second scanning line driving circuit 1302b Therefore, the signal input to the scanning lines G1 to Gn can be reduced by half compared to FIG. The delay of the signal (output signals of the first scanning line driving circuit 1302a and the second driving circuit 1302b) Furthermore, the display device of FIG. 13 includes the first scanning line driving circuit 13. Since the load on the first scanning line driving circuit 1302a and the load on the second scanning line driving circuit 1302b are reduced, the load on the second scanning line driving circuit 1302a and the load on the second scanning line driving circuit 1302b are reduced. Furthermore, the scanning lines G1 to Gn can be scanned at high speed. Since the image can be scanned in a single scan, it is possible to increase the size of the panel or the resolution of the panel. Note that the same reference numerals are used for the components common to the configuration of FIG. 11, and the description thereof will be omitted.

[0151] As another example, FIG. 14 shows a display device that can write video signals to pixels at high speed. In the display device of FIG. 14, the pixels 1103 in the odd-numbered rows receive video signals from signal lines in the odd-numbered columns. A video signal is input to the pixels 1103 in the even-numbered rows from the signal lines in the even-numbered columns. Furthermore, in the display device of FIG. 14, the odd-numbered scanning lines among the scanning lines G1 to Gn are The scanning lines G1 to Gn are scanned by the scanning line driving circuit 1402a. The first scanning line is scanned by the second scanning line driving circuit 1402b. The start signal input to the first scanning line driver circuit 1402a is input to the second scanning line driver circuit 1402b. The input signal is delayed by 1 / 4 cycle of the clock signal from the input start signal.

[0152] The display device of FIG. 14 outputs a positive video signal to each signal line and column during one frame period. By simply inputting a positive polarity video signal and a negative polarity video signal, dot inversion driving can be performed. In the display device of FIG. 14, the polarity of the video signal input to each signal line is changed every frame period. By inverting the above, frame inversion driving can be performed.

[0153] The operation of the display device of FIG. 14 will be described with reference to the timing chart of FIG. In the timing chart of FIG. 15, the first scanning line G1, the (i-1)th scanning line Gi-1, The i-th scanning line Gi, the i+1-th scanning line Gi+1, and the n-th scanning line Gn are respectively Furthermore, the timing chart in FIG. 15 shows the timing at which one The selection period is divided into selection period a and selection period b. In this example, the display device of FIG. 14 is driven by dot inversion and frame inversion. I will explain.

[0154] In FIG. 15, for example, the selection period a of the i-th row scanning line Gi is The selection period b of the i-th scanning line Gi overlaps with the selection period b of the i+1-th scanning line Gi. The selection period a of the eye scanning line Gi+1 overlaps with the selection period a. Therefore, in the selection period a, i The same video signal as that input to pixel 1103 in the -1th row and j+1th column is input to pixel 1103 in the ith row and jth column. Furthermore, during the selection period b, the pixel 1103 in the i-th row and j-th column The same video signal as the input signal is input to pixel 1103 in row i+1 and column j+1. In addition, the video signal input to the pixel 1103 during the selection period b is the original video signal. In the selection period a, the video signal input to the pixel 1103 is Therefore, each pixel 1103 is The pixel 1103 in the (i-1)th row and the (j+1)th column is precharged by a video signal input to the pixel 1103 in the (i-1)th row and the (j+1)th column. After that, the original video signal (row i, column j) is input during selection period b.

[0155] From the above, the display device of FIG. 14 can write video signals to the pixels 1103 at high speed. Therefore, it is possible to easily realize a larger size and higher resolution. In a display device, video signals of the same polarity are input to each signal line during one frame period. Therefore, the charge and discharge of each signal line is small, and low power consumption can be achieved. The load on the IC for inputting the video signal is significantly reduced, reducing the heat generated by the IC and the I Furthermore, the display device of FIG. The driving frequencies of the driving circuit 1402a and the second scanning line driving circuit 1402b can be reduced by approximately half. This allows for power savings.

[0156] The display device of this embodiment mode can achieve various display effects depending on the configuration and driving method of the pixel 1103. For example, in one frame period, the scanning line driving circuit The scan line may be scanned multiple times.

[0157] The display devices of FIGS. 11, 13 and 14 may be configured with different wirings etc. depending on the configuration of the pixel 1103. For example, a power supply line, a capacitance line, and a new scanning line that are kept at a constant potential may be added. When a new scanning line is added, the shift register of this embodiment is As another example, a scanning line driver circuit using a dummy scanning A line, a signal line, a power supply line or a capacitance line may be disposed in the pixel portion.

[0158] In the present embodiment, various drawings have been used to describe the present invention. or part of the content may also be applied to or combined with the content or part of the content described in another figure. Furthermore, in the figures described above, each part can be represented as another part. By combining these, even more diagrams can be constructed.

[0159] The contents or part of the contents described in each drawing of this embodiment may be described in a drawing of another embodiment. The present invention may also be applied to or combined with the above content or part of the content. In the drawings of the embodiment, each part may be combined with parts of another embodiment. Many more diagrams can be constructed.

[0160] This embodiment is an example of a case where the contents described in the other embodiments are embodied, and is a slightly modified version. An example of a case where the product has been partially changed, an example of an improvement, or an example of a case where the product has been described in detail. Examples of the application and related parts are shown. Therefore, the contents described in the other embodiments can also be applied to this embodiment. It can be combined.

[0161] (Embodiment 2) In this embodiment, a flip-flop different from that in the first embodiment is used. and driving method for a display device having the driving circuit - Patents.com The same components as those in the first embodiment are designated by the same reference numerals, and the same parts are A detailed description of the components or components having similar functions will be omitted.

[0162] The configuration of the flip-flop of this embodiment is the same as that of the first embodiment. Therefore, in this embodiment, the structure of the flip-flop can be described. However, the timing of driving the flip-flop is different from that of the first embodiment. .

[0163] The drive timing of this embodiment will be described when applied to FIG. 1(A). The driving timing of the embodiment is shown in FIGS. 1(B), 1(C), 4(A), 4(B), and 4 (C) Implemented in any combination with the flip-flops in Figures 5(A) and 5(B). Furthermore, the driving timing of this embodiment can be the same as the driving timing described in the first embodiment. It can also be freely combined with timing.

[0164] The operation of the flip-flop of this embodiment will be described with reference to the flip-flop of FIG. 16. Furthermore, the timing chart of FIG. The period will be explained by dividing it into a set period, a selection period, a reset period, and a non-selection period. The set period is divided into a first set period and a second set period, and the selection period is the first It is divided into a selection period and a second selection period.

[0165] The first wiring 121, the fifth wiring 125 and the second wiring 122 are respectively connected to the wirings shown in FIG. The signals 1621, 1625, and 1622 are input to the third wiring. 16. Here, the signal 1621, the signal 1622, and the signal 1623 are output from the signal 123. 625, signal 1622 and signal 1623 correspond to signals 221 and 222 shown in FIG. 25, signal 222 and signal 223. Furthermore, signals 1621, 1625, The signals 1622 and 1623 are respectively a start signal, a clock signal, and a reset signal. These may also be referred to as input and output signals.

[0166] The flip-flop of this embodiment is basically the same as the flip-flop described in the first embodiment. However, the flip-flop of this embodiment operates in the same manner as the flip-flop. The timing at which the H signal is input is delayed by 1 / 4 of the clock signal period. , which is different from the flip-flop of the first embodiment.

[0167] The flip-flop of this embodiment has a first set period (A1) and a second set period (A2) shown in FIG. In the set period (A2), reset period (C) and non-selection period (D), 2 shows the non-selection period (D), set period (A), reset period (C) and non-selection period The operation is the same as (D), so the explanation is omitted.

[0168] As shown in FIG. 17, the flip-flop of this embodiment has a second wiring 122 connected to an H signal. The timing of inputting the clock is delayed by 1 / 4 of the clock signal. The fall time can be significantly shortened. During the first reset period shown in FIG. 17, the flip-flop supplies L When a signal is input, the potential of the node 141 drops to approximately V1+Vth101. Therefore, the first transistor 101 remains on, and the L signal is output from the third wiring 123. The third wiring 123 is connected to the first transistor 101 having a large W / L value. Therefore, the potential of the third wiring 123 changes from the H level to the L level. After that, the flip-flop of this embodiment, which is shown in FIG. In the second reset period shown in FIG. 17(C2), the seventh transistor 107 is turned on, and the potential of the node 141 becomes V2. At this time, the potential of the node 142 ( The potential 1642) becomes V1-Vth103, and the third transistor 103 turns on. Therefore, the L signal is output from the third wiring 123.

[0169] The flip-flop of this embodiment is similar to the flip-flop shown in Embodiment 1. The effect can be obtained.

[0170] Next, the configuration of the shift register having the flip-flop of the present embodiment and The driving method will be explained.

[0171] The configuration of the shift register of this embodiment will be described with reference to FIG. The shift register consists of n flip-flops (flip-flop 1801_1 to flip-flop It has flop 1801_n).

[0172] The connection relationship of the shift register in FIG. 18 will be described. The flip-flop 1801_i (flip-flop 1801_1 to flip-flop In any one of the flops 1801_n, the first wiring 121 shown in FIG. , is connected to the tenth wiring 1820_i-1. The second wiring 122 shown in FIG. , is connected to the tenth wiring 1820_i+2. The third wiring 123 shown in FIG. , and the tenth wiring 1820_i. The first wiring 128, the ninth wiring 129, the tenth wiring 130 and the eleventh wiring 131 are The fifth wiring 125 shown in FIG. 1(A) is connected to the wiring 1817 of 4N-3(N is a natural number equal to or greater than 1) is connected to the second wiring 1812 in the flip-flop of the 4N-th stage. The flip-flop in the second stage is connected to the third wiring 1813, and the flip-flop in the 4N-1 stage is connected to the third wiring 1814. In the flip-flop, it is connected to the fourth wiring 1814, and in the 4Nth stage flip-flop, it is connected to the fifth wiring 1815. The sixth wiring 126 and the seventh wiring 127 shown in FIG. , and is connected to the sixth wiring 1816. However, the first-stage flip-flop 1801_1 1A is connected to the first wiring 1811. In the first stage flip-flop 1801_n-1, the second wiring 12 shown in FIG. 2 is connected to the ninth wiring 1819. In the n-th stage flip-flop 1801_n, Thus, the second wiring 122 shown in FIG. 1A is connected to the eighth wiring 1818 .

[0173] When the timing chart of FIG. 17 is applied to the flip-flop of this embodiment, In the flip-flop 1801_i in the i-th stage, the second wiring 122 shown in FIG. 0 wiring 1820_i+3. Therefore, the n-3th flip-flop 1 In 801_n-3, the second wiring 122 shown in FIG. 1(A) is replaced with a newly added wiring is connected.

[0174] First wiring 1811, second wiring 1812, third wiring 1813, fourth wiring 1814 , the fifth wiring 1815, the eighth wiring 1818, and the ninth wiring 1819 are respectively the first signal line, the second signal line, the third signal line, the fourth signal line, the fifth signal line, the sixth signal line, and The sixth wiring 1816 and the seventh wiring 1817 may also be referred to as the sixth wiring 1816 and the seventh wiring 1817. may be referred to as the first power line and the second power line, respectively.

[0175] Next, the operation of the shift register shown in FIG. 18 will be described with reference to the timing chart and 19 and the timing chart of FIG. 20. The port is divided into a scan period and a retrace period.

[0176] The sixth wiring 1816 is supplied with a potential of V1. The potential V2 is supplied.

[0177] First wiring 1811, second wiring 1812, third wiring 1813, fourth wiring 1814 , the fifth wiring 1815, the eighth wiring 1818, and the ninth wiring 1819 are respectively 19 shows signals 1911, 1912, 1913, 1914, and 1915, Signals 1918 and 1919 are input. Here, signals 1911, 1912, Signals 1913, 1914, 1915, 1918 and 1919 are H signals. The potential of the L signal is V1, and the potential of the L signal is V2. No. 1912, Signal 1913, Signal 1914, Signal 1915, Signal 1918 and Signal 19 19 are respectively the start signal, the first clock signal, the second clock signal, and the third clock signal. These signals are called the first clock signal, the fourth clock signal, the first reset signal and the second reset signal. Good too.

[0178] However, the first wiring 1811 to the ninth wiring 1819 are respectively connected to various signals and electric The position and current may be input.

[0179] The tenth wirings 1820_1 to 1820_n respectively output the potentials of H signals at V1 and L signals at V2. Digital signals 1920_1 to 1920_n with a potential of V2 are output. As in the first embodiment, the tenth wirings 1820_1 to 1820_n are connected to the buffers. This makes it easier to operate.

[0180] The tenth wiring 1820_i-1 is used as a start signal for the flip-flop 1801_i. The signal output from the tenth wiring 1820_i+2 is used as a reset signal. Here, the start signal of the flip-flop 1801_1 is the first The second reset signal of the flip-flop 1801_n-1 is input from the wiring 1811. The signal is input from the ninth wiring 1819. The bit signal is input from the eighth wiring 1818. The signal output from the tenth wiring 1820_1 is used as the second reset signal of n-1. As a first reset signal for the flip-flop 1801_n, the tenth wiring 1820 Alternatively, the signal output from the flip-flop 1801_n-1 may be used. As the second reset signal, a signal output from the tenth wiring 1820_2 is used. As a first reset signal of the flip-flop 1801_n, a signal is output from the tenth wiring 1820_3. Alternatively, a signal output from the first dummy flip-flop and the second dummy flip-flop may be used. The output of the first dummy flip-flop is The output signal of the second dummy flip-flop is connected to the first reset signal. This can be used as a first reset signal and a second reset signal. can be reduced.

[0181] As shown in FIG. 20, for example, the flip-flop 1801_i is in the first selection period. When this occurs, an H signal (selection signal) is output from the tenth wiring 1820_i. The flip-flop 1801_i+1 then goes into the second set period. Even when the 1801_i is in the second selection period, the H signal is output from the 10th wiring 1820_i. At this time, the flip-flop 1801_i+1 remains at the first selection After that, when the flip-flop 1801_i enters the reset period, the 10th At this time, the flip-flop 1801_i outputs an L signal. +1 is the second selection period. After that, the flip-flop 1801_i is in the non-selection period. Even if this happens, the L signal continues to be output from the tenth wiring 1820_i. At this time, the flip-flop 1801_i+1 enters a reset period.

[0182] In this way, the shift register of FIG. 18 sequentially transmits the selection signal from the tenth wiring 1820_1. Furthermore, the shift register of FIG. The second selection period of the flip-flop 1801_i and the first selection period of the flip-flop 1801_i+1 Since the selection period of the 10th wiring 1820_i and the 10th wiring 1820_i are the same period, A selection signal can be output from the wiring 1820_i+1.

[0183] The shift register to which the flip-flop of this embodiment is applied is suitable for a high-definition display device or The shift register of this embodiment can be applied to a large display device. The same effect as that of the shift register shown in FIG.

[0184] Next, the configuration and driving method of a display device having the shift register of the present embodiment described above will be described. However, the display device of this embodiment is at least It is sufficient to have a flip-flop.

[0185] The structure of the display device of this embodiment will be described with reference to FIG. In this arrangement, the scanning lines G1 to Gn are scanned by a scanning line driving circuit 2102. In the display device of FIG. 21, the pixels 1103 on the odd-numbered rows receive a video signal from the signal lines on the odd-numbered rows. and a video signal is input to the pixels 1103 on the even-numbered rows from the signal lines on the even-numbered rows. Note that the same components as those in the configuration of FIG. 11 are denoted by the same reference numerals and their description will be omitted.

[0186] In the display device of FIG. 21, the shift register of this embodiment mode is applied to a scanning line driver circuit 2102. By using this, the same operation as that of the display device of FIG. 14 can be achieved with one scanning line driving circuit. As a result, the same effect as that of the display device in FIG. 14 can be obtained.

[0187] As in FIG. 13, the scanning lines G1 to Gn are connected to the first scanning line driving circuit 2202a and The second scanning line driver circuit 2202b may be used for scanning. As a result, the display device shown in FIG. The same effect as that of the device can be obtained. The configuration in this case is shown in Figure 22.

[0188] In the present embodiment, various drawings have been used to describe the present invention. or part of the content may also be applied to or combined with the content or part of the content described in another figure. Furthermore, in the figures described above, each part can be represented as another part. By combining these, even more diagrams can be constructed.

[0189] The contents or part of the contents described in each drawing of this embodiment may be described in a drawing of another embodiment. The present invention can be applied to or combined with the above content or part of the content. In the drawings of the embodiments, each part may be combined with a part of another embodiment. allows for the construction of even more diagrams.

[0190] This embodiment is an example of a case where the contents described in the other embodiments are embodied, and is a slightly modified version. An example of a case where the product has been partially changed, an example of an improvement, or an example of a case where the product has been described in detail. Examples of the application and related parts are shown. Therefore, the contents described in the other embodiments can be applied to this embodiment or can be combined with it. It is possible.

[0191] (Embodiment 3) In this embodiment, a flip-flop different from those in the first and second embodiments is used. Configuration of a drive circuit having a flip-flop and a display device having the drive circuit The flip-flop of this embodiment mode is a flip-flop having a driving method. The output signal and the transfer signal of the flip-flop are routed to separate wiring by separate transistors. The output is similar to that of the first and second embodiments. In the following description, common reference numerals are used to denote the same parts or parts having similar functions. is omitted.

[0192] The basic structure of a flip-flop of this embodiment mode will be described with reference to FIG. The flip-flop shown in 23 is the flip-flop of FIG. 1(A) with a ninth transistor 109 and a tenth transistor 110 are added.

[0193] The connection relationship of the flip-flop in FIG. 23 will be described. The first electrode of the ninth transistor 109 is connected to the thirteenth wiring 133, and the second electrode of the ninth transistor 109 is connected to the thirteenth wiring 133. is connected to the twelfth wiring 132, and the gate electrode of the ninth transistor 109 is connected to the node The first electrode of the tenth transistor 110 is connected to the fourteenth wiring 141. 34, and the second electrode of the tenth transistor 110 is connected to the twelfth wiring 132. The gate electrode of the tenth transistor 110 is connected to the node 142. The other connections are the same as those in FIG. 1(A).

[0194] The thirteenth wiring 133 and the fourteenth wiring 134 are connected to the fifth signal line and the eighth signal line, respectively. It may also be called a power line.

[0195] Next, the operation of the flip-flop shown in FIG. 23 will be explained with reference to the timing chart of FIG. Here, the timing chart of FIG. 24 will be explained in terms of the set period, the selection period, The explanation will be divided into a reset period and a non-selection period. The selection period and non-selection period are sometimes collectively referred to as the non-selection period.

[0196] The third wiring 123 and the twelfth wiring 132 transmit signals 223 and 232, respectively. The signal 232 is the output signal of the flip-flop, and the signal 223 is the output signal of the flip-flop. The transfer signal of the flip-flop. However, the signal 223 is the output signal of the flip-flop, and the signal 2 32 may be used as a transfer signal for the flip-flop.

[0197] The signal 232 is the output signal of the flip-flop, and the signal 223 is the transfer signal of the flip-flop. When the ninth transistor 109 is used as the first transistor 106, the value of W / L of the ninth transistor 109 is set to It is preferable that the W / L of the first to tenth transistors 110 is the largest. is used as the output signal of the flip-flop, and signal 232 is used as the transfer signal of the flip-flop. In this case, the value of W / L of the first transistor 101 is set to the value of W / L of the first to tenth transistors 101 to 10 It is preferable to set the W / L of the transistor 110 to the maximum.

[0198] In this embodiment, as already described, the output signal of the flip-flop and the The transfer signal of the flop is output from a separate wiring by a separate transistor. That is, the flip-flop of FIG. The transistor 102 outputs a signal from the third wiring 123. The tenth transistor 109 and the tenth transistor 110 transfer the signal from the twelfth wiring 132. Furthermore, the ninth transistor 109 and the tenth transistor 110 output a signal. , the first transistor 101 and the second transistor 102 are connected in the same manner. Therefore, as shown in FIG. 24, the signal (signal 232) output from the twelfth wiring 132 is The waveform is roughly the same as that of the signal (signal 223) output from the wiring 123 of No. 3.

[0199] The first transistor 101 is connected to the gate electrode of the fifth transistor 105 in the next stage, and Since it is sufficient to supply charges to the gate electrodes of the first and eighth transistors 108, The W / L value of the fifth transistor 101 is set to be equal to or less than twice the W / L value of the fifth transistor 105. It is more preferable that the value of W / L of the fifth transistor 105 is equal to or less than that of the fifth transistor 105. stomach.

[0200] The ninth transistor 109 and the tenth transistor 110 are the first transistors. The ninth transistor 101 and the second transistor 102 have the same functions. The transistor 109 and the tenth transistor 110 may be called a buffer unit.

[0201] From the above, in the flip-flop of FIG. 23, a large load is connected to the twelfth wiring 132. Even if the signal 232 is delayed or distorted, malfunctions can be prevented. Therefore, the flip-flop in Figure 23 has the output signal of the flip-flop and By outputting the transfer signal of the flop and the transfer signal from separate wiring using separate transistors, This is because the output signal is not affected by delays or distortions.

[0202] The flip-flop of FIG. 23 is the flip-flop described in the first and second embodiments. It has the same effect as a lop.

[0203] The flip-flop of this embodiment is shown in FIGS. 1B, 1C, 4A, and 4B. ), and can be freely combined with Figure 4(C), Figure 5(A) and Figure 5(B). Furthermore, the flip-flop of this embodiment mode is driven by the same timing as that described in Embodiment 1. and the driving timing described in the second embodiment can be freely combined. do.

[0204] Next, the configuration of the shift register having the flip-flop of the present embodiment and The driving method will be explained.

[0205] The configuration of the shift register of this embodiment will be described with reference to FIG. The shift register consists of n flip-flops (flip-flop 2501_1 to flip-flop flop 2501_n).

[0206] Flip-flops 2501_1 to 2501_n, first wiring 2511 , a second wiring 2512, a third wiring 2513, a fourth wiring 2514, and a fifth wiring 2515 7. The sixth wiring 2516 is connected to the flip-flops 701_1 to 701_2 in FIG. 01_n, a first wiring 711, a second wiring 712, a third wiring 713, and a fourth wiring 714 , the fifth wiring 715 and the sixth wiring 716, and the same signal or the same power supply voltage is input. Then, the seventh wiring 2517_1 to the seventh wiring 2517_n and the eighth wiring The eighth wiring 2518_1 to the eighth wiring 2518_n correspond to the seventh wiring 717_1 to the seventh wiring 717_n in FIG. Equivalent to 17_n.

[0207] Next, regarding the operation of the shift register shown in FIG. 25, the timing chart of FIG. 26 will be explained. Please refer to the following for explanation.

[0208] The operation of the shift register shown in Figure 25 is different from that of the shift register shown in Figure 7. The difference is that the output signal and the transfer signal are output to separate wiring. The signals are output to the eighth wiring 2518_1 to the eighth wiring 2518_n, and are transmitted. The signals are output to the seventh wirings 2517_1 to 2517_n, respectively.

[0209] The shift register of FIG. 25 has eighth wirings 2518_1 to 2518_n. Even if a large load (such as resistance or capacitance) is connected, the device will operate without being affected by the load. Furthermore, the shift register of FIG. 25 has eighth wiring 2518_1 to eighth wiring 2518_2. Even if any of the 8_n pins is shorted to the power supply line or signal line, normal operation can continue. Therefore, the shift register of FIG. 25 has the advantages of improved operation efficiency, improved reliability, and reduced step size. This is because the shift register of FIG. This is because the transfer signal of the flip-flop and the output signal of each flip-flop are separated.

[0210] The shift register to which the flip-flop of this embodiment is applied is the same as that of the first embodiment and the second embodiment. The same effects as those of the shift register described in the second embodiment can be obtained.

[0211] The shift register of this embodiment can be freely combined with the shift registers of FIGS. Furthermore, the shift register of this embodiment can be implemented in combination with the shift register of the first embodiment. This can also be freely combined with the description of the second embodiment.

[0212] As the display device of this embodiment, the display devices shown in FIGS. 11, 13, 14, 21 and 22 are Therefore, the display device of this embodiment can be used in the same manner as in the first embodiment. The same effects as those of the display device described in the second embodiment can be obtained.

[0213] In the present embodiment, various drawings have been used to describe the present invention. The content or part of the content may also be applied to or combined with the content or part of the content described in another figure. Furthermore, in the figures described above, each part can be represented as another part. By combining the minutes, even more figures can be constructed.

[0214] The contents or part of the contents described in each drawing of this embodiment may be described in a drawing of another embodiment. The present invention can be applied to or combined with the above content or part of the content. In the drawings of the embodiments, each part may be combined with a part of another embodiment. allows for the construction of even more diagrams.

[0215] This embodiment is an example of a case where the contents described in the other embodiments are embodied, and is a slightly modified version. An example of a case where the product has been partially changed, an example of an improvement, or an example of a case where the product has been described in detail. Examples of the application and related parts are shown. Therefore, the contents described in the other embodiments can be applied to this embodiment or can be combined with it. It is possible.

[0216] (Fourth embodiment) In this embodiment, a P-channel transistor is used as the transistor included in the flip-flop of this specification. The case where a flip-flop is applied will be described. The present invention also describes a driving circuit for a display device having the driving circuit and a driving method thereof. do.

[0217] The flip-flop of this embodiment mode has a transistor included in the flip-flop of FIG. The polarity of the transistor is P-channel. The flip-flop can achieve the same effect as the flip-flop in Figure 1. B), Fig. 1(C), Fig. 4(A), Fig. 4(B), Fig. 4(C), Fig. 5(A), Fig. 5(B) and The polarity of the transistors of the flip-flop shown in FIG. 23 is set to P-channel type. The flip-flop of this embodiment mode can be configured as any of the flip-flops of Embodiments 1 to 3. This can also be implemented in any combination with the description of 3.

[0218] The basic structure of a flip-flop of this embodiment mode will be described with reference to FIG. The flip-flop shown in FIG. 27 includes a first transistor 2701 to an eighth transistor 2702. 08. The first to eighth transistors 2701 to 2708 have 1A. However, the first transistor 2701 to the eighth transistor 2708 are P-channel transistors. The absolute value of the gate-source voltage (|Vgs|) is the absolute value of the threshold voltage. When the voltage exceeds the threshold (|Vth|) (when Vgs falls below Vth), the transistor becomes conductive. It shall be.

[0219] The flip-flop of this embodiment includes a first transistor 2701 to an eighth transistor The capacitor 2708 is characterized in that it is all composed of P-channel transistors. Therefore, the flip-flop of this embodiment mode can simplify the manufacturing process, reduce the manufacturing cost, and This can improve the yield.

[0220] The connection relationship of the flip-flops in FIG. 27 is the same as that in FIG. 1(A), so it will be omitted here.

[0221] The first wiring 2721 to the eleventh wiring 2731 in FIG. 27 correspond to the first wiring 121 to the eleventh wiring 2731 in FIG. 11 correspond to the wiring 131.

[0222] Next, the operation of the flip-flop shown in FIG. 27 will be explained with reference to the timing chart of FIG. Here, the timing chart of FIG. 28 will be explained with reference to the set period, selection period, and reset period. The explanation will be divided into a set period and a non-selection period. The selection period and non-selection period are sometimes collectively referred to as the non-selection period.

[0223] The timing chart in Figure 28 shows the H and L levels of the timing chart in Figure 2 reversed. In other words, the flip-flop in FIG. 27 is the same as the flip-flop in FIG. Compared to a flop, the H and L levels of the input and output signals are simply inverted. In addition, signals 2821, 2825, 2841, 2842, and 282 2 and signal 2823 correspond to signals 221, 225, 241, 242, and 283 in FIG. These correspond to signal 222 and signal 223, respectively.

[0224] The power supply voltage supplied to the flip-flop in FIG. 27 is the same as that of the flip-flop in FIG. Compared to the flop, V1 and V2 are inverted.

[0225] First, the operation of the flip-flop during the set period shown in FIG. 28(A) will be explained. The potential 2841 of the node 2741 becomes V2+|Vth2705|. 741 is in a floating state while maintaining the potential at V2+|Vth2705|. At the node 2742, the potential 2842 is V1-θ (θ: any positive number). Since the first transistor 2701 and the second transistor 2702 are on, the H signal is output from the third wiring 2723.

[0226] The operation of the flip-flop during the selection period shown in FIG. 28(B) will be described. The voltage 2841 of 2741 becomes V2-|Vth2701|- by the bootstrap operation. γ (Vth2701: threshold voltage of the first transistor 2701, γ: any positive number) Therefore, the first transistor 2701 is turned on, and the L signal is supplied to the third wiring 27 It is output from 23.

[0227] The operation of the flip-flop during the reset period shown in FIG. 28(C) will be described. Since the transistor 2707 of No. 7 is turned on, the potential 2841 of the node 2741 becomes V1. Therefore, the first transistor 2701 is turned off. At this time, the potential of the node 2742 2842 becomes V2+|Vth2703|, and the second transistor 2702 turns on. Therefore, the H signal is output from the third wiring 2723.

[0228] The operation of the flip-flop during the non-selection period shown in FIG. 28(D) will be described. The potential 2841 of the node 2741 remains at V1. Since V2+ remains at |Vth2703|, the second transistor 2702 remains on. Therefore, an H signal is output from the third wiring 2723.

[0229] The shift register of this embodiment is the flip-flop of this embodiment, The shift registers described in any of the above embodiments can be freely combined with the shift registers described in any of the above embodiments. For example, the shift register of this embodiment may be a flip-flop as shown in FIG. It can be freely combined with the shift registers of FIG. 10 and FIG. 25. However, the shift register of this embodiment is the same as the shift register described in the first to third embodiments. Compared to the register, the H and L levels are inverted.

[0230] The display device of this embodiment is a display device in which the shift register of this embodiment is used in the display device of the first to third embodiments. The present embodiment can be freely combined with the display device according to the third embodiment. The display device of the embodiment is the same as the display devices of FIGS. 11, 13, 14, 21 and 22. However, the display device of this embodiment can be implemented in any combination. Compared with the display devices described in the first to third embodiments, the H level and the L level are inverted. .

[0231] In the present embodiment, various drawings have been used to describe the present invention. The content or part of the content may also be applied to or combined with the content or part of the content described in another figure. Furthermore, in the figures described above, each part can be represented as another part. By combining the minutes, even more figures can be constructed.

[0232] The contents or part of the contents described in each drawing of this embodiment may be described in the drawings of another embodiment. It can be applied to or combined with the entire content or part of the content. In the drawings of this embodiment, each part is combined with a part of another embodiment. This allows for even more diagrams to be constructed.

[0233] This embodiment is an example of a case where the contents described in the other embodiments are embodied, and is a slightly modified version. An example of a case where the product has been partially changed, an example of an improvement, or an example of a case where the product has been described in detail. Examples of the application and related parts are shown. Therefore, the contents described in the other embodiments can be applied to this embodiment or can be combined with it. It is possible.

[0234] (Embodiment 5) In this embodiment mode, the signal line driver included in the display device described in any of Embodiments 1 to 4 is The operating circuit will now be described.

[0235] The signal line driver circuit shown in Fig. 31 will be described. The signal line driver circuit shown in Fig. 31 includes a driver IC 5601, switch group 5602_1 to 5602_M, first wiring 5611, second wiring The switch includes a line 5612, a third wiring 5613, and wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M includes a first switch 5603a, a second switch 5603b, and a The first switch 5603b and the second switch 5603c.

[0236] The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, and the third wiring 56 13 and the wiring 5621_1 to 5621_M. _1 to 5602_M are the first wiring 5611, the second wiring 5612, and the third wiring 5613. 5613 and wiring 5621 corresponding to each of the switch groups 5602_1 to 5602_M _1 to 5621_M. Each of the first switch 5603a, the second switch 5603b, and the third switch 5603c is connected to the first switch 5603a. For example, the wiring 5621 in the Jth column is connected to three signal lines via the switch 5603c. _J (one of the wirings 5621_1 to 5621_M) is connected to the switch group 5602 The first switch 5603a, the second switch 5603b and the third switch 5603c included in the The signal line Sj-1, the signal line Sj, and the signal line Sj+1 are connected via the switch 5603c. .

[0237] The first wiring 5611, the second wiring 5612, and the third wiring 5613 are each connected to a signal line. The number is entered.

[0238] The driver IC5601 is formed on a glass substrate using a single crystal substrate or polycrystalline semiconductor. Furthermore, the switch groups 5602_1 to 5602_M are preferably configured as It is desirable that the pixel portion shown in the first embodiment and the pixel portion shown in the second embodiment be formed on the same substrate. Therefore, the driver IC 5601 and the switch groups 5602_1 to 5602_M are It is recommended to connect via an FPC or similar.

[0239] Next, the operation of the signal line driver circuit shown in FIG. 31 will be described with reference to the timing chart of FIG. The timing chart in FIG. 32 is for when the i-th scanning line Gi is selected. Furthermore, the selection period of the i-th scanning line Gi is The first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 are Furthermore, the signal line driving circuit of FIG. 31 is divided into Even in this case, the same operation as in FIG. 32 is performed.

[0240] In the timing chart of FIG. 32, the wiring 5621_J in the Jth column is connected to the first switch 560 3a, the second switch 5603b, and the third switch 5603c, and the signal line Sj 1, and is connected to signal line Sj and signal line Sj+1.

[0241] The timing chart of FIG. 32 shows the timing when the i-th scanning line Gi is selected, the timing when the first The on / off timing 5703a of the switch 5603a, the timing of the second switch 5603b On / off timing 5703b, on / off timing of the third switch 5603c 5703c and a signal 5721_J input to the wiring 5621_J in the Jth column. do.

[0242] The wirings 5621_1 to 5621_M are connected to the first sub-selection period T1 and the second sub-selection period T2. In the period T2 and the third sub-selection period T3, different video signals are input. For example, in the first sub-selection period T1, the video signal input to the wiring 5621_J is input to the signal line Sj-1. The video signal input to the third sub-selection period T3 is input to the signal line Sj. The video signal input to the wiring 5621_J is input to the signal line Sj+1. In the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, The video signals input to the wiring 5621_J are respectively designated as Dataj-1 and Dataj and Dataj+1.

[0243] As shown in FIG. 32, during the first sub-selection period T1, the first switch 5603a The first switch 5603b and the third switch 5603c are turned on, and the second switch 5603b and the third switch 5603c are turned off. Then, Dataj-1 input to the wiring 5621_J is input via the first switch 5603a. During the second sub-selection period T2, the second switch 5603 b is turned on, and the first switch 5603a and the third switch 5603c are turned off. At this time, Dataj input to the wiring 5621_J is input via the second switch 5603b. During the third sub-selection period T3, the third switch 5603c The first switch 5603a and the second switch 5603b are turned on, and the first switch 5603a and the second switch 5603b are turned off. Then, Dataj+1 input to the wiring 5621_J is input via the third switch 5603c. and input to the signal line Sj+1.

[0244] From the above, the signal line driver circuit of FIG. 31 can divide one gate selection period into three. During one gate selection period, a video signal is input from one wiring 5621 to three signal lines. Therefore, the signal line driver circuit in FIG. The number of connections between the substrate on which the pixel part is formed and the substrate on which the pixel part is formed is approximately 1 / 2 of the number of signal lines. 3. By reducing the number of connections to about one-third, the signal line driver circuit of FIG. can improve reliability, yield, etc.

[0245] The signal line driver circuit of this embodiment mode is applied to the display devices shown in Embodiments 1 to 4. By applying this technology, the number of connections between the substrate on which the pixel section is formed and the external substrate can be further reduced. Therefore, the display device of the present invention can improve reliability and yield. It is possible to aim higher.

[0246] Next, the first switch 5603a, the second switch 5603b and the third switch 5603c are connected to the The case where an N-channel transistor is applied to 603c will be explained with reference to FIG. In addition, the same parts as those in FIG. 31 are denoted by the same reference numerals, and the same parts or A detailed description of parts having similar functions will be omitted.

[0247] The first transistor 5903a in FIG. 33 corresponds to the first switch 56 in FIG. The second transistor 5903b in FIG. 33 corresponds to the first transistor 5903a in FIG. The third transistor 5903c in FIG. This corresponds to the third switch 5603c in FIG.

[0248] For example, in the case of the switch group 5602_M, the first transistor 5903a The first electrode is connected to the wiring 5621_J, the second electrode is connected to the signal line Sj-1, and the gate electrode The first electrode of the second transistor 5903b is connected to the first wiring 5611. The gate electrode is connected to the signal line Sj, and the second electrode is connected to the second wiring 5621_J. A first electrode of the third transistor 5903c is connected to a wiring 5621. _J, the second electrode is connected to the signal line Sj+1, and the gate electrode is connected to the third wiring 56 Connected to 13.

[0249] A first transistor 5903a, a second transistor 5903b, and a third transistor The first transistor 5903c functions as a switching transistor. The transistor 5903a, the second transistor 5903b and the third transistor 59 03c are turned on when the signal input to the gate electrode is at H level, and When the signal input to the electrode is at L level, it is turned off.

[0250] A first switch 5603a, a second switch 5603b and a third switch 5603 By using an N-channel transistor as c, the semiconductor layer of the transistor Since amorphous silicon can be used as the material, the manufacturing process can be simplified and manufacturing costs can be reduced. Furthermore, it is possible to reduce costs and improve yields. It is also possible to fabricate devices using polysilicon as the semiconductor layer of a transistor. Even if silicon or polycrystalline silicon is used, the manufacturing process can be simplified.

[0251] In the signal line driver circuit of FIG. 33, the first transistor 5903a and the second transistor 5 N-channel transistors are used as the first transistor 903b and the second transistor 5903c. In the above description, the first transistor 5903a and the second transistor 59 P-channel transistors are used as the first transistor 5903b and the third transistor 5903c. In this case, the transistor is turned on when the signal input to the gate electrode is at L level. When the signal input to the gate electrode is at H level, the transistor is turned on.

[0252] As shown in Figure 31, one gate selection period is divided into multiple sub-selection periods. A video signal is input to each of the multiple signal lines from one wiring in each of the If this is possible, there are no restrictions on the arrangement, number, driving method, etc. of the switches.

[0253] For example, in each of three or more sub-selection periods, three or more signal lines are connected to one wiring. When inputting a video signal to each, a switch and a wiring for controlling the switch are required. However, if one gate selection period is divided into four or more sub-selection periods, Therefore, one gate selection period is divided into two or Preferably, it is divided into three sub-selection periods.

[0254] As another example, as shown in the timing chart of FIG. 34, one selection period is precharged. a page period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third selection period Furthermore, the timing chart of FIG. 34 shows that the scanning line Gi of the i-th row Selected timing, on / off timing 5803a of first switch 5603a , the on / off timing 5803b of the second switch 5603b, the third switch 56 The on / off timing of 03c is input to 5803c and the Jth row wiring 5621_J. As shown in FIG. 34, during the precharge period Tp, , a first switch 5603a, a second switch 5603b and a third switch 5603 At this time, the precharge voltage Vp input to the wiring 5621_J is via the first switch 5603a, the second switch 5603b and the third switch 5603c. The signals are input to the signal lines Sj-1, Sj, and Sj+1, respectively. During the selection period T1, the first switch 5603a is turned on and the second switch 5603b is turned off. At this time, the third switch 5603c is turned off. Dataj-1 is input to signal line Sj-1 via the first switch 5603a. In the second sub-selection period T2, the second switch 5603b is turned on, and the first switch 56 At this time, the input terminal 5621_J is connected to the wiring 5621_J. The resulting Dataj is input to the signal line Sj via the second switch 5603b. In the third sub-selection period T3, the third switch 5603c is turned on, and the first switch 560 3a and the second switch 5603b are turned off. At this time, Dataj+1 is input to the signal line Sj+1 via the third switch 5603c. do.

[0255] From the above, the signal line driver circuit of FIG. 31 to which the timing chart of FIG. 34 is applied has the following characteristics: By providing a precharge selection period before the sub-selection period, the signal line is precharged. Therefore, video signals can be written to the pixels at high speed. The same reference numerals are used to denote the same parts or parts having similar functions. The explanation will be omitted.

[0256] In Figure 35, as in Figure 31, one gate selection period is divided into multiple sub-selection periods. In each of the sub-selection periods, a signal is transmitted from one wiring to each of the signal lines. In addition, FIG. 35 shows the signal line driver circuit for the J-th column. Only the switch group 6022_J is shown. The switch group 6022_J includes the first transistor a first transistor 6001, a second transistor 6002, a third transistor 6003, a fourth transistor a fifth transistor 6004, a fifth transistor 6005 and a sixth transistor 6006. The first transistor 6001, the second transistor 6002, the third transistor a fourth transistor 6003, a fifth transistor 6004, a sixth transistor 6005, and a The transistor 6006 is an N-channel transistor. , a first wiring 6011, a second wiring 6012, a third wiring 6013, and a fourth wiring 6014 , the fifth wiring 6015, the sixth wiring 6016, the wiring 5621_J, the signal line Sj-1, the signal It is connected to the line Sj and the signal line Sj+1.

[0257] A first electrode of the first transistor 6001 is connected to a wiring 5621_J, and a second electrode of the first transistor 6001 is connected to a wiring 5621_J. The electrode is connected to the signal line Sj-1, and the gate electrode is connected to the first wiring 6011. A first electrode of the second transistor 6002 is connected to the wiring 5621_J, and a second electrode of the second transistor 6002 is connected to the wiring 5621_J. , is connected to the signal line Sj-1, and the gate electrode is connected to the second wiring 6012. A first electrode of the transistor 6003 is connected to the wiring 5621_J, and a second electrode of the transistor 6003 is connected to the signal line 5621_J. The gate electrode is connected to the third wiring 6013. The first electrode of the signal line 6004 is connected to the wiring 5621_J, and the second electrode is connected to the signal line Sj. The fifth transistor 60 is connected to the fourth wiring 6014, and the gate electrode of the fifth transistor 60 is connected to the fourth wiring 6014. A first electrode of the transistor 05 is connected to the wiring 5621_J, and a second electrode of the transistor 05 is connected to the signal line Sj+1. The sixth transistor 6006 has a gate electrode connected to a fifth wiring 6015. The first electrode of the pixel 5621 is connected to the wiring 5621_J, and the second electrode of the pixel 5621 is connected to the signal line Sj+1. The gate electrode is connected to a sixth wiring 6016 .

[0258] A first transistor 6001, a second transistor 6002, and a third transistor 60 03, a fourth transistor 6004, a fifth transistor 6005 and a sixth transistor The first transistor 6006 functions as a switching transistor. a first transistor 6001, a second transistor 6002, a third transistor 6003, a fourth transistor 6004, a The first transistor 6004, the fifth transistor 6005 and the sixth transistor 600 6 are turned on when the signal input to the gate electrode is at H level, and It is turned off when the signal input to is at L level.

[0259] The first wiring 6011 and the second wiring 6012 in FIG. 35 are the same as the first wiring 561 in FIG. 35 corresponds to the second wiring 6013 and the fourth wiring 6014 in FIG. The fifth wiring 6015 and the sixth wiring 6016 in FIG. This corresponds to the third wiring 5613 in FIG. 33. and the second transistor 6002 corresponds to the first transistor 5903a in FIG. The third transistor 6003 and the fourth transistor 6004 in FIG. This corresponds to the second transistor 5903b. The sixth transistor 6006 corresponds to the third transistor 5903c in FIG.

[0260] In FIG. 35, during the first sub-selection period T1 shown in FIG. 32, the first transistor 6 Either the first transistor 6001 or the second transistor 6002 is turned on. 2, either the third transistor 6003 or the fourth transistor 6004 In the third sub-selection period T3, the fifth transistor 6005 or the sixth transistor 6006 is turned on. In addition, either of the transistors 6006 is turned on. During Tp, the first transistor 6001, the third transistor 6003, and the fifth transistor 6004 the first transistor 6005, the second transistor 6002, and the fourth transistor 6004 and the sixth transistor 6006 is turned on.

[0261] Therefore, in FIG. 35, the on time of each transistor can be shortened, and each This can suppress the deterioration of the transistor characteristics. For example, in the first example shown in FIG. In the first sub-selection period T1, the first transistor 6001 or the second transistor If either of the switches 6002 is on, the video signal can be input to the signal line Sj-1. Here, in the first sub-selection period T1 shown in FIG. By simultaneously turning on the first transistor 6001 and the second transistor 6002, A high-speed video signal can also be input to the signal line Sj-1.

[0262] In FIG. 35, when two transistors are connected in parallel between the wiring 5621 and the signal line, However, the present invention is not limited to this, and three or more transistors may be connected to the wiring 56. 21 and the signal line. The deterioration of characteristics can be suppressed.

[0263] In the present embodiment, various drawings have been used to describe the present invention. The content or part of the content may also be applied to or combined with the content or part of the content described in another figure. Furthermore, in the figures described above, each part can be represented as another part. By combining the minutes, even more figures can be constructed.

[0264] The contents or part of the contents described in each drawing of this embodiment may be described in a drawing of another embodiment. The present invention can be applied to or combined with the above content or part of the content. In the drawings of the embodiments, each part may be combined with a part of another embodiment. allows for the construction of even more diagrams.

[0265] This embodiment is an example of a case where the contents described in the other embodiments are embodied, and is a slightly modified version. An example of a case where the product has been partially changed, an example of an improvement, or an example of a case where the product has been described in detail. Examples of the application and related parts are shown. Therefore, the contents described in the other embodiments can be applied to this embodiment or can be combined with it. It is possible.

[0266] (Embodiment 6) In this embodiment mode, the display devices described in Embodiment Modes 1 to 4 are prevented from being damaged by electrostatic discharge. A configuration for preventing such defects will be described below.

[0267] Electrostatic discharge occurs when positive or negative charges accumulated on a person or object are transferred to a semiconductor device. When touched, a large current is instantly discharged through the input / output terminals of the device, preventing it from entering the device. This refers to the destruction caused by the flow of water.

[0268] Figure 36(A) shows a protective diode to prevent electrostatic breakdown occurring on the scanning line. FIG. 36(A) shows the configuration of a protection diode disposed between the wiring 6111 and the scan line. Although not shown, a plurality of pixels are connected to the i-th row scanning line Gi. The transistor 6101 is used as a protection diode. 1 is an N-channel transistor. However, if a P-channel transistor is used, The polarity of the transistor 6101 may be changed by the polarity of the transistor included in the scan line driver circuit or the pixel. The polarity of the polarity may be the same as that of the polarity ...

[0269] Although only one protection diode is installed, multiple protection diodes are installed in series. They may be arranged separately, in parallel, or in series and parallel.

[0270] The transistor 6101 has a first electrode connected to the i-th scan line Gi and a second electrode is connected to the wiring 6111, and the gate electrode is connected to the scanning line Gi of the i-th row.

[0271] The operation of FIG. 36(A) will be described. A certain potential is input to the wiring 6111. The potential is lower than the L level of the signal input to the i-th row scanning line Gi. Or, if the negative charge is not discharged to the ith scanning line Gi, the charge of the ith scanning line Gi Since the signal is at H level or L level, the transistor 6101 is off. On the other hand, when a negative charge is discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi becomes At this time, the potential of the scanning line Gi in the i-th row is gradually lowered from the potential of the wiring 6111 to the potential of the transistor When the voltage drops below the threshold voltage of the transistor 6101, the transistor 6101 is turned on. As a result, a current flows through the transistor 6101 to the wiring 6111. Therefore, the configuration shown in FIG. 36(A) can prevent a large current from flowing into the pixel. Therefore, electrostatic damage to the pixels can be prevented.

[0272] FIG. 36(B) shows the structure for preventing electrostatic breakdown when a positive charge is discharged to the i-th scanning line Gi. The transistor 6102, which functions as a protection diode, is It is placed between the line and the wiring 6112. Only one protection diode is placed. However, multiple protection diodes may be arranged in series or in parallel. The transistor 6102 may be an N-channel However, a P-channel transistor may also be used. The polarity of the transistor 6102 is the same as the polarity of the transistors in the scanning line driver circuit and the pixel. The first electrode of the transistor 6102 is connected to the i-th scan line Gi. The second electrode is connected to a wiring 6112, and the gate electrode is connected to the wiring 6112. The wiring 6112 has a signal higher than the H level of the signal input to the i-th row scanning line Gi. Therefore, the transistor 6102 transfers the charge to the i-th scanning line G On the other hand, if a positive charge is not discharged to the i-th scanning line Gi, When discharged, the potential of the i-th scanning line Gi rises instantaneously. The potential of the scan line Gi is greater than the sum of the potential of the wiring 6112 and the threshold voltage of the transistor 6102. When the voltage becomes higher than the reference voltage, transistor 6102 turns on. Therefore, the current flows through the wiring 6112. Therefore, it is possible to prevent a large current from flowing into the pixel, and thus it is possible to prevent electrostatic damage to the pixel. It is possible.

[0273] As shown in FIG. 36(C), a configuration in which FIG. 36(A) and FIG. 36(B) are combined is used. By doing so, even if a positive charge is discharged to the i-th scanning line Gi, a negative charge is Even if a discharge occurs to the scanning line Gi, electrostatic damage to the pixel can be prevented. 6(A) and (B) are shown with the same symbols, and the same parts or A detailed description of the parts having various functions will be omitted.

[0274] FIG. 37A shows a transistor 6201 functioning as a protective diode connected to a scan line. The figure shows the configuration when connected between the capacitance lines. Note that only one protection diode is provided. However, multiple protection diodes may be arranged in series or in parallel. The transistor 6201 may be an N-channel transistor. However, a P-channel transistor may also be used. The polarity of the transistor 6201 is the same as the polarity of the transistors in the scanning line driver circuit and the pixel. The wiring 6211 functions as a storage capacitor line. The first electrode of 6201 is connected to the i-th scanning line Gi, and the second electrode is connected to the wiring 6211. The gate electrode is connected to the i-th row scanning line Gi. , a potential lower than the L level of the signal input to the i-th row scanning line Gi is input. Therefore, when the charge is not discharged to the i-th row scanning line Gi, the transistor 6201 On the other hand, when negative charges are discharged to the i-th row scanning line Gi, At this time, the potential of the scanning line Gi of the i-th row drops instantaneously. When the potential of the transistor 6201 becomes lower than the potential of the transistor 211 minus the threshold voltage of the transistor 6201, As a result, the current flows through the transistor 6201. Therefore, the configuration shown in FIG. 37(A) prevents a large current from flowing to the pixel. Therefore, electrostatic damage to the pixels can be prevented. Furthermore, in the configuration shown in FIG. 37(A), the storage capacitance line is used as a wiring for dissipating the electric charge. So there is no need to add new wiring.

[0275] FIG. 37(B) shows how to prevent electrostatic breakdown when a positive charge is discharged to the i-th scanning line Gi. Here, the wiring 6211 is configured to receive the signal input to the i-th row scanning line Gi. A potential higher than the H level of the signal is input. When no charge is discharged to the i-th scanning line Gi, the gate is turned off. When a charge is discharged to the ith scanning line Gi, the potential of the ith scanning line Gi rises instantaneously. At this time, the potential of the i-th scan line Gi is the potential of the wiring 6211 and the potential of the transistor 62 When the voltage Vout becomes higher than the sum of the threshold voltages of transistors 6202 and 6203, transistor 6202 turns on. As a result, a current flows through the transistor 6202 to the wiring 6211. The configuration shown in (B) can prevent a large current from flowing into the pixel. Therefore, electrostatic damage to the pixels can be prevented. The storage capacitance line is used as a wiring to release the charge, so there is no need to add a new wiring. In addition, the same parts as those in FIG. 37(A) are indicated by the same reference numerals, and the same parts are Alternatively, detailed descriptions of parts having similar functions will be omitted.

[0276] Next, we will show the configuration for preventing electrostatic breakdown that occurs in signal lines using a protection diode. 38(A). In FIG. 38(A), a protection diode is connected between the wiring 6411 and the signal line. Although not shown, the j-th column signal line Sj has a plurality of pixels. The transistor 6401 is used as a protection diode. 401 is an N-channel transistor. However, if a P-channel transistor is used, The polarity of the transistor 6401 can be changed depending on the polarity of the transistor included in the signal line driver circuit or the pixel. The polarity of the polarity of the starter may be the same as that of the starter.

[0277] Although only one protection diode is installed, multiple protection diodes are installed in series. They may be arranged separately, in parallel, or in series and parallel.

[0278] The transistor 6401 has a first electrode connected to the j-th signal line Sj and a second electrode is connected to a wiring 6411 , and the gate electrode is connected to the wiring 6411 .

[0279] The operation of FIG. 38A will be described. A certain potential is input to the wiring 6411. The potential is lower than the minimum value of the video signal input to the j-th column signal line Sj. If no positive or negative charge is discharged to the j-th signal line Sj, Since the potential of j is the same as the video signal, the transistor 6401 is off. On the other hand, when a negative charge is discharged to the jth row signal line Sj, the potential of the jth column signal line Sj momentarily becomes At this time, the potential of the j-th signal line Sj drops from the potential of the wiring 6411 to the potential of the transistor. When the voltage drops below the threshold voltage of the transistor 6401, the transistor 6401 is turned on. As a result, a current flows through the transistor 6401 to the wiring 6411. Therefore, the configuration shown in FIG. 38(A) can prevent a large current from flowing into the pixel. Therefore, electrostatic damage to the pixels can be prevented.

[0280] FIG. 38(B) shows how to prevent electrostatic breakdown when a positive charge is discharged to the j-th signal line Sj. The transistor 6402, which functions as a protection diode, It is placed between the line and the wiring 6412. Only one protection diode is placed. However, multiple protection diodes may be arranged in series or in parallel. The transistor 6402 may be an N-channel transistor. However, a P-channel transistor may also be used. The polarity of 6402 is the same as the polarity of the transistors in the signal line driver circuit and the pixel. The first electrode of the transistor 6402 is connected to the j-th signal line Sj. The second electrode is connected to the wiring 6412, and the gate electrode is connected to the signal line Sj in the j-th column. The wiring 6412 has a maximum value of 1 / 2 of the video signal input to the signal line Sj of the jth column. Therefore, the charge in the j-th column of the transistor 6402 is When no discharge is made to the signal line Sj, it is turned off. On the other hand, when a positive charge is made to the j-th column signal When a discharge occurs in the line Sj, the potential of the j-th signal line Sj rises instantaneously. The potential of the signal line Sj in the column 1 is the potential of the wiring 6412 and the threshold voltage of the transistor 6402. When the voltage becomes higher than the sum of A current flows through the wiring 6412 via 402. Therefore, in the configuration shown in FIG. This prevents a large current from flowing into the pixel, thus preventing electrostatic damage to the pixel. This can be prevented.

[0281] As shown in FIG. 38(C), a configuration in which FIG. 38(A) and FIG. 38(B) are combined is used. By doing so, even if a positive charge is discharged to the j-th signal line Sj, a negative charge is not discharged to the j-th signal line Sj. Even if a discharge occurs to the first signal line Sj, electrostatic damage to the pixel can be prevented. The same parts as those in Figures 38(A) and (B) are indicated by the same reference numerals, and the same parts or A detailed description of parts having similar functions will be omitted.

[0282] In this embodiment, in order to prevent electrostatic breakdown of pixels connected to scanning lines and signal lines, However, the configuration of this embodiment is different from the configuration of the pixel connected to the scanning line and the signal line. For example, the present invention is not limited to the prevention of electrostatic breakdown in the first embodiment. 4 is inputted to the scanning line driver circuit and the signal line driver circuit. When this embodiment is applied to the wiring, the electrostatic Destruction can be prevented.

[0283] In the present embodiment, various drawings have been used to describe the present invention. The content or part of the content may also be applied to or combined with the content or part of the content described in another figure. Furthermore, in the figures described above, each part can be represented as another part. By combining the minutes, even more figures can be constructed.

[0284] The contents or part of the contents described in each drawing of this embodiment may be described in the drawings of another embodiment. It can also be applied to or combined with the entire content or part of the content. In the drawings of the embodiments, each part may be combined with a part of another embodiment. By doing so, even more diagrams can be constructed.

[0285] This embodiment is an example of a case where the contents described in the other embodiments are embodied, and is a slightly modified version. An example of a case where the product has been partially changed, an example of an improvement, or an example of a case where the product has been described in detail. Examples of the application and related parts are shown. Therefore, the contents described in the other embodiments can be applied to this embodiment or can be combined with it. It is possible.

[0286] (Embodiment 7) In this embodiment mode, a display device that can be applied to the display devices described in any of Embodiments 1 to 4 will be described. A new configuration of the device will be described.

[0287] Figure 39(A) shows a diode-connected transistor between two scan lines. In FIG. 39(A), the scanning line Gi-1 in the i-1th row and the scanning line Gi-2 in the i-th row are arranged in the A diode-connected transistor 6301a is placed between the i-th scanning line Gi, A diode-connected transistor is connected between the scanning line Gi of the first row and the scanning line Gi+1 of the (i+1)th row. The figure shows the configuration when the transistor 6301a and the transistor 6301b are arranged. The transistor 6301b is an N-channel transistor. A transistor may be used. The polarity may be the same as that of the transistors in the scanning line driver circuit and the pixels. .

[0288] In FIG. 39(A), the scanning line Gi-1 in the (i-1)th row, the scanning line Gi in the i-th row, and The scan line Gi+1 on the i+1th row is shown, but the other scan lines are also diode-connected in the same way. The transistor is arranged.

[0289] A first electrode of the transistor 6301a is connected to the i-th scan line Gi, and a second electrode is connected to the scanning line Gi-1 in the (i-1)th row, and the gate electrode is connected to the scanning line Gi in the Gi-1th row. A first electrode of the transistor 6301b is connected to the scan line Gi+1 in the (i+1)th row. 1, the second electrode is connected to the scanning line Gi of the i-th row, and the gate electrode is It is connected to the scanning line Gi.

[0290] The operation of Fig. 39(A) will be described. In the driving circuit, during the non-selection period, the (i-1)th scanning line Gi-1 and the i-th scanning line Gi The i+1th row scanning line Gi+1 is maintained at the L level. However, for example, the transistor 6301a and the transistor 6301b are turned off. When the potential of the ith scanning line Gi rises due to noise or other reasons, the ith scanning line Gi Therefore, the wrong pixel will be selected and an incorrect video signal will be written to the pixel. As shown in A), by placing a diode-connected transistor between the scan lines, This prevents an incorrect video signal from being written to the i-th row. The potential of the scan line Gi is the potential of the scan line Gi-1 of the (i-1)th row and the threshold of the transistor 6301a. When the voltage rises above the sum of the voltages of the i-th row and the Therefore, the pixel is not selected by the i-th row scanning line Gi. Because there isn't.

[0291] The configuration of FIG. 39(A) is such that the scanning line driving circuit and the pixel section are integrally formed on the same substrate. This is advantageous when using N-channel transistors or P-channel transistors. In a scanning line driver circuit that is composed only of transistors, the scanning lines may be in a floating state. This is because noise is likely to occur in the scanning lines.

[0292] FIG. 39(B) shows a case where the direction of the diode-connected transistors arranged between the scanning lines is reversed. This is a configuration in which the transistors 6302a and 6302b is an N-channel transistor. However, if a P-channel transistor is used, The polarities of the transistors 6302a and 6302b may be changed by the scanning line driver circuit. The polarity of the transistors in the transistors and pixels may be the same as that of the transistors in the transistors in the transistors. A first electrode of the transistor 6302a is connected to the i-th scan line Gi, and a second electrode of the transistor 6302a is connected to the i-th scan line Gi. , the gate electrode is connected to the scanning line Gi-1 of the i-1th row, and the gate electrode is connected to the scanning line Gi of the i-th row. A first electrode of the transistor 6302b is connected to the scan line Gi+1 of the (i+1)th row. , the second electrode is connected to the i-th scanning line Gi, and the gate electrode is connected to the i+1-th scanning line G FIG. 39(B) shows the same as FIG. 38(A) in that the voltage of the scanning line Gi in the i-th row is The potential of the scanning line Gi+1 of the (i-1)th row and the threshold voltage of the transistor 6302b are When the potential of the scanning line Gi of the i-th row rises above the sum of Therefore, the pixel is not selected by the scanning line Gi of the i-th row, and the pixel This can prevent an incorrect video signal from being written to the memory card.

[0293] As shown in FIG. 39(C), a configuration in which FIG. 39(A) and FIG. 39(B) are combined is used. By this, even if the potential of the i-th scan line Gi rises, the transistors 6301a and 6301b Since the transistor 6302b is turned on, the potential of the scanning line Gi in the i-th row drops. In 9(C), the current flows through two transistors, so it can eliminate larger noise. It is possible to remove the same parts as those in Figures 39(A) and (B). The same parts or parts having similar functions will be shown using reference numerals, and detailed descriptions of the same parts or parts having similar functions will be omitted.

[0294] As shown in Figures 37(A) and (B), a diode is connected between the scanning line and the storage capacitor line. Even if the transistors are arranged in this way, the same effects as those in Figures 39(A), (B), and (C) can be obtained. This can be done.

[0295] In the present embodiment, various drawings have been used to describe the present invention. The content or part of the content may also be applied to or combined with the content or part of the content described in another figure. Furthermore, in the figures described above, each part can be represented as another part. By combining the minutes, even more figures can be constructed.

[0296] The contents or part of the contents described in each drawing of this embodiment may be described in the drawings of another embodiment. It can also be applied to or combined with the entire content or part of the content. In the drawings of the embodiments, each part may be combined with a part of another embodiment. By doing so, even more diagrams can be constructed.

[0297] This embodiment is an example of a case where the contents described in the other embodiments are embodied, and is a slightly modified version. An example of a case where the product has been partially changed, an example of an improvement, or an example of a case where the product has been described in detail. Examples of the application and related parts are shown. Therefore, the contents described in the other embodiments can be applied to this embodiment or can be combined with it. It is possible.

[0298] (Embodiment 8) In this embodiment, a structure and a manufacturing method of a transistor will be described.

[0299] FIG. 40(A) is a diagram showing an example of the structure of a transistor. ) illustrates an example of a method for manufacturing a transistor.

[0300] The structure and manufacturing method of the transistor are shown in FIGS. 40(A) to 40(G). Various structures and fabrication methods can be used, without being limited to the above.

[0301] First, an example of the structure of a transistor will be described with reference to FIG. ) are cross-sectional views of transistors having a variety of different structures. In the figure, transistors having different structures are arranged side by side. This is an expression used to explain the structure of a transistor. They do not need to be arranged side by side as in (A), and can be made separately as needed.

[0302] Next, the characteristics of each layer constituting the transistor will be described.

[0303] The substrate 110111 is made of barium borosilicate glass, aluminoborosilicate glass, etc. A glass substrate, a quartz substrate, a ceramic substrate, or a metal substrate including stainless steel may be used. Other materials include polyethylene terephthalate (PET) and polyethylene naphthalate. Plastics such as polyethersulfone (PEN) and polyethersulfone (PES) or aluminum It is also possible to use a substrate made of flexible synthetic resin such as acrylic. By using a substrate having such a structure, a bendable semiconductor device can be manufactured. As long as the substrate is flexible, there are no significant limitations on the area and shape of the substrate. Therefore, the substrate 110111 is, for example, a rectangular substrate with one side longer than 1 meter. By using this, productivity can be improved dramatically. This is a major advantage compared to using a conductive substrate.

[0304] The insulating film 110112 functions as a base film. To prevent alkaline metals or alkaline earth metals from adversely affecting the characteristics of semiconductor elements The insulating film 110112 is made of silicon oxide (SiOx), silicon nitride (SiNx), or oxide Silicon nitride (SiOxNy)(x>y), silicon nitride oxide (SiNxOy)(x>y), etc. The insulating film may have a single layer structure containing oxygen or nitrogen, or a laminated structure of these. For example, when the insulating film 110112 is provided in a two-layer structure, the first insulating film is made of nitride. It is preferable to provide a silicon oxide film and then provide a silicon oxynitride film as the second insulating film. When the insulating film 110112 is provided in a three-layer structure, a silicon oxynitride film is used as the first insulating film. A silicon nitride oxide film is provided as the second insulating film, and a silicon oxynitride film is provided as the third insulating film. It is advisable to provide a membrane.

[0305] The semiconductor layer 110113, the semiconductor layer 110114, and the semiconductor layer 110115 are amorphous. (Amorphous) semiconductor, microcrystalline semiconductor, or semi-amorphous Alternatively, a polycrystalline semiconductor layer may be used. SAS has an intermediate structure between amorphous and crystalline structures (including single crystals and polycrystals), and has free electrons. A semiconductor with an energetically stable third state, which has short-range order and no lattice distortion At least a part of the film contains a crystalline region having a thickness of 0.5 to 20 nm. The crystalline region of silicon can be observed, and the Raman spectrum shows 52 0cm -1 X-ray diffraction shows that the nuclei are shifted to the lower wavenumber side. Diffraction peaks of (111) and (220) are observed. It contains at least 1 atomic % or more of hydrogen or halogen as a compensation for the The SAS is formed by glow discharge decomposition (plasma CVD) of the material gas. The feed gases are SiH4, Si2H6, SiH2Cl2, SiHCl3, SiCl4, It is possible to use SiF4 or the like. Alternatively, GeF4 may be mixed. The material gas is H2, or H2 and one or more selected from He, Ar, Kr and Ne. It may be diluted with several rare gas elements. The dilution ratio is in the range of 2 to 1000 times. The pressure is approximately The range is 0.1 Pa to 133 Pa, and the power frequency is 1 MHz to 120 MHz, preferably 13 The frequency is set to MHz to 60 MHz. The substrate heating temperature can be 300°C or less. The impurities of atmospheric components such as oxygen, nitrogen, and carbon are 1×10 20 cm -1 The following shall be done: In particular, the oxygen concentration is 5×10 19 / cm 3 Less than 1 × 10 19 / c m 3 Here, sputtering, LPCVD, plasma CVD, etc. are used. Silicon (Si)-based materials (e.g., Si(x)Ge(1-x)(0 <x<1) An amorphous semiconductor layer is formed by a method such as laser crystallization, RTA, or Thermal crystallization using an annealing furnace, thermal crystallization using a metal element that promotes crystallization The crystallization is carried out by a crystallization method such as the method for crystallization.

[0306] The insulating film 110116 is made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy)(x>y), silicon nitride oxide (SiNxOy)(x>y) The insulating film may have a single layer structure of an insulating film containing nitrogen or a laminated structure of these insulating films.

[0307] The gate electrode 110117 has a single layer conductive film or a laminated structure of two or three layers of conductive films. The gate electrode 110117 can be made of, for example, tantalum (Ta), Titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), silicon (Si) or a nitride film of the element (typically a tantalum nitride film, tungsten nitride film, titanium nitride film), or alloy film combining the above elements (typical Mo-W alloy, Mo-Ta alloy), or a silicide film of the above elements (typically Ta For example, a tungsten silicide film, a titanium silicide film, etc. can be used. The single film, nitride film, alloy film, silicide film, etc. may be used as a single layer or as a laminate. It's fine.

[0308] The insulating film 110118 is formed by depositing silicon oxide ( SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y), nitride oxide Insulating films containing oxygen or nitrogen, such as silicon carbide (SiNxOy) (x>y), and DLC (Diamond-Like Carbon) A single layer structure of a film containing carbon such as yamond-like carbon, or a laminated structure of these. It can be established.

[0309] The insulating film 110119 is made of siloxane resin, silicon oxide (SiOx), silicon nitride ( SiNx), silicon oxynitride (SiOxNy)(x>y), silicon nitride oxide (SiNxOy) Insulating films containing oxygen or nitrogen, such as (x>y), and DLC (Diamond-Like Carbon Carbon-containing films such as epoxy, polyimide, polyamide, polyvinyl fluoride, etc. Single layer or multilayer structure made of organic materials such as phenol, benzocyclobutene, and acrylic. The siloxane resin is a resin containing Si-O-Si bonds. Siloxane has a skeleton structure made up of bonds between silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (e.g., an alkyl group, an aryl group) is used. A fluoro group can also be used as the substituent. Alternatively, the following can be used as the substituent: An organic group containing at least hydrogen and a fluoro group may be used. 8 is not provided, and an insulating film 110119 is provided directly to cover the gate electrode 110117. It is also possible.

[0310] The conductive film 110123 is made of Al, Ni, C, W, Mo, Ti, Pt, Cu, Ta, Au, A film of a single element such as Mn, a nitride film of the element, an alloy film of a combination of the elements, or For example, a silicide film of the above elements can be used. The following alloys are available: Al alloy containing C and Ti, Al alloy containing Ni, and Al alloy containing C and Ni. For example, an Al alloy containing C and Mn can be used. When providing a conductive film with a layered structure, it is possible to sandwich Al between Mo or Ti. This improves the resistance of Al to heat and chemical reactions.

[0311] Next, referring to the cross-sectional view of a transistor having a plurality of different structures shown in FIG. The characteristics of each structure will be explained below.

[0312] The transistor 110101 is a single drain transistor and can be easily manufactured. This has the advantage of low manufacturing costs and high yields. The semiconductor layer 110113 and the semiconductor layer 110115 have different impurity concentrations. 110113 is a channel region, and semiconductor layer 110115 is a source region and a drain region. In this way, the resistivity of the semiconductor layer can be controlled by controlling the concentration of impurities. Therefore, the electrical connection between the semiconductor layer and the conductive film 110123 is ohmic contact. In addition, as a method for forming semiconductor layers with different impurity concentrations, The method involves doping impurities into the semiconductor layer using the gate electrode 110117 as a mask. You can be there.

[0313] The transistor 110102 has a tapered gate electrode 110117. The taper angle is preferably 45° or more and less than 95°, more preferably 60° or more and less than 95°. However, it is also possible to make the taper angle less than 45°. The conductor layer 110113, the semiconductor layer 110114, and the semiconductor layer 110115 are each The impurity concentration is different. The semiconductor layer 110113 is the channel region, and the semiconductor layer 110114 indicates a lightly doped drain (LDD) region, and semiconductor layer 1 10115 is used as the source and drain regions. Therefore, the resistivity of the semiconductor layer can be controlled by controlling the thickness of the conductive film 1101. The electrical connection state with the LDD region 23 can be made closer to an ohmic connection. Therefore, it is difficult for a high electric field to be applied inside the transistor, and deterioration of the element due to hot carriers is prevented. In addition, as a method for forming semiconductor layers with different impurity concentrations, The method involves doping impurities into the semiconductor layer using the gate electrode 110117 as a mask. In the transistor 110102, the gate electrode 110117 is Since the gate electrode 110117 has a bevel angle, the doped semiconductor layer This allows for a gradient in the impurity concentration, making it possible to easily form an LDD region. This has the advantage of lowering the manufacturing cost and increasing the manufacturing yield.

[0314] The transistor 110103 has a gate electrode 110117 made up of at least two layers. The lower gate electrode has a shape longer than the upper gate electrode. Such a shape of the upper gate electrode and the lower gate electrode is called a hat-type. The hat-shaped design of the pole 110117 allows for the production of a photoresist without the need for an additional photomask. It is possible to form an LDD region. The structure in which the region overlaps with the gate electrode 110117 is called the GOLD structure (Gate O The gate electrode 110117 is called a hat-shaped gate electrode. As a method for this, the following method may be used.

[0315] First, when patterning the gate electrode 110117, the lower The gate electrode of the layer and the gate electrode of the upper layer are etched to form a tapered shape on the side. Next, anisotropic etching is performed to make the slope of the upper gate electrode nearly vertical. As a result, a gate electrode with a hat-shaped cross section is formed. By doping with an impurity element, the semiconductor layer 110 used as a channel region is 113, semiconductor layer 110 used as LDD region, 1114, source electrode and drain electrode A semiconductor layer 110115 is formed to be used as a substrate.

[0316] The LDD region overlapping with the gate electrode 110117 is the Lov region, and the gate electrode 1 The LDD region that does not overlap with 10117 is called the Loff region. Although the effect of suppressing the off-state current is high, it is necessary to relax the electric field near the drain and to reduce the hot carriers. On the other hand, the Lov region reduces the electric field near the drain. Although it is effective in preventing the deterioration of the on-current value, it is not very effective in suppressing the off-current value. It is preferable to fabricate transistors with structures according to the characteristics required for each of the various circuits. For example, when the semiconductor device is used as a display device, the pixel transistor To suppress the value, it is preferable to use a transistor having an Loff region. The transistor in the peripheral circuit reduces the electric field near the drain and prevents the deterioration of the on-current value. To prevent this, it is preferable to use a transistor having an Lov region.

[0317] The transistor 110104 is in contact with the side of the gate electrode 110117 and has a sidewall. By having the sidewall 110121, The area overlapping with the ball 110121 can be the LDD area.

[0318] The transistor 110105 is formed by doping the semiconductor layer using a mask. The LDD (Loff) region is formed. By doing this, the LDD region is reliably formed. This allows the off-state current of the transistor to be reduced.

[0319] The transistor 110106 is formed by doping the semiconductor layer using a mask. The LDD (Lov) region is formed. By doing this, the LDD region is reliably formed. This reduces the electric field near the drain of the transistor and reduces the deterioration of the on-current value. It is possible.

[0320] Next, an example of a method for manufacturing a transistor is shown in FIGS.

[0321] In this embodiment, the surface of the substrate 110111, the surface of the insulating film 110112, the semiconductor The surface of the insulating layer 110113, the surface of the insulating layer 110114, the surface of the insulating layer 110115, The surface of the insulating film 110118 or the surface of the insulating film 110119 is subjected to plasma treatment. By performing oxidation or nitridation using the compound, the semiconductor layer or the insulating film can be oxidized or nitrided. In this way, the semiconductor layer or the insulating film can be oxidized or The surface of the semiconductor layer or insulating film is modified by nitriding or nitriding, and then the surface is A denser insulating film can be formed compared to an insulating film formed by sputtering. Therefore, it is possible to suppress defects such as pinholes and improve the characteristics of semiconductor devices. It becomes Noh.

[0322] The sidewall 110121 is made of silicon oxide (SiOx) or silicon nitride (SiNx). The sidewalls 110121 can be formed on the sides of the gate electrode 110117. As a method for forming the gate electrode 110117, for example, after forming the gate electrode 110117, silicon oxide (Si After forming a film of silicon oxide (SiOx) or silicon nitride (SiNx), anisotropic etching is performed to remove the silicon oxide. A method for etching a silicon nitride (SiOx) film or a silicon nitride (SiNx) film can be used. By doing this, a silicon oxide (SiOx) film is formed only on the side surface of the gate electrode 110117. Since the silicon nitride (SiNx) film can be left behind, the side of the gate electrode 110117 Sidewalls 110121 can be formed.

[0323] FIG. 44 shows a cross-sectional structure of a bottom-gate transistor and a cross-sectional structure of a capacitor. Figure.

[0324] A first insulating film (insulating film 110502) is formed on the entire surface of a substrate 110501. However, this is not limitative, and the first insulating film (insulating film 110502) may not be formed. The first insulating film prevents impurities from the substrate side from affecting the semiconductor layer and causing transistor damage. In other words, the first insulating film has the function of preventing the properties of the underlying Therefore, highly reliable transistors can be fabricated. The first insulating film may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. A single layer such as a SiOxNy film or a laminate of these can be used.

[0325] On the first insulating film, a first conductive layer (conductive layer 110503 and conductive layer 110504) is formed. The conductive layer 110503 is formed as a gate electrode of the transistor 110520. The conductive layer 110504 includes a portion that functions as a first electrode of the capacitor element 110521. The first conductive layer includes a functional portion. The first conductive layer may be made of Ti, Mo, Ta, Cr, W, or Al. Elements such as Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, and Ge, Alternatively, a stack of these elements (including alloys) can be used. can be used.

[0326] A second insulating film (insulating film 110514) is formed so as to cover at least the first conductive layer. The second insulating film functions as a gate insulating film. Examples include silicon oxide film, silicon nitride film, and silicon oxynitride film (SiOxNy). Any single layer or laminate of these may be used.

[0327] It is preferable to use a silicon oxide film as the second insulating film in contact with the semiconductor layer. This is because the trap levels at the interface between the semiconductor layer and the second insulating film are reduced. Because.

[0328] When the second insulating film is in contact with Mo, the second insulating film in the portion in contact with Mo is an oxide silicon. It is preferable to use a silicon film because silicon oxide does not oxidize Mo. is.

[0329] A portion of the second insulating film overlapping the first conductive layer is photolithographically formed. The semiconductor layer is formed by a method such as a graphic method, an inkjet method, or a printing method. A part of the semiconductor layer is formed on the second insulating film so as to overlap the first conductive layer. The semiconductor layer extends to the channel formation region (channel formation region 11051 0), LDD region (LDD region 110508, LDD region 110509), impurity region ( impurity region 110505, impurity region 110506, impurity region 110507) The channel forming region 110510 is the channel forming region of the transistor 110520. The LDD region 110508 and the LDD region 110509 function as transistors. It functions as the LDD region of the LDD area 110520. The D region 110509 is not necessarily required. This includes the portion that functions as one of the source and drain electrodes of the FET 110520. The material region 100506 is a semiconductor layer that includes the source and drain electrodes of the transistor 110520. The impurity region 110507 includes a portion that functions as a second It includes a portion that functions as an electrode.

[0330] Impurity region 110505, LDD region 110508, channel formation region 110510, The LDD region 110509, the impurity region 110506, the second insulating film 110514, and the impurity A third insulating film (insulating film 110511) is formed on the entire surface of the pure region 110507. A contact hole is selectively formed in a part of the third insulating film. The third insulating film is made of an inorganic material (silicon oxide). silicon nitride, silicon oxynitride, etc.) or organic compound materials with low dielectric constant (sensor Photosensitive or non-photosensitive organic resin materials can be used. Alternatively, siloxane It is also possible to use a material containing silicon (Si) and oxygen (O). The skeleton structure is made up of bonds with the organic compound containing at least hydrogen as a substituent. A group (e.g., an alkyl group, an aryl group) is used as a substituent. Alternatively, a fluoro group is used as a substituent. Alternatively, a compound having an organic group containing at least hydrogen and a fluoro group as a substituent may be used. and may also be used.

[0331] A second conductive layer (conductive layer 110512 and conductive layer 110513) is formed on the third insulating film. The conductive layer 110512 is formed through a contact hole formed in the third insulating film. The other of the source electrode and the drain electrode of the transistor 110520 is connected to the other of the source electrode and the drain electrode of the transistor 110520 via the Therefore, the conductive layer 110512 serves as the source electrode and The conductive layer 110513 includes a portion that functions as the other of the drain electrodes. When electrically connected to the capacitor element 110521, the conductive layer 110513 Alternatively, the conductive layer 110513 may include a portion that functions as the first electrode. When electrically connected to the capacitor element 11052, the conductive layer 110513 Alternatively, the conductive layer 110513 may include a portion that functions as the second electrode of the conductive layer 110513. When the capacitor element 110521 is not connected to the conductive layer 110504 and the conductive layer 110507, A capacitor element is formed separately from the conductive layer 1105. This capacitor element is formed by the conductive layer 1105. 07 and insulating film 110511 are the first electrode, the second electrode, and the insulating film of the capacitor element, respectively. The second conductive layer is made of Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, etc. Alternatively, the product of these elements (including alloys) can be used. A layer can be used.

[0332] After the second conductive layer is formed, various insulating films or various conductive layers may be formed. A film may be formed.

[0333] Next, the semiconductor layer of the transistor is coated with an amorphous silicon (a-Si:H) film or a When using a microcrystalline silicon film, the structure of a transistor and a capacitor element We will explain about this.

[0334] FIG. 41 shows a cross-sectional structure of a top-gate transistor and a cross-sectional structure of a capacitor. Figure.

[0335] A first insulating film (insulating film 110202) is formed on the entire surface of a substrate 110201. The first insulating film prevents impurities from the substrate from affecting the semiconductor layer and deteriorating the properties of the transistor. In other words, the first insulating film functions as a base film. Therefore, a highly reliable transistor can be manufactured. The insulating film 1 may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (Si OxNy) or a laminate thereof can be used.

[0336] It is not always necessary to form the first insulating film. In this case, the number of steps can be reduced and This allows for a reduction in manufacturing costs, and also simplifies the structure, improving yield. This can be achieved.

[0337] On the first insulating film, a first conductive layer (conductive layer 110203, conductive layer 110204 and conductive layer 110205) is formed. The conductive layer 110203 is formed on the transistor 11022. The conductive layer 11 includes a portion that functions as one of the source electrode and the drain electrode of the conductive layer 11. 0204 is the other electrode of the source electrode and the drain electrode of the transistor 110220. The conductive layer 110205 includes a portion that functions as a first electrode of the capacitor 110221. The first conductive layer includes a portion that functions as a conductive layer. Elements such as Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, and Ge or alloys thereof. Alternatively, Lamination may be used.

[0338] A first semiconductor layer (semiconductor layer 1) is formed on the conductive layer 110203 and the conductive layer 110204. The semiconductor layer 110206 is formed of a semiconductor layer 110207. The semiconductor layer 110 includes a portion that functions as one of the source electrode and the drain electrode. 207 includes a portion that functions as the other of the source and drain electrodes. The first semiconductor layer may be made of silicon containing phosphorus or the like.

[0339] Between the conductive layer 110203 and the conductive layer 110204 and on the first insulating film, The second semiconductor layer (semiconductor layer 110208) is formed on the semiconductor substrate 11020. A part of the conductive layer 8 extends onto the conductive layer 110203 and the conductive layer 110204. The conductor layer 110208 is a layer that functions as a channel region of the transistor 110220. The second semiconductor layer may be made of a non-crystalline silicon such as amorphous silicon (a-Si:H). A semiconductor layer having crystallinity or a semiconductor layer such as a microcrystalline semiconductor (μ-Si:H) is used. You can be there.

[0340] A second insulating layer is formed to cover at least the semiconductor layer 110208 and the conductive layer 110205. The second insulating film is formed on the insulating film 110209. The second insulating film functions as a gate insulating film. A single layer of silicon nitride or silicon oxynitride (SiOxNy) or Lamination may be used.

[0341] A silicon oxide film may be used as the second insulating film in contact with the second semiconductor layer. This is desirable because the traps at the interface between the second semiconductor layer and the second insulating film This is because there are fewer levels.

[0342] When the second insulating film is in contact with Mo, the second insulating film in the portion in contact with Mo is It is desirable to use a silicon oxide film because the silicon oxide film does not oxidize Mo. Because it is.

[0343] A second conductive layer (conductive layer 110211 and conductive layer 110212) is formed on the second insulating film. The conductive layer 110211 is formed as a gate electrode of the transistor 110220. The conductive layer 110212 includes a second electrode of the capacitor element 110221, The second conductive layer functions as a wiring. W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, etc. Alternatively, these elements (including alloys) can be used. ) can be used as a laminate.

[0344] After the second conductive layer is formed, various insulating films or various conductive layers may be formed. A film may be formed.

[0345] Figure 42 shows the cross-sectional structure of an inverted staggered (bottom gate) transistor and the capacitance element. 42 is a diagram showing a cross-sectional structure. In particular, the transistor shown in FIG. 42 is called a channel etch type. It is a structure that can be used.

[0346] A first insulating film (insulating film 110302) is formed on the entire surface of a substrate 110301. The first insulating film prevents impurities from the substrate from affecting the semiconductor layer and deteriorating the properties of the transistor. In other words, the first insulating film functions as a base film. Therefore, a highly reliable transistor can be manufactured. The insulating film may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO xNy) or a laminate thereof can be used.

[0347] It is not always necessary to form the first insulating film. In this case, the number of steps can be reduced and This allows for a reduction in manufacturing costs, and also simplifies the structure, improving yield. This can be achieved.

[0348] On the first insulating film, a first conductive layer (conductive layer 110303 and conductive layer 110304) is formed. The conductive layer 110303 is formed as a gate electrode of the transistor 110320. The conductive layer 110304 includes a portion that functions as a first electrode of the capacitor element 110321. The first conductive layer includes a functional portion. The first conductive layer may be made of Ti, Mo, Ta, Cr, W, or Al. Elements such as Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, and Ge, Alternatively, a stack of these elements (including alloys) can be used. can be used.

[0349] A second insulating film (insulating film 110305) is formed so as to cover at least the first conductive layer. The second insulating film functions as a gate insulating film. Examples include silicon oxide film, silicon nitride film, and silicon oxynitride film (SiOxNy). Any single layer or laminate of these may be used.

[0350] It is preferable to use a silicon oxide film as the second insulating film in contact with the semiconductor layer. This is because the trap levels at the interface where the semiconductor layer and the second insulating film contact each other are reduced. Because.

[0351] When the second insulating film is in contact with Mo, the second insulating film in the area in contact with Mo is made of silicon oxide. It is preferable to use a silicon oxide film because the silicon oxide film does not oxidize Mo. is.

[0352] A photoresist is formed on a part of the second insulating film that is formed to overlap with the first conductive layer. The first semiconductor layer (semiconductor) is formed by a lithography method, an inkjet method, a printing method, or the like. A part of the semiconductor layer 110306 is connected to the second insulating layer. The insulating film extends to a portion that is not formed overlapping the first conductive layer. The semiconductor layer 110306 includes a portion that functions as a channel region of the transistor 110320. The semiconductor layer 110306 is made of amorphous silicon (a-Si:H) or the like. A semiconductor layer having amorphous properties, or a semiconductor layer such as a microcrystalline semiconductor (μ-Si:H) can be used.

[0353] A second semiconductor layer (semiconductor layer 110307 and semiconductor layer 1) is formed on a portion of the first semiconductor layer. The semiconductor layer 110307 is formed with a source electrode and a drain electrode. The semiconductor layer 110308 includes a portion that functions as one of the electrodes. The second conductor layer includes a portion that functions as the other electrode of the drain electrode. Silicon containing silicon or the like can be used.

[0354] A second conductive layer (conductive layer 110309, conductive The conductive layer 110309 is formed on the substrate 110310 and the conductive layer 110311. The part that functions as one of the source electrode and drain electrode of the transistor 110320 The conductive layer 110310 forms a source electrode and a drain electrode of the transistor 110320. The conductive layer 110311 includes a portion that functions as the other electrode of the capacitor element 110321. The second conductive layer includes a portion that functions as an electrode. The second conductive layer may be made of Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge or alloys thereof can be used. Alternatively, these elements (including alloys) can be used. ) can be used as a laminate.

[0355] After the second conductive layer is formed, various insulating films or A conductive film may be formed on the surface.

[0356] Here, an example of a process for forming a channel-etched transistor will be described. The first semiconductor layer and the second semiconductor layer can be formed using a mask. The first semiconductor layer and the second semiconductor layer are deposited successively. The two semiconductor layers are formed using the same mask.

[0357] Another example of a process that features a channel-etched transistor will be described. The channel region of the transistor can be formed without using a mask. After the second conductive layer is formed, the second conductive layer is used as a mask to form a second semiconductor Alternatively, a portion of the second semiconductor layer is removed using the same mask as the second conductive layer. Then, the first semiconductor layer formed under the removed second semiconductor layer is removed. The body layer becomes the channel region of the transistor.

[0358] Figure 43 shows the cross-sectional structure of an inverted staggered (bottom gate) transistor and the capacitance element. 43 is a diagram showing a cross-sectional structure. In particular, the transistor shown in FIG. 43 is a channel protection type (channel This structure is called a "rustop type."

[0359] A first insulating film (insulating film 110402) is formed on the entire surface of a substrate 110401. The first insulating film prevents impurities from the substrate from affecting the semiconductor layer and deteriorating the properties of the transistor. In other words, the first insulating film functions as a base film. Therefore, a highly reliable transistor can be manufactured. The insulating film 1 may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (Si OxNy) or a laminate thereof can be used.

[0360] It is not always necessary to form the first insulating film. In this case, the number of steps can be reduced and This allows for a reduction in manufacturing costs, and also simplifies the structure, improving yield. This can be achieved.

[0361] On the first insulating film, a first conductive layer (conductive layer 110403 and conductive layer 110404) is formed. The conductive layer 110403 is formed as a gate electrode of the transistor 110420. The conductive layer 110404 includes a portion that functions as a first electrode of the capacitor 110421. The first conductive layer includes a functional portion. The first conductive layer may be made of Ti, Mo, Ta, Cr, W, or Al. Elements such as Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, and Ge, Alternatively, a stack of these elements (including alloys) can be used. can be used.

[0362] A second insulating film (insulating film 110405) is formed so as to cover at least the first conductive layer. The second insulating film functions as a gate insulating film. Examples include silicon oxide film, silicon nitride film, and silicon oxynitride film (SiOxNy). Any single layer or laminate of these may be used.

[0363] It is preferable to use a silicon oxide film as the second insulating film in contact with the semiconductor layer. This is because the trap levels at the interface where the semiconductor layer and the second insulating film contact each other are reduced. Because.

[0364] When the second insulating film is in contact with Mo, the second insulating film in the area in contact with Mo is made of silicon oxide. It is preferable to use a silicon oxide film because the silicon oxide film does not oxidize Mo. be.

[0365] A photoresist is formed on a part of the second insulating film that is formed to overlap with the first conductive layer. The first semiconductor layer (semiconductor) is formed by a lithography method, an inkjet method, a printing method, or the like. A portion of the semiconductor layer 110406 ​​is connected to the second insulating layer. The insulating film extends to a portion that is not formed overlapping the first conductive layer. The semiconductor layer 110406 ​​includes a portion that functions as a channel region of the transistor 110420. The semiconductor layer 110406 ​​is made of amorphous silicon (C-Si:H) or the like. A semiconductor layer having amorphous properties, or a semiconductor layer such as a microcrystalline semiconductor (μ-Si:H) can be used.

[0366] A third insulating film (insulating film 110412) is formed on a portion of the first semiconductor layer. The insulating film 110412 is formed by etching the channel region of the transistor 110420. In other words, the insulating film 110412 has a function of preventing the channel from being removed. The third insulating film functions as a silicon oxide film (channel stop film). A single layer of silicon nitride film, silicon oxynitride film (SiOxNy), or A laminate of these can be used.

[0367] A second semiconductor layer (semiconductor layer 1) is formed on a part of the first semiconductor layer and a part of the third insulating film. The semiconductor layer 110407 is formed on the insulating film 110408. The semiconductor layer 110 includes a portion that functions as one of the source electrode and the drain electrode. 408 includes a portion that functions as the other of the source and drain electrodes. The second conductor layer may be made of silicon containing phosphorus or the like.

[0368] On the second semiconductor layer, a second conductive layer (conductive layer 110409, conductive layer 110410 and The conductive layer 110409 is formed on the transistor 1104. The conductive layer 1104 includes a portion that functions as one of the source electrode and the drain electrode of 20. 10 serves as the other of the source and drain electrodes of the transistor 110420. The conductive layer 110411 functions as a second electrode of the capacitor 110421. The second conductive layer includes a portion where Ti, Mo, Ta, Cr, W, Al, Nd , Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, etc., or any of these Alloys can be used. Alternatively, stacks of these elements (including alloys) can be used. can be done.

[0369] After the second conductive layer is formed, various insulating films or various conductive layers may be formed. A film may be formed.

[0370] So far, the structure of a transistor and a method for manufacturing a transistor have been described. , wiring, electrodes, conductive layers, conductive films, terminals, vias, plugs, etc. are made of aluminum (Al), Ta (Ta), Titanium (Ti), Molybdenum (Mo), Tungsten (W), Neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag) , Copper (Cu), Magnesium (Mg), Scandium (Sc), Cobalt (Co), Zinc (Zn), niobium (Nb), silicon (Si), phosphorus (P), boron (B), arsenic (As ), gallium (Ga), indium (In), tin (Sn), and oxygen (O) or one or more elements selected from the group Compounds and alloy materials containing indium (e.g., indium tin oxide (ITO), indium Zinc oxide (IZO), indium tin oxide with silicon oxide (ITSO), zinc oxide (Z nO), tin oxide (SnO), cadmium tin oxide (CTO), aluminum neodymium (Al-Nd ), magnesium silver (Mg-Ag), molybdenum niobium (Mo-Nb), etc. Alternatively, wiring, electrodes, conductive layers, conductive films, terminals, etc., may be made of these compounds. It is preferable that the material is a combination of the above materials. Compounds of silicon (silicides) (e.g., aluminum silicides) with one or more elements selected from the above silicon, molybdenum silicon, nickel silicide, etc.), one or more selected from the group is a compound of multiple elements and nitrogen (e.g., titanium nitride, tantalum nitride, molybdenum nitride, etc.) ) is preferably formed.

[0371] Silicon (Si) contains n-type impurities (such as phosphorus) or p-type impurities (such as boron). The impurities in silicon improve its electrical conductivity, making it as good as a normal conductor. Therefore, it becomes easier to use it as wiring, electrodes, etc. .

[0372] Silicon can be monocrystalline, polycrystalline (polysilicon), or microcrystalline (microcrystalline silicon). Silicon having various crystallinity can be used, such as amorphous ( Silicon that does not have crystallinity, such as amorphous silicon, can be used. By using crystalline silicon or polycrystalline silicon, wiring, electrodes, conductive layers, conductive films, The resistance of the silicon can be reduced. This allows wiring and the like to be formed through simple steps.

[0373] Aluminum or silver has high conductivity, which can reduce signal delay. In addition, it is easy to etch, so it is easy to pattern and can be finely processed.

[0374] Copper has high conductivity, so it can reduce signal delay. To improve the performance, it is desirable to use a laminated structure.

[0375] Molybdenum or titanium is in contact with oxide semiconductors (ITO, IZO, etc.) or silicon. It has the advantages of not causing defects even when touched, being easy to etch, and having high heat resistance. ,desirable.

[0376] Tungsten is desirable because it has advantages such as high heat resistance.

[0377] Neodymium is desirable because it has advantages such as high heat resistance. When alloyed with aluminum, the heat resistance improves and the aluminum becomes less likely to develop hillocks. .

[0378] Silicon can be formed at the same time as the semiconductor layer of the transistor. It is desirable because it has advantages.

[0379] ITO, IZO, ITSO, zinc oxide (ZnO), silicon (Si), tin oxide (SnO ) and cadmium tin oxide (CTO) are translucent and are used in areas where light is to pass through. For example, it can be used as a pixel electrode or a common electrode.

[0380] IZO is desirable because it is easy to etch and process. It is also unlikely that residue will remain when chipping. When IZO is used as an electrode, problems occur in the liquid crystal element and the light emitting element (short circuit, alignment disorder, etc.). This can reduce the risk of

[0381] The wiring, electrodes, conductive layers, conductive films, terminals, vias, plugs, etc. may have a single layer structure. A multi-layer structure is also possible. By forming a single layer structure, wiring, electrodes, conductive layers, conductive films and terminals can be easily formed. The manufacturing process can be simplified, the number of steps can be reduced, and costs can be further reduced. Alternatively, by using a multi-layer structure, it is possible to take advantage of the advantages of each material while minimizing their disadvantages. This reduces the number of contacts and allows for the formation of high-performance wiring and electrodes. By including a resistance material (such as aluminum) in the multilayer structure, the resistance of the wiring can be reduced. As another example, a laminated structure can be created in which a low heat-resistant material is sandwiched between high heat-resistant materials. This allows us to take advantage of the benefits of low heat resistance materials while improving the heat resistance of wiring and electrodes. For example, a layer containing aluminum can be replaced with a layer containing molybdenum, titanium, or nickel. It is desirable to have a laminated structure in which the metal is sandwiched between layers containing chromium or the like.

[0382] When wiring, electrodes, etc. come into direct contact with each other, they may have a negative effect on each other. For example, When one wiring or electrode penetrates into the material of the other wiring or electrode, it changes its properties. As another example, a high resistance portion may be formed or When manufacturing, problems may occur and the product may not be manufactured properly. ,By using a laminated structure, reactive materials are sandwiched or covered with less reactive materials. For example, when connecting ITO and aluminum, It is preferable to sandwich a titanium, molybdenum, or neodymium alloy. When connecting silicon and aluminum, titanium, molybdenum, etc. It is desirable to sandwich it between chromium or neodymium alloys.

[0383] Wiring refers to an arrangement of conductors. It may be linear or may not be linear. The electrodes may be arranged in a short manner. Therefore, the electrodes are included in the wiring.

[0384] Carbon nanotubes can be used as wiring, electrodes, conductive layers, conductive films, terminals, vias, plugs, etc. Furthermore, since carbon nanotubes have a light-transmitting property, they can transmit light. For example, it can be used as a pixel electrode or a common electrode. Cut.

[0385] In this embodiment, various drawings have been used to explain the present invention. The contents (or a part of them) of another figure may be applied or combined with the contents (or a part of them) of another figure. Furthermore, in the diagrams described above, For each part, more figures can be constructed by combining other parts.

[0386] Similarly, the contents (or even a part thereof) described in each drawing of this embodiment may be applied to other embodiments. The contents described in the diagram (even a part of them) can be freely applied, combined, or replaced. Furthermore, each part of the figure of this embodiment can be used in another embodiment. By combining parts, even more diagrams can be constructed.

[0387] This embodiment is a case where the contents (or a part thereof) described in other embodiments are embodied. An example, a slightly modified example, an example with some changes, an example with improvements, details Examples of cases where it has been mentioned, examples of cases where it has been applied, and examples of related parts are given below. Therefore, the contents described in the other embodiments may be applied to and combined with this embodiment. can be freely combined or substituted.

[0388] (Embodiment 9) In this embodiment, a configuration of a display device will be described.

[0389] The configuration of the display device will be described with reference to Fig. 47(A). FIG.

[0390] Pixel section 170101, scanning line side input terminal 170103 and signal line side input terminal 1701 04 is formed on the substrate 170100. Also, the scanning lines are connected to the scanning line side input terminals 170 103 is formed on the substrate 170100, extending in the row direction, and the signal line is connected to the signal line side input terminal The electrodes 170104 are formed on the substrate 170100, extending in the column direction. The pixel 170102 is provided in the pixel section 170101, and the matrix is ​​provided in the area where the scanning line and the signal line intersect. The plates are arranged in a square pattern.

[0391] So far, we have explained how to input signals using an external drive circuit. However, the present invention is not limited to this, and an IC chip can be mounted on the display device.

[0392] For example, as shown in FIG. 48(A), a COG (Chip On Glass) method In this way, the IC chip 170201 can be mounted on the substrate 170100. Since the IC chip 170201 can be inspected before being mounted on the substrate 170100, the display device This can improve the yield of the device and increase the reliability. Common parts are designated by common reference numerals and their explanations are omitted.

[0393] As another example, as shown in FIG. 48(B), The IC chip 170201 is mounted on the FPC (Flexible Printed Circuit) by the bonding method. It can be implemented in a 170200 (Printed Circuit) system. The IC chip 170201 can be inspected before being mounted on the FPC 170200, allowing for easy inspection of the display. This can improve the yield of the device and increase the reliability. Common parts are designated by common reference numerals and their explanations are omitted.

[0394] Not only is the IC chip mounted on the board 170100, but the drive circuit is also mounted on the board 170100. It can be formed into.

[0395] For example, as shown in FIG. 47(B), the scanning line driving circuit 170105 is In this case, the number of parts can be reduced, thereby reducing costs. In addition, the number of connection points with circuit components can be reduced, thereby improving reliability. In addition, the driving frequency of the scanning line driving circuit 170105 is low. As the semiconductor layer, amorphous silicon or microcrystalline silicon is used, and the scanning line driver circuit 17 0105 can be easily formed. The chip may be mounted on the board 170100 using the COG method. The IC chip for this is mounted on the FPC by the TAB method and placed on the board 170100. In addition, an IC chip for controlling the scanning line driving circuit 170105 may be mounted on the substrate 170105. Alternatively, the scanning line driver circuit 170105 may be controlled by the COG method. The IC chip for this is mounted on the FPC by the TAB method and placed on the board 170100. In addition, the same reference numerals are used for the parts common to the configuration of FIG. 47(A), and the explanation thereof will be omitted. is omitted.

[0396] As another example, as shown in FIG. 47(C), a scanning line driving circuit 170105 and a signal line The drive circuitry 170106 can be formed on the substrate 170100. Costs can be reduced by reducing the number of connections to circuit components. This reduces the power consumption and improves reliability. An IC chip for this purpose may be mounted on the substrate 170100 using the COG method. The IC chip for controlling the scanning line driver circuit 170105 is mounted using the TAB method. The PC may be disposed on the substrate 170100. In addition, the signal line driver circuit 170106 may be controlled by the An IC chip for this purpose may be mounted on the substrate 170100 using the COG method. The IC chip for controlling the signal line driver circuit 170106 is mounted using the TAB method. The PC may be placed on the substrate 170100. Note that the same points as those in the configuration of FIG. Common reference numerals are used for the first and second components, and their explanations will be omitted.

[0397] In this embodiment, various drawings have been used to explain the present invention. The contents (or a part of them) of another figure may be applied or combined with the contents (or a part of them) of another figure. Furthermore, in the diagrams described above, For each part, more figures can be constructed by combining other parts.

[0398] Similarly, the contents (or even a part thereof) described in each drawing of this embodiment may be applied to other embodiments. The contents described in the diagram (even a part of them) can be freely applied, combined, or replaced. Furthermore, each part of the figure of this embodiment can be used in another embodiment. By combining parts, even more diagrams can be constructed.

[0399] This embodiment is a case where the contents (or a part thereof) described in other embodiments are embodied. An example, a slightly modified example, an example with some changes, an example with improvements, details Examples of cases where it has been mentioned, examples of cases where it has been applied, and examples of related parts are given below. Therefore, the contents described in the other embodiments may be applied to and combined with this embodiment. can be freely combined or substituted.

[0400] (Embodiment 10) In this embodiment, a method for driving a display device will be described. The driving method will be explained.

[0401] The liquid crystal panel that can be used in the liquid crystal display device described in this embodiment is a liquid crystal The material is sandwiched between two substrates. Each of the two substrates contains a liquid crystal material. The liquid crystal material is provided with electrodes for controlling the electric field applied to the It is a material whose optical and electrical properties change depending on the field. The liquid crystal material is controlled by controlling the voltage applied to the liquid crystal material using the electrodes on the substrate. The device is capable of obtaining desired optical and electrical properties. By arranging them side by side in a plane, each becomes a pixel, and the voltage applied to the pixel can be controlled individually. This allows high-definition images to be displayed on the LCD panel.

[0402] Here, the response time of the liquid crystal material to a change in the electric field depends on the distance between the two substrates (cell gap ) and the type of liquid crystal material, but it is generally several milliseconds to several tens of milliseconds. Furthermore, when the change in the electric field is small, the response time of the liquid crystal material becomes even longer. When displaying moving images on an LCD panel, afterimages, trailing images, and contrast This can cause problems with image display, such as a decrease in brightness, especially when changing from one gray level to another. When the change in the electric field is small, the degree of the above-mentioned damage becomes significant.

[0403] On the other hand, a problem specific to liquid crystal panels using active matrices is that they are driven by a constant charge. The constant charge driving in this embodiment will be explained below. do.

[0404] The pixel circuit in an active matrix consists of a switch that controls writing and a The pixel circuit in the active matrix is ​​driven by a switch. After turning on the switch and writing a predetermined voltage to the pixel circuit, the switch is immediately turned off. In the hold state, the charge in the pixel circuit is held (hold state). There is no charge exchange between the inside and outside of the element circuit (constant charge). The period when the device is in the OFF state is several hundred times longer (number of scanning lines) than the period when the device is in the ON state. Therefore, the pixel circuit switch can be considered to be almost in the off state. As described above, the constant charge driving in this embodiment means that when the liquid crystal panel is driven, the pixel circuit It is assumed that this is a driving method in which the hold state is maintained for most of the period.

[0405] Next, the electrical properties of the liquid crystal material will be explained. When the dielectric constant changes, the optical properties change and the dielectric constant also changes. When each pixel of the panel is considered as a capacitance element (liquid crystal element) sandwiched between two electrodes, The element is a capacitance element whose capacitance changes depending on the applied voltage. This is called dynamic capacitance.

[0406] In this way, the capacitance element whose capacitance changes depending on the applied voltage is called the constant charge capacitor. When driving the device by driving, the following problems occur: Holes that do not transfer charge In the switched state, if the capacitance of the liquid crystal element changes, the applied voltage also changes. This is a problem in the relational equation (amount of charge) = (capacitance) x (applied voltage). This can be understood from the fact that the amount of charge is constant.

[0407] For the above reasons, in liquid crystal panels using an active matrix, constant charge drive is used. As a result, the voltage during the hold state changes from the voltage during the write state. As a result, the change in the transmittance of the liquid crystal element is the same as the change in the driving method that does not take the hold state. This is shown in Figure 45. Figure 45(A) shows the horizontal The axis represents time and the vertical axis represents the absolute value of the voltage, showing an example of controlling the voltage written to the pixel circuit. FIG. 45(B) shows the voltage written to the pixel circuit when the horizontal axis represents time and the vertical axis represents voltage. FIG. 45(C) shows an example of pressure control. The horizontal axis represents time and the vertical axis represents the transmittance of the liquid crystal element. When the voltage shown in FIG. 45(A) or FIG. 45(B) is written to the pixel circuit, 45(A) to 45(C) show the time change in the transmittance of the liquid crystal element when In this case, period F represents the voltage rewrite cycle, and the times at which the voltage is rewritten are t1, t2, and t3. , t4.

[0408] Here, the write voltage corresponding to the image data input to the liquid crystal display device is The rewrite at time t1, t2, t3, and t4 is |V2| (See FIG. 45(A)).

[0409] The write voltage corresponding to the image data input to the liquid crystal display device periodically changes its polarity. This method can be used to reverse the voltage applied to the liquid crystal. This prevents burn-in caused by deterioration of the liquid crystal element. The polarity switching period (reversal period) is the voltage rewriting period. In this case, the inversion period is short, so the occurrence of flicker due to inversion drive can be prevented. Furthermore, the inversion period is an integer multiple of the voltage rewriting period. In this case, the inversion period is long, and the frequency of writing voltage by changing polarity is reduced. Therefore, power consumption can be reduced.

[0410] When the voltage shown in FIG. 45(A) or FIG. 45(B) is applied to the liquid crystal element, The time change in the transmittance of the liquid crystal element when a voltage |V The transmittance of the liquid crystal element after a sufficient time has passed after applying voltage 1 is defined as TR1. A voltage |V2| is applied to the liquid crystal element, and the transmittance of the liquid crystal element after a sufficient time has passed is defined as TR2. At time t1, the voltage applied to the liquid crystal element changes from |V1| to |V2| As shown by the broken line 30401, the transmittance of the liquid crystal element does not immediately become TR2, but gradually decreases. For example, if the voltage rewrite cycle is equal to the frame cycle of a 60Hz image signal, When the period is the same as that of the time (16.7 ms), it takes several frames for the transmittance to change to TR2. It will take some time.

[0411] However, the smooth change in transmittance over time, as shown by the dashed line 30401, is caused by the liquid crystal element. This is exactly what happens when a voltage |V2| is applied. In a liquid crystal panel using a passive matrix, the hold state is maintained by constant charge driving. The voltage at the time of writing changes from the voltage at the time of writing, so the transmittance of the liquid crystal element does not change over time as shown by the dashed line 30401, but instead changes over time as shown by the solid line 30402. This is because the voltage changes gradually over time due to the constant charge drive. This is because the target voltage cannot be reached in a single write. As a result, the response time of the transmittance of the liquid crystal element is longer than the original response time (dashed line 30401). This makes the image appear longer, resulting in image afterimages, trailing images, and reduced contrast. This will cause significant problems in image display.

[0412] By using overdrive, the original response time of the liquid crystal element and the dynamic response time can be apparent due to dynamic capacitance and lack of writing due to constant charge driving This can simultaneously solve the problem of the response time becoming longer. , and Fig. 46. In Fig. 46(A), the horizontal axis is time and the vertical axis is the absolute value of the voltage. This shows an example of controlling the voltage to be written. In FIG. 46(B), the horizontal axis represents time and the vertical axis represents voltage. FIG. 46(C) shows an example of controlling the voltage written to the pixel circuit when The horizontal axis represents time and the vertical axis represents the transmittance of the liquid crystal element. This shows the time change in the transmittance of the liquid crystal element when the voltage shown is written to the pixel circuit. In FIG. 46(A) to FIG. 46(C), period F represents a voltage rewriting cycle, and voltage The times at which the value is rewritten are t1, t2, t3, and t4.

[0413] Here, the write voltage corresponding to the image data input to the liquid crystal display device is In the rewrite at time t1, |V3| is used, and in the rewrite at time t2, t3, The rewrite at t4 is assumed to be |V2| (see FIG. 46(A)).

[0414] The write voltage corresponding to the image data input to the liquid crystal display device periodically changes its polarity. This method can be used to apply a DC voltage to the liquid crystal. This prevents burn-in caused by deterioration of the liquid crystal element. The polarity switching period (reversal period) is the voltage rewriting period. In this case, the inversion period is short, so the occurrence of flicker due to inversion drive can be prevented. Furthermore, the inversion period is an integer multiple of the voltage rewriting period. In this case, the inversion period is long, and the frequency of writing voltage by changing polarity is reduced. Therefore, power consumption can be reduced.

[0415] When the voltage shown in FIG. 46(A) or FIG. 46(B) is applied to the liquid crystal element, The time change in the transmittance of the liquid crystal element when a voltage |V The transmittance of the liquid crystal element after a sufficient time has passed after applying voltage 1 is defined as TR1. A voltage |V2| is applied to the liquid crystal element, and the transmittance of the liquid crystal element after a sufficient time has passed is defined as TR2. Similarly, when a voltage |V3| is applied to the liquid crystal element, the The transmittance is TR3. At time t1, the voltage applied to the liquid crystal element changes from |V1| to | When the voltage changes to V3|, the transmittance of the liquid crystal element decreases for several frames as shown by the dashed line 30501. However, the voltage |V3| is applied at time t2 After time t2, the voltage |V2| is applied. does not become as shown by the dashed line 30501, but becomes as shown by the solid line 30502. At time t2, the value of the voltage |V3| is set so that the transmittance is approximately TR2. Here, the voltage |V3| is also called the overdrive voltage. Let's say.

[0416] By changing the overdrive voltage |V3|, the response time of the liquid crystal element can be adjusted to some extent. This is because the response time of the liquid crystal element changes depending on the strength of the electric field. Specifically, the stronger the electric field, the shorter the response time of the liquid crystal element. The lower the value, the longer the response time of the liquid crystal element.

[0417] The overdrive voltage |V3| is the amount of change in voltage, i.e., the desired transmittance The voltages |V1| and |V2| applied to TR1 and TR2 are changed according to This is preferable because even if the response time of the liquid crystal element changes depending on the amount of change in voltage, , and by changing the overdrive voltage |V3| accordingly, you can always achieve the optimal response. Because it gives you time.

[0418] The overdrive voltage |V3| is the voltage for TN, VA, IPS, OCB, and other liquid crystal elements. It is preferable to change the response time depending on the mode because the response speed of the liquid crystal element varies depending on the mode of the liquid crystal. Even if the overdrive voltage |V3| varies depending on the This is because by changing the response time, the optimum response time can be obtained at all times.

[0419] The voltage rewrite period F may be the same as the frame period of the input signal. Since the peripheral driving circuit of the display device can be simplified, a liquid crystal display device can be obtained at low manufacturing costs. can.

[0420] The voltage rewrite period F may be shorter than the frame period of the input signal. The switching period F may be 1 / 2 or 1 / 3 of the frame period of the input signal. This method may include black insertion driving, backlight blinking, backlight scanning, Video quality caused by hold driving of LCD displays, such as intermediate image insertion driving using motion compensation It is effective to use it together with the countermeasures against the decrease in the hold The countermeasures for the degradation of video quality caused by driving are as follows: By using the overdrive driving method described in this embodiment, it is relatively easy to The response time of the liquid crystal element varies depending on the cell gap, the liquid crystal material, and Although it is possible to shorten the time by changing the mode of the liquid crystal element, it is technically difficult. Therefore, the response time of the liquid crystal element is shortened by using a driving method such as overdrive. It is very important to use a method that

[0421] The voltage rewrite period F may be longer than the frame period of the input signal. The rewrite period F may be twice or three times the frame period of the input signal, or may be more than that. This method is a means for determining whether or not the voltage has not been rewritten for a long period of time (recovery It is effective to use it in combination with a circuit that does not rewrite the voltage for a long period of time. If the voltage is not changed, the circuit operation is stopped during that period by not performing the voltage rewrite operation. Since the power supply voltage can be stopped, a liquid crystal display device with low power consumption can be obtained.

[0422] Next, the overdrive voltage |V3| is set to the desired transmittances TR1 and TR2. This explains the specific method for changing the voltages |V1| and |V2| do.

[0423] The overdrive circuit generates a voltage |V1| that gives the desired transmittances TR1 and TR2. and |V2|, the circuit to properly control the overdrive voltage |V3| Since the signal input to the overdrive circuit is a voltage | and a signal related to the voltage |V2| that gives the transmittance TR2. The signal output from the overdrive circuit is a signal related to the overdrive voltage |V3|. These signals are the voltages (|V1|, |V2 It may be an analog voltage value such as |V|, |V3|, or the voltage applied to the liquid crystal element may be It may be a digital signal to provide the overdrive circuit. The signals will be described as being digital signals.

[0424] First, the overall configuration of the overdrive circuit will be described with reference to FIG. Here, the input image signal 301 is used as a signal for controlling the overdrive voltage. As a result of processing these signals, the overdrive voltage Assume that an output image signal 30104 is output as a signal that applies pressure.

[0425] The voltages |V1| and |V2| that give the desired transmittances TR1 and TR2 are Since the input image signals 30101a and 30101b are image signals in adjacent frames, Similarly, 101b is preferably an image signal in a frame adjacent to each other. To obtain such a signal, the input image signal 30101a is converted into the delayed signal shown in FIG. The signal output as a result is designated as an input image signal 30101b. The delay circuit 30102 can be, for example, a memory. That is, in order to delay the input image signal 30101a by one frame, the input image signal 30101a is stored in the memory. The signal 30101a is stored, and at the same time, the signal stored in the previous frame is stored. The signal thus obtained is taken out from the memory as an input image signal 30101b, and the input image signal 3010 1a and the input image signal 30101b are input to the correction circuit 30103 at the same time. It is possible to handle image signals in adjacent frames. By inputting the image signals of adjacent frames to the correction circuit 30103, the output A signal output from the delay circuit 30102 can be obtained. When the image signal is delayed by one frame, the capacity to store one frame of image signal is This allows the memory to be a memory with a The memory capacitance is just right to function as a delay circuit.

[0426] Next, the delay circuit 30102 is designed mainly to reduce the memory capacity. By using such a circuit as the delay circuit 30102, the memory capacity can be increased. Since the amount can be reduced, the manufacturing cost can be reduced.

[0427] A specific example of a delay circuit 30102 having such characteristics is shown in FIG. The delay circuit 30102 shown in FIG. 30105, memory 30106 and decoder 30107.

[0428] The operation of the delay circuit 30102 shown in FIG. 82(B) is as follows. Before storing the input image signal 30101a in the memory 30106, the encoder 301 05 performs the compression process. This reduces the size of the data, which in turn reduces the memory capacity. Therefore, the manufacturing cost can be reduced. The data is sent to the encoder 30107, where it is decompressed. 5. Here, the signal compressed by the encoder 301 can be restored. The compression and decompression processes performed by the decoder 30105 and the decoder 30107 are lossless processes. By doing so, there is no deterioration of the image signal even after the compression / expansion process, This allows you to reduce memory capacity without reducing the quality of the image ultimately displayed on the device. Furthermore, the compression performed by the encoder 30105 and the decoder 30107 can be The compression / expansion process may be a lossy process. The size of the data can be made very small, which reduces the memory capacity significantly. can be done.

[0429] There are various other ways to reduce memory capacity besides those listed above. Instead of compressing the image using an encoder, the image signal has Reduce the color information (for example, from 260,000 colors to 65,000 colors) or reduce the amount of data. (reducing the resolution), etc.

[0430] Next, a specific example of the correction circuit 30103 will be described with reference to FIGS. 82(C) to 82(E). The correction circuit 30103 outputs an output image signal of a certain value from two input image signals. Here, the relationship between the two input image signals and the output image signal is nonlinear. If it is difficult to calculate it by a simple calculation, the correction circuit 30103 may be used. A look-up table (LUT) may be used. The LUT contains two input image signals and an output image signal. The relationship between the two input image signals is already known by measurement. The corresponding output image signal can be obtained simply by referring to the LUT (see FIG. 82(C)). ) By using the LUT30108 as the correction circuit 30103, it is possible to simplify complex circuit designs. The correction circuit 30103 can be realized without performing the above steps.

[0431] Since LUT30108 is a type of memory, it is important to reduce the memory capacity as much as possible. This is preferable in terms of reducing manufacturing costs. As a result, the circuit shown in FIG. 82(D) can be considered. The correction circuit 30103 shown in FIG. 82(D) The LUT 30109 includes an LUT 30109 and an adder 30110. The difference data between the image signal 30101a and the output image signal 30104 to be output is stored. That is, from the input image signal 30101a and the input image signal 30101b, The difference data is extracted from LUT30109 and the extracted difference data is compared with the input image signal 3 0101a is added by an adder 30110 to obtain an output image signal 30104. In addition, by storing the data in LUT30109 as differential data, This reduces the memory capacity of the LUT30109 because the output image signal is Since the differential data size is smaller than that of LUT30104, This is because the required memory capacity can be reduced.

[0432] Furthermore, the output image signal is obtained by simple arithmetic operations of the two input image signals. If it is possible to do this, it can be realized by combining simple circuits such as adders, subtractors, and multipliers. As a result, there is no need to use an LUT, which can significantly reduce manufacturing costs. An example of such a circuit is the circuit shown in FIG. The correction circuit 30103 shown in FIG. 3E includes a subtractor 30111, a multiplier 30112, and an adder 30113. First, the difference between the input image signal 30101a and the input image signal 30101b is The subtractor 30111 calculates the fraction. Then, the multiplier 30112 calculates the fraction by an appropriate factor. Then, the input image signal 30101a is multiplied by the appropriate coefficient to obtain the difference value. The output image signal 30104 can be obtained by adding these signals by an adder 30113. By using such a circuit, it is not necessary to use an LUT, and manufacturing costs are reduced. This can significantly reduce the cost.

[0433] Under certain conditions, the correction circuit 30103 shown in FIG. 82(E) can be used to correct the improper This prevents the output of an inappropriate output image signal 30104. The output image signal 30104 provides a power drive voltage, and the input image signal 30101a and The difference between the input image signal 30101b and the input image signal 30101b has linearity. The slope of the curve is used as the coefficient to be multiplied by the multiplier 30112. It is preferable to use a correction circuit 30103 shown in FIG. 82(E) for the liquid crystal element. An example of a liquid crystal element with such properties is an IPS mode liquid crystal, which has a small response time depending on the gradation. For example, the IPS mode liquid crystal element shown in FIG. By using the correction circuit 30103, the manufacturing cost can be reduced significantly and An overdrive circuit that can prevent an inappropriate output image signal 30104 from being output. You can get a path.

[0434] The same functions as the circuits shown in Figures 82(A) to 82(E) can be achieved by software processing. The memory used in the delay circuit may be the same as other memories included in the liquid crystal display device. , a device (for example, a personal computer) that sends out an image to be displayed on a liquid crystal display device. It is possible to reuse memory etc. that is included in a device such as a video card (or a similar device). This not only reduces manufacturing costs, but also reduces the strength and usage of the overdrive. The user can select the situation in which the message is to be sent according to his / her preference.

[0435] Next, the driving for manipulating the potential of the common line will be described with reference to FIG. A) is a scanning method for a display device using a display element with a capacitive property such as a liquid crystal element. This diagram shows multiple pixel circuits when one common line is arranged for each line. The pixel circuit shown in FIG. 83(A) includes a transistor 30201, an auxiliary capacitor 30202, a display The element 30203, the video signal line 30204, the scanning line 30205 and the common line 30206 are It is prepared.

[0436] The gate electrode of the transistor 30201 is electrically connected to the scanning line 30205. One of the source electrode and the drain electrode of the transistor 30201 is connected to the video signal line 30204. The other of the source electrode and the drain electrode of the transistor 30201 is electrically connected to One electrode of the auxiliary capacitance 30202 and one electrode of the display element 30203 are electrically connected. The other electrode of the auxiliary capacitor 30202 is electrically connected to the common line 30206. is connected to.

[0437] First, the pixel selected by the scanning line 30205 has the transistor 30201 turned on. Therefore, the display element 30203 and the auxiliary capacitor 30204 are connected to each other via the video signal line 30204. A voltage corresponding to the video signal is applied to the capacitor 30202. At this time, the video signal is applied to the common line If the lowest gradation is displayed for all pixels connected to 30206, Or, it displays the highest gray level for all pixels connected to the common line 30206. In this case, it is not necessary to write a video signal to each pixel via the video signal line 30204. Instead of writing the video signal through the video signal line 30204, the common line 30206 By changing the potential, the voltage applied to the display element 30203 can be changed.

[0438] Next, FIG. 83(B) shows a display device using a display element having a capacitive property such as a liquid crystal element. In a device, when two common lines are arranged for one scanning line, The pixel circuit shown in FIG. 83(B) includes a transistor 30211, an auxiliary capacitance 30212, display element 30213, video signal line 30214, scanning line 30215, first It has a common line 30216 and a second common line 30217.

[0439] The gate electrode of the transistor 30211 is electrically connected to the scanning line 30215. One of the source electrode and the drain electrode of the transistor 30211 is connected to the video signal line 30214. The other of the source electrode and the drain electrode of the transistor 30211 is electrically connected to One electrode of the auxiliary capacitor 30212 and one electrode of the display element 30213 are electrically connected. The other electrode of the auxiliary capacitor 30212 is connected to the first common line 30216. In addition, in the pixel adjacent to the pixel, the auxiliary capacitance 3021 The other electrode of the two is electrically connected to a second common line 30217.

[0440] The pixel circuit shown in FIG. 83(B) has a small number of pixels electrically connected to one common line. Therefore, instead of writing the video signal through the video signal line 30214, the first common line By changing the potential of the display element 30216 or the second common line 30217, The frequency with which the voltage applied to the gate can be changed is significantly increased. By using source inversion driving or dot inversion driving, the Flicker can be suppressed while improving reliability.

[0441] Next, the scanning type backlight will be described with reference to Fig. 84. Fig. 84(A) shows a scanning type backlight. This is a diagram showing a scanning backlight in which cathode tubes are arranged side by side. The light source is composed of a diffuser 30301 and N cold cathode fluorescent lamps 30302-1 to 30302-N. N cold cathode fluorescent lamps 30302-1 to 30302-N are arranged on the diffuser 30301. By arranging them side by side, the N cold cathode fluorescent lamps 30302-1 to 30302-N can be can be varied and scanned.

[0442] The change in brightness of each cold cathode tube during scanning will be explained using Figure 84(C). The brightness of the cold cathode tube 30302-1 is changed for a certain period of time. The brightness of the cold cathode fluorescent lamp 30302-2 placed next to the The brightness of the cold cathode fluorescent lamps 30302-1 to 30302-N is changed in sequence. In 84(C), the brightness that is changed for a certain period of time is smaller than the original brightness. It may be brighter than the original. Also, the cold cathode tubes 30302-1 to 30302-N are running. However, it is also possible to scan in the reverse direction from cold cathode tube 30302-N to 30302-1. stomach.

[0443] By driving as shown in Figure 84(C), the average brightness of the backlight can be reduced. Therefore, the power consumption of the backlight, which accounts for the majority of the power consumption of a liquid crystal display device, can be reduced. can be reduced.

[0444] An LED may be used as the light source of the scanning backlight. The scanning backlight shown in Fig. 84(B) is a diffuser plate. 30311 and light sources 30312-1 to 30312-N in which LEDs are arranged side by side. When LEDs are used as the light source for a scanning backlight, the backlight can be made thinner and lighter. Another advantage is that the color reproduction range can be expanded. The LEDs arranged in parallel with the light sources 30312-1 to 30312-N in which D is arranged in parallel are also Since the light can be scanned in the same way, it can also be used as a point scanning backlight. This will further improve the image quality of the moving image.

[0445] Even when LEDs are used as the light source for the backlight, the brightness can be changed as shown in Figure 84(C). It can be driven by converting it into a

[0446] Next, high frequency driving will be explained with reference to Fig. 85. Fig. 85(A) shows the high frequency driving for one frame. This is a diagram showing one image and one intermediate image displayed during a period 30400. 1 is the image of the current frame, 30402 is the intermediate image of the current frame, and 30403 is the image of the next frame. 30404 is the intermediate image of the next frame.

[0447] The intermediate image 30402 of the frame is generated based on the video signals of the frame and the next frame. The intermediate image 30402 of the frame may be an image created in the frame. It may be an image created from the image 30401 of the frame. The image 30402 may be a black image. In addition, one image and one intermediate image are recorded in one frame period (30400). When displaying an image, it is easy to match the frame rate of the video signal, and the image processing circuit It has the advantage of being less complicated.

[0448] FIG. 85(B) shows a period consisting of two consecutive 1-frame periods (2-frame periods). This is a diagram showing one image and two intermediate images. 30411 is the frame ,30412 is the intermediate image of the frame, 30413 is the intermediate image of the next frame, 3 0414 is the image of the next frame.

[0449] The intermediate image 30412 of the frame and the intermediate image 30413 of the next frame are It may be an image created based on the video signal of the next frame, the next frame, or the frame after that. In addition, the intermediate image 30412 of the current frame and the intermediate image 30413 of the next frame are black images. In the case where one image and two intermediate images are displayed in two frame periods, Therefore, the image quality of moving images can be effectively improved without significantly increasing the operating frequency of the peripheral driving circuits. It has the advantage of being able to

[0450] In this embodiment, various drawings have been used to describe the present invention. (may be part of) the content described in another figure may be applied, combined or You can freely replace the parts. With regard to parts, more figures can be constructed by combining other parts.

[0451] The contents (or even a part thereof) described in each drawing of this embodiment may be the same as those described in the drawings of another embodiment. You may freely apply, combine, or replace the contents (even a part of them) Furthermore, in the drawings of this embodiment, each part can be used in a different embodiment. More diagrams can be constructed by combining parts.

[0452] This embodiment is a case where the contents (or a part thereof) described in other embodiments are embodied. An example, a slightly modified example, an example with some changes, an example with improvements, details Examples of cases where it has been mentioned, examples of cases where it has been applied, and examples of related parts are given below. Therefore, the contents described in the other embodiments may be applied to and combined with this embodiment. can be freely combined or substituted.

[0453] (Embodiment 11) In this embodiment, the peripheral portion of the liquid crystal panel will be described.

[0454] Figure 49 shows the backlight unit 20101, which is called an edge-light type, and the LCD panel. 20107. An edge-light type liquid crystal display device is A light source is placed at the edge of the backlight unit, and the fluorescent light from the light source is emitted from the entire light-emitting surface. The edge-light type backlight unit 20101 is thin and energy-efficient. It is possible.

[0455] The backlight unit 20101 includes a diffusion plate 20102, a light guide plate 20103, and a reflector 20104. 0104, a lamp reflector 20105 and a light source 20106.

[0456] The light source 20106 has a function of emitting light as needed. Cold cathode fluorescent lamps, hot cathode fluorescent lamps, light emitting diodes, inorganic EL elements, or organic EL elements are used. I can.

[0457] Figures 50(A), (B), (C) and (D) show edge-light type backlight units. 1 is a diagram showing a detailed configuration of the device. Note that explanations of the diffusion plate, light guide plate, and reflector plate are omitted. Abbreviated.

[0458] The backlight unit 20201 shown in FIG. 50(A) uses a cold cathode fluorescent lamp 2020 as a light source. 3. In order to efficiently reflect the light from the cold cathode fluorescent lamp 20203, A reflector 20202 is provided. This configuration allows the light from the cold cathode fluorescent lamp 20203 Because of its high brightness, it is often used in large display devices.

[0459] The backlight unit 20211 shown in FIG. 50(B) uses a light emitting diode ( For example, a white light emitting diode (LED) 20213 is used. ) 20213 are arranged at predetermined intervals. And, light emitting diodes (LED) 2021 A lamp reflector 20212 is provided to efficiently reflect the light from 3.

[0460] The backlight unit 20221 shown in FIG. 50(C) emits light of each color RGB as a light source. Diode (LED) 20223, Light Emitting Diode (LED) 20224 and Light Emitting Diode The LEDs are 20225. ) 20223, Light Emitting Diode (LED) 20224 and Light Emitting Diode (LED) 2 0225 are arranged at predetermined intervals. Light emitting diodes (LEDs) of each color RGB 20223, light emitting diode (LED) 20224 and light emitting diode (LED) 20 By using 225, color reproducibility can be improved. A lamp reflector 20222 is provided to efficiently reflect the light from the lamp.

[0461] The backlight unit 20231 shown in FIG. 50(D) emits light of each color RGB as a light source. Diode (LED) 20233, Light Emitting Diode (LED) 20234 and Light Emitting Diode This is a configuration using LEDs 20235. For example, each color RGB light emitting diode (LED) 20233, Light Emitting Diode (LED) 20234 and Light Emitting Diode (L Among LEDs (LED) 20235, colors with low luminous intensity (e.g., green) are more common than other LEDs. RGB light-emitting diodes (LEDs) 20233, light-emitting diodes By using (LED) 20234 and light emitting diode (LED) 20235 This allows for improved color reproducibility. To achieve this, a lamp reflector 20232 is provided.

[0462] FIG. 53 shows a liquid crystal display having a backlight unit called a direct type and a liquid crystal panel. The direct type is a type in which a light source is placed directly under the light-emitting surface. This is a method in which the fluorescent light from the light source is emitted from the entire light-emitting surface. The amount of light can be used efficiently.

[0463] The backlight unit 20500 is composed of a diffusion plate 20501, a light shielding plate 20502, and a lamp It is composed of a reflector 20503, a light source 20504 and a liquid crystal panel 20505.

[0464] The light source 20504 has a function of emitting light as needed. For example, the light source 20504 Examples include cold cathode fluorescent lamps, hot cathode fluorescent lamps, light-emitting diodes, inorganic EL elements, and organic EL elements. is used.

[0465] FIG. 51 is a diagram showing an example of the configuration of a polarizing plate (also called a polarizing film).

[0466] Polarizing film 20300 is made up of protective film 20301, substrate film 20302, and PV A polarizing film 20303, substrate film 20304, adhesive layer 20305 and release film It has film 20306.

[0467] PVA polarizing film 20303 is a film with a substrate film on both sides (substrate film 2030 2 and substrate film 20304), the reliability can be increased. VA Polarizing Film 20303 is made of highly transparent and durable triacetyl cellulose (TAC) The substrate film and the TAC film may be sandwiched between PVA films. It functions as a protective layer for the polarizer of the polarizing film 20303.

[0468] One of the substrate films (substrate film 20304) is attached to the glass substrate of the LCD panel. The adhesive layer 20305 is attached to one side of the adhesive. The adhesive layer 20 is formed by applying the adhesive to the substrate film (substrate film 20304). 305 is provided with a release film 20306 (separate film).

[0469] The other substrate film (substrate film 20302) is provided with a protective film 20301. It is being done.

[0470] The surface of the polarizing film 20300 is provided with a hard coat scattering layer (anti-glare layer). The hard coat scattering layer may have fine irregularities formed on the surface by AG treatment. It also has an anti-glare function that scatters external light, preventing external light from being reflected on the LCD panel. In addition, surface reflection can be prevented.

[0471] Multiple optical thin film layers with different refractive indices are multi-layered on the surface of polarizing film 20300 (anti-reflection It may be possible to use a multi-layered multi-refractive index (also called a reflection treatment or an AR treatment). The different optical thin film layers can reduce the reflectance of the surface by the optical interference effect.

[0472] FIG. 52 is a diagram showing an example of a system block of a liquid crystal display device.

[0473] In the pixel portion 20405, a signal line 20412 is extended from a signal line driver circuit 20403. In the pixel portion 20405, a scanning line 20410 is connected to a scanning line driver circuit 2040. 4. The signal line 20412 and the scanning line 20410 are arranged at the intersections thereof. A plurality of pixels are arranged in a matrix in the area. Therefore, each of the multiple pixels has a switching element that controls the tilt of the liquid crystal molecules. In this way, the voltage for controlling the switching can be input independently to each crossover area. A structure in which a display element is provided is called an active matrix type. The structure is not limited to the passive matrix type, but may be a passive matrix type. The pixel type has no switching element, and therefore the manufacturing process is simple.

[0474] The driver circuit section 20408 includes a control circuit 20402, a signal line driver circuit 20403, and a scanning The control circuit 20402 has a line driver circuit 20404. A video signal 20401 is input to the control circuit 20402. The control circuit 20402 controls the signal line driving circuit 20401 in response to the video signal 20401. The control circuit 20402 controls the signal line driver circuit 20403 and the scanning line driver circuit 20404. Control signals are input to the driving circuit 20403 and the scanning line driving circuit 20404. In response to this control signal, the signal line driver circuit 20403 outputs a video signal to the signal line 204. 12, and the scanning line driving circuit 20404 inputs the scanning signal to the scanning line 20410. The switching element of the pixel is selected in response to the scanning signal, and a signal is applied to the pixel electrode of the pixel. A video signal is input.

[0475] The control circuit 20402 also controls the power supply 20407 in response to the video signal 20401. The power supply 20407 has a means for supplying power to the lighting means 20406. The 20406 is available in edge-lit backlight units or direct-type backlight units. However, a front light unit can be used as the lighting means 20406. A front light is a light-emitting element attached to the front side of the pixel section to illuminate the entire display. The light source is a plate-shaped light unit composed of a body and a light guide. It consumes low power and can illuminate the pixel area evenly.

[0476] As shown in FIG. 52(B), the scanning line driving circuit 20404 includes a shift register 20441, It has circuits that function as a level shifter 20442 and a buffer 20443. Register 20441 contains the gate start pulse (GSP) and gate clock signal (GCK ) and other signals are input.

[0477] As shown in FIG. 52(C), the signal line driver circuit 20403 includes a shift register 20431, The first latch 20432, the second latch 20433, the level shifter 20434 and the buffer A circuit that functions as a buffer 20435 is provided. A level switch is a circuit that has the function of amplifying weak signals, and includes an operational amplifier. The cover 20434 receives a signal such as a start pulse (SSP) from a first latch 20432. Data (DATA) such as a video signal is input to the second latch 20433. The latch (LAT) signal can be temporarily held and input to the pixel section 20405 all at once. This is called line sequential driving. Therefore, pixels that are driven point sequentially rather than line sequentially are If so, the second latch may not be necessary.

[0478] In this embodiment, various liquid crystal panels can be used. For example, The liquid crystal panel may have a structure in which a liquid crystal layer is sealed between two substrates. On one substrate, a transistor, a capacitor, a pixel electrode, an alignment film, etc. are formed. A polarizing plate, a retardation plate or a prism sheet is disposed on the opposite side of the upper surface of one of the substrates. On the other substrate, a color filter, a black matrix, a counter electrode or On the other side of the substrate, a polarizing plate or a retardation plate is formed. The color filter and the black matrix may be disposed on one of the substrates. Alternatively, a slit ( By arranging the grid, a three-dimensional display can be achieved.

[0479] A polarizing plate, a retardation plate, and a prism sheet can be disposed between the two substrates. Alternatively, it can be integral with either of the two substrates.

[0480] In this embodiment, various drawings have been used to explain the present invention. The contents (or a part of them) of another figure may be applied or combined with the contents (or a part of them) of another figure. Furthermore, in the diagrams described above, For each part, more figures can be constructed by combining other parts.

[0481] Similarly, the contents (or even a part thereof) described in each drawing of this embodiment may be applied to other embodiments. The contents described in the diagram (even a part of them) can be freely applied, combined, or replaced. Furthermore, each part of the figure of this embodiment can be used in another embodiment. By combining parts, even more diagrams can be constructed.

[0482] This embodiment is a case where the contents (or a part thereof) described in other embodiments are embodied. An example, a slightly modified example, an example with some changes, an example with improvements, details Examples of cases where it has been mentioned, examples of cases where it has been applied, and examples of related parts are given below. Therefore, the contents described in the other embodiments may be applied to and combined with this embodiment. can be freely combined or substituted.

[0483] (Embodiment 12) In this embodiment, the configuration and operation of a pixel applicable to a liquid crystal display device will be described. and explain.

[0484] In this embodiment, the operation mode of the liquid crystal element is TN (Twisted Nem). atic) mode, IPS (In-Plane-Switching) mode, FFS ( Fringe Field Switching) mode, MVA (Multi-dom Vertical Alignment mode, PVA (Patterned Vertical Alignment mode, ASM (Axially Symmetry Mode) metric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferro electric Liquid Crystal) mode and AFLC (AntiF It is possible to use modes such as ferroelectric liquid crystal. can.

[0485] FIG. 54(A) is a diagram showing an example of a pixel configuration that can be applied to a liquid crystal display device.

[0486] The pixel 40100 includes a transistor 40101, a liquid crystal element 40102, and a capacitor element 40 The gate of the transistor 40101 is connected to a wiring 40105. A first terminal of the transistor 40101 is connected to a wiring 40104. The second terminal of the resistor 40101 is connected to the first electrode of the liquid crystal element 40102 and the capacitor element 4010 The second electrode of the liquid crystal element 40102 is connected to the counter electrode 40107. A second electrode of the capacitor 40103 is connected to a wiring 40106.

[0487] The wiring 40104 functions as a signal line, and the wiring 40105 functions as a scanning line. The wiring 40106 functions as a capacitor line. The transistor 40101 functions as a switch. The capacitor 40103 functions as a storage capacitor.

[0488] The transistor 40101 only needs to function as a switch. The polarity of 101 may be either P-channel or N-channel.

[0489] FIG. 54(B) is a diagram showing an example of a pixel configuration that can be applied to a liquid crystal display device. 54(B) is a liquid crystal display device suitable for horizontal electric field mode (including IPS mode and FFS mode). FIG. 10 is a diagram illustrating an example of a pixel configuration that can be applied to the device.

[0490] The pixel 40110 includes a transistor 40111, a liquid crystal element 40112, and a capacitor element 40 The gate of the transistor 40111 is connected to a wiring 40115. A first terminal of the transistor 40111 is connected to a wiring 40114. The second terminal of the resistor 40111 is connected to the first electrode of the liquid crystal element 40112 and the capacitor element 4011 The second electrode of the liquid crystal element 40112 is connected to a wiring 40116. A second electrode of the capacitor 40113 is connected to a wiring 40116.

[0491] The wiring 40114 functions as a signal line, and the wiring 40115 functions as a scanning line. The wiring 40116 functions as a capacitance line. The transistor 40111 functions as a switch. The capacitor element 40113 functions as a storage capacitor.

[0492] The transistor 40111 only needs to function as a switch. The polarity of 111 may be either P-channel or N-channel.

[0493] FIG. 55 is a diagram showing an example of a pixel configuration that can be applied to a liquid crystal display device. In particular, FIG. This is an example of a pixel configuration that can reduce the number of wirings and increase the aperture ratio of the pixel.

[0494] FIG. 55 shows two pixels (pixel 40200 and pixel 40210) arranged in the same column direction. For example, if the pixel 40200 is arranged in the Nth row, the pixel 40210 is arranged in the Nth row. It is located on the +1st line.

[0495] The pixel 40200 includes a transistor 40201, a liquid crystal element 40202, and a capacitor element 40 The gate of the transistor 40201 is connected to a wiring 40205. A first terminal of the transistor 40201 is connected to a wiring 40204. The second terminal of the resistor 40201 is connected to the first electrode of the liquid crystal element 40202 and the capacitor element 4020 The second electrode of the liquid crystal element 40202 is connected to the counter electrode 40207. The second electrode of the capacitor 40203 is connected to the same wiring as the gate of the transistor in the previous row. It continues.

[0496] The pixel 40210 includes a transistor 40211, a liquid crystal element 40212, and a capacitor element 40 The gate of the transistor 40211 is connected to a wiring 40215. A first terminal of the transistor 40211 is connected to a wiring 40204. The second terminal of the resistor 40211 is connected to the first electrode of the liquid crystal element 40212 and the capacitor element 4021 The second electrode of the liquid crystal element 40212 is connected to the counter electrode 40217. The second electrode of the capacitor element 40213 is connected to the same wiring (wiring) as the gate of the transistor in the previous row. It is connected to the line 40205.

[0497] The wiring 40204 functions as a signal line. The wiring 40205 functions as a scanning line for the Nth row. The wiring 40205 also functions as a capacitance line for the N+1th stage. The switch 40201 functions as a switch. The capacitor 40203 functions as a storage capacitor. It works.

[0498] The wiring 40215 functions as a scanning line for the (N+1)th row. It also functions as the N+2 stage capacitance line. Transistor 40211 functions as a switch. The capacitor 40213 functions as a storage capacitor.

[0499] The transistors 40201 and 40211 function as switches. The polarity of the transistor 40201 and the polarity of the transistor 40211 are P It may be either a channel type or an N-channel type.

[0500] FIG. 56 is a diagram showing an example of a pixel configuration that can be applied to a liquid crystal display device. In particular, FIG. This is an example of a pixel configuration that can improve the viewing angle by using sub-pixels.

[0501] The pixel 40320 has a sub-pixel 40300 and a sub-pixel 40310. Below, a case where pixel 40320 has two sub-pixels will be described. 320 may have three or more sub-pixels.

[0502] The sub-pixel 40300 includes a transistor 40301, a liquid crystal element 40302, and a capacitor element The gate of the transistor 40301 is connected to a wiring 40305. A first terminal of the transistor 40301 is connected to a wiring 40304. The second terminal of the transistor 40301 is connected to the first electrode of the liquid crystal element 40302 and the capacitor element 40 The second electrode of the liquid crystal element 40302 is connected to the first electrode of the counter electrode 403. 07. A second electrode of the capacitor 40303 is connected to a wiring 40306. .

[0503] The sub-pixel 40310 includes a transistor 40311, a liquid crystal element 40312, and a capacitor element The gate of the transistor 40311 is connected to a wiring 40315. A first terminal of the transistor 40311 is connected to a wiring 40304. The second terminal of the transistor 40311 is connected to the first electrode of the liquid crystal element 40312 and the capacitor element 40 The second electrode of the liquid crystal element 40312 is connected to the first electrode of the counter electrode 403. 17. A second electrode of the capacitor 40313 is connected to the wiring 40306. .

[0504] The wiring 40304 functions as a signal line, and the wiring 40305 functions as a scanning line. The wiring 40315 functions as a signal line. The wiring 40306 functions as a capacitance line. The transistor 40301 functions as a switch. The capacitor 40303 functions as a storage capacitor. 313 functions as a storage capacitor.

[0505] The transistor 40301 only needs to function as a switch. The polarity of the transistor 301 may be either a P-channel type or an N-channel type. The transistor 11 only needs to function as a switch. The polarity of the transistor 40311 is P-channel. It may be either an N-channel type or an N-channel type.

[0506] The video signal input to the sub-pixel 40300 is the same as the video signal input to the sub-pixel 40310. In this case, the alignment of the liquid crystal molecules of the liquid crystal...

Claims

1. having first to eighth transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to an output signal wiring; one of the source electrode and the drain electrode of the second transistor is always electrically connected to a power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the output signal wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the third transistor is always electrically connected to the first wiring; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the fourth transistor is always electrically connected to a gate electrode of the first transistor; one of a source electrode and a drain electrode of the fifth transistor is always electrically connected to a first signal line; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the gate of the first transistor; a gate electrode of the fifth transistor is always electrically connected to the first signal line; one of a source electrode and a drain electrode of the sixth transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the sixth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the sixth transistor is always electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the seventh transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the seventh transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the seventh transistor is always electrically connected to a second signal line; one of a source electrode and a drain electrode of the eighth transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the eighth transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the eighth transistor is always electrically connected to the first signal line; a first conductive layer having a function as one of a source electrode and a drain electrode of the second transistor also has a function as one of a source electrode and a drain electrode of the fourth transistor, a function as one of a source electrode and a drain electrode of the sixth transistor, a function as one of a source electrode and a drain electrode of the seventh transistor, and a function as one of a source electrode and a drain electrode of the eighth transistor; the second conductive layer having a function as a gate electrode of the second transistor has a function as a gate electrode of the sixth transistor; At least one of the first to eighth transistors includes an oxide semiconductor in a channel formation region.

2. having first to eighth transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to an output signal wiring; one of the source electrode and the drain electrode of the second transistor is always electrically connected to a power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the output signal wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the third transistor is always electrically connected to the first wiring; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the fourth transistor is always electrically connected to a gate electrode of the first transistor; one of a source electrode and a drain electrode of the fifth transistor is always electrically connected to a first signal line; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the gate of the first transistor; a gate electrode of the fifth transistor is always electrically connected to the first signal line; one of a source electrode and a drain electrode of the sixth transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the sixth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the sixth transistor is always electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the seventh transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the seventh transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the seventh transistor is always electrically connected to a second signal line; one of a source electrode and a drain electrode of the eighth transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the eighth transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the eighth transistor is always electrically connected to the first signal line; a first conductive layer having a function as one of a source electrode and a drain electrode of the second transistor also has a function as one of a source electrode and a drain electrode of the fourth transistor, a function as one of a source electrode and a drain electrode of the sixth transistor, a function as one of a source electrode and a drain electrode of the seventh transistor, and a function as one of a source electrode and a drain electrode of the eighth transistor; the second conductive layer having a function as a gate electrode of the second transistor has a function as a gate electrode of the sixth transistor; a third conductive layer functioning as the other of the source electrode and the drain electrode of the third transistor is always electrically connected to a fourth conductive layer functioning as the other of the source electrode and the drain electrode of the eighth transistor via the second conductive layer; At least one of the first to eighth transistors includes an oxide semiconductor in a channel formation region.

3. having first to eighth transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to an output signal wiring; one of the source electrode and the drain electrode of the second transistor is always electrically connected to a power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the output signal wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the third transistor is always electrically connected to the first wiring; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the fourth transistor is always electrically connected to a gate electrode of the first transistor; one of a source electrode and a drain electrode of the fifth transistor is always electrically connected to a first signal line; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the gate of the first transistor; a gate electrode of the fifth transistor is always electrically connected to the first signal line; one of a source electrode and a drain electrode of the sixth transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the sixth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the sixth transistor is always electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the seventh transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the seventh transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the seventh transistor is always electrically connected to a second signal line; one of a source electrode and a drain electrode of the eighth transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the eighth transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the eighth transistor is always electrically connected to the first signal line; a first conductive layer having a function as one of a source electrode and a drain electrode of the second transistor also has a function as one of a source electrode and a drain electrode of the fourth transistor, a function as one of a source electrode and a drain electrode of the sixth transistor, a function as one of a source electrode and a drain electrode of the seventh transistor, and a function as one of a source electrode and a drain electrode of the eighth transistor; the second conductive layer having a function as a gate electrode of the second transistor has a function as a gate electrode of the sixth transistor; W (channel width) / L (channel length) of the first transistor is larger than W / L of the second transistor, the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the first transistor is greater than the W / L of the seventh transistor; the W / L of the first transistor is greater than the W / L of the eighth transistor; In a plan view, a channel length direction of the first transistor is a first direction, a channel length direction of the third transistor is the first direction in a plan view; a channel length direction of the seventh transistor is the first direction in a plan view; In a plan view, the third conductive layer functioning as the output signal wiring has a region extending in a second direction intersecting the first direction, At least one of the first to eighth transistors includes an oxide semiconductor in a channel formation region.

4. having first to eighth transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to an output signal wiring; one of the source electrode and the drain electrode of the second transistor is always electrically connected to a power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the output signal wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the third transistor is always electrically connected to the first wiring; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the fourth transistor is always electrically connected to a gate electrode of the first transistor; one of a source electrode and a drain electrode of the fifth transistor is always electrically connected to a first signal line; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the gate of the first transistor; a gate electrode of the fifth transistor is always electrically connected to the first signal line; one of a source electrode and a drain electrode of the sixth transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the sixth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the sixth transistor is always electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the seventh transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the seventh transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the seventh transistor is always electrically connected to a second signal line; one of a source electrode and a drain electrode of the eighth transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the eighth transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the eighth transistor is always electrically connected to the first signal line; a first conductive layer having a function as one of a source electrode and a drain electrode of the second transistor also has a function as one of a source electrode and a drain electrode of the fourth transistor, a function as one of a source electrode and a drain electrode of the sixth transistor, a function as one of a source electrode and a drain electrode of the seventh transistor, and a function as one of a source electrode and a drain electrode of the eighth transistor; the second conductive layer having a function as a gate electrode of the second transistor has a function as a gate electrode of the sixth transistor; a third conductive layer functioning as the other of the source electrode and the drain electrode of the third transistor is always electrically connected to a fourth conductive layer functioning as the other of the source electrode and the drain electrode of the eighth transistor via the second conductive layer; W (channel width) / L (channel length) of the first transistor is larger than W / L of the second transistor, the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the first transistor is greater than the W / L of the seventh transistor; the W / L of the first transistor is greater than the W / L of the eighth transistor; In a plan view, a channel length direction of the first transistor is a first direction, a channel length direction of the third transistor is the first direction in a plan view; a channel length direction of the seventh transistor is the first direction in a plan view; In a plan view, the fifth conductive layer functioning as the output signal wiring has a region extending in a second direction intersecting the first direction, At least one of the first to eighth transistors includes an oxide semiconductor in a channel formation region.

Images