Power packet transmission system

Abstract

To realize a surge suppression method which facilitates analytical design without an additional circuit for surge suppression in a power packet transmission system of a pulse transmission system.SOLUTION: In a power packet transmission system, each of a plurality of routers 51 connected with each other like a network comprises: a capacitor 73 for accumulating DC power; and a bidirectional switch 72 connected with wiring 52 corresponding to a high potential side node of the capacitor 73. When a power packet 62 is transmitted from a first router 51Q to a second router 51P, current is started to be applied to first wiring 52 by switching a first bidirectional switch 72Q and a second bidirectional switch 72P from an open state to a closed state, and at least one of the first bidirectional switch 72Q and the second bidirectional switch 72P is switched from the closed state to the open state according to timing in which current flowing in the first wiring first makes zero cross.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to a power converter and a power packet transmission system. [Background technology]

[0002] The practical application of wide-gap semiconductors such as SiC and GaN has made it possible to switch at higher frequencies and with higher power than conventional power converters using Si. This has led to the miniaturization and weight reduction of power converters. However, high-frequency switching increases dv / dt and di / dt, making the problem of surges during switching more apparent.

[0003] Conventionally, methods of using additional circuits such as snubber circuits and active clamp circuits to suppress surges have been known. However, these methods increase the volume of the converter, which goes against the miniaturization of power converters, which is a feature of using wide-gap semiconductors. In addition, the use of additional circuits can increase switching losses.

[0004] Another known surge suppression method is to use a resonant power converter such as an E-class converter (see, for example, Japanese Patent Laid-Open Publication No. 2010-148311 (Patent Document 1)). By utilizing resonance, soft switching can be achieved.

[0005] Next, we will introduce the power packet transmission system to which this disclosure relates. A power packet is a unit of power transmission that combines pulsed DC power and information related to that power. In a transmission network using power packets, power packets are transmitted via routers using a time-division multiplexing method. Transmission methods between routers include those that use resonance (see, for example, Non-Patent Document 1) and those that use pulse transmission of DC power waveforms (see, for example, Patent No. 6210496 (Patent Document 2)).

[0006] Specifically, a transmission method that utilizes resonance (hereinafter referred to as a resonance transmission method) uses an LC resonator in which an inductor is connected in series to a capacitor used as a power buffer. Then, power is transmitted between routers through LC resonance. On the other hand, a method that uses DC pulse transmission (hereinafter referred to as a pulse transmission method) uses a capacitor or a battery as a power buffer, and power is transmitted based on the potential difference between the buffer voltages of the routers that exchange power.

[0007] Compared to the resonant transmission method, the pulse transmission method of the power packet transmission system is superior in terms of the freedom of selection of the transmission voltage and the number of routers connected, but it has the disadvantage of being susceptible to surges during switching. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-148311 [Patent Document 2] Patent No. 6210496 [Non-patent literature]

[0009] [Non-Patent Document 1] Hiroki Nakano and Toshio Okabe, "Design and Implementation of a Power Packet Router," Proceedings of the Symposium on Multimedia, Distributed, Coordinated and Mobile (DICOMO2017), 2017, pp. 1875-1880 Summary of the Invention [Problem to be solved by the invention]

[0010] Resonant power converters such as class E converters require individual design depending on the circuit to be applied and the voltage used, and their operating conditions are limited, making analytical design difficult. This necessitates tuning to determine circuit parameters. Therefore, a first objective of the present disclosure is to provide a power converter that achieves a surge suppression method that is easy to analytically design without the need for additional circuits for surge suppression, such as snubber circuits.

[0011] The above-mentioned surge suppression problem may also apply to a power packet transmission system using a pulse transmission method. In particular, since a power packet transmission system must handle multiple voltage levels, it is difficult to apply surge suppression measures that perform switching under Class E operating conditions, which require individual design for each operating voltage. Therefore, a second object of the present disclosure is to realize a surge suppression method that is easy to analytically design in a power packet transmission system using a pulse transmission method, without requiring an additional circuit for surge suppression. Other objects and features of the present disclosure will be described in the following embodiments. [Means for solving the problem]

[0012] The first and second problems can be solved by substantially the same means. Specifically, a power converter according to one embodiment includes a first node to which DC power is input, a second node connected to a load, an inductor, a semiconductor switching device, a capacitor, and a controller. A first end of the inductor is connected to the second node. The semiconductor switching device is connected between the first node and a second end of the inductor. A high-potential node of the capacitor is connected to the second node. The controller controls the opening and closing of the semiconductor switching device. When the semiconductor switching device is in a closed state, the semiconductor switching device, the inductor, and the capacitor form a series resonant circuit having underdamping characteristics. The controller switches the semiconductor switching device from an open state to a closed state to start flowing current through the inductor, and switches the semiconductor switching device from a closed state to an open state in accordance with the timing of the first zero crossing of the current flowing through the inductor. The time from when the current starts flowing through the inductor to when the current first crosses zero is a constant determined solely by the circuit parameters of the series resonant circuit.

[0013] In one embodiment, a power packet transmission system transmits a power packet that combines pulsed DC power and information related to the DC power. The power packet transmission system includes a plurality of routers connected in a network via a plurality of wirings. Each of the plurality of routers includes a capacitor for storing DC power, a plurality of bidirectional switches, and a controller that controls opening and closing of the plurality of bidirectional switches. Each of the plurality of bidirectional switches is connected between a high-potential node of the capacitor and a corresponding one of the plurality of wirings. The plurality of routers includes a first router and a second router connected to each other via a first wiring. The first router includes a first capacitor and a first bidirectional switch connected between a high-potential node of the first capacitor and a first end of the first wiring. The second router includes a second capacitor and a second bidirectional switch connected between a high-potential node of the second capacitor and a second end of the first wiring. When the first bidirectional switch and the second bidirectional switch are both in a closed state, the first bidirectional switch, the second bidirectional switch, the first capacitor, the second capacitor, and the first wiring form a series resonant circuit having underdamping characteristics. When transmitting a power packet from the first router to the second router, the controller of the first router and the controller of the second router start to flow current through the first wiring by switching the first bidirectional switch and the second bidirectional switch from an open state to a closed state, and switch at least one of the first bidirectional switch and the second bidirectional switch from a closed state to an open state in accordance with the timing of the first zero crossing of the current flowing through the first wiring. The time from when the current starts to flow through the first wiring to the first zero crossing is a constant determined only by the circuit parameters of the above-mentioned series resonant circuit. [Effects of the Invention]

[0014] According to the power converter of the above embodiment, the underdamping characteristics of the series resonant circuit are utilized to switch the semiconductor switching element to the off state in time with the first zero crossing of the current flowing through the inductor, thereby providing a power converter that realizes a surge suppression method that is easy to analytically design and does not require additional circuits for surge suppression such as snubber circuits.

[0015] According to the power packet transmission system of the above embodiment, as in the case of the power converter, at least one of the first bidirectional switch and the second bidirectional switch connected to the first wiring is switched to the off state in accordance with the timing of the first zero crossing of the current flowing through the first wiring by utilizing the underdamping characteristics of the series resonant circuit. This makes it possible to provide a power packet transmission system that realizes a surge suppression method that is easy to analytically design, without requiring any additional circuitry for surge suppression. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a diagram illustrating a configuration and operation of a power converter according to a first embodiment. [Figure 2] FIG. 10 is a diagram showing current characteristics in an RLC series resonant circuit in the case of underdamping. [Figure 3] 1 is a conceptual diagram showing the overall configuration of a power packet transmission system. [Figure 4] FIG. 2 is a diagram illustrating the configuration of a power packet. [Figure 5] FIG. 1 is a diagram for explaining the configuration of a router using a pulse transmission method. [Figure 6] FIG. 1 is a diagram for conceptually explaining a method for transmitting power packets between two routers. [Figure 7] FIG. 1 is a circuit diagram showing the configuration of two routers connected via wiring. [Figure 8] 10A and 10B are diagrams for explaining voltage and current waveforms at various parts during power transmission between two routers. [Figure 9] FIG. 1 is a diagram for explaining a method of transmitting power between a large number of routers that constitute a power packet transmission network. [Figure 10] 10A and 10B are diagrams for explaining an example of a method for identifying an on-time of a bidirectional switch. [Figure 11] FIG. 10 is a diagram for explaining a power transmission method according to a third embodiment. [Figure 12] FIG. 1 is a circuit diagram illustrating a simulation model. [Figure 13] 10 is a diagram showing voltage and current waveforms when neither of the surge suppression methods described in the second and third embodiments is used. FIG. [Figure 14] 10A and 10B are diagrams showing voltage and current waveforms when the surge suppression method described in the second embodiment is used. [Figure 15] 10A and 10B are diagrams showing voltage and current waveforms when the surge suppression method described in the third embodiment is used. [Figure 16] 10A and 10B are diagrams showing voltage and current waveforms when the surge suppression methods described in the second and third embodiments are both used. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, the embodiments will be described in detail with reference to the drawings. First, in the first embodiment, a power converter capable of suppressing surges without an additional circuit will be described. Next, in the second to fourth embodiments, a power packet transmission system using a pulse transmission method capable of suppressing surges without an additional circuit will be described. Note that the same or corresponding parts will be given the same reference symbols, and their description may not be repeated.

[0018] <First Embodiment> [Power converter configuration] Figure 1 shows the configuration and operation of a power converter according to embodiment 1. Figure 1(A) shows a circuit diagram of power converter 10, and Figure 1(B) shows voltage and current waveforms at various parts of power converter 10.

[0019] Referring to FIG. 1A, the circuit configuration of power converter 10 is known as a step-down chopper circuit, which is a non-isolated power converter. Specifically, power converter 10 includes a high-potential input node (node) 11P (first node), a low-potential input node 11N, a high-potential output node 12P (second node), a low-potential output node 12N, a semiconductor switching element 15, a diode 18, an inductor 17, and an output capacitor 19. In the case of FIG. 1A, an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as semiconductor switching element 15, but other types of semiconductor switching elements may also be used. Diode 16 is a parasitic diode when semiconductor switching element 15 is a MOSFET.

[0020] A DC power supply 21 is connected between input nodes 11P and 11N. A load 22 is connected between output nodes 12P and 12N. The load 22 in FIG. 1A is modeled by a load resistor. The low-potential side input node 11N and the low-potential side output node 12N are directly connected by wiring, and a reference potential (for example, ground potential) is applied to them. In the present disclosure, the input node 11N and the output node 12N may be collectively referred to as a reference node 13.

[0021] The connections of the components of power converter 10 in Fig. 1 will be briefly described below. The drain of NMOSFET serving as semiconductor switching element 15 is connected to input node 11P, and the source is connected to one end of inductor 17. The other end of inductor 17 is connected to output node 12P. The cathode of diode 18 is connected to connection node 14 between semiconductor switching element 15 and inductor 17, and the anode of diode 18 is connected to reference node 13. Therefore, diode 18 serving as a rectifying element blocks current flowing from connection node 14 to reference node 13 when semiconductor switching element 15 is on. Output capacitor 19 is connected between output nodes 12P and 12N.

[0022] A semiconductor switching element for synchronous rectification (hereinafter referred to as a synchronous rectifier element) may be provided as a rectifier element instead of the diode 18. The synchronous rectifier element is controlled to the off state when the semiconductor switching element 15 is controlled to the on state, and is controlled to the on state when the semiconductor switching element 15 is controlled to the off state. Note that, as will be described later, the power converter 10 of this embodiment does not necessarily need to include the diode 18 or the synchronous rectifier element.

[0023] The power converter 10 further includes a voltage detector (not shown) for detecting an input voltage Vin applied between input nodes 11P and 11N, a voltage detector (not shown) for detecting an output voltage Vout output from between output nodes 12P and 12N to a load 22, and a controller 20. The power converter 10 further includes a controller 20 for detecting an inductor current I L A current detector may be provided to detect the current.

[0024] Based on the detection values ​​of these detectors, controller 20 generates a control signal u to be input to the control electrode to control the switching of semiconductor switching element 15. Controller 20 may be configured based on a microcomputer including a CPU (Central Processing Unit) and memory, or may be configured with an FPGA (Field Programmable Gate Array), or may be configured with a dedicated circuit such as an ASIC (Application Specific Integrated Circuit), or may be configured with a combination of two or more of the above.

[0025] [Power converter operation] Next, the operation of the power converter 10 will be described with reference to Fig. 1(B). In Fig. 1(B), from the top, a control signal u, an inductor current I L1B, the waveforms of the input voltage Vin, the voltage Vs at the connection node 14, and the output voltage Vout are shown. The input voltage Vin is equal to the output voltage of the DC power supply 21. In the example of FIG. 1B, the capacity of the DC power supply 21 is sufficiently large, so the input voltage Vin is constant.

[0026] At time t1 in FIG. 1B, the controller 20 inputs a high-level (H-level) control signal u to the control electrode of the semiconductor switching element 15, thereby switching the semiconductor switching element 15 to the ON state (also referred to as a closed state or a conducting state). This causes a current to flow from the DC power supply 21 through the semiconductor switching element 15 and the inductor 17 to the output capacitor 19 and the load 22. As a result, the inductor current I L starts to increase from 0, the output capacitor 19 starts to charge, and the output voltage Vout increases over time. Part of the current is consumed by the load 22. The voltage Vs at the connection node 14 is equal to the value obtained by subtracting the voltage drop due to the on-resistance of the semiconductor switching element 15 from the input voltage Vin.

[0027] Here, the above current path forms a series resonant circuit consisting of a combined resistance component R of the parasitic resistances of semiconductor switching element 15, inductor 17, and output capacitor 19, an inductance L of inductor 17, and a capacitance C of output capacitor 19. In power converter 10 of this embodiment, the values ​​of inductance L and capacitance C are set in advance so that the current characteristics of this series resonant circuit are underdamped. The condition for underdamping is given by the following equation (1):

[0028]

number

[0029] Figure 2 shows the current characteristics in the case of underdamping in an RLC series resonant circuit. In the case of underdamping, the current characteristics include an oscillatory current component, resulting in multiple current zeros as shown in Figure 2. The change in current i over time t is expressed by the following equation (2A). The damping ratio ζ of equation (2A) is expressed by the following equation (2B), the angular frequency ω is expressed by the following equation (2C), and the coefficient A is expressed by the following equation (2D) using the input voltage Vin.

[0030]

number

[0031] Furthermore, the time t0 until the first current zero point is expressed by the following equation (3). In equation (3), π is the circular constant. As shown in equation (3), the time t0 is a constant determined only by the circuit parameters of the RLC series resonant circuit. The time t0 does not depend on the values ​​of the voltage and current supplied from the DC power supply 21, nor on the values ​​of the voltage and current consumed by the load 22.

[0032]

number

[0033] Returning to Figure 1(B), at time t2, when the above-mentioned time t0 has passed from time t1, the inductor current I Lpasses through the zero point. At this timing, the controller 20 switches the semiconductor switching element 15 to the OFF state (also referred to as the open state or non-conducting state) by inputting a low-level (L-level) signal to the control electrode of the semiconductor switching element 15. As described above, the time t0 is a constant determined solely by the circuit parameters, and therefore the time t0 can be determined in advance based on the design parameters. Therefore, the controller 20 may switch the semiconductor switching element 15 to the OFF state when a predetermined time t0 has elapsed since the time t1 using, for example, an internal timer. In other words, the controller 20 switches the semiconductor switching element 15 from the closed state to the open state when a predetermined time has elapsed since the semiconductor switching element 15 was switched from the open state to the closed state. This predetermined time is the time from when current begins to flow through the inductor 17 to the first zero crossing, and is a constant determined solely by the circuit parameters of the RLC series resonant circuit. In principle, the inductor current I L It is possible to actually measure the zero-crossing point and detect the zero-crossing point. However, providing such a zero-crossing detection circuit complicates the device configuration and increases costs. In the power converter 10 of this embodiment, simply by measuring the time from when the semiconductor switching element 15 is switched to the closed state, the semiconductor switching element 15 can be switched to the open state accurately at the timing when the current crosses zero, thereby suppressing surges. A feature of the power converter 10 of this embodiment is that surges can be suppressed without adding any special circuitry.

[0034] After time t2, when the semiconductor switching element 15 is in the off state, the inductor current I L is 0. Therefore, the potential difference Vs between the connection node 14 and the reference node 13 is equal to the output voltage Vout. Since the voltage of the output capacitor 19 is consumed by the load 22, the output voltage Vout decreases over time.

[0035] Thereafter, at time t3, the controller 20 again inputs an H-level control signal u to the control electrode of the semiconductor switching element 15, thereby switching the semiconductor switching element 15 to the ON state. The timing of turning on the semiconductor switching element 15 is determined, for example, based on the detected value of the output voltage Vout. Specifically, the controller 20 may turn on the semiconductor switching element 15 when the output voltage Vout reaches a set value, or may turn on the semiconductor switching element 15 when the average value of the output voltage Vout per switching cycle of the semiconductor switching element 15 reaches a set value.

[0036] At time t3, the semiconductor switching element 15 is switched to the ON state, and the inductor current I L starts to increase from 0. The operation of power converter 10 after time t3 is similar to that after time t1, and therefore will not be described repeatedly.

[0037] In this way, the on-time of semiconductor switching element 15 is a fixed value t0, and the off-time and switching period Ts vary depending on the set value of output voltage Vout. That is, the control method of power converter 10 is pulse density modulation (PDM).

[0038] [Effects of the First Embodiment] According to the power converter 10 having the above configuration, the current value when the semiconductor switching element 15 is turned on (at times t1 and t3) and the current value when the semiconductor switching element 15 is turned off (at times t2 and t4) can both be set to zero. Therefore, surges caused by the switching of the semiconductor switching element 15 can be suppressed. Note that the switching timing is determined by the inductor current I L Even if the current is slightly deviated from the zero point, the surge can be suppressed because the current value is small.

[0039] Furthermore, the circuit configuration is similar to that of a conventional step-down chopper circuit, and no additional circuitry is required for surge suppression. The control method for the semiconductor switching element 15 is pulse density modulation. In this case, the on-pulse width t0 is a fixed value that can be determined only from the circuit parameters, making design easy.

[0040] In the configuration of the power converter 10 in Fig. 1(A), the diode 18 is not necessarily required. In the control method of the conventional step-down chopper circuit, when the semiconductor switching element 15 is turned off, the inductor current I flows in the normal direction through the inductor 17, the output capacitor 19, and the diode 18. L In contrast, in the case of the power converter 10 according to the first embodiment, when the semiconductor switching element 15 is turned off, the inductor current I L is already zero. Therefore, the inductor current I L There is no need to provide a diode 18 to allow the current to flow.

[0041] <Embodiment 2> In the second embodiment, a configuration example and operation of a power packet transmission system using a pulse transmission method will be described. As in the first embodiment, a feature is that a power packet transmission method capable of suppressing surges is realized without providing an additional circuit for suppressing surges. Below, first, the configuration of the power packet transmission system using a pulse transmission method will be described, and then the power packet transmission method characteristic of this embodiment will be described.

[0042] [Overall configuration of the power packet transmission system] Fig. 3 is a conceptual diagram showing the overall configuration of a power packet transmission system. Referring to Fig. 3, a power packet transmission network 50 includes a number of power packet routers (hereinafter simply referred to as "routers") 51 that generate and transfer power packets 53, which are transmission units, and wiring 52 that connects the routers. As shown in Fig. 3, the many routers 51 are connected in a network form via the wiring 52. The power packets 53 can be transmitted in both directions on the wiring.

[0043] Some of the routers constituting the power packet transmission network 50 are directly connected to one or more DC power sources 54, one or more power storage devices 55, one or more motors 56, or one or more loads 57 outside the network. In this way, the power packet transmission network 50 exchanges power with external devices.

[0044] Fig. 4 is a diagram showing the configuration of a power packet. As shown in Fig. 4, a power packet 53 has a header 61 and a footer 63 for transmitting information, and a payload 62 for transmitting power. In the case of Fig. 4, binary digital information is transmitted as the header 61 and the footer 63. In the power packet transmission network 50, by transmitting this power packet 53 using a time division multiplexing method, it is possible to transmit power of different voltages in addition to information via the same wiring 52.

[0045] In order to synchronize the operation timing between routers that transmit and receive power packets, a synchronization clock pulse may be transmitted as a preamble before the header 61. Alternatively, a clock signal may be transmitted from the transmitting router 51 to the receiving router 51 using a clock signal line provided in parallel with the wiring 52. The transmitting router 51 and the receiving router 51 open and close their switches in synchronization with the rising edge of a common clock signal.

[0046] Alternatively, the built-in clocks of the routers 51 constituting the power packet transmission network 50 may be synchronized in advance with a common clock signal. For this purpose, the clock may be distributed using optical fiber, or a positioning satellite signal may be used.

[0047] [Outline of the pulse transmission router] Figure 5 is a diagram for explaining the configuration of a pulse transmission type router. Figure 5(A) shows a schematic configuration diagram of a router 51, Figure 5(B) shows an example configuration of a bidirectional switch 72 in Figure 5(A), and Figure 5(C) shows an example configuration of a signal circuit 76 in Figure 5(A).

[0048] 5A, the router 51 includes a plurality of power storage elements 73, a plurality of bidirectional switches 72, a plurality of input / output nodes 70, signal circuits 76a and 76b, a controller 74, and a gate driver 75.

[0049] In the case of a general pulse transmission system, the power storage element 73 may be a capacitor such as an electric double layer capacitor, or may be a storage battery. However, in the case of this embodiment, the power storage element 73 is limited to a capacitor. Although two power storage elements 73 are shown in Fig. 5(A), three or more power storage elements 73 may be provided, or only one power storage element 73 may be provided.

[0050] The input / output nodes 70 are provided corresponding to the wiring 52 connected to the router 51, and are connected to the corresponding wiring. In the case of Fig. 5(A), input / output nodes 70a to 70d are provided corresponding to the wirings 52a to 52d, respectively. In the case of Fig. 5(A), the wiring 52 is configured as an unbalanced circuit together with the ground wiring 59. Note that the router 51 may be configured to be connected to any number of wirings 52, as long as the number is two or more.

[0051] Bidirectional switches 72 are provided between positive electrode node 71 of each storage element 73 and each input / output node 70. In the case of Fig. 5(A), positive electrode node 71a of storage element 73a is connected to input / output nodes 70a to 70d via bidirectional switches 72a, 72c, 72e, and 72f, respectively. Positive electrode node 71b of storage element 73b is connected to input / output nodes 70a to 70d via bidirectional switches 72b, 72d, 72g, and 72h, respectively.

[0052] 5B shows an example of a bidirectional switch 72 configured with NMOSFETs. The bidirectional switch 72 includes two NMOSFETs 81X and 81Y connected in series in opposite directions, and diodes 82X and 82Y connected in parallel to each of the two NMOSFETs 81X and 81Y so that the source-to-drain direction is the forward direction. In the case of NMOSFETs, each of the diodes 82X and 82Y may be a parasitic diode of the corresponding NMOSFET. This type of connection is also referred to as a back-to-back connection.

[0053] To turn on the bidirectional switch 72, an H-level signal is input to the gates of both NMOSFETs 81X and 81Y. To turn off the bidirectional switch 72, an L-level signal is input to the gates of both NMOSFETs 81X and 81Y.

[0054] In FIG. 5B, the sources of NMOSFETs 81X and 81Y are coupled together, but the drains may also be coupled together. Instead of NMOSFETs, semiconductor switching elements of other types or conductivity types may be used. In either case, two semiconductor switching elements of the same type are connected in series in opposite directions. Furthermore, a diode is connected in antiparallel to the corresponding semiconductor switching element.

[0055] The signal circuits 76a and 76b (collectively referred to as the signal circuit 76) are circuits for transmitting and receiving the header 61 and footer 63 of a power packet 53 to the corresponding power packet 53. As shown in FIG. 5C , the signal circuit 76 includes NMOSFETs 84 and 86 as semiconductor switching elements, a resistor 88, a DC power supply 89, diodes 90 and 91, a connection node 83, and an isolator 92. The connection node 83 is coupled to the corresponding wiring 52. The NMOSFETs 84 and 86 have parasitic diodes 85 and 87, respectively. The resistor 88 is provided to protect the NMOSFET 86. If the NMOSFET 86 has a sufficient withstand voltage and current rating, the resistor 88 and the diode 91 may be omitted.

[0056] The connections of the components constituting the signal circuit 76 will now be described. The diode 90, the NMOSFET 84, and the DC power supply 89 are connected in series, in this order, between the connection node 83 and the GND node. The cathode of the diode 90 is connected to the connection node 83, and the anode of the diode 90 is connected to the source S of the NMOSFET 84. The positive electrode of the DC power supply 89 is connected to the drain D of the NMOSFET 84, and the negative electrode of the DC power supply 89 is connected to the GND node. A resistor 88 and an NMOSFET 86 are further connected in series, in this order, between the connection node 83 and the GND node, in parallel with the series connection. The drain D of the NMOSFET 86 is connected to one end of the resistor 88, and the source of the NMOSFET 86 is connected to the GND node. The anode of the diode 91 is connected to the source of the NMOSFET 84, and the cathode of the diode 91 is connected to the drain of the NMOSFET 86.

[0057] The operation of the signal circuit 76 configured as described above will now be described. When transmitting the header 61 and footer 63 of the power packet 53, a binary digital signal is generated by complementarily turning on and off the NMOSFETs 84 and 86 in accordance with instructions from the controller 74. When receiving the header 61 and footer 63 of the power packet 53, both the NMOSFETs 84 and 86 are controlled to the off state. The controller 74 receives the digital signal via the isolator 92.

[0058] As described above, the controller 74 controls the transmission and reception of the header 61 and the footer 63 via the signal circuit 76. Furthermore, when transmitting and receiving power, which is the payload 62 of the power packet 53, the controller 74 outputs a control signal for controlling the on / off of the bidirectional switch 72 via the gate driver 75. At this time, the controller 74 turns on and off the bidirectional switch 72 connected to the wiring 52 between the router to which the power packet 53 is addressed and its own router, based on the information in the header 61.

[0059] The controller 74 may be configured based on a microcomputer including a CPU and memory, may be configured by an FPGA, may be configured by a dedicated circuit such as an ASIC, or may be configured by a combination of two or more of the above.

[0060] [Method of transmitting power packets between two routers] Fig. 6 is a diagram for conceptually explaining a method for transmitting a power packet between two routers. Figs. 6(A) to 6(C) show routers 51P and 51Q and a wiring 52 connecting the routers 51P and 51Q. As a configuration of the router 51P, a bidirectional switch 72P and a power storage element 73P connected to the wiring 52 are shown, and as a configuration of the router 51Q, a bidirectional switch 72Q and a power storage element 73Q connected to the wiring 52 are shown. As shown in Fig. 6(A), in the initial state, both the bidirectional switches 72P and 72Q are in the off state. Below, a procedure for transferring a power packet 53 from the router 51Q to the router 51P will be described.

[0061] First, as shown in Fig. 6(B), the controller 74 of the router 51Q generates information for the header 61 using the signal circuit 76Q and outputs it to the wiring 52. The output header information is transmitted to the router 51P via the wiring 52. The controller 74 of the router 51P reads the information for the header 61 of the transmitted power packet 53 via the isolator 92 of the signal circuit 76P.

[0062] 6(C), the routers 51Q and 51P drive the corresponding bidirectional switches 72Q and 72P to the on state (closed state), respectively, based on the information in the header 61 of the power packet 53. As a result, the power of the payload 62 is transmitted from the power storage element 73Q of the router 51Q to the power storage element 73P of the router 51P and stored in the power storage element 73P of the router 51P.

[0063] The output control methods for the power packet transmission network include pulse density modulation (PDM), which controls the transmission density of power packets, and pulse width modulation (PWM), which adjusts the length of the payload of the power packet. In the present embodiment, the PDM method is used. Therefore, when a time corresponding to the set pulse width has elapsed, the controller 74 of the router 51Q drives the bidirectional switch 72Q to the off state, and the controller 74 of the router 51P drives the bidirectional switch 72P to the off state. Details of the timing control of opening and closing the bidirectional switches 72P and 72Q will be described later with reference to FIGS. 7 and 8.

[0064] 6(B), the controller 74 of the router 51Q generates information for the footer 63 using the signal circuit 76Q and outputs it to the wiring 52. The output footer information is transmitted to the router 51P via the wiring 52. The controller 74 of the router 51P reads the information in the footer 63 of the transmitted power packet 53 via the isolator 92 of the signal circuit 76P. The power packet 53 is transferred through the above series of operations.

[0065] Next, the timing of opening and closing the corresponding bidirectional switch 72 when transferring the power that is the payload of the power packet 53 will be described in more detail.

[0066] Figure 7 is a circuit diagram showing the configuration of two routers connected via wiring. In Figure 7, the bidirectional switch 72P of the router 51P and the bidirectional switch 72Q of the router 51Q in Figure 6(A) are replaced with the two NMOSFETs described in Figure 5(B). Furthermore, the signal circuit 76P of the router 51P and the signal circuit 76Q of the router 51Q are replaced with the circuits described in Figure 5(C).

[0067] Furthermore, the wiring 52 is modeled using an inductor 95. Considering that the power packet transmission network 50 is applicable to electric vehicles, in-home wiring, microgrids, etc., the length of the wiring can be estimated to be at most 10+ meters. Furthermore, considering that SiC MOSFETs rated at about 1200 V are used in these applications, the power transmission time is about 1.0 μs. The wavelength of a sine wave with a period of 1.0 μs is about 300 m. Therefore, since a wiring length of at most 10+ meters is about 1 / 30 of the wavelength, no significant error will occur even if the wiring is modeled using an inductor.

[0068] Here, when transferring power, which is the payload of the power packet 53, the bidirectional switches 72P and 72Q are controlled to an ON state. Furthermore, the NMOSFETs 84P and 86P constituting the signal circuit 76P and the NMOSFETs 84Q and 86Q constituting the signal circuit 76Q are both controlled to an OFF state. In this case, a series resonant circuit 96 is formed by a combined resistance R obtained by combining the ON resistance of the bidirectional switches 72P and 72Q, the parasitic resistance of the wiring 52, and the parasitic resistance of the power storage elements (capacitors) 73P and 73Q, an inductance L of the wiring 52 (inductor 95), and capacitances C1 and C2 of the power storage elements (capacitors) 73P and 73Q. Specifically, the attenuation ratio ζ is expressed by the following equation (4A), and the time t0 until the first current zero crossing occurs in the case of underdamping (0<ζ<1) is expressed by the following equation (4B):

[0069]

number

[0070] As with a power converter, current continues to flow during overdamping and critical damping, whereas underdamping causes power to shuttle between the two storage elements (capacitors) 73P and 73Q. Therefore, surges can be suppressed by switching the bidirectional switches 72P and 72Q to their off states at the point in time t0, when the current first reaches zero after the bidirectional switches 72P and 72Q are switched on. As shown in equation (4B) above, the time t0 until the current zero crossing is determined solely by the circuit constants of the series resonant circuit 96 and is a fixed value independent of the DC power transfer voltage and current during transfer of the power packet. Because the power pulse width is thus fixed, the power transfer method is PDM control. Below, with reference to Figure 8, the voltage and current waveforms of each part of the router during power transfer between two routers are described in more detail.

[0071] Figure 8 is a diagram for explaining the voltage and current waveforms of each part when power is transmitted between two routers. Figure 8(A) shows a simplified circuit diagram of Figure 7, and Figure 8(B) conceptually shows the voltage and current waveforms of each part in Figure 8(A). Figure 8 focuses only on the power, which is the payload 62 of the power packet 53, and does not take into account the header 61 and footer 63.

[0072] In Fig. 8(A), a DC power supply 54 is connected to one end (opposite the wiring 52) of a bidirectional switch 72P of a router 51P instead of a storage element (capacitor) 73P. A load 57 is also connected to one end (opposite the wiring 52) of a bidirectional switch 72Q of a router 51Q. Since this is necessary to set connection nodes 83P and 83Q to the reference potential, only NMOSFETs 86P and 86Q are considered as signal circuits 76P and 76Q. The circuit configuration of Fig. 8(A) is similar to that of a bidirectional non-inverting buck-boost converter.

[0073] In FIG. 8B, the control signal u input to the bidirectional switch 72P of the router 51P is H1 , the control signal u input to the gate of the NMOSFET 86P of the signal circuit 76P of the router 51P. L1, the control signal u input to the bidirectional switch 72Q of the router 51Q. H2 , a control signal u input to the gate of an NMOSFET 86Q of a signal circuit 76Q of a router 51Q. L2 , the current I flowing through the wiring 52 (inductor 95) L , the waveforms of the voltage Vs at the connection node 83P, the voltage Vr at the connection node 83Q, and the output voltage Vout are shown.

[0074] At time t20 in FIG. 8(B), the controller 74P of the router 51P applies a high-level control signal u to the control electrode of the semiconductor switching element that constitutes the bidirectional switch 72P. H1 Furthermore, the controller 74P of the router 51P applies a low-level control signal u to the gate electrode of the NMOSFET 86P that constitutes the signal circuit 76P. L1 By inputting GND, the NMOSFET 86P is switched to the off state.

[0075] At time t20, in synchronization with the switching timing of each switch of the router 51P, the controller 74Q of the router 51Q transmits a control signal u of H level to the control electrode of the semiconductor switching element constituting the bidirectional switch 72Q. H2 Furthermore, the controller 74Q of the router 51Q applies a low-level control signal u to the gate electrode of an NMOSFET 86Q that constitutes a signal circuit 76Q. L2 By inputting GND, the NMOSFET 86Q is switched to the off state.

[0076] By switching the switches, a current flows from the DC power supply 54 through the bidirectional switch 72P, the wiring 52 (inductor 95), and the bidirectional switch 72Q in this order to the storage element 73Q and the load 57. As a result, the current I Lbegins to increase from 0, charging of the storage element 73Q begins, and the output voltage Vout increases over time. The voltage Vs at the connection node 83P is equal to the value obtained by subtracting the voltage drop due to the on-resistance of the bidirectional switch 72P from the input voltage Vin. The voltage Vr at the connection node 83P is equal to the value obtained by adding the voltage drop due to the on-resistance of the bidirectional switch 72Q to the output voltage Vout.

[0077] As described above, the current path forms a series resonant circuit consisting of the on-resistance R1 of the bidirectional switch 72P, the inductance L of the inductor 95, the on-resistance R2 of the bidirectional switch 72Q, and the capacitance C1 of the storage element (capacitor) 73Q. The circuit parameters are adjusted in advance so that the current characteristics of this series resonant circuit are underdamped.

[0078] At time t21, when the time t0 from time t20 to the first occurrence of the current zero crossing has elapsed, the controller 74P of the router 51P outputs the control signal u H1 is switched to the L level to turn off the bidirectional switch 72P, and the control signal u L1 By switching to the H level, the NMOSFET 86P is turned on.

[0079] Furthermore, at time t21, in accordance with the switching timing of each switch of the router 51P, the controller 74Q of the router 51Q outputs the control signal u H2 is switched to the L level to turn off the bidirectional switch 72P, and the control signal u L2 By switching the switch to the H level, the NMOSFET 86P is turned on. By switching the switch at a timing when the current is zero in this way, surges can be suppressed.

[0080] After time t21, the inductor current I Lbecomes almost zero. As the voltage of the storage element (capacitor) 73Q is consumed by the load 57, the output voltage Vout gradually decreases. The timing t22 at which the bidirectional switches 72P and 72Q are next switched to the conductive state is determined based on the transmission density of the power packets to be transmitted. In other words, the output control of the power packets is performed by PDM.

[0081] [Power packet transmission method when many routers are connected] Even when three or more routers are connected simultaneously, by reducing the capacitance of the storage element (capacitor) to a certain extent, a time when the current becomes zero occurs, just as in the case of underdamping. However, this timing depends not only on the circuit parameters but also on the power supply voltage and the voltage of the storage element. This makes it difficult to control the switching timing, and it is also difficult to control the transmission density of power packets using PDM.

[0082] Therefore, when transferring power packets between three or more routers, each router is connected to only one other router. In other words, the power packets are transmitted one stage at a time, like a bucket brigade system. This will be explained in detail below with reference to the drawings.

[0083] 9 is a diagram for explaining a method of transmitting power among a number of routers constituting a power packet transmission network. In Fig. 9, a power packet 53 is transferred from a router 51a connected to a DC power supply 54 to a router 51d connected to a load 57 via routers 51b and 51c in this order.

[0084] First, the bidirectional switches 72 of the routers 51a and 51b connected to the wiring 52a are switched on, thereby transferring the power packet 53 from the router 51a to the router 51b. The bidirectional switches 72 of the routers 51a and 51b are switched off at the timing of the first current zero crossing point. The on-time Ta of the bidirectional switches 72 is determined only by circuit parameters such as the inductance of the wiring 52a and the capacitance of the storage elements 73 of the routers 51a and 51b.

[0085] Next, the bidirectional switches 72 of the routers 51b and 51c connected to the wiring 52b are switched on, thereby transferring the power packet 53 from the router 51b to the router 51c. The bidirectional switches 72 of the routers 51b and 51c are switched off at the timing of the first current zero crossing point. The on-time Tb of the bidirectional switch 72 is determined by circuit parameters such as the inductance of the wiring 52b and the capacitance of the storage elements 73 of the routers 51b and 51c, and is a value different from the on-time Ta.

[0086] Next, the bidirectional switches 72 of the routers 51c and 51d connected to the wiring 52c are switched to the ON state, thereby transferring the power packet 53 from the router 51c to the router 51d. The bidirectional switches 72 of the routers 51c and 51d are switched to the OFF state at the timing of the first current zero crossing point. The ON time Tc of the bidirectional switch 72 is determined by circuit parameters such as the inductance of the wiring 52c and the capacitance of the storage elements 73 of the routers 51c and 51d, and is a value different from the ON times Ta and Tb.

[0087] At approximately the same time as this transfer, the bidirectional switches 72 of the routers 51a and 51b connected to the wiring 52a may be switched on to transfer the next power packet 53 from the router 51a to the router 51b. By performing similar control thereafter, the power packets 53 can be sequentially transferred from the router 51a to the router 51d at the desired transmission density.

[0088] [Method for identifying on-time] As described above, the on-time (t0, Ta to Tc) of the bidirectional switch 72 is determined only by the circuit parameters. Therefore, the on-time can be easily identified by calculation using the design value or the measured value of each circuit parameter. Once the on-time value is identified, it can be stored in the memory of the controller 74, which makes it easy to control the transmission density of power packets using PDM.

[0089] Alternatively, the on-time (t0, Ta to Tc) of the bidirectional switch 72 may be identified from the time it takes for the magnitude of the current to drop below a threshold value by actually measuring the current flowing through the wiring 52. Alternatively, the controller 74 may control the bidirectional switch 72 so as to switch the bidirectional switch 72 to the off state when the magnitude of the current drops below a threshold value.

[0090] Furthermore, as another method for identifying the on-time, the on-time (t0, Ta to Tc) can be estimated from changes in the output voltage due to PWM control. FIG. 10 is a diagram illustrating an example of a method for identifying the on-time of a bidirectional switch. FIG. 10 shows actual measurements of the output voltage Vout when the duty ratio is changed with a fixed PWM period. The PWM period is fixed at 100 μs. The horizontal axis of FIG. 10 represents the pulse width of the PWM signal (i.e., the on-time). As shown in FIG. 10, as the pulse width of the PWM signal (i.e., the on-time) increases, the value of the output voltage Vout increases and decreases. In this case, the pulse width of the PWM signal when the output voltage Vout first reaches its peak value corresponds to the on-time (t0, Ta to Tc) described above.

[0091] [Effects of the second embodiment] As described above, with the power pulse transmission system of the second embodiment, the wiring is treated as an inductor, and the capacitance of the capacitor serving as the storage element 73 is adjusted to satisfy the underdamping condition, thereby enabling the bidirectional switch 72 to be turned off when the current is zero. This significantly reduces surges. Because the duration of the payload is a fixed value determined solely by the circuit parameters, power pulse output control is limited to the PDM method, but the control method and circuit design are easy.

[0092] <Third Embodiment> In the third embodiment, a method will be described in which, of two routers 51 that transmit and receive power packets to and from each other, the turn-off timing of one bidirectional switch 72 that is desired to suppress a surge is delayed compared to the turn-off timing of the other bidirectional switch 72. This will be specifically described below with reference to the drawings.

[0093] Fig. 11 is a diagram for explaining the power transmission method according to the embodiment 3. Fig. 11 shows a procedure for transmitting power, which is the payload 62 of the power packet 53.

[0094] 11(A), the controller 74 of the router 51Q turns on the bidirectional switch 72Q, and the controller 74 of the router 51P turns on the bidirectional switch 72P. As a result, power, which is the payload 62 of the power packet 53, is transmitted from the power storage element 73Q of the router 51Q to the power storage element 73P of the router 51P based on the voltage difference between the power storage elements 73Q and 73P.

[0095] 11(B), the controller 74 of one router 51Q switches off the bidirectional switch 72Q at a timing according to PWM or PDM control, etc. As a result, a surge occurs in the bidirectional switch 72Q, but the current flowing through the wiring 52 and the bidirectional switch 72P of the other router 51P decreases.

[0096] 11(C), the controller 74 of the other router 51P switches off the bidirectional switch 72P. At this point, the current flowing through the bidirectional switch 72P is small, so even if a surge occurs in the bidirectional switch 72P, it can be suppressed more effectively than the surge that occurs when the bidirectional switch 72Q is turned off.

[0097] In the above, the bidirectional switch 72Q of the power transmitting side router 51Q is turned off first, but conversely, the bidirectional switch 72P of the power receiving side router 51P may be turned off first. In this case, it is possible to suppress a surge in the bidirectional switch 72Q of the power transmitting side router 51Q, which is turned off later.

[0098] [Effects of the Third Embodiment] As described above, according to the power packet transmission system of the third embodiment, it is possible to suppress a surge in the bidirectional switch 72 of the router that has a later turn-off timing between the router on the power transmitting side and the router on the power receiving side of the power packet. For example, since the impact of a surge occurring in a router connected to a load is large, it is desirable to delay the turn-off timing of the bidirectional switch 72 provided in the router connected to the load.

[0099] Furthermore, the surge suppression method of the third embodiment can be applied to a wider range of conditions than the surge suppression method of the second embodiment. For example, the third embodiment can be applied not only to underdamped cases but also to overdamped cases, and the storage element can be a storage battery instead of a capacitor. The surge suppression method of the third embodiment can also be combined with the surge suppression method of the second embodiment, thereby further increasing the surge suppression effect.

[0100] <Fourth Embodiment> In the fourth embodiment, a description will be given of the surge suppression method in the second embodiment, the surge suppression method in the third embodiment, and the results of simulations of a combination of these.

[0101] FIG. 12 is a circuit diagram showing a simulation model. As shown in FIG. 12(A), three routers 51P, 51Q, and 51R are connected in series. The signal circuit 76 of each router 51 is simply modeled using a resistor and a diode. Back-to-back connected MOSFETs are used as the bidirectional switches 72P, 72Q1, 72Q2, and 72R. A DC power supply 54 is connected to the positive node of a storage element (capacitor) 73Q of the router 51P on the left side of the drawing via a diode D1. A load 57 is connected to the positive node of a storage element (capacitor) 73R of the router 51R on the right side of the drawing. FIG. 12(B) is a model circuit diagram of the load 57.

[0102] In the simulation, the IRFH5015 was used as the MOSFET element model, and the uf4002 was used as the diode element model. The switching period was set to 200 μs, the capacitance of the capacitors serving as the storage elements 73P, 73Q, and 73R was set to 40 μF, and the inductances L1 and L2 of the inductors modeling the wiring 52P and 52Q were set to 1 μH. The voltage of the DC power supply 54 was set to 24 V, and the load resistor R5 was set to 33 Ω. Other settings were set to 1 kΩ for resistors R1 to R4, 1 mH for inductor L3, and 1 mF for capacitor C1.

[0103] In the simulation, the voltage Vs on the power transmission side (the side of the router 51Q) of the wiring 52Q, the voltage Vr on the power receiving side (the side of the router 51R) of the wiring 52Q, and the current I flowing through the inductor L2 that models the wiring 52Q are L The simulation results will be described below with reference to FIGS. 13 to 16. In the graphs, the voltage Vs is represented by a dashed line, the voltage Vr is represented by a solid line, and the current I L is represented by a solid line.

[0104] 13 shows voltage and current waveforms when none of the surge suppression methods described in the second and third embodiments is used. Three routers 51P, 51Q, and 51R are connected and disconnected simultaneously. It can be seen that a surge voltage and surge current are generated when the bidirectional switch 72 is turned off. A surge voltage of 34V is generated compared to a power supply voltage of 24V, which poses a risk of element destruction.

[0105] 14 is a diagram showing voltage and current waveforms when using the surge suppression method described in embodiment 2. When router 51Q and router 51R are connected, each bidirectional switch 72 is controlled so that router 51P and router 51Q are not connected. As shown in FIG. 14, surges are suppressed in both voltage and current.

[0106] FIG. 15 shows voltage and current waveforms when the surge suppression method described in the third embodiment is used. The bidirectional switch 72Q2 of the power transmitting router 51Q is turned off first, and then the bidirectional switch 72R of the power receiving router 51R is turned off. A large surge is observed in the power transmitting voltage Vs, but the surge in the power receiving voltage Vr is suppressed. Also, the current I L Surges are also observed.

[0107] 16 is a diagram showing voltage and current waveforms when using both the surge suppression methods described in Embodiments 2 and 3. Although a slight surge is observed in the voltage Vs on the power transmission side, it can be seen that surges are almost completely suppressed in both voltage and current.

[0108] As described above, the effects of the second and third embodiments were verified by simulation.

[0109] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of this application is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0110] 10 Power converter, 11N, 11P Input node, 12N, 12P Output node, 13 Reference node, 14, 83 Connection node, 15 Semiconductor switching element, 16, 18, 82, 90, 91 Diode, 17, 95 Inductor, 19 Output capacitor, 20 Control unit (controller), 21, 54, 89 DC power supply, 22, 57 Load, 50 Power packet transmission network, 51 Router, 52 Wiring, 53 Power packet, 55 Power storage device, 56 Motor, 59 Ground wiring, 61 Header, 62 Payload, 63 Footer, 70 Input / output node, 71 Positive side node, 72 Bidirectional switch, 73 Power storage element, 74 Controller, 75 Gate driver, 76 Signal circuit, 81, 84, 86 MOSFET, 85, 87 Parasitic diode, 88 Resistor element, 92 Isolator, 96 Series resonant circuit.

Claims

1. A power packet transmission system for transmitting a power packet that combines pulsed DC power and information about the DC power, A plurality of routers connected in a network via a plurality of wires are provided, Each of the plurality of routers a capacitor for storing the DC power; A plurality of two-way switches; a controller for controlling opening and closing of the plurality of bidirectional switches; each of the plurality of bidirectional switches is connected between a high potential side node of the capacitor and a corresponding wiring among the plurality of wirings; the plurality of routers include a first router and a second router connected to each other via a first wiring; the first router includes a first capacitor and a first bidirectional switch connected between a high-potential node of the first capacitor and a first end of the first wiring; the second router includes a second capacitor and a second bidirectional switch connected between a high-potential node of the second capacitor and a second end of the first wiring; when the first bidirectional switch and the second bidirectional switch are both in a closed state, the first bidirectional switch, the second bidirectional switch, the first capacitor, the second capacitor, and the first wiring form a series resonant circuit having an underdamping characteristic; When transmitting a power packet from the first router to the second router, the controller of the first router and the controller of the second router start to flow a current through the first wiring by switching the first bidirectional switch and the second bidirectional switch from an open state to a closed state, and switch at least one of the first bidirectional switch and the second bidirectional switch from a closed state to an open state in synchronization with the timing at which the current flowing through the first wiring first crosses zero; A power packet transmission system, wherein the time from when current starts to flow through the first wiring until the first zero crossing is a constant determined solely by circuit parameters of the series resonant circuit.

2. The power packet transmission system of claim 1 , wherein the first bidirectional switch and the second bidirectional switch are simultaneously switched to a closed state and then simultaneously switched to an open state.

3. 2. The power packet transmission system of claim 1, wherein the first bidirectional switch and the second bidirectional switch are switched to a closed state simultaneously, and then one of the switches is switched to an open state before the other is switched to an open state.

4. The power packet transmission system according to any one of claims 1 to 3, wherein the controller of the first router and the controller of the second router control the timing of switching the first bidirectional switch and the second bidirectional switch from an open state to a closed state when transmitting a power packet from the first router to the second router so that the transmission density of the power packet becomes a desired value.

5. the second router includes a third bidirectional switch connected to a first end of the second wiring; the plurality of routers includes a third router including a fourth bidirectional switch connected to a second end of the second wiring; The power packet transmission system according to any one of claims 1 to 4, wherein the controller of the second router switches the second bidirectional switch to an open state and then switches the third bidirectional switch to a closed state when transmitting the power packet received from the first router to the third router.

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