Semiconductor device

Abstract

To suppress increase of a space of wiring.SOLUTION: A semiconductor device 10 comprises: a substrate 20 that includes a first substrate surface 20S and a second substrate surface being at an opposite side of the first substrate surface 20S; a first wiring pattern 31 that is provided on the first substrate surface 20S; and a sensor chip 50 that is used to detect current which flows in the first wiring pattern 31. The first wiring pattern 31 includes a detection pattern 43 having predetermined width. The sensor chip 50 is implemented in the first substrate surface 20S in a state arranged to stride the detection pattern 43. The sensor chip 50 includes a first detection element 51 and a second detection element 52 as detection elements that detect a magnetic field generated by the current flowing in the detection pattern 43.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a magnetic field sensor that includes a first magnetic field detection unit and a second magnetic field detection unit and detects a magnetic field generated by a current flowing in a wiring of a printed circuit board. The wiring includes an outgoing path section, a return path section in which a current flows in the opposite direction to that of the outgoing path section, and a connecting section that connects the outgoing path section and the return path section. The magnetic field sensor is arranged so that the first magnetic field detection unit detects the magnetic field of the outgoing path section and the second magnetic field detection unit detects the magnetic field of the return path section. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-85711

[0004] [overview] The magnetic field sensor of Patent Document 1 requires a large space for the wiring because it is necessary to provide a forward path and a return path so that the current flows in opposite directions in order to detect the current in the wiring.

[0005] A semiconductor device according to one embodiment of the present disclosure includes a substrate including a first substrate surface and a second substrate surface opposite the first substrate surface, a wiring pattern including a first wiring pattern provided on the first substrate surface, and a sensor chip used to detect current flowing in the wiring pattern, wherein the first wiring pattern includes a detection pattern having a predetermined width, the sensor chip is mounted on the first substrate surface in a state in which it straddles the detection pattern, and the sensor chip includes a detection element that detects a magnetic field generated by the current flowing in the detection pattern. [Brief explanation of the drawings]

[0006] [Figure 1]FIG. 1 is a schematic perspective view of an exemplary semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic side view of the substrate of the semiconductor device of FIG. [Figure 3] FIG. 3 is a schematic side view of the substrate of the semiconductor device of FIG. 1, seen from a direction different from that of FIG. [Figure 4] FIG. 4 is a schematic plan view of a wiring pattern provided on the substrate of FIG. [Figure 5] FIG. 5 is an enlarged schematic plan view of the sensor chip and its periphery in the semiconductor device of FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of the semiconductor device taken along line F6-F6 in FIG. [Figure 7] FIG. 7 is an enlarged schematic cross-sectional view of the sensor chip of FIG. [Figure 8] FIG. 8 is a schematic circuit diagram showing the circuit configuration of the sensor chip of FIG. [Figure 9] FIG. 9 is a schematic circuit diagram showing the circuit configuration of an inverter device to which the semiconductor device of the first embodiment is applied. [Figure 10] FIG. 10 is a schematic plan view showing an enlarged view of the semiconductor device and its periphery in the inverter device of FIG. [Figure 11] FIG. 11 is a schematic plan view showing an enlarged view of the sensor chip and its periphery in an exemplary semiconductor device according to the second embodiment. [Figure 12] FIG. 12 is a schematic plan view showing an enlarged view of the sensor chip and its periphery in an exemplary semiconductor device according to the third embodiment. [Figure 13] FIG. 13 is a schematic cross-sectional view of the sensor chip taken along line F13-F13 in FIG. [Figure 14] FIG. 14 is a schematic perspective view of a semiconductor device according to a modified example. [Figure 15] FIG. 15 is a schematic side view of the substrate of the semiconductor device of FIG. [Figure 16] FIG. 16 is a schematic side view of the substrate of the semiconductor device of FIG. 14, seen from a direction different from that of FIG. [Figure 17] FIG. 17 is a schematic plan view of a wiring pattern in a semiconductor device according to a modified example. [Figure 18] FIG. 18 is a schematic plan view of a wiring pattern in a semiconductor device according to a modified example. [Figure 19] FIG. 19 is a schematic enlarged cross-sectional view of a sensor chip and its periphery in a semiconductor device according to a modified example. [Figure 20] FIG. 20 is an enlarged schematic plan view of a sensor chip and its periphery in a semiconductor device according to a modified example. [Figure 21] FIG. 21 is a schematic plan view of a semiconductor device according to a modified example. [Figure 22] FIG. 22 is a schematic plan view of a semiconductor device according to a modified example. [Figure 23] FIG. 23 is a schematic plan view of a sensor chip in a semiconductor device according to a modified example. [Figure 24] FIG. 24 is a schematic cross-sectional view of the sensor chip taken along line F24-F24 in FIG.

[0007] [Detailed explanation] Hereinafter, several embodiments of semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The phrase "at least one" used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] As used in this disclosure, "the dimensions (width, length) of A are equal to the dimensions (width, length) of B" or "the dimensions (width, length) of A and the dimensions (width, length) of B are equal to each other" also includes a relationship in which the difference between the dimensions (width, length) of A and the dimensions (width, length) of B is, for example, within 10% of the dimensions (width, length) of A.

[0011] First Embodiment [Overall configuration of semiconductor device] The configuration of a semiconductor device 10 according to a first embodiment will be described with reference to Figures 1 to 3. Figure 1 schematically shows a perspective view of the semiconductor device 10 according to the first embodiment. Figure 2 schematically shows a side view of a substrate 20 (described later) of the semiconductor device 10 shown in Figure 1. Figure 3 schematically shows the structure of the substrate 20 viewed from a different direction than that shown in Figure 2.

[0012] As shown in FIG. 1, the semiconductor device 10 includes a substrate 20, a wiring pattern 30 provided on the substrate 20, and a sensor chip 50 mounted on the substrate 20. The substrate 20 is made of an insulating material such as glass epoxy resin. The substrate 20 is flat with its thickness direction in the Z direction. The substrate 20 includes a first substrate surface 20S and a second substrate surface 20R opposite to the first substrate surface 20S. In the following description, "planar view" refers to viewing the semiconductor device 10 from the Z direction. Therefore, "planar view" has the same meaning as "viewed from the thickness direction of the substrate 20."

[0013] As shown in Figures 2 and 3, the substrate 20 is configured as a multi-layer substrate. In the example shown in Figures 2 and 3, the substrate 20 is a four-layer substrate. More specifically, the substrate 20 includes a first substrate 21, a second substrate 22, and a third substrate 23. The first substrate 21 includes a first substrate surface 20S. The second substrate 22 includes a second substrate surface 20R. The third substrate 23 is provided between the first substrate 21 and the second substrate 22 in the Z direction.

[0014] The wiring pattern 30 constitutes a part of the conductive layer of the multilayer substrate. More specifically, the wiring pattern 30 includes a first wiring pattern 31 provided on the first substrate surface 20S. In the first embodiment, the semiconductor device 10 further includes a first heat dissipation pattern 32 provided between the first substrate 21 and the third substrate 23, a second heat dissipation pattern 33 provided between the third substrate 23 and the second substrate 22, and a third heat dissipation pattern 34 provided on the second substrate 22. The first wiring pattern 31 can also be said to be provided on the first substrate surface 20S. The third heat dissipation pattern 34 can also be said to be provided on the second substrate surface 20R. Here, each of the first to third heat dissipation patterns 32 to 34 is an example of a "heat dissipation pattern." The detailed configurations of the first wiring pattern 31 and the first to third heat dissipation patterns 32 to 34 will be described later.

[0015] The first wiring pattern 31, the first heat dissipation pattern 32, the second heat dissipation pattern 33, and the third heat dissipation pattern 34 are made of a conductive material such as copper (Cu), aluminum (Al), titanium (Ti), or titanium nitride (TiN). In one example, the first wiring pattern 31, the first heat dissipation pattern 32, the second heat dissipation pattern 33, and the third heat dissipation pattern 34 are made of the same material. In the first embodiment, the first wiring pattern 31, the first heat dissipation pattern 32, the second heat dissipation pattern 33, and the third heat dissipation pattern 34 are made of a material containing Cu. Note that the first wiring pattern 31 and the first to third heat dissipation patterns 32 to 34 may be made of different materials.

[0016] 1, the sensor chip 50 is used to detect a current flowing through the wiring pattern 30 (first wiring pattern 31 in the first embodiment). The sensor chip 50 is mounted on the first substrate surface 20S of the substrate 20. More specifically, the sensor chip 50 is mounted on first to fourth sensor patterns 71 to 74 provided on the first substrate surface 20S. The detailed configurations of the sensor chip 50 and the first to fourth sensor patterns 71 to 74 will be described later.

[0017] [Wiring pattern configuration] The detailed configuration of the wiring pattern 30 will be described with reference to Figures 2 to 4. Figure 4 shows a schematic planar structure of the first wiring pattern 31.

[0018] 4, the first wiring pattern 31 includes a first pattern 41, a second pattern 42, and a detection pattern 43. The first pattern 41, the second pattern 42, and the detection pattern 43 are arranged side by side in the Y direction. The detection pattern 43 is arranged between the first pattern 41 and the second pattern 42 in the Y direction.

[0019] The first pattern 41 extends in the Y direction. The first pattern 41 has a first width W1, which is the length in the X direction. The first pattern 41 includes a first portion 41A and a second portion 41B. The first portion 41A and the second portion 41B are arranged side by side in the Y direction. Here, the Y direction is an example of the "first direction."

[0020] The first portion 41A is a portion of the first pattern 41 having a first width W1. In one example, the first portion 41A extends in the Y direction with a constant first width W1. The first portion 41A is disposed on the opposite side of the second portion 41B from the detection pattern 43 in the Y direction. The shape of the first portion 41A in a plan view can be changed arbitrarily. In one example, the first width W1 of the first portion 41A may be changed in the Y direction.

[0021] The second portion 41B is a portion that connects the first portion 41A and the detection pattern 43. The second portion 41B is provided so that its width narrows from the first portion 41A toward the detection pattern 43 in a plan view. In the example shown in Fig. 4, the second portion 41B has a tapered shape that gradually narrows from the first portion 41A toward the detection pattern 43 in a plan view.

[0022] The second pattern 42 is disposed apart from the first pattern 41 in the Y direction. The second pattern 42 extends in the Y direction. The second pattern 42 has a second width W2, which is the length in the X direction. The second pattern 42 includes a first portion 42A and a second portion 42B. The first portion 42A and the second portion 42B are disposed side by side in the Y direction.

[0023] The first portion 42A is a portion of the second pattern 42 having a second width W2. In one example, the first portion 42A extends in the Y direction with a constant second width W2. The first portion 42A is disposed on the opposite side of the second portion 42B from the detection pattern 43 in the Y direction. The shape of the first portion 42A in a plan view can be changed as desired. In one example, the second width W2 of the first portion 42A may be changed in the Y direction.

[0024] The second portion 42B is a portion that connects the first portion 42A and the detection pattern 43. The second portion 42B is provided so that its width narrows from the first portion 42A toward the detection pattern 43 in a plan view. In the example shown in Fig. 4, the second portion 42B has a tapered shape that gradually narrows from the first portion 42A toward the detection pattern 43 in a plan view.

[0025] 4, the second width W2 of the first portion 42A of the second pattern 42 is equal to the first width W1 of the first portion 41A of the first pattern 41. The taper angle of the second portion 42B of the second pattern 42 is equal to the taper angle of the second portion 41B of the first pattern 41. The length in the Y direction of the second portion 42B of the second pattern 42 is equal to the length in the Y direction of the second portion 41B of the first pattern 41.

[0026] The detection pattern 43 connects the first pattern 41 and the second pattern 42. The detection pattern 43 has a predetermined width. Here, the width of the detection pattern 43 is defined by the length of the detection pattern 43 in the X direction. The X direction can be considered an example of a "second direction." The X direction can also be considered an example of a "width direction of the detection pattern." The detection pattern 43 extends in the Y direction in a planar view. Therefore, the Y direction can be considered the "direction in which the detection pattern extends." The detection pattern 43 has a constant width throughout the entire Y direction. Hereinafter, the width of the detection pattern 43 may be referred to as the "connection width WC."

[0027] In one example, the connection width WC of the detection pattern 43 is narrower than the first width W1 of the first pattern 41 and the second width W2 of the second pattern 42. In one example, the connection width WC of the detection pattern 43 is 1 mm. The length LC of the detection pattern 43 in the Y direction is shorter than the length L1 of the first pattern 41 and the length L2 of the second pattern 42 in the Y direction. In one example, the length LC of the detection pattern 43 in the Y direction is shorter than the length of the second portion 41B of the first pattern 41 and the length of the second portion 42B of the second pattern 42 in the Y direction. In the example shown in FIG. 4, the length LC of the detection pattern 43 in the Y direction is 1 mm.

[0028] The first to third heat dissipation patterns 32 to 34 extend in the Y direction. In one example, the first to third heat dissipation patterns 32 to 34 have the same size and shape. As shown in FIG. 2, each of the first to third heat dissipation patterns 32 to 34 has a heat dissipation width WP that is larger than the first width W1 of the first pattern 41. Here, as described above, the first width W1 of the first pattern 41 is equal to the second width W2 of the second pattern 42, and therefore the heat dissipation width WP of the first to third heat dissipation patterns 32 to 34 is larger than the second width W2 of the second pattern 42.

[0029] [Sensor chip configuration] The detailed configuration of the sensor chip 50 will be described with reference to FIGS. Fig. 5 schematically shows a part of the planar structure of the semiconductor device 10 in a state where a sensor chip 50 is mounted on a substrate 20. Fig. 6 schematically shows a cross-sectional structure of the semiconductor device 10 taken along line F6-F6 in Fig. 5. Fig. 7 shows a detailed cross-sectional structure of the sensor chip 50 in Fig. 6. Fig. 8 schematically shows an example of the circuit configuration of the sensor chip 50.

[0030] 5, the sensor chip 50 is mounted on the first substrate surface 20S of the substrate 20 in a state in which it is disposed so as to straddle the detection pattern 43 of the wiring pattern 30. The sensor chip 50 has a rectangular shape having long and short sides in a plan view. The sensor chip 50 is disposed so that the long sides extend along the X direction and the short sides extend along the Y direction.

[0031] 5 and 6, the sensor chip 50 has a WLCSP (Wafer Level Chip Size Package) package structure. The sensor chip 50 includes a first chip surface 50S and a second chip surface 50R opposite to the first chip surface 50S. The second chip surface 50R faces the detection pattern 43. A plurality of terminals 61 to 64 (four in the first embodiment) are provided on the second chip surface 50R. The terminals 61 to 64 are formed, for example, by solder bumps.

[0032] The terminals 61 to 64 are arranged dispersedly at both ends of the sensor chip 50 in the X direction. The terminals 61 and 63 are arranged at one end of the sensor chip 50. The terminals 62 and 64 are arranged at the other end of the sensor chip 50. The terminal 61 is configured as, for example, a ground terminal. The terminal 62 is, for example, a REFOUT terminal used to set the output current of the sensor chip 50. The terminal 63 is configured as, for example, a power supply terminal. The terminal 64 is configured as, for example, a signal output terminal.

[0033] The terminals 61, 63 and the terminals 62, 64 are distributed and arranged on both sides of the detection pattern 43 in the X direction in a plan view. Meanwhile, in a plan view, the terminals 61 to 64 are arranged in a recess 44 defined by the second portion 41B of the first pattern 41, the detection pattern 43, and the second portion 42B of the second pattern 42. In other words, the terminals 61 to 64 are arranged in a space SP between the first portion 41A of the first pattern 41 and the first portion 42A of the second pattern 42 in the Y direction, and formed by the first portions 41A, 42A, the second portions 41B, 42B, and the detection pattern 43. In the first embodiment, the space SP has a trapezoidal shape with the detection pattern 43 as its upper base. Thus, the multiple terminals 61 to 64 are arranged inside the outer edges of the first pattern 41 and the second pattern 42. Here, the outer edges of the first pattern 41 are both edges of the first portion 41A of the first pattern 41 in the X direction. The outer edges of the second pattern 42 are both end edges of the first portion 42A of the second pattern 42 in the X direction.

[0034] The terminals 61 to 64 are individually connected to first to fourth sensor patterns 71 to 74 provided on the first substrate surface 20S. As shown in FIG. 6, both the top surface 71S of the first sensor pattern 71 and the top surface 72S of the second sensor pattern 72 are disposed closer to the first substrate surface 20S than the top surface 43S of the detection pattern 43. That is, the thickness TS of each of the first sensor pattern 71 and the second sensor pattern 72 is thinner than the thickness TC of the detection pattern 43. Although not shown, both the top surface 73S of the third sensor pattern 73 and the top surface 74S of the fourth sensor pattern 74 are also disposed closer to the first substrate surface 20S than the top surface 43S of the detection pattern 43. That is, the thickness of each of the third sensor pattern 73 and the fourth sensor pattern 74 is thinner than the thickness TC of the detection pattern 43. The thicknesses of the first to fourth sensor patterns 71 to 74 may be equal to each other.

[0035] When the sensor chip 50 is mounted on the first to fourth sensor patterns 71 to 74, a gap GP is provided between the sensor chip 50 and the detection pattern 43 in the Z direction. In other words, the sensor chip 50 is not in contact with the wiring pattern 30. Due to the relationship between the detection pattern 43 and the first to fourth sensor patterns 71 to 74 described above, the second chip surface 50R of the sensor chip 50 is close to the detection pattern 43 in the Z direction. In one example, the distance DA between the second chip surface 50R of the sensor chip 50 and the upper surface 43S of the detection pattern 43 in the Z direction is smaller than the thickness TC of the detection pattern 43. The distance DA can be changed arbitrarily. In one example, the distance DA may be equal to or greater than the thickness TC of the detection pattern 43. Alternatively, the sensor chip 50 may be in contact with the upper surface 43S of the detection pattern 43. In other words, the distance DA may be zero.

[0036] 5 to 7, the sensor chip 50 includes a first detection element 51 and a second detection element 52 that detect a magnetic field generated by a current flowing through the detection pattern 43. Here, both the first detection element 51 and the second detection element 52 are examples of a "detection element." The first detection element 51 and the second detection element 52 are, for example, Hall elements. Note that the first detection element 51 and the second detection element 52 are not limited to Hall elements, and a magnetic impedance element (MI element) or a magnetoresistive effect element (MR element) may also be used.

[0037] In a plan view, the first detection element 51 and the second detection element 52 are disposed at the same position in the Y direction and spaced apart from each other in the X direction. Therefore, the first detection element 51 and the second detection element 52 are disposed opposite each other in the X direction. In one example, the first detection element 51 and the second detection element 52 are disposed on both sides of the detection pattern 43 in the X direction in a plan view. In other words, the first detection element 51 is disposed closer to one side in the X direction than the center of the detection pattern 43 in the X direction in a plan view. The second detection element 52 is disposed closer to the other side in the X direction than the center of the detection pattern 43 in the X direction in a plan view. In one example, the first detection element 51 and the second detection element 52 are disposed at positions facing both edges of the detection pattern 43 in the X direction in the Z direction. In the first embodiment, the first detection element 51 is disposed so as to straddle one edge of the detection pattern 43 in the X direction in a plan view. The second detection element 52 is disposed so as to straddle the other edge of the detection pattern 43 in the X direction in a plan view.

[0038] As shown in FIG. 7, the sensor chip 50 includes a semiconductor substrate 55 and a semiconductor layer 56 provided on the semiconductor substrate 55. The semiconductor substrate 55 has a rectangular flat plate shape with its thickness direction aligned in the Z direction. The semiconductor substrate 55 includes, for example, a first chip surface 50S. The semiconductor substrate 55 is made of a material containing, for example, any one of indium antimony (InSb), indium arsenic (InAs), gallium arsenic (GaAs), and silicon (Si).

[0039] The semiconductor layer 56 is a layer in which, for example, a first detection element 51 and a second detection element 52 serving as Hall elements are provided. The semiconductor layer 56 is formed, for example, by epitaxial growth on a semiconductor substrate 55. An arithmetic circuit 80 is provided in the semiconductor layer 56. The arithmetic circuit 80 is electrically connected to both the first detection element 51 and the second detection element 52. In one example, the arithmetic circuit 80 is provided outward in the X direction from both the first detection element 51 and the second detection element 52. The position at which the arithmetic circuit 80 is provided can be changed as desired. The configuration of the arithmetic circuit 80 will be described later.

[0040] The semiconductor layer 56 is covered on the side opposite to the semiconductor substrate 55 in the Z direction with an insulating layer 57. The insulating layer 57 is made of at least one of silicon oxide (SiO2), silicon nitride (SiN), and a photosensitive resin material, for example. The insulating layer 57 can also be considered a protective layer for the sensor chip 50.

[0041] The sensor chip 50 is provided with wiring 58 that electrically connects the arithmetic circuit 80 and the terminals 61 to 64. The wiring 58 is provided inside the insulating layer 57. The wiring 58 is made of a conductive material such as Al, Cu, Ti, TiN, or W. The wiring 58 may be configured to electrically connect the arithmetic circuit 80 with the first detection element 51 and the second detection element 52.

[0042] [Circuit configuration of sensor chip] 8, the arithmetic circuit 80 of the sensor chip 50 is configured to output a signal corresponding to the output from the first detection element 51 and the second detection element 52. In one example, the arithmetic circuit 80 is configured to output a signal corresponding to the output voltage of the first detection element 51 (hereinafter referred to as the "first output voltage") and the output voltage of the second detection element 52 (hereinafter referred to as the "second output voltage"). In one example, the arithmetic circuit 80 includes a bias circuit 81, a subtraction circuit 82, an analog front end (hereinafter referred to as the "AFE 83"), and a signal processing circuit 84. Note that the configuration of the arithmetic circuit 80 can be changed as desired.

[0043] The bias circuit 81 is electrically connected to both the first detection element 51 and the second detection element 52, individually. The bias circuit 81 is electrically connected to a terminal 63 (see FIG. 5 ), which serves as a power supply terminal. The first output voltage and the second output voltage are individually input to the bias circuit 81. The bias circuit 81 is configured to suppress fluctuations in the output voltages due to, for example, power supply fluctuations and temperature fluctuations in the first output voltage and the second output voltage. The bias circuit 81 is configured to output the first output voltage and the second output voltage to a subtraction circuit 82.

[0044] The subtraction circuit 82 is electrically connected to the bias circuit 81. The subtraction circuit 82 generates an output signal from which the influence of a magnetic field external to the sensor chip 50 has been removed, based on the first output voltage and the second output voltage input from the bias circuit 81. In one example, the subtraction circuit 82 is configured to calculate the difference between the first output voltage and the second output voltage.

[0045] The AFE 83 electrically connects the subtraction circuit 82 and the signal processing circuit 84. The AFE 83 is configured to adjust, for example, an analog signal as an output signal output from the subtraction circuit 82. For this reason, the AFE 83 may be referred to as a signal adjustment circuit. The AFE 83 may be configured by an amplifier, a sample-and-hold (S / H) circuit, a filter, etc.

[0046] The signal processing circuit 84 is configured to convert an analog signal into a digital signal. The signal processing circuit 84 is electrically connected to the terminal 64 (see FIG. 7). The signal processing circuit 84 is configured to convert an output signal input from the AFE 83 into a digital signal and output the digital signal to the terminal 64.

[0047] In this way, in the sensor chip 50, the first detection element 51 and the second detection element 52 detect a magnetic field generated by a current flowing through the detection pattern 43. The arithmetic circuit 80 is configured to output a signal corresponding to the value of the current flowing through the detection pattern 43 (wiring pattern 30) based on the difference between the first output voltage and the second output voltage.

[0048] <Application examples of semiconductor devices> The semiconductor device 10 of the first embodiment may be applied to, for example, an inverter device 200 shown in Fig. 9. The schematic configuration of this inverter device 200 will be described.

[0049] As shown in Fig. 9, inverter device 200 is configured to control the currents supplied to, for example, a U-phase coil CU, a V-phase coil CV, and a W-phase coil CW of a three-phase brushless motor. Three-phase brushless motors are used in products requiring relatively large currents, such as air conditioners and home appliances. Here, a current of, for example, 10 A or more is supplied to the three-phase brushless motor. Depending on the product to which the three-phase brushless motor is applied, a current of, for example, 20 A or more may also be supplied to the three-phase brushless motor.

[0050] The inverter device 200 is configured to convert a DC current from a DC power supply 300 into a three-phase AC current. The inverter device 200 mainly includes a power supply unit 210, a main control unit 220, a gate drive circuit 230, a U-phase arm unit 240, a V-phase arm unit 250, a W-phase arm unit 260, a temperature sensor 270, and two semiconductor devices 10U and 10W.

[0051] The U-phase arm section 240 includes a pair of switching elements 241, 242 connected in series. The V-phase arm section 250 includes a pair of switching elements 251, 252 connected in series. The W-phase arm section 260 includes a pair of switching elements 261, 262 connected in series. These switching elements 241, 242, 251, 252, 261, 262 may be transistors such as SiMOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), or SiCMOSFETs.

[0052] The power supply unit 210 is electrically connected to the positive terminal of the DC power supply 300 and the main control unit 220. The power supply unit 210 is configured to convert the voltage from the DC power supply 300 into an operating voltage for the main control unit 220. The power supply unit 210 includes, for example, a DC / DC converter and a linear regulator (LDO: Low Dropout).

[0053] The main control unit 220 is configured to operate using an operating voltage input from the power supply unit 210. The main control unit 220 is electrically connected to the gate drive circuit 230, the temperature sensor 270, and the semiconductor devices 10U and 10W. The main control unit 220 is configured to control the gate drive circuit 230 based on, for example, information about the three-phase brushless motor and information about the U-phase arm unit 240, the V-phase arm unit 250, and the W-phase arm unit 260. Here, the information about the three-phase brushless motor includes, for example, the rotational position of the motor rotor. The information about the U-phase arm unit 240, the V-phase arm unit 250, and the W-phase arm unit 260 includes, for example, the temperature of at least one of the U-phase arm unit 240, the V-phase arm unit 250, and the W-phase arm unit 260, the amount of current supplied to the U-phase arm unit 240, and the amount of current supplied to the W-phase arm unit 260. The temperatures are acquired based on, for example, information detected by the temperature sensor 270. The amount of current supplied to the U-phase arm unit 240 is obtained based on, for example, detection information by the semiconductor device 10U. The amount of current supplied to the W-phase arm unit 260 is obtained based on, for example, detection information by the semiconductor device 10W. The temperature sensor 270 may be used to detect the ambient temperature of the inverter device 200.

[0054] The gate drive circuit 230 is electrically connected to the positive and negative electrodes of the DC power supply 300. The gate drive circuit 230 is electrically connected to the gates of the switching elements 241 and 242 of the U-phase arm section 240, the switching elements 251 and 252 of the V-phase arm section 250, and the switching elements 261 and 262 of the W-phase arm section 260. The gate drive circuit 230 is configured to generate gate drive signals based on control signals from the main control section 220, and then output the signals to the gates of the switching elements 241 and 242 of the U-phase arm section 240, the switching elements 251 and 252 of the V-phase arm section 250, and the switching elements 261 and 262 of the W-phase arm section 260.

[0055] The drain of switching element 241 of U-phase arm section 240, the drain of switching element 251 of V-phase arm section 250, and the drain of switching element 261 of W-phase arm section 260 are electrically connected to the positive electrode of DC power supply 300. The source of switching element 242 of U-phase arm section 240, the source of switching element 252 of V-phase arm section 250, and the source of switching element 262 of W-phase arm section 260 are electrically connected to the negative electrode of DC power supply 300.

[0056] A node N1 between the source of switching element 241 and the drain of switching element 242 of U-phase arm section 240 is electrically connected to U-phase coil CU. A node N2 between the source of switching element 251 and the drain of switching element 252 of V-phase arm section 250 is electrically connected to V-phase coil CV. A node N3 between the source of switching element 261 and the drain of switching element 262 of W-phase arm section 260 is electrically connected to W-phase coil CW.

[0057] Semiconductor device 10U is provided in a part of the U-phase current path between node N1 and U-phase coil CU. Semiconductor device 10U is provided to output to main control unit 220 information indicating the amount of current supplied to U-phase arm section 240, i.e., the amount of current flowing through the U-phase current path.

[0058] Semiconductor device 10W is provided in a part of the W-phase current path between node N3 and W-phase coil CW. Semiconductor device 10W is provided to output to main control unit 220 information indicating the amount of current supplied to W-phase arm section 260, i.e., the amount of current flowing through the W-phase current path.

[0059] In the inverter device 200 configured as described above, the on / off of the switching elements 241, 242, 251, 252, 261, and 262 is controlled by a predetermined energization method based on the gate drive signal of the gate drive circuit 230. Examples of the energization method include sine wave drive and square wave drive. Sine wave drive can improve the motor efficiency of the three-phase brushless motor. Square wave drive can reduce the switching loss of the switching elements 241, 242, 251, 252, 261, and 262.

[0060] [Partial wiring configuration of inverter device] FIG. 10 shows an example of a planar structure of the wiring configuration of the U-phase arm section 240, the V-phase arm section 250, and the W-phase arm section 260 of the inverter device 200. As shown in FIG.

[0061] 10, inverter device 200 includes a substrate 280, and U-phase wiring 281, V-phase wiring 282, and W-phase wiring 283 provided on substrate 280. Substrate 280 is made of, for example, glass epoxy resin.

[0062] The U-phase wiring 281 is connected to the sources and drains of the switching elements 241, 242 of the U-phase arm section 240. The U-phase wiring 281 includes a first wiring portion 281A, a second wiring portion 281B, and a third wiring portion 281C. The first wiring portion 281A configures a part of a current path that electrically connects the drain of the switching element 241 and the positive electrode of the DC power supply 300 (see FIG. 9). The second wiring portion 281B configures a current path that electrically connects the source of the switching element 241 and the drain of the switching element 242. The third wiring portion 281C configures a part of a current path that electrically connects the source of the switching element 242 and the negative electrode of the DC power supply 300.

[0063] The U-phase wiring 281 forms a node N1 (see FIG. 9) in the second wiring portion 281B, and also includes a fourth wiring portion 281D that forms part of a current path that electrically connects the node N1 and the coil CU (see FIG. 9). The fourth wiring portion 281D is connected to a land pattern 281E. A U-phase connecting terminal (not shown) is joined to the land pattern 281E by, for example, soldering.

[0064] The V-phase wiring 282 is connected to the sources and drains of the switching elements 251, 252 of the V-phase arm section 250. The V-phase wiring 282 includes a first wiring portion 282A, a second wiring portion 282B, and a third wiring portion 282C. The first wiring portion 282A constitutes a part of a current path that electrically connects the drain of the switching element 251 and the positive electrode of the DC power supply 300. The second wiring portion 282B constitutes a current path that electrically connects the source of the switching element 251 and the drain of the switching element 252. The third wiring portion 282C constitutes a part of a current path that electrically connects the source of the switching element 252 and the negative electrode of the DC power supply 300.

[0065] The V-phase wiring 282 forms a node N2 (see FIG. 9) in the second wiring portion 282B, and also includes a fourth wiring portion 282D that forms part of a current path that electrically connects the node N2 and the coil CV (see FIG. 9). The fourth wiring portion 282D is connected to a land pattern 282E. A V-phase connecting terminal (not shown) is joined to the land pattern 282E by, for example, soldering.

[0066] The W-phase wiring 283 is connected to the sources and drains of the switching elements 261, 262 of the W-phase arm section 260. The W-phase wiring 283 includes a first wiring portion 283A, a second wiring portion 283B, and a third wiring portion 283C. The first wiring portion 283A configures a part of a current path electrically connecting the drain of the switching element 261 and the positive electrode of the DC power supply 300. The second wiring portion 283B configures a current path electrically connecting the source of the switching element 261 and the drain of the switching element 262. The third wiring portion 283C configures a part of a current path electrically connecting the source of the switching element 262 and the negative electrode of the DC power supply 300.

[0067] The W-phase wiring 283 forms a node N3 (see FIG. 9) in the second wiring portion 283B, and also includes a fourth wiring portion 283D that forms part of a current path that electrically connects the node N3 and the coil CW (see FIG. 9). The fourth wiring portion 283D is connected to a land pattern 283E. A W-phase connecting terminal (not shown) is joined to the land pattern 283E by, for example, soldering.

[0068] Although not shown, the substrate 280 is provided with U-phase gate wiring, V-phase gate wiring, and W-phase gate wiring. The U-phase gate wiring includes a first gate wiring electrically connected to the gate of the switching element 241 of the U-phase arm section 240, and a second gate wiring electrically connected to the gate of the switching element 242. These gate wirings are electrically connected to the gate drive circuit 230.

[0069] The V-phase gate wiring includes a first gate wiring electrically connected to the gate of the switching element 251 of the V-phase arm section 250, and a second gate wiring electrically connected to the gate of the switching element 252. These gate wirings are electrically connected to the gate drive circuit 230.

[0070] The W-phase gate wiring includes a first gate wiring electrically connected to the gate of the switching element 261 of the W-phase arm section 260, and a second gate wiring electrically connected to the gate of the switching element 262. These gate wirings are electrically connected to the gate drive circuit 230.

[0071] The configuration of the semiconductor devices 10U and 10W is the same as that of the semiconductor device 10. That is, the semiconductor device 10U is provided including the substrate 280 and the fourth wiring portion 281D of the U-phase wiring 281. The semiconductor device 10W is provided including the substrate 280 and the fourth wiring portion 283D of the W-phase wiring 283. The configurations of these semiconductor devices 10U and 10W are the same. Here, the substrate 280 of the semiconductor devices 10U and 10W corresponds to the substrate 20 of the semiconductor device 10 (see FIG. 1), and the fourth wiring portions 281D and 283D of the semiconductor devices 10U and 10W correspond to the wiring pattern 30 of the semiconductor device 10 (see FIG. 1). Therefore, the fourth wiring portions 281D and 283D include a first pattern 41, a second pattern 42, and a detection pattern 43 (all of which are shown in FIG. 4), similar to the wiring pattern 30.

[0072] The sensor chip 50U of the semiconductor device 10U is mounted on the substrate 280 so as to straddle the fourth wiring portion 281D. Although not shown, the sensor chip 50U is mounted on the substrate 280 so as to straddle the detection pattern 43 of the fourth wiring portion 281D in the width direction. The sensor chip 50U is electrically connected to the main control unit 220. More specifically, the substrate 280 is provided with sensor patterns 291U to 294U corresponding to the sensor chip 50U. The sensor patterns 291U to 294U correspond to the first to fourth sensor patterns 71 to 74. The sensor chip 50U is mounted on the sensor patterns 291U to 294U. The sensor patterns 291U to 294U are electrically connected to, for example, the main control unit 220 (see FIG. 9). Therefore, the sensor chip 50U is electrically connected to the main control unit 220 through the sensor patterns 291U to 294U. The sensor chip 50U is configured to output to the main control unit 220 a signal according to the amount of current flowing through the detection pattern 43 of the fourth wiring portion 281D.

[0073] The sensor chip 50W of the semiconductor device 10W is mounted on the substrate 280 so as to straddle the fourth wiring portion 283D. Although not shown, the sensor chip 50W is mounted on the substrate 280 so as to straddle the detection pattern 43 of the fourth wiring portion 283D in the width direction. The sensor chip 50W is electrically connected to the main control unit 220. More specifically, the substrate 280 is provided with sensor patterns 291W to 294W corresponding to the sensor chip 50W. The sensor patterns 291W to 294W correspond to the first to fourth sensor patterns 71 to 74. The sensor chip 50W is mounted on the sensor patterns 291W to 294W. The sensor patterns 291W to 294W are electrically connected to, for example, the main control unit 220. Therefore, the sensor chip 50W is electrically connected to the main control unit 220 through the sensor patterns 291W to 294W. The sensor chip 50W is configured to output to the main control unit 220 a signal according to the amount of current flowing through the detection pattern 43 of the fourth wiring portion 283D.

[0074] The inverter device 200 may include a semiconductor device 10 provided in a portion of the V-phase current path between the node N2 and the V-phase coil CV. The semiconductor device 10 is configured to output information indicating the amount of current flowing through the V-phase current path to the main control unit 220. The sensor chip 50 of the semiconductor device 10 is mounted on the substrate 280 so as to straddle the fourth wiring portion 282D. Although not shown, the sensor chip 50W is mounted on the substrate 280 so as to straddle the detection pattern 43 of the fourth wiring portion 282D in the width direction. The sensor chip 50 is electrically connected to the main control unit 220 through first to fourth sensor patterns 71 to 74 provided around the fourth wiring portion 282D. The sensor chip 50 is configured to output a signal to the main control unit 220 according to the amount of current flowing through the detection pattern 43 of the fourth wiring portion 282D. In this way, by providing the semiconductor device 10 in each of the U-phase current path, the V-phase current path, and the W-phase current path, it is possible to detect the current supplied to each of the U-phase coil CU, the V-phase coil CV, and the W-phase coil CW.

[0075] Here, a current of, for example, 10 A or more is supplied to the U-phase coil CU, V-phase coil CV, and W-phase coil CW of the three-phase brushless motor. Therefore, a current of, for example, 10 A or more flows through each of the U-phase wiring 281, V-phase wiring 282, and W-phase wiring 283. As a result, a current of, for example, 10 A or more flows through each of the detection patterns 43 of the U-phase wiring 281 and W-phase wiring 283. In this manner, semiconductor devices 10U and 10W are used with a current of 10 A or more flowing through detection pattern 43. Note that, if a current of, for example, 20 A or more is supplied to the U-phase coil CU, V-phase coil CV, and W-phase coil CW of the three-phase brushless motor, it can be said that semiconductor devices 10U and 10W are used with a current of 20 A or more flowing through detection pattern 43.

[0076] In addition, in the inverter device 200, the semiconductor device 10 may be provided on a power supply wiring that connects the U-phase arm section 240, the V-phase arm section 250, and the W-phase arm section 260 to the positive electrode of the DC power supply 300. That is, the semiconductor device 10 may be configured to detect a current flowing through the power supply wiring. In addition, in the inverter device 200, the semiconductor device 10 may be provided on a ground wiring that connects the U-phase arm section 240, the V-phase arm section 250, and the W-phase arm section 260 to the negative electrode of the DC power supply 300. That is, the semiconductor device 10 may be configured to detect a current flowing through the ground wiring. In this way, the current supplied to the V-phase current path can be detected using the semiconductor devices 10U and 10W and the semiconductor device 10 provided on the power supply wiring or the ground wiring.

[0077] In addition, when the semiconductor device 10 is provided in the power supply wiring or the ground wiring in the inverter device 200 shown in Figure 9, if the semiconductor device 10 is provided in two of the U-phase current path, the V-phase current path, and the W-phase current path, the currents supplied to the U-phase coil CU, the V-phase coil CV, and the W-phase coil CW can be detected.

[0078] [Operation of the first embodiment] The operation of the semiconductor device 10 of the first embodiment will be described. Generally, current sensors using magnetic detection elements such as Hall elements can be classified into the following first and second configurations. In the first configuration, a current sensor electrically connects a first separated pattern and a second separated pattern, which are mutually separated wiring patterns. That is, in the first configuration, a current flowing through the wiring patterns is drawn into the current sensor, and a Hall element provided in the current sensor detects a magnetic field generated by the current drawn into the current sensor. In the second configuration, the wiring pattern is formed into a rectangular shape by an outgoing path section, a return path section, and a connecting section connecting the outgoing path section and the return path section, and the current sensor is disposed to face the outgoing path section and the return path section. The current sensor is configured to detect a magnetic field based on a current flowing in the outgoing path section and a magnetic field based on a current flowing in the return path section.

[0079] However, in the first configuration, the current flowing through the wiring pattern is drawn into the current sensor, so the insulating structure provided in the current sensor becomes large when a large current flows, whereas in the second configuration, the wiring pattern needs to be formed in a rectangular shape, so the space for the wiring pattern to detect the current flowing through the wiring pattern becomes large.

[0080] In this regard, in the first embodiment, the sensor chip 50 is mounted on the first substrate surface 20S of the substrate 20 so as to straddle in the X direction the detection pattern 43 of the wiring pattern 30 extending in the Y direction. The sensor chip 50 can detect a magnetic field based on a current flowing through the detection pattern 43 without contacting the detection pattern 43. Therefore, even if a large current flows through the detection pattern 43, the insulating structure of the sensor chip 50 can be prevented from increasing in size. Furthermore, the wiring pattern 30 only needs to include the detection pattern 43, and does not need to be formed in a rectangular shape to detect a current flowing through the wiring pattern 30 as in the second configuration. The wiring pattern 30 in the first embodiment extends linearly in the Y direction. Therefore, it is possible to prevent the space required for the wiring pattern 30 to detect a current flowing through the wiring pattern 30 from becoming large.

[0081] [Effects of the first embodiment] According to the semiconductor device 10 of the first embodiment, the following effects can be obtained. (1-1) The semiconductor device 10 includes a substrate 20 including a first substrate surface 20S and a second substrate surface 20R opposite to the first substrate surface 20S, a wiring pattern 30 provided on the first substrate surface 20S, and a sensor chip 50 used to detect a current flowing through the wiring pattern 30. The wiring pattern 30 includes a detection pattern 43 having a predetermined width. The sensor chip 50 is mounted on the first substrate surface 20S in a state where it straddles the detection pattern 43. The sensor chip 50 includes a first detection element 51 and a second detection element 52 as detection elements that detect a magnetic field generated by a current flowing through the detection pattern 43.

[0082] According to this configuration, it is not necessary to make the shape of the wiring pattern 30 rectangular in order to detect the current flowing through the wiring pattern 30, and therefore it is possible to prevent the space of the wiring pattern 30 from becoming large in order to detect the current flowing through the wiring pattern 30. Therefore, it is possible to improve the degree of freedom in the layout of the wiring pattern 30.

[0083] (1-2) In a plan view, the first detection element 51 and the second detection element 52 are provided on both sides of the detection pattern 43 in the X direction, which is the width direction of the detection pattern 43. The first detection element 51 and the second detection element 52 are arranged opposite each other in the X direction with the detection pattern 43 interposed therebetween.

[0084] With this configuration, the first detection element 51 and the second detection element 52 can detect magnetic fields generated by the current flowing through the detection pattern 43, but in opposite directions. Meanwhile, an external magnetic field is superimposed as a positive value on one of the magnetic field directions and as a negative value on the other of the magnetic field directions. As a result, the output voltages of the first detection element 51 and the second detection element 52 have different values ​​due to the influence of the external magnetic field. Therefore, the external magnetic field can be eliminated, for example, by using the difference between the output voltages of the first detection element 51 and the second detection element 52. Therefore, the magnetic field of the detection pattern 43, with the influence of the external magnetic field eliminated, can be detected based on the first detection element 51 and the second detection element 52.

[0085] (1-3) In the Z direction, which is the thickness direction of the substrate 20, a gap GP is provided between the sensor chip 50 and the detection pattern 43. This configuration can prevent the heat generated by the detection pattern 43 from affecting the sensor chip 50.

[0086] (1-4) The distance DA between the first detection element 51 and the second detection element 52 and the detection pattern 43 in the Z direction is smaller than the thickness TC of the detection pattern 43. According to this configuration, both the first detection element 51 and the second detection element 52 can be brought closer to the detection pattern 43. Therefore, the magnetic flux entering both the first detection element 51 and the second detection element 52 approaches perpendicularly to the first detection element 51 and the second detection element 52, thereby improving the detection accuracy of the first detection element 51 and the second detection element 52.

[0087] (1-5) The wiring pattern 30 includes a first pattern 41 extending in the Y direction, a second pattern 42 extending in the Y direction and spaced apart from the first pattern 41 in the Y direction, and a detection pattern 43 provided between the first pattern 41 and the second pattern 42 and connecting the first pattern 41 and the second pattern 42. The first pattern 41 has a first width W1 that is the length in the X direction in a plan view. The second pattern 42 has a second width W2 that is the length in the X direction. The detection pattern 43 has a connection width WC that is the length in the X direction. The connection width WC is narrower than the first width W1 and the second width W2. The sensor chip 50 is mounted on the first substrate surface 20S and arranged to straddle the detection pattern 43.

[0088] With this configuration, current concentrates in the detection pattern 43, and the magnetic force generated by the current flowing through the detection pattern 43 becomes stronger. This makes it easier for the first detection element 51 and the second detection element 52 to detect the magnetic field of the detection pattern 43. In addition, as the connection width WC of the detection pattern 43 becomes narrower, the length in the X direction of the sensor chip 50 that straddles the detection pattern 43 in the X direction can be reduced. This allows the sensor chip 50 to be made smaller.

[0089] (1-6) The length LC of the detection pattern 43 in the Y direction is shorter than the length L1 of the first pattern 41 in the Y direction and the length L2 of the second pattern 42 in the Y direction. According to this configuration, the Y-direction length LC of the narrow detection pattern 43 is shorter than the Y-direction lengths L1, L2 of the wide first pattern 41 and second pattern 42, thereby suppressing an increase in the electrical resistance of the wiring pattern 30.

[0090] (1-7) The first pattern 41 includes a first portion 41A having a first width W1 and a second portion 41B that narrows from the first portion 41A toward the detection pattern 43. According to this configuration, for example, when an external force is applied to the substrate 20, it is possible to prevent the first pattern 41 from being broken.

[0091] (1-8) The second pattern 42 includes a first portion 42A having a second width W2 and a second portion 42B that narrows from the first portion 42A toward the detection pattern 43. According to this configuration, for example, when an external force is applied to the substrate 20, it is possible to prevent the second pattern 42 from being broken.

[0092] (1-9) The sensor chip 50 includes a plurality of terminals 61 to 64. The sensor chip 50 is mounted in the space SP provided in the X direction of the detection pattern 43 so that the plurality of terminals 61 to 64 are arranged in the space SP.

[0093] According to this configuration, the multiple terminals 61-62 are arranged in the space SP formed according to the shapes of the first pattern 41, the second pattern 42, and the detection pattern 43 of the wiring pattern 30, so there is no need to provide a separate space for arranging the multiple terminals 61-64. This makes it possible to effectively utilize the space formed by the wiring pattern 30 on the first substrate surface 20S.

[0094] (1-10) When viewed from the Y direction, the terminals 61 to 64 are arranged inside the outer edges of the first pattern 41 and the second pattern 42. According to this configuration, the plurality of terminals 61-64 are arranged in the space SP formed by the connection width WC of the detection pattern 43 being narrower than the first width W1 of the first pattern 41 and the second width W2 of the second pattern 42, and therefore there is no need to provide a space for arranging the plurality of terminals 61-64 outside the wiring pattern 30 in the X direction. This makes it possible to effectively utilize the space formed by the wiring pattern 30 on the first substrate surface 20S. Therefore, wiring patterns other than the wiring pattern 30 on the first substrate surface 20S of the substrate 20 can be arranged close to the wiring pattern 30, thereby improving the degree of freedom in the layout of the wiring patterns other than the wiring pattern 30.

[0095] (1-11) The semiconductor device 10 includes first to fourth sensor patterns 71 to 74 that are provided on the first substrate surface 20S and are individually connected to the multiple terminals 61 to 64. Upper surfaces 71S to 74S of the first to fourth sensor patterns 71 to 74 are located closer to the first substrate surface 20S than the upper surface 43S of the detection pattern 43.

[0096] This configuration allows the sensor chip 50 to be brought closer to the upper surface 43S of the detection pattern 43. That is, the first detection element 51 and the second detection element 52 can be brought closer to the detection pattern 43. Therefore, the magnetic flux entering both the first detection element 51 and the second detection element 52 approaches perpendicularly to the first detection element 51 and the second detection element 52, thereby improving the detection accuracy of the first detection element 51 and the second detection element 52.

[0097] (1-12) The substrate 20 includes a first base material 21, a second base material 22 located closer to the second substrate surface 20R than the first base material 21, and a third base material 23 located closer to the second substrate surface 20R than the second base material 22 and including the second substrate surface 20R. A first heat dissipation pattern 32 is provided between the first base material 21 and the second base material 22. A second heat dissipation pattern 33 is provided between the second base material 22 and the third base material 23. A third heat dissipation pattern 34 is provided on the second substrate surface 20R.

[0098] According to this configuration, heat from the first wiring pattern 31 is transferred to the first to third heat dissipation patterns 32 to 34. Therefore, the heat dissipation performance of the wiring pattern 30 can be improved, and the temperature of the wiring pattern 30 can be prevented from increasing.

[0099] (1-13) Each of the first to third heat dissipation patterns 32 to 34 has a heat dissipation width WP that is larger than both the first width W1 and the second width W2. According to this configuration, the area of ​​each of the first to third heat dissipation patterns 32 to can be increased, and therefore the heat dissipation performance of the wiring pattern 30 based on the first to third heat dissipation patterns 32 to can be improved.

[0100] (1-14) The semiconductor device 10 is used when the current flowing through the detection pattern 43 is 10 A or more. According to this configuration, when a large current of 10 A or more flows through the detection pattern 43, the magnetic field of the detection pattern 43 is detected by the sensor chip 50, which is not in contact with the detection pattern 43, thereby preventing the insulating structure within the sensor chip 50 from becoming larger.

[0101] (1-15) The package structure of the sensor chip 50 is WLCSP. This configuration allows the sensor chip 50 to be made smaller than when the package structure of the sensor chip 50 is, for example, an SOP (Small Outline Package), and therefore the space required for detecting the current in the wiring pattern 30 on the substrate 20 can be reduced.

[0102] (1-16) The sensor chip 50 includes a semiconductor substrate 55 and a semiconductor layer 56 provided on the semiconductor substrate 55. The first detection element 51 and the second detection element 52 are provided on the semiconductor layer 56. The semiconductor layer 56 is disposed closer to the detection pattern 43 than the semiconductor substrate 55. A plurality of terminals 61 to 64 are provided on the semiconductor layer 56 on the opposite side of the semiconductor substrate 55.

[0103] According to this configuration, when the sensor chip 50 is mounted on the first substrate surface 20S, the first detection element 51 and the second detection element 52 are disposed near the wiring pattern 30 within the sensor chip 50. This improves the accuracy with which the first detection element 51 and the second detection element 52 detect the magnetic field of the detection pattern 43.

[0104] (1-17) The multiple terminals 61 to 64 are arranged on both sides of the detection pattern 43 in the X direction, which is the width direction of the detection pattern 43. With this configuration, the sensor chip 50 is supported on the first substrate surface 20S at positions spaced apart in the X direction by the multiple terminals 61 to 64. Therefore, compared to a configuration in which the sensor chip 50 is supported on the first substrate surface 20S only on one side in the X direction, it is possible to prevent the multiple terminals 61 to 64 from peeling off from the first substrate surface 20S when an external force is applied to the sensor chip 50. This can improve the reliability of mounting the sensor chip 50 on the first substrate surface 20S.

[0105] (1-18) The sensor chip 50 includes an arithmetic circuit 80 configured to output a signal according to the outputs from the first detection element 51 and the second detection element 52. According to this configuration, the number of parts can be reduced compared to when a chip for the arithmetic circuit 80 is provided separately from the sensor chip 50.

[0106] (1-19) The arithmetic circuit 80 is configured to output a signal according to the value of the current flowing through the wiring pattern 30 based on the difference between the output voltage of the first detection element 51 and the output voltage of the second detection element 52.

[0107] According to this configuration, the external magnetic field can be removed by the difference between the output voltage of the first detection element 51 and the output voltage of the second detection element 52. Therefore, the magnetic field of the detection pattern 43, from which the influence of the external magnetic field has been removed, can be detected based on the output voltage of the first detection element 51 and the output voltage of the second detection element 52.

[0108] (1-20) The first detection element 51, the second detection element 52, and the arithmetic circuit 80 are provided in the semiconductor layer 56. This configuration shortens the current paths between the first detection element 51 and the second detection element 52 and the arithmetic circuit 80, thereby reducing the inductance caused by these current paths. Therefore, the arithmetic circuit 80 can accurately calculate the value of the current flowing through the detection pattern 43.

[0109] (1-21) The first detection element 51 and the second detection element 52 are Hall elements. According to this configuration, the cost of the sensor chip 50 can be reduced compared to when the first detection element 51 and the second detection element 52 are MR elements, MI elements, or the like.

[0110] Second Embodiment The configuration of the semiconductor device 10 of the second embodiment will be described with reference to Fig. 11. The semiconductor device 10 of the second embodiment differs from the semiconductor device 10 of the first embodiment in the number of detection elements. In the following, components common to the semiconductor device 10 of the first embodiment are given the same reference numerals, and their description will be omitted. Fig. 11 shows an enlarged planar structure of the sensor chip 50 and its surrounding area in the semiconductor device 10 of the second embodiment.

[0111] As shown in FIG. 11, the sensor chip 50 of the semiconductor device 10 of the second embodiment further includes a third detection element 53 and a fourth detection element 54. The third detection element 53 and the fourth detection element 54 are, for example, Hall elements. Note that the third detection element 53 and the fourth detection element 54 are not limited to Hall elements, and a magneto-impedance element (MI element) or a magneto-resistance effect element (MR element) may also be used. The first to fourth detection elements 51 to 54 may be magnetic detection elements of the same type. In the second embodiment, each of the first to fourth detection elements 51 to 54 is a Hall element.

[0112] The third detection element 53 and the fourth detection element 54 are arranged closer to the second pattern 42 than the first detection element 51 and the second detection element 52 in a plan view. The third detection element 53 and the fourth detection element 54 are arranged at the same position in the Y direction and spaced apart from each other in the X direction.

[0113] The third detection element 53 is arranged alongside the first detection element 51 in the Y direction. In one example, the third detection element 53 is arranged at a position overlapping the first detection element 51 when viewed from the Y direction. In the second embodiment, the third detection element 53 is arranged at the same position as the first detection element 51 in the X direction. In other words, the third detection element 53 is arranged so as to straddle one edge of the detection pattern 43 in the X direction in a plan view.

[0114] The fourth detection element 54 is arranged alongside the second detection element 52 in the Y direction. In one example, the fourth detection element 54 is arranged at a position overlapping the second detection element 52 when viewed from the Y direction. In the second embodiment, the fourth detection element 54 is arranged at the same position as the second detection element 52 in the X direction. In other words, the fourth detection element 54 is arranged so as to straddle the other edge of the detection pattern 43 in the X direction in a plan view.

[0115] Although not shown, the third detection element 53 and the fourth detection element 54 are arranged at the same position in the Z direction. The third detection element 53 and the fourth detection element 54 are arranged at the same position in the Z direction as the first detection element 51 and the second detection element 52. The third detection element 53 and the fourth detection element 54 are provided in the semiconductor layer 56 (see FIG. 7) of the sensor chip 50. The third detection element 53 and the fourth detection element 54 are electrically connected to the arithmetic circuit 80 (see FIG. 8) of the sensor chip 50.

[0116] In the semiconductor device 10 configured as described above, the arithmetic circuit 80 is configured to output a signal corresponding to the value of a current flowing through the wiring pattern 30 based on the output voltages of the first to fourth detection elements 51 to 53. More specifically, the arithmetic circuit 80 calculates the difference between a first output voltage, which is the output voltage of the first detection element 51, and a second output voltage, which is the output voltage of the second detection element 52. This generates a first signal from which the influence of an external magnetic field on the first detection element 51 and the second detection element 52 has been eliminated. The arithmetic circuit 80 calculates the difference between a third output voltage, which is the output voltage of the third detection element 53, and a fourth output voltage, which is the output voltage of the fourth detection element 54. This generates a second signal from which the influence of an external magnetic field on the third detection element 53 and the fourth detection element 54 has been eliminated. The arithmetic circuit 80 then generates an output signal based on the average value of the first and second signals. This output signal is a signal corresponding to the value of a current flowing through the wiring pattern 30.

[0117] [Effects of the second embodiment] According to the semiconductor device 10 of the second embodiment, the following effects can be obtained. (2-1) The sensor chip 50 includes a third detection element 53 arranged alongside the first detection element 51 in the Y direction, which is the direction in which the detection pattern 43 extends, and a fourth detection element 54 arranged in the same position as the third detection element 53 in the Y direction and alongside the second detection element 52. With this configuration, the first to fourth detection elements 51 to 54 detect the current flowing through the detection pattern 43, thereby improving detection accuracy.

[0118] (2-2) The sensor chip 50 includes an arithmetic circuit 80 configured to output a signal corresponding to the outputs from the first detection element 51, the second detection element 52, the third detection element 53, and the fourth detection element 54. The arithmetic circuit 80 is configured to output a signal corresponding to the value of the current flowing through the detection pattern 43 based on the average value of the difference between the output voltage of the first detection element 51 and the output voltage of the second detection element 52 and the difference between the output voltage of the third detection element 53 and the output voltage of the fourth detection element 54.

[0119] According to this configuration, the detection variations by the first detection element 51 and the second detection element 52 and the detection variations by the third detection element 53 and the fourth detection element 54 can be averaged, and therefore signals with small detection variations by these first to fourth detection elements 51 to 54 can be output.

[0120] Third Embodiment A semiconductor device 10 of the third embodiment will be described with reference to Figures 12 and 13. The semiconductor device 10 of the third embodiment differs from the semiconductor device 10 of the first embodiment mainly in the packaging structure of the sensor chip 50. In the following, components common to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0121] Fig. 12 is a schematic diagram illustrating an enlarged planar structure of the sensor chip 50 and its surroundings in the semiconductor device 10 of the third embodiment. Fig. 13 is a schematic diagram illustrating a cross-sectional structure of the sensor chip 50 taken along line F13-F13 in Fig. 12.

[0122] 12 and 13, the package structure of the sensor chip 50 is SOP instead of WLCSP. Therefore, the sensor chip 50 includes a sealing resin 90. Furthermore, the terminals 61 to 64 of the sensor chip 50 are configured by leads instead of solder bumps.

[0123] 12, the terminals 61 to 64 protrude from the sealing resin 90 in the X direction. The terminals 61 to 64 are joined to the corresponding first to fourth sensor patterns 71 to 74 by, for example, solder. The terminals 61 to 64 are arranged in a recess 44 of the wiring pattern 30. The terminals 61 to 64 are arranged in a trapezoidal space SP formed by the first pattern 41, the second pattern 42, and the detection pattern 43 of the wiring pattern 30 in a plan view.

[0124] As shown in FIG. 13 , the sealing resin 90 includes a first sealing surface 91 and a second sealing surface 92 opposite to the first sealing surface 91. The sealing resin 90 is made of an insulating material. An example of the insulating material is epoxy resin. The first sealing surface 91 faces the same side as the first substrate surface 20S of the substrate 20. The second sealing surface 92 faces the wiring pattern 30.

[0125] The sensor chip 50 includes a sensor element 100 and a die pad 110 provided within a sealing resin 90. The sensor element 100 is composed of a semiconductor substrate 55, a semiconductor layer 56, an insulating layer 57 (see FIG. 8), and wiring 58 (see FIG. 8). That is, the sealing resin 90 seals the semiconductor substrate 55 and the semiconductor layer 56. Both the first detection element 51 and the second detection element 52 are provided on the semiconductor layer 56, as in the first embodiment. The die pad 110 holds the sensor element 100. The die pad 110 is made of a non-magnetic metal material such as Al or Cu. The die pad 110 has a flat plate shape with its thickness direction aligned in the Z direction. The sensor element 100 is bonded to the die pad 110 with a conductive bonding material SD such as solder paste or silver (Ag) paste.

[0126] 13, the sensor element 100 is disposed closer to the first sealing surface 91 than the die pad 110. Therefore, both the first detection element 51 and the second detection element 52 are disposed closer to the first sealing surface 91 than the second sealing surface 92 of the sealing resin 90 in the Z direction. Four pads 59 are provided on the semiconductor layer 56 of the sensor element 100. These pads 59 are electrically connected to wiring 58. That is, these pads 59 are electrically connected to the arithmetic circuit 80 through the wiring 58.

[0127] The four pads 59 are individually and electrically connected to corresponding terminals 61 to 64 by a plurality of wires WR. Each wire WR is a bonding wire made of a conductive material such as Al, Cu, Ag, or Au. Each wire WR is sealed with sealing resin 90. The semiconductor device 10 of the third embodiment can achieve the same effects as those of the first embodiment.

[0128] <Example of change> The above-described embodiments can be modified as follows: Furthermore, the above-described embodiments and the following modifications can be combined with each other within the scope of technical compatibility.

[0129] In each embodiment, the wiring pattern 30 may be modified as shown in FIGS. 14 to 16. FIG. 14 schematically shows a perspective view of the semiconductor device 10 of a modified example. FIG. 15 schematically shows a side view of the substrate 20 of the semiconductor device 10 of FIG. 14. FIG. 16 schematically shows the structure of the substrate 20 viewed from a different direction than that of FIG. 14.

[0130] As shown in FIGS. 14 to 16 , the wiring pattern 30 of the modified example includes a second wiring pattern 35 instead of the first heat dissipation pattern 32. The second wiring pattern 35 is provided between the first substrate 21 and the third substrate 23. In one example, the second wiring pattern 35 is disposed opposite the first wiring pattern 31 in the Z direction. In one example, the second wiring pattern 35 has the same size and shape as the first wiring pattern 31. Therefore, like the first wiring pattern 31, the second wiring pattern 35 includes a first pattern 41, a second pattern 42, and a detection pattern 43. The second wiring pattern 35 is electrically connected to the first wiring pattern 31.

[0131] The wiring pattern 30 includes at least one through hole 36 that connects the first wiring pattern 31 and the second wiring pattern 35 in the Z direction. The through hole 36 penetrates the first base material 21 in the Z direction.

[0132] Here, the through holes 36 are connecting conductors including a metal layer provided on the inner surface of a through hole that penetrates the first substrate 21. The metal layer is made of a conductive material such as Al, Cu, Ti, TiN, or W. In one example, the metal layer is made of the same material as the first wiring pattern 31 and the second wiring pattern 35. The metal layer of the through holes 36 may be provided so as to fill the through holes.

[0133] 14 and 15, the wiring pattern 30 includes a plurality of through holes 36. The plurality of through holes 36 are provided in the first pattern 41 and the second pattern 42. On the other hand, the plurality of through holes 36 are not provided in the detection pattern 43.

[0134] The multiple through holes 36 are arranged spaced apart in the X and Y directions in the first portion 41A of the first pattern 41. In one example, the multiple through holes 36 are arranged in a matrix (e.g., 5 × 3) in a plan view. One of the multiple through holes 36 is provided in the second portion 41B of the first pattern 41. This through hole 36 is provided in the center of the second portion 41B in the X and Y directions.

[0135] The multiple through holes 36 are arranged spaced apart in the X and Y directions in the first portion 42A of the second pattern 42. In one example, the multiple through holes 36 are arranged in a matrix (e.g., 5 × 3) in a plan view. One of the multiple through holes 36 is provided in the second portion 42B of the second pattern 42. This through hole 36 is provided in the center of the second portion 42B in the X and Y directions.

[0136] The through holes 36 are configured to connect the first wiring pattern 31 and the second wiring pattern 35, and are arranged to be spaced apart from the second heat dissipation pattern 33 and the third heat dissipation pattern 34 in the Z direction. Therefore, the second heat dissipation pattern 33 and the third heat dissipation pattern 34 are insulated from the first wiring pattern 31 and the second wiring pattern 35. The sizes and shapes of the second heat dissipation pattern 33 and the third heat dissipation pattern 34 are the same as those in the first embodiment.

[0137] According to the semiconductor device 10 of the modified example shown in FIGS. 14 to 16, the following effects can be obtained. The substrate 20 is a multilayer substrate including a laminated structure in which a first substrate 21 and a second substrate 22 are stacked. The first substrate 21 includes a first substrate surface 20S. The wiring pattern 30 includes a first wiring pattern 31 provided on the first substrate 21 and a second wiring pattern 35 provided between the first substrate 21 and the third substrate 23 and electrically connected to the first wiring pattern 31. Each of the first wiring pattern 31 and the second wiring pattern 35 includes a first pattern 41, a second pattern 42, and a detection pattern 43.

[0138] According to this configuration, the current flowing through the wiring pattern 30 branches off to flow through the first wiring pattern 31 and the second wiring pattern 35. This reduces the amount of current flowing through each of the first wiring pattern 31 and the second wiring pattern 35, thereby reducing the amount of heat generated by the first wiring pattern 31 and the second wiring pattern 35. This prevents the temperature of the wiring pattern 30 from becoming excessively high.

[0139] The wiring pattern 30 includes at least one through-hole 36 that penetrates the first base material 21 in the Z direction and connects the first wiring pattern 31 and the second wiring pattern 35 together. According to this configuration, heat can be dissipated to the outside of the wiring pattern 30 through the through holes 36. Therefore, the heat dissipation performance of the wiring pattern 30 can be improved, and the temperature of the wiring pattern 30 can be further prevented from increasing.

[0140] The through-hole 36 is not provided in the detection pattern 43, but is provided in at least one of the first pattern 41 and the second pattern 42. According to this configuration, since the through holes 36 are not provided in the detection pattern 43, it is possible to prevent the magnetic field caused by the current flowing through the through holes 36 from affecting the first detection element 51 and the second detection element 52. In addition, since the through holes 36 are provided in the first pattern 41 and the second pattern 42, which have larger areas than the detection pattern 43, it is possible to increase the number of through holes 36. Therefore, it is possible to improve the heat dissipation performance of the wiring pattern 30.

[0141] In the modified examples shown in FIGS. 14 to 16, the second wiring pattern 35 may have a shape different from that of the first wiring pattern 31. 14 to 16, the arrangement positions of the through holes 36 can be changed as desired. In one example, the through holes 36 in the second portion 41B of the first pattern 41 may be omitted. In another example, the through holes 36 in the second portion 42B of the second pattern 42 may be omitted.

[0142] 14 to 16, the configuration of the substrate 20 can be changed as desired. For example, the substrate 20 may have a laminated structure of a first substrate 21 and a second substrate 22. In this case, the second heat dissipation pattern 33 may be omitted. For example, the substrate 20 may be formed of the first substrate 21. In this case, for example, both the second heat dissipation pattern 33 and the third heat dissipation pattern 34 may be omitted. That is, the first substrate surface 20S of the substrate 20 is provided with the first wiring pattern 31, and the second substrate surface 20R is provided with the second wiring pattern 35.

[0143] In the modified example shown in FIGS. 14 to 16, a third wiring pattern may be provided between the second base material 22 and the third base material 23 of the substrate 20, instead of the second heat dissipation pattern 33. The third wiring pattern has the same size and shape as the first wiring pattern 31 and the second wiring pattern 35. In this case, the through-hole 36 is provided so as to penetrate both the first base material 21 and the third base material 23. Therefore, the first wiring pattern 31, the second wiring pattern 35, and the third wiring pattern are electrically connected to one another by the through-hole 36. On the other hand, the third wiring pattern is insulated from the third heat dissipation pattern 34.

[0144] In each embodiment, the shape of the wiring pattern 30 in a plan view can be changed as desired. Figures 17 and 18 show modified examples of the wiring pattern 30. Figures 17 and 18 schematically show the planar structure of the wiring pattern 30.

[0145] 17 , in the wiring pattern 30 of the first modified example, the second portion 41B of the first pattern 41 may be provided in a stepped shape. The width of the second portion 41B decreases toward the detection pattern 43. The second portion 42B of the second pattern 42 may also be provided in a stepped shape. The width of the second portion 42B decreases toward the detection pattern 43.

[0146] 18, in the wiring pattern 30 of the second modified example, the second portion 41B of the first pattern 41 may be provided in a curved shape, and the second portion 42B of the second pattern 42 may be provided in a curved shape.

[0147] In each embodiment, the second portion 41B may be omitted from the first pattern 41. In this case, the detection pattern 43 is connected to the first portion 41A of the first pattern 41. Also, in each embodiment, the second portion 42B may be omitted from the second pattern 42. In this case, the detection pattern 43 is connected to the first portion 42A of the second pattern 42.

[0148] In each embodiment, the length LC of the detection pattern 43 in the Y direction may be greater than or equal to the length L1 of the first pattern 41 in the Y direction and the length L2 of the second pattern 42 in the Y direction. In the first to third embodiments, the heat dissipation widths WP of the first to third heat dissipation patterns 32 to 34 can be changed as desired. For example, the heat dissipation width WP of the first heat dissipation pattern 32 may be equal to or smaller than the first width W1 of the first pattern 41. For example, the heat dissipation width WP of the first heat dissipation pattern 32 may be equal to or smaller than the second width W2 of the second pattern 42. For example, the heat dissipation width WP of the second heat dissipation pattern 33 may be equal to or smaller than the first width W1 of the first pattern 41. For example, the heat dissipation width WP of the second heat dissipation pattern 33 may be equal to or smaller than the second width W2 of the second pattern 42. For example, the heat dissipation width WP of the third heat dissipation pattern 34 may be equal to or smaller than the first width W1 of the first pattern 41. For example, the heat dissipation width WP of the third heat dissipation pattern 34 may be equal to or smaller than the second width W2 of the second pattern 42. The heat dissipation widths WP of the first to third heat dissipation patterns 32 to 34 may be different from one another.

[0149] In each embodiment, the sensor chip 50 may include one detection element instead of the first detection element 51 and the second detection element 52. In the second embodiment, the sensor chip 50 may include one detection element instead of the first to fourth detection elements 51 to 54. In these cases, the arithmetic circuit 80 of the sensor chip 50 is configured to output a signal corresponding to the output from the one detection element.

[0150] In each embodiment, it is possible to arbitrarily change the arrangement of the multiple terminals 61 to 64. In one example, the multiple terminals 61 to 64 may be arranged in a space SP on one side of the detection pattern 43 in the X direction in a plan view.

[0151] In each embodiment, the number of terminals of the sensor chip 50 is not limited to four, ie, the terminals 61 to 64, and can be changed arbitrarily. In each embodiment, the multiple terminals 61 to 64 may be arranged outward in the X direction from the trapezoidal space SP formed by the second portion 41B of the first pattern 41, the detection pattern 43, and the second portion 42B of the second pattern 42.

[0152] In each embodiment, the thickness TS of each of the first sensor pattern 71 and the second sensor pattern 72 may be equal to or greater than the thickness of the wiring pattern 30 (the thickness TC of the detection pattern 43). Also, the thickness of each of the third sensor pattern 73 and the fourth sensor pattern 74 may be equal to or greater than the thickness of the wiring pattern 30 (the thickness TC of the detection pattern 43).

[0153] In the first and second embodiments, it is possible to arbitrarily change the configuration of the first to fourth sensor patterns 71 to 74. Fig. 19 shows a modified example of the first to fourth sensor patterns 71 to 74, and schematically shows the cross-sectional structure of the sensor chip 50, the substrate 20, the wiring pattern 30, the first sensor pattern 71, and the second sensor pattern 72.

[0154] As shown in FIG. 19 , the first to fourth sensor patterns 71 to 74 may be embedded in the substrate 20. In this case, the upper surface 71S of the first sensor pattern 71 and the upper surface 72S of the second sensor pattern 72 may be flush with the first substrate surface 20S. This reduces the gap GP between the sensor chip 50 and the detection pattern 43 in the Z direction compared to the first and second embodiments. That is, when the modification shown in FIG. 19 is applied to the first embodiment, both the first detection element 51 and the second detection element 52 are arranged close to the detection pattern 43. This allows the magnetic field generated by the detection pattern 43 to approach perpendicularly to the detection surfaces of the first detection element 51 and the second detection element 52, thereby improving the magnetic field detection accuracy of the first detection element 51 and the second detection element 52. When the modification shown in FIG. 19 is applied to the second embodiment, each of the first to fourth detection elements 51 to 54 is arranged close to the detection pattern 43. This causes the magnetic field generated by the detection pattern 43 to approach perpendicular to the detection surfaces of the first to fourth detection elements 51 to 54, thereby improving the detection accuracy of the magnetic field of the first to fourth detection elements 51 to 54. The first to fourth sensor patterns 71 to 74 of the third embodiment may also be modified in the same manner as in FIG. 19.

[0155] In the second embodiment, the positions of the third detection element 53 and the fourth detection element 54 can be changed as desired. Fig. 20 shows an example of a change in the positions of the third detection element 53 and the fourth detection element 54. Fig. 20 schematically shows an enlarged planar structure of the sensor chip 50 and its surrounding area in the semiconductor device 10 of the modified example.

[0156] As shown in FIG. 20 , the third detector element 53 is arranged side by side with the first detector element 51 on the opposite side of the first detector element 51 from the second detector element 52 in the X direction. The fourth detector element 54 is arranged side by side with the second detector element 52 on the opposite side of the first detector element 51 from the second detector element 52 in the X direction. The third detector element 53 is arranged at a position overlapping with the first detector element 51 when viewed from the X direction. More specifically, the third detector element 53 is arranged at the same position as the first detector element 51 in the Y direction. The fourth detector element 54 is arranged at a position overlapping with the second detector element 52 when viewed from the X direction. More specifically, the fourth detector element 54 is arranged at the same position as the second detector element 52 in the Y direction.

[0157] The third detection element 53 is arranged outward in the X direction from the detection pattern 43. The fourth detection element 54 is arranged outward in the X direction from the detection pattern 43. On the other hand, the third detection element 53 and the fourth detection element 54 are arranged in a trapezoidal space SP formed by the second portion 41B of the first pattern 41, the second portion 42B of the second pattern 42, and the detection pattern 43.

[0158] In the third embodiment, the sensor chip 50 may have the first detection element 51, the second detection element 52, and the arithmetic circuit 80 provided on separate semiconductor layers. In one example, the sensor chip 50 includes a first semiconductor substrate, a first semiconductor layer provided on the first semiconductor substrate, a second semiconductor substrate, and a second semiconductor layer provided on the second semiconductor substrate. The first semiconductor substrate is disposed at a distance from the second semiconductor substrate. The first semiconductor layer includes the first detection element 51 and the second detection element 52. The second semiconductor layer includes the arithmetic circuit 80. The first detection element 51 and the second detection element 52 are electrically connected to the arithmetic circuit 80 by, for example, wires.

[0159] In the third embodiment, the arrangement of the sensor element 100 of the sensor chip 50 can be changed as desired. In one example, the sensor element 100 may be arranged so that the semiconductor layer 56 is closer to the second sealing surface 92 of the sealing resin 90 than the semiconductor substrate 55. In this case, the sensor element 100 is mounted on the die pad 110 in a state where it is closer to the second sealing surface 92 than the die pad 110. As a result, both the first detection element 51 and the second detection element 52 are arranged closer to the second sealing surface 92 of the sealing resin 90 in the Z direction than the first sealing surface 91.

[0160] In each embodiment, as shown in Fig. 21, two semiconductor devices 10A and 10B may be provided adjacent to each other in the X direction, for example. Fig. 21 schematically shows the planar structures of the semiconductor devices 10A and 10B. The semiconductor device 10A includes a substrate 20, a wiring pattern 30A, and a sensor chip 50A. The semiconductor device 10B includes a substrate 20, a wiring pattern 30B, and a sensor chip 50B. In this way, the semiconductor devices 10A and 10B include a common substrate 20.

[0161] The two wiring patterns 30A and 30B are arranged adjacent to each other in the X direction. As in each embodiment, each of the wiring patterns 30A and 30B includes a first pattern 41, a second pattern 42, and a detection pattern 43. The wiring patterns 30A and 30B have the same size and shape.

[0162] The sensor chip 50A is mounted on the substrate 20 so as to straddle the detection pattern 43 of the wiring pattern 30A in the X direction. The sensor chip 50B is mounted on the substrate 20 so as to straddle the detection pattern 43 of the wiring pattern 30B in the X direction. The sensor chips 50A and 50B have the same size and shape.

[0163] The substrate 20 is provided with first to fourth sensor patterns 71A to 74A and 71B to 74B. The first to fourth sensor patterns 71A to 74A are electrically connected to the terminals 61 to 64 of the sensor chip 50A, respectively. The first to fourth sensor patterns 71B to 74B are electrically connected to the terminals 61 to 64 of the sensor chip 50B, respectively. The first to fourth sensor patterns 71A to 74A and 71B to 74B are provided between the second base material 22 and the third base material 23, instead of the second heat dissipation pattern 33 (see FIG. 2) of each embodiment.

[0164] The first substrate surface 20S of the substrate 20 is provided with first to fourth lands 75A to 78A and 75B to 78B that are electrically connected to the first to fourth sensor patterns 71A to 74A and 71B to 74B, respectively. The first to fourth sensor patterns 71A to 74A and the first to fourth lands 75A to 78A are connected by through holes (not shown). The first to fourth sensor patterns 71B to 74B and the first to fourth lands 75B to 78B are connected by through holes (not shown). These through holes penetrate both the first base material 21 and the second base material 22 in the Z direction.

[0165] The positions of the first to fourth sensor patterns 71A to 74A and 71B to 74B in the Z direction on the substrate 20 can be changed as desired. The positions of the through holes in the substrate 20 in the Z direction may be changed depending on the positions of the first to fourth sensor patterns 71A to 74A and 71B to 74B in the Z direction. In one example, the first to fourth sensor patterns 71A to 74A and 71B to 74B may be provided on the second substrate surface 20R of the substrate 20.

[0166] The third sensor pattern 73A is connected to the third sensor pattern 73B and extends in the X direction. Signals output from the sensor chips 50A and 50B are supplied to the third sensor patterns 73A and 73B. The third sensor patterns 73A and 73B are electrically connected to a main control unit 220 (see FIG. 9), not shown. In this manner, by connecting the third sensor patterns 73A and 73B, the semiconductor devices 10A and 10B are configured to serially communicate signals from the sensor chips 50A and 50B. In the example shown in FIG. 21, a UART (Universal Asynchronous Receiver Transmitter) is used for serial communication.

[0167] The fourth sensor pattern 74A, the fourth sensor pattern 74B, and the first sensor pattern 71B are connected to one another. The fourth sensor patterns 74A, 74B, and the first sensor pattern 71B form, for example, a ground wiring.

[0168] The first sensor pattern 71A, the second sensor pattern 72A, and the second sensor pattern 72B are connected to one another. The first sensor pattern 71A and the second sensor patterns 72A and 72B are connected to the third sensor pattern 73A via a pull-up resistor 79. The first sensor pattern 71A and the second sensor patterns 72A and 72B form, for example, power supply wiring.

[0169] The connection manner between the first to fourth sensor patterns 71A to 74A, 71B to 74B and the sensor chips 50A, 50B can be changed arbitrarily depending on the device to which the semiconductor device 10 is applied. The connection manner between the first to fourth sensor patterns 71A to 74A, 71B to 74B and the sensor chips 50A, 50B can be changed arbitrarily depending on the terminal configuration of the sensor chips 50A, 50B.

[0170] Furthermore, the shapes of the wiring patterns 30A and 30B in a planar view can be arbitrarily changed. For example, as shown in FIG. 22, the wiring pattern 30B may be tilted 90° counterclockwise relative to the wiring pattern 30A in a planar view. In this case, the first portion 42A of the second pattern 42 of the wiring pattern 30B extends in the Y direction. The second portion 42B is connected to the first portion 42A in the X direction. Therefore, the second portion 42B extends in the X direction in a planar view. The detection pattern 43 connected to the second portion 42B and the first pattern 41 connected to the detection pattern 43 both extend in the X direction in a planar view. The sensor chip 50B is disposed in a position tilted 90° counterclockwise relative to the sensor chip 50A, for example.

[0171] In each embodiment, the sensor chip 50 does not have to include the arithmetic circuit 80. In other words, a circuit chip including the arithmetic circuit 80 may be provided separately from the sensor chip 50.

[0172] In each embodiment, at least one through-hole may be provided to connect the first heat dissipation pattern 32 and the second heat dissipation pattern 33. The through-hole penetrates the third base material 23 in the Z direction. Instead of the through-hole, at least one through-hole may be provided to penetrate the third base material 23 in the Z direction.

[0173] In another example, at least one through hole may be provided to connect the first to third heat dissipation patterns 32 to 34. The through hole passes through both the second base material 22 and the third base material 23 in the Z direction. Note that, instead of the through hole, at least one through hole may be provided that passes through both the second base material 22 and the third base material 23.

[0174] In addition, in one example, in each embodiment, at least one through hole may be provided to connect the second heat dissipation pattern 33 and the third heat dissipation pattern 34. The through hole penetrates the second base material 22 in the Z direction. Note that, instead of the through hole, at least one through hole may be provided to penetrate the second base material 22 in the Z direction.

[0175] In each embodiment, the configuration of the substrate 20 can be changed as desired. For example, the substrate 20 may have a laminated structure of the first base material 21 and the second base material 22. In this case, the second heat dissipation pattern 33 may be omitted. For example, the substrate 20 may be made of the first base material 21. In this case, for example, both the second heat dissipation pattern 33 and the third heat dissipation pattern 34 may be omitted. That is, the first wiring pattern 31 is provided on the first substrate surface 20S of the substrate 20, and the first heat dissipation pattern 32 is provided on the second substrate surface 20R. In another example, when the substrate 20 is made of the first base material 21, the first to third heat dissipation patterns 32 to 34 may be omitted. That is, the first wiring pattern 31 is provided on the first substrate surface 20S of the substrate 20, and no wiring pattern is provided on the second substrate surface 20R.

[0176] In each embodiment, the package structure of the sensor chip 50 can be changed as desired. The package structure of the sensor chip 50 may be a QFN (Quad For Non-Lead Package), a DFP (Dual Flat Package), a DIP (Dual Inline Package), a QFP (Quad Flat Package), a SIP (Single Inline Package), or an SOJ (Small Outline J-leaded Package), or various similar package structures.

[0177] 23 and 24 show an example of a modification of the packaging structure of the sensor chip 50. Fig. 23 schematically shows the planar structure of the sensor chip 50. Fig. 24 schematically shows the cross-sectional structure of the sensor chip 50 taken along line F24-F24 in Fig. 23. Note that sealing resin 140, which will be described later, has been omitted from Fig. 23 to make the drawing easier to understand.

[0178] As shown in FIGS. 23 and 24, the sensor chip 50 includes an insulating substrate 120 on which the sensor element 100 is mounted, and first to fourth conductive layers 131 to 134 electrically connected to the sensor element 100.

[0179] The insulating substrate 120 is made of, for example, epoxy resin. The insulating substrate 120 includes a first substrate surface 121, a second substrate surface 122 opposite to the first substrate surface 121, and a recess 123 recessed from the first substrate surface 121 toward the second substrate surface 122. The sensor element 100 is disposed in the recess 123.

[0180] The first to fourth conductive layers 131 to 134 are individually electrically connected to the four pads 59 of the sensor element 100. More specifically, the four pads 59 of the sensor element 100 are individually bonded to the first to fourth conductive layers 131 to 134 using a conductive bonding material SD. In a plan view, the first to fourth conductive layers 131 to 134 extend from near the center of the bottom surface 124 of the recess 123 to the first substrate surface 121 provided on the insulating substrate 120 closer to the periphery than the recess 123. The first to fourth conductive layers 131 to 134 are made of a conductive material such as Al, Cu, Ti, TiN, or W.

[0181] The sensor element 100 is disposed such that the semiconductor substrate 55 is closer to the bottom surface 124 of the recess 123 than the semiconductor layer 56. The sensor element 100 is mounted by four pads 59 on the portions of the first to fourth conductive layers 131 to 134 that are provided on the bottom surface 124, respectively.

[0182] The sensor chip 50 includes a sealing resin 140 that seals the sensor element 100, and terminals 151 to 154 that are connected to the first to fourth conductive layers 131 to 134, respectively. The sealing resin 140 fills the recess 123 and covers the first substrate surface 121. The sealing resin 140 is made of, for example, epoxy resin. The sealing resin 140 includes a sealing surface 141 that forms the mounting surface of the sensor chip 50.

[0183] The terminals 151 to 154 are provided so as to be exposed from the sealing surface 141. The terminals 151 to 154 include a columnar conductor portion 155 that penetrates the portion of the sealing resin 140 that covers the first substrate surface 121 in the Z direction, and a joint portion 156 that is connected to the columnar conductor portion 155 and protrudes from the sealing surface 141.

[0184] The columnar conductor portion 155 of the terminal 151 is connected to a portion of the first conductive layer 131 that is provided on the first substrate surface 121. The columnar conductor portion 155 of the terminal 152 is connected to a portion of the second conductive layer 132 that is provided on the first substrate surface 121. The columnar conductor portion 155 of the terminal 153 is connected to a portion of the third conductive layer 133 that is provided on the first substrate surface 121. The columnar conductor portion 155 of the terminal 154 is connected to a portion of the fourth conductive layer 134 that is provided on the first substrate surface 121. When the sensor chip 50 is mounted on the first substrate surface 20S of the substrate 20 (see FIG. 1), the bonding portions 156 of the terminals 151 to 154 are individually mounted on the first to fourth sensor patterns 71 to 74 (see FIG. 1).

[0185] 23 and 24, the sensor element 100 may have the same configuration as the sensor chip 50 of the first embodiment. In this case, the terminals 61 to 64 are individually bonded to the first to fourth conductive layers 131 to 134. In one example, the terminal 61 is bonded to the first conductive layer 131. The terminal 62 is bonded to the second conductive layer 132. The terminal 63 is bonded to the third conductive layer 133. The terminal 64 is bonded to the fourth conductive layer 134.

[0186] In each embodiment, the positional relationship between the first detection element 51 and the second detection element 52 and the detection pattern 43 in a plan view can be changed as desired. For example, the first detection element 51 may be disposed between the center of the detection pattern 43 in the X direction and one edge in the X direction in a plan view. In other words, the first detection element 51 does not have to be disposed so as to straddle one edge in the X direction of the detection pattern 43. For example, the second detection element 52 may be disposed between the center of the detection pattern 43 in the X direction and the other edge in the X direction in a plan view. In other words, the second detection element 52 does not have to be disposed so as to straddle one edge in the X direction of the detection pattern 43.

[0187] In each embodiment, one of the first detection element 51 and the second detection element 52 may be omitted. In this case, the position of the remaining detection element can be changed as desired within the range in which the magnetic field of the detection pattern 43 can be detected.

[0188] One or more of the various examples described in the present disclosure may be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0189] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described in this disclosure being "up" and "down" of the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0190] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0191] [Appendix 1] a substrate (20) including a first substrate surface (20S) and a second substrate surface (20R) opposite to the first substrate surface (20S); a wiring pattern (30) including a first wiring pattern (31) provided on the first substrate surface (20S); a sensor chip (50) used to detect a current flowing through the wiring pattern (30); Including, the first wiring pattern (31) includes a detection pattern (43) having a predetermined width; The sensor chip (50) is mounted on the first substrate surface (20S) in a state in which the sensor chip (50) is disposed so as to straddle the detection pattern (43), The sensor chip (50) includes a detection element (51 / 52) that detects a magnetic field generated by a current flowing through the detection pattern (43). A semiconductor device (10).

[0192] [Appendix 2] The detection elements (51 / 52) are provided on both sides of the detection pattern (43) in the width direction (X) of the detection pattern (43) when viewed from the thickness direction (Z) of the substrate (20), and include a first detection element (51) and a second detection element (52) that are arranged opposite each other in the width direction (X) across the detection pattern (43). 2. The semiconductor device according to claim 1.

[0193] [Appendix 3] A gap (GP) is provided between the sensor chip (50) and the detection pattern (43) in the thickness direction (Z) of the substrate (20). 3. The semiconductor device according to claim 1 or 2.

[0194] [Appendix 4] The distance (DA) between the detection element (51 / 52) and the detection pattern (43) in the thickness direction (Z) of the substrate (20) is smaller than the thickness (TC) of the detection pattern (43). 4. The semiconductor device according to claim 3.

[0195] [Appendix 5] The first wiring pattern (31) is a first pattern (41) extending in a first direction (Y); a second pattern (42) provided at a position spaced apart from the first pattern (41) in the first direction (Y) and extending in the first direction (Y); the detection pattern (43) provided between the first pattern (41) and the second pattern (42) and connecting the first pattern (41) and the second pattern (42); Including, The first pattern (41) has a first width (W1) that is a length in a second direction (X) perpendicular to the first direction (Y) when viewed from the thickness direction (Z) of the substrate (20), The second pattern (42) has a second width (W2) that is a length in the second direction (X), The detection pattern (43) has a connection width (WC) that is a length in the second direction (X), The connection width (WC) is narrower than the first width (W1) and the second width (W2), The sensor chip (50) is mounted on the first substrate surface (20S) in a state where it is arranged so as to straddle the detection pattern (43). 5. The semiconductor device according to any one of claims 1 to 4.

[0196] [Appendix 6] The length (LC) of the detection pattern (43) in the first direction (Y) is shorter than the length (L1) of the first pattern (41) in the first direction (Y) and the length (L2) of the second pattern (42) in the first direction (Y). 6. The semiconductor device according to claim 5.

[0197] [Appendix 7] The first pattern (41) is a first portion (41A) having the first width (W1); a second portion (41B) that narrows from the first portion (41A) toward the detection pattern (43); Contains 7. The semiconductor device according to claim 5 or 6.

[0198] [Appendix 8] The second pattern (42) is a first portion (42A) having the second width (W2); a second portion (42B) that narrows from the first portion (42A) toward the detection pattern (43); Contains 8. The semiconductor device according to any one of claims 5 to 7.

[0199] [Appendix 9] The sensor chip (50) includes a plurality of terminals (61 to 64), The sensor chip (50) is arranged so that the plurality of terminals (61 to 64) are arranged in a space (SP) provided in the second direction (X) of the detection pattern (43). 9. The semiconductor device according to any one of claims 5 to 8.

[0200] [Appendix 10] When viewed from the first direction (Y), the plurality of terminals (61 to 64) are arranged inside the outer edges of the first pattern (41) and the second pattern (42). 10. The semiconductor device according to claim 9.

[0201] [Appendix 11] a plurality of sensor patterns (71-74) provided on the first substrate surface (20S) and to which the plurality of terminals (61-64) are individually connected; The upper surfaces (71S to 74S) of the plurality of sensor patterns (71 to 74) are located closer to the first substrate surface (20S) than the upper surface (43S) of the detection pattern (43). 11. The semiconductor device according to claim 9 or 10.

[0202] [Appendix 12] The substrate (20) is a multilayer substrate, The substrate (20) is provided with heat dissipation patterns (32-34) insulated from the first wiring pattern (31), The heat dissipation patterns (32 to 34) have a heat dissipation width (WP) that is larger than both the first width (W1) and the second width (W2). 12. The semiconductor device according to any one of claims 5 to 11.

[0203] [Appendix 13] The substrate (20) is a first substrate (21) including the first substrate surface (20S); a second substrate (22) including the second substrate surface (20R); a third substrate (23) provided between the first substrate (21) and the second substrate (22); Including, The heat dissipation pattern is a first heat dissipation pattern (32) provided between the first base material (21) and the third base material (23); a second heat dissipation pattern (33) provided between the second base material (22) and the third base material (23); a third heat dissipation pattern (34) provided on the second substrate surface (20R); Contains 13. The semiconductor device according to claim 12.

[0204] [Appendix 14] The substrate (20) is a multilayer substrate including a laminated structure in which a first substrate (21) and a second substrate (22) are laminated, the first base material (21) includes the first substrate surface (20S), the second base material (22) includes the second substrate surface (20R), the wiring pattern (30) is provided between the first substrate (21) and the second substrate (22) and includes a second wiring pattern (35) electrically connected to the first wiring pattern (31); Each of the first wiring pattern (31) and the second wiring pattern (35) includes the first pattern (41), the second pattern (42), and the detection pattern (43). 12. The semiconductor device according to any one of claims 5 to 11.

[0205] [Appendix 15] The wiring pattern (30) includes at least one through hole (36) that connects the first wiring pattern (31) and the second wiring pattern (32) in the thickness direction (Z) of the substrate (20). 15. The semiconductor device according to claim 14.

[0206] [Appendix 16] The through-hole (36) is not provided in the detection pattern (43), but is provided in at least one of the first pattern (41) and the second pattern (42). 16. The semiconductor device according to claim 15.

[0207] [Appendix 17] The substrate (20) includes a third base material (23) provided between the first base material (21) and the second base material (22), the second wiring pattern (35) is provided between the first base material (21) and the third base material (23), a second heat dissipation pattern (33) provided between the second base material (22) and the third base material (23); a third heat dissipation pattern (34) provided on the second substrate surface (20R); Including, Both the second heat dissipation pattern (33) and the third heat dissipation pattern (34) have a heat dissipation width (WP) greater than both the first width (W1) and the second width (W2). 17. The semiconductor device according to any one of claims 14 to 16.

[0208] [Appendix 18] The sensor chip (50) a third detection element (53) arranged alongside the first detection element (51) in the direction (Y) in which the detection pattern (43) extends; a fourth detection element (54) arranged at the same position as the third detection element (53) and alongside the second detection element (52) in the direction (Y) in which the detection pattern (43) extends; Contains 3. The semiconductor device according to claim 2.

[0209] [Appendix 19] The semiconductor device (10) is used when the current flowing through the detection pattern (43) is 10 A or more. 19. The semiconductor device according to any one of appendices 1 to 18.

[0210] [Appendix 20] The detection element (51 / 52) is a Hall element 20. The semiconductor device according to any one of appendices 1 to 19.

[0211] [Appendix 21] The upper surfaces (71S to 74S) of the plurality of sensor patterns (71 to 74) are flush with the first substrate surface (20S). 12. The semiconductor device according to claim 11.

[0212] [Appendix 22] The first width (W1) of the first pattern (41) is equal to the second width (W2) of the second pattern (42). 18. The semiconductor device according to any one of claims 13 to 17.

[0213] [Appendix 23] Both the second heat dissipation pattern (33) and the third heat dissipation pattern (34) are electrically insulated from both the first wiring pattern (31) and the second wiring pattern (35). 18. The semiconductor device according to claim 17.

[0214] [Appendix 24] The package structure of the sensor chip (50) is WLCSP. 12. The semiconductor device according to claim 11.

[0215] [Appendix 25] The sensor chip (50) A semiconductor substrate (55); a semiconductor layer (56) provided on the semiconductor substrate (55); Including, The detection element (51 / 52) is provided on the semiconductor layer (56), the semiconductor layer (56) is disposed closer to the detection pattern (43) than the semiconductor substrate (55); The plurality of terminals (61 to 64) are provided on the semiconductor layer (56) on the opposite side to the semiconductor substrate (55). 25. The semiconductor device according to claim 24.

[0216] [Appendix 26] The plurality of terminals (61 to 64) are arranged on both sides of the detection pattern (43) in the width direction (X) of the detection pattern (43). 26. The semiconductor device according to claim 24 or 25.

[0217] [Appendix 27] The package structure of the sensor chip (50) is SOP. 12. The semiconductor device according to claim 11.

[0218] [Appendix 28] The sensor chip (50) A semiconductor substrate (55); a semiconductor layer (56) provided on the semiconductor substrate (55); a sealing resin (90) that seals the semiconductor substrate (55) and the semiconductor layer (56); Including, The detection element (51 / 52) is provided on the semiconductor layer (56). 28. The semiconductor device according to claim 27.

[0219] [Appendix 29] The sensor chip (50) a third detection element (53) arranged alongside the first detection element (51) on the opposite side of the first detection element (51) from the second detection element (52) in the width direction (X); a fourth detection element (54) arranged alongside the second detection element (52) on the opposite side of the first detection element (51) with respect to the second detection element (52) in the width direction (X); Contains 3. The semiconductor device according to claim 2.

[0220] [Appendix 30] the third detection element (53) is disposed outward of the detection pattern (43) in the width direction (X); The fourth detection element (54) is disposed outward of the detection pattern (43) in the width direction (X). 30. The semiconductor device according to claim 29.

[0221] [Appendix 31] The sensor chip (50) includes an arithmetic circuit (80) configured to output a signal according to the outputs from the first detection element (51) and the second detection element (52). 3. The semiconductor device according to claim 2.

[0222] [Appendix 32] The arithmetic circuit (80) is configured to output a signal corresponding to the value of the current flowing through the detection pattern (43) based on the difference between the output voltage of the first detection element (51) and the output voltage of the second detection element (52). 32. The semiconductor device according to claim 31.

[0223] [Appendix 33] the sensor chip (50) includes an arithmetic circuit (80) configured to output a signal according to outputs from the first detection element (51), the second detection element (52), the third detection element (53), and the fourth detection element (54); The arithmetic circuit (80) is configured to output a signal corresponding to the value of the current flowing through the detection pattern (43) based on an average value of the difference between the output voltage of the first detection element (51) and the output voltage of the second detection element (52) and the difference between the output voltage of the third detection element (53) and the output voltage of the fourth detection element (54). 19. The semiconductor device according to claim 18.

[0224] [Appendix 34] The arithmetic circuit (80) a subtraction circuit (82) that calculates the difference between the output voltage of the first detection element (51) and the output voltage of the second detection element (52); a signal processing circuit (84) for converting an analog signal into a digital signal; an analog front end (83) connecting the subtraction circuit (82) and the signal processing circuit (84); Contains 33. The semiconductor device according to claim 31 or 32.

[0225] [Appendix 35] The sensor chip (50) A semiconductor substrate (55); a semiconductor layer (56) provided on the semiconductor substrate (55); Including, Both the detection element (51 / 52) and the arithmetic circuit (80) are provided in the semiconductor layer (56). 35. The semiconductor device according to any one of claims 31 to 34.

[0226] [Appendix 36] The semiconductor device (10) is used when the current flowing through the detection pattern (43) is 20 A or more. 19. The semiconductor device according to any one of appendices 1 to 18.

[0227] [Appendix 37] A sensor chip (50) is used to detect a current flowing in a wiring pattern (30) provided on a first substrate surface (20S) of a substrate, and is mounted on the first substrate surface (20S) in a state in which the sensor chip is disposed across a detection pattern (43) of the wiring pattern (30), The detecting element (51 / 52) detects a magnetic field generated by a current flowing through the detecting pattern (43). A sensor chip (50).

[0228] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0229] 10, 10A, 10B, 10U, 10W...Semiconductor device 20...Substrate 20S...1st board surface 20R...Second board surface 21...First base material 22…Second base material 23…Third base material 30, 30A, 30B...wiring pattern 31...First wiring pattern 32...First heat dissipation pattern 33...Second heat dissipation pattern 34...Third heat dissipation pattern 35...Second wiring pattern 36...Through hole 41...First pattern 41A…First part 41B…Second part 42...Second pattern 42A…First part 42B…Second part 43...Detection pattern 43S…Top surface 44...recess 50, 50A, 50B, 50U, 50W...sensor chip 50S...First chip side 50R...Second chip surface 51...First detection element (detection element) 52...Second detection element (detection element) 53...Third detection element 54...Fourth detection element 55...Semiconductor substrate 56...Semiconductor layer 57...insulating layer 58...Wiring 59...Pad 61 to 64: Sensor chip terminals 71, 71A, 71B...First sensor pattern 71S…Top surface 72, 72A, 72B... Pattern for second sensor 72S…Top surface 73, 73A, 73B...Third sensor pattern 73S…Top surface 74, 74A, 74B...Fourth sensor pattern 74S…Top surface 75A~78A, 75B~78B...1st to 4th lands 79...Pull-up resistor 80...Arithmetic circuit 81...Bias circuit 82...Subtraction circuit 83…Analog Front End (AFE) 84...Signal processing circuit 90...Sealing resin 91...First sealing surface 92…Second sealing surface 100...sensor element 110...Die pad 120...Insulating substrate 121...First board surface 122...Second board surface 123...recess 124...Bottom 131 to 134...First to fourth conductive layers 140…Sealing resin 141...Sealing surface 151~154...Terminals 155...Columnar conductor part 156…Joint part 200...Inverter device 210...Power supply section 220...Main control unit 230...Gate drive circuit 240...U-phase arm section 241, 242...Switching elements 250...V-phase arm 251, 252...Switching elements 260...W-phase arm section 261, 262...Switching elements 270...Temperature sensor 280... Circuit board 281...U phase wiring 281A…1st wiring section 281B…Second wiring section 281C...Third wiring section 281D...4th wiring section 281E…Land pattern 282…V phase wiring 282A…1st wiring section 282B…Second wiring section 282C...Third wiring section 282D…4th wiring section 282E…Land pattern 283…W phase wiring 283A…1st wiring section 283B…Second wiring section 283C…Third wiring section 283D…4th wiring section 283E…Land pattern 291U~294U, 291W~294W...Sensor pattern 300…DC power supply CU...U-phase coil CV...V-phase coil CW...W-phase coil SD: Conductive adhesive N1~N3...Nodes W1…1st width W2...Second width WP…heat dissipation width WC…Connection width WR...Wire TC: Thickness of detection pattern TS: thickness of each of the first sensor pattern and the second sensor pattern DA: Distance between the sensor chip and the detection pattern LC: Length of the detection pattern in the first direction L1: Length of the first pattern in the first direction L2: Length of the second pattern in the first direction SP...Space GP: Gap between the sensor chip and the detection pattern

Claims

1. a substrate including a first substrate surface and a second substrate surface opposite the first substrate surface; a wiring pattern including a first wiring pattern provided on the first substrate surface; a sensor chip used to detect a current flowing through the wiring pattern; Including, the first wiring pattern includes a detection pattern having a predetermined width; the sensor chip is mounted on the first substrate surface in a state in which the sensor chip is disposed across the detection pattern, The sensor chip includes a detection element that detects a magnetic field generated by a current flowing through the detection pattern. Semiconductor device.

2. The detection elements include a first detection element and a second detection element that are provided on both sides of the detection pattern in a width direction of the detection pattern when viewed from the thickness direction of the substrate and are arranged opposite to each other in the width direction with the detection pattern interposed therebetween. The semiconductor device according to claim 1 .

3. A gap is provided between the sensor chip and the detection pattern in the thickness direction of the substrate. The semiconductor device according to claim 1 .

4. The distance between the detection element and the detection pattern in the thickness direction of the substrate is smaller than the thickness of the detection pattern. The semiconductor device according to claim 3 .

5. The first wiring pattern is a first pattern extending in a first direction; a second pattern provided at a position spaced apart from the first pattern in the first direction and extending in the first direction; the detection pattern is provided between the first pattern and the second pattern and connects the first pattern and the second pattern; Including, the first pattern has a first width that is a length in a second direction perpendicular to the first direction when viewed from the thickness direction of the substrate; the second pattern has a second width that is a length in the second direction; the detection pattern has a connection width that is a length in the second direction; the connection width is narrower than the first width and the second width; The sensor chip is mounted on the first substrate surface in a state where it is arranged so as to straddle the detection pattern. The semiconductor device according to claim 1 .

6. The length of the detection pattern in the first direction is shorter than the length of the first pattern in the first direction and the length of the second pattern in the first direction. The semiconductor device according to claim 5 .

7. The first pattern is a first portion having the first width; a second portion that narrows from the first portion toward the detection pattern; Contains The semiconductor device according to claim 5 .

8. The second pattern is a first portion having the second width; a second portion that narrows from the first portion toward the detection pattern; Contains The semiconductor device according to claim 5 .

9. the sensor chip includes a plurality of terminals; The sensor chip is arranged so that the plurality of terminals are arranged in spaces provided in the second direction of the detection pattern. The semiconductor device according to claim 5 .

10. When viewed from the first direction, the plurality of terminals are arranged inside outer edges of the first pattern and the second pattern. The semiconductor device according to claim 9 .

11. a plurality of sensor patterns provided on the first substrate surface and connected to the plurality of terminals individually; An upper surface of each of the plurality of sensor patterns is located closer to the first substrate surface than an upper surface of the detection pattern. The semiconductor device according to claim 9 .

12. the substrate is a multilayer substrate, a heat dissipation pattern insulated from the first wiring pattern is provided within the substrate; The heat dissipation pattern has a heat dissipation width greater than both the first width and the second width. The semiconductor device according to claim 5 .

13. The substrate is a first substrate including the first substrate surface; a second substrate including the second substrate surface; a third substrate provided between the first substrate and the second substrate; Including, The heat dissipation pattern is a first heat dissipation pattern provided between the first base material and the third base material; a second heat dissipation pattern provided between the second base material and the third base material; a third heat dissipation pattern provided on the second substrate surface; Contains The semiconductor device according to claim 12.

14. the substrate is a multilayer substrate including a laminated structure in which a first substrate and a second substrate are laminated, the first substrate includes the first substrate surface; the second substrate includes the second substrate surface; the wiring pattern includes a second wiring pattern provided between the first base material and the second base material and electrically connected to the first wiring pattern; Including, Each of the first wiring pattern and the second wiring pattern includes the first pattern, the second pattern, and the detection pattern. The semiconductor device according to claim 5 .

15. The wiring pattern includes at least one through hole that connects the first wiring pattern and the second wiring pattern in the thickness direction of the substrate. The semiconductor device according to claim 14.

16. The through-hole is not provided in the detection pattern, but is provided in at least one of the first pattern and the second pattern. The semiconductor device according to claim 15.

17. the substrate includes a third substrate provided between the first substrate and the second substrate, the second wiring pattern is provided between the first base material and the third base material, a second heat dissipation pattern provided between the second base material and the third base material; a third heat dissipation pattern provided on the second substrate surface; Including, Both the second heat dissipation pattern and the third heat dissipation pattern have a heat dissipation width greater than both the first width and the second width. The semiconductor device according to claim 14.

18. The sensor chip comprises: a third detection element arranged alongside the first detection element in the extension direction of the detection pattern; a fourth detection element disposed at the same position as the third detection element and alongside the second detection element in the direction in which the detection pattern extends; Contains The semiconductor device according to claim 2 .

19. The semiconductor device is used when the current flowing through the detection pattern is 10 A or more. The semiconductor device according to claim 1 .

20. The detection element is a Hall element. The semiconductor device according to any one of claims 1 to 19.

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