Semiconductor device and manufacturing method

Abstract

To provide a semiconductor device capable of reducing a source contact resistance.SOLUTION: A semiconductor device includes: a first electrode; a second electrode disposed separately from the first electrode in a first direction; a control electrode disposed to face the second electrode in a second direction intersecting the first direction; a first insulating portion provided between the second electrode and the control electrode; a semiconductor layer provided between the first electrode and the second electrode; a first region provided between the second electrode and the first insulating portion in the semiconductor layer and connected to the second electrode by a Schottky junction; and a second region joined to the first region, disposed on the first electrode side, connected to the second electrode by a Schottky junction, and having a smaller width in the second direction than at least a part of the first region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] In a semiconductor device that switches between an on state and an off state by controlling the height of the Schottky barrier with a voltage applied to a gate electrode, it is preferable that the source contact resistance is low. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-22074 [Patent Document 2] Japanese Patent Publication No. 2023-60154 [Patent Document 3] Japanese Patent Application Publication No. 2023-136874 [Patent Document 4] Japanese Patent Publication No. 2021-150483 [Patent Document 5] Japanese Patent Publication No. 2020-43243 [Patent Document 6] Japanese Patent Application Laid-Open No. 2019-3968 [Patent Document 7] Special Publication No. 2008-536316 [Patent Document 8] Japanese Patent Application Laid-Open No. 2011-9387 [Patent Document 9] Japanese Patent Application Laid-Open No. 2011-181840 Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE INVENTION An embodiment of the present invention provides a semiconductor device capable of reducing source contact resistance. [Means for solving the problem]

[0005] The semiconductor device according to this embodiment includes a first electrode and a second electrode disposed spaced apart from the first electrode in a first direction; a control electrode disposed opposite the second electrode in a second direction intersecting the first direction; a first insulating portion provided between the second electrode and the control electrode; a semiconductor layer provided between the first electrode and the second electrode; a first region provided between the second electrode and the first insulating portion in the semiconductor layer and connected to the second electrode by a Schottky junction; The semiconductor device further comprises a second region joined to the first region and disposed on the first electrode side, connected to the second electrode by a Schottky junction, and having a width in the second direction narrower than at least a portion of the first region. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is an enlarged view of the pillar portion and the surrounding area of ​​FIG. [Figure 3] 1 is a schematic diagram of a three-dimensional structure of a semiconductor device according to an embodiment of the present disclosure. [Figure 4A] 1A to 1C are diagrams illustrating a process for forming a field plate of a semiconductor device according to an embodiment of the present disclosure. [Figure 4B] 3A to 3C illustrate a first oxidation step of a semiconductor layer of a semiconductor device according to an embodiment of the present disclosure. [Figure 4C] 3A to 3C are diagrams illustrating a first film formation step of an insulating film of a semiconductor element according to an embodiment of the present disclosure. [Figure 4D] 6A to 6C are diagrams illustrating a second step of forming an insulating film of a semiconductor element according to an embodiment of the present disclosure. [Figure 4E] 3A to 3C illustrate a first etching back step of an insulating film of a semiconductor element according to an embodiment of the present disclosure. [Figure 4F] 3A to 3C are diagrams illustrating a first step of removing an insulating film of a semiconductor element according to an embodiment of the present disclosure. [Figure 4G] 10A to 10C are diagrams illustrating a second step of removing an insulating film of a semiconductor element according to an embodiment of the present disclosure. [Figure 4H] 6A and 6B illustrate a second oxidation step of the semiconductor layer of the semiconductor device according to the embodiment of the present disclosure. [Figure 4I] 10A to 10C are diagrams illustrating a third step of removing an insulating film of a semiconductor element according to an embodiment of the present disclosure. [Figure 4J] 1A to 1C are diagrams illustrating a half-etchback process of an insulating film of a semiconductor device according to an embodiment of the present disclosure. [Figure 4K] 1A to 1C illustrate a process for forming a body region of a semiconductor device according to an embodiment of the present disclosure. [Figure 4L] 6A and 6B illustrate a third oxidation step of the semiconductor layer of the semiconductor device according to the embodiment of the present disclosure. [Figure 4M] 1A to 1C are diagrams illustrating a process for forming a control electrode of a semiconductor element according to an embodiment of the present disclosure. [Figure 4N] 1A to 1C are diagrams illustrating an etching back process of a control electrode of a semiconductor device according to an embodiment of the present disclosure. [Figure 4O] 6A to 6C are diagrams illustrating a step of forming a second insulating section of a semiconductor element according to an embodiment of the present disclosure. [Figure 4P] 1A to 1C illustrate an etch-back process of an insulating portion of a semiconductor device according to an embodiment of the present disclosure. [Figure 4Q] 5A to 5C are diagrams illustrating a first step of forming a mesa portion of a semiconductor element according to an embodiment of the present disclosure. [Figure 4R] 6A to 6C are diagrams illustrating a second step of forming a mesa portion of a semiconductor element according to an embodiment of the present disclosure. [Figure 4S] 10A and 10B illustrate a fourth oxidation step of the semiconductor layer of the semiconductor element according to the embodiment of the present disclosure. [Figure 4T] 1A and 1B are diagrams illustrating a process of doping impurities and thermal diffusion of a semiconductor device according to an embodiment of the present disclosure. [Figure 4U] 10A to 10C are diagrams illustrating a third step of forming an insulating film of a semiconductor element according to an embodiment of the present disclosure. [Figure 4V] 10A to 10C illustrate a second etching back step of an insulating film of a semiconductor element according to an embodiment of the present disclosure. [Figure 4W] 1A to 1C illustrate a process for forming a trench in a semiconductor device according to an embodiment of the present disclosure. [Figure 4X] 1A to 1C are diagrams illustrating an etching step of an insulating portion of a semiconductor element according to an embodiment of the present disclosure. [Figure 4Y] 3A to 3C are diagrams illustrating a metal film formation step for a first metal layer of a semiconductor element according to an embodiment of the present disclosure. [Figure 4Z] 10A to 10C are diagrams illustrating a metal deposition step for a second metal layer of a semiconductor element according to an embodiment of the present disclosure. [Figure 5A] FIG. 1 is a first diagram illustrating a configuration of a semiconductor device according to a comparative example. [Figure 5B] FIG. 2 is a second diagram illustrating the configuration of a semiconductor device according to a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments do not limit the present invention. The drawings are schematic or conceptual, and the proportions of each part are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0008] For ease of explanation, an XYZ Cartesian coordinate system is adopted, as shown in FIG. 1 etc. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device. The Y-axis direction is one of the planar directions of the semiconductor device, more specifically, the direction in which multiple semiconductor elements are arranged. In addition, in the Z-axis direction, the source electrode side is also referred to as "upper" and the drain electrode side is also referred to as "lower." However, these expressions are for convenience and are unrelated to the direction of gravity. In this specification, the Z-axis direction, Y-axis direction, and X-axis direction are also referred to as the first direction Z, the second direction Y, and the third direction X, respectively.

[0009] In the following description, n is used to indicate the relative level of impurity concentration in each conductivity type. + , n, n - , and ,p + , p, p- In some cases, the notation n + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than p. When both p-type and n-type impurities are contained in each region, these notations indicate the relative level of the net impurity concentration after the impurities compensate for each other. In this specification, n-type, n + Shape and n - In this specification, the terms p-type, p-type, and p-type are also used. + Shape and p - The n-type and p-type may be reversed in the following description.

[0010] The impurity concentration of a semiconductor region can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS), and the relative level of the impurity concentration can be determined from the carrier concentration determined by, for example, Scanning Capacitance Microscopy (SCM).

[0011] Furthermore, dimensions such as the width of the contact portion can be measured by surface and / or cross-sectional analysis using, for example, a transmission electron microscope (TEM), energy dispersive X-ray spectroscopy (EDX), or a scanning electron microscope (SEM).

[0012] The composition of the conductive portion can be analyzed by energy dispersive X-ray spectroscopy.

[0013] (Embodiments of the present disclosure) 1 is a schematic cross-sectional view illustrating a semiconductor device 1 according to an embodiment of the present disclosure. The semiconductor device 1 in FIG. 1 has one or more semiconductor elements 10. Each semiconductor element 10 includes a first electrode 11, a second electrode 12, a control electrode 13, a first insulating portion 21, and a semiconductor layer 30. The semiconductor element 10 may further include a conductive portion 16, an interlayer film 17, and a second insulating portion 22.

[0014] The semiconductor element 10 according to this embodiment is a vertical transistor. More specifically, the semiconductor element 10 is a vertical MOSFET (Metal Oxide Silicon Field Effect Transistor) that switches between an on state and an off state by controlling the potential of a gate electrode (a control electrode 13 described later) to control the thickness of a Schottky barrier.

[0015] The vertical direction and horizontal direction in FIG. 1 correspond to the first direction Z and second direction Y, respectively.

[0016] The semiconductor layer 30 may be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate and an epitaxial layer disposed on the semiconductor substrate. In this specification, an example in which the semiconductor layer 30 is made of Si will be described. In this case, for example, As, P, or Sb is used as the n-type impurity (hereinafter also referred to as a donor) doped into the semiconductor layer 30, and for example, B is used as the p-type impurity (hereinafter also referred to as an acceptor). The semiconductor layer 30 may also be made of a compound semiconductor such as SiC or GaN.

[0017] The first electrode 11 is disposed on the first surface A1 side of the semiconductor layer 30. The first electrode 11 is electrically connected to the semiconductor layer 30. The first electrode 11 is made of, for example, Cu, Ti, W, or Al. The first electrode 11 is, for example, a drain electrode of the semiconductor element 10.

[0018] The second electrode 12 is disposed apart from the first electrode 11 in the first direction Z. The second electrode 12 is disposed on the second surface side A2 of the semiconductor layer 30 and has a protrusion 23 extending toward the first surface A1. The second electrode 12 may further include a first metal layer 14 and a second metal layer 15 that are stacked on top of each other. The second electrode 12 is, for example, a source electrode of the semiconductor element 10.

[0019] The semiconductor element 10 may have a configuration in which the first electrode 11 is a source electrode and the second electrode 12 is a drain electrode.

[0020] The first metal layer 14 includes a first metal element, such as at least one of Ti, W, Mo, Ta, Zr, Al, Sn, V, Re, Os, Ir, Pt, Pd, Rh, Ru, Nb, Sr, Co, and Hf (e.g., Co or Pt). The first metal layer 14 may be a metal layer doped with an impurity.

[0021] The second metal layer 15 is disposed so as to cover the first metal layer 14. The second metal layer 15 includes a second metal element having a lower work function than the first metal element. The second metal element is, for example, at least one of Al, Cu, Mo, W, Ta, Co, Ru, Ti, and Pt (for example, W).

[0022] The control electrode 13 is disposed opposite the second electrode 12 (source electrode) in the second direction Y. The control electrode 13 is made of, for example, polysilicon. The control electrode 13 is, for example, a gate electrode of the semiconductor element 10 that controls the current flowing between the first electrode 11 and the second electrode 12.

[0023] The first insulating portion 21 is disposed between the control electrode 13 and the protruding portion 23 of the second electrode 12. More specifically, the first insulating portion 21 is disposed so as to surround the control electrode 13, the interlayer film 17, and the conductive portion 16, and insulates the control electrode 13 from the semiconductor layer 30. The first insulating portion 21 is made of, for example, SiO2. A portion of the first insulating portion 21 is used, for example, as a gate insulating film.

[0024] The second insulating portion 22 is disposed adjacent to the control electrode 13 and on the second surface A2 side of the control electrode 13. More specifically, the second insulating portion 22 is disposed between the control electrode 13 and the second electrode 12, and insulates the control electrode 13 from the second electrode 12. The second insulating portion 22 is made of, for example, SiO2.

[0025] The control electrode 13 and a part of the second insulating portion 22 form a cylindrical shape.

[0026] The semiconductor layer 30 is in contact with the first electrode 11 and is electrically connected to the first electrode 11. In this specification, an example in which the semiconductor layer 30 is made of an n-type (first conductivity type) semiconductor will be described, but the semiconductor layer 30 may also be made of a p-type (second conductivity type) semiconductor.

[0027] The semiconductor layer 30 has a pillar portion 40 disposed between the protrusion 23 of the second electrode 12 and the first insulating portion 21. The pillar portion 40 has a first region 41 disposed on the second surface A2 side, and a second region 42 bonded to the first region 41 and disposed on the first surface A1 side. The first region 41 and the second region 42 are connected to the first metal layer 14 in the second electrode 12 (source electrode) by a Schottky junction. The first region 41 is used, for example, as a source contact region. The second region 42 is used, for example, as a channel region.

[0028] The control electrode 13 can control the current flowing between the first electrode 11 and the second electrode 12. For example, a Schottky barrier is formed at the interface between the second electrode 12 and the second region 42, and a depletion layer is formed in the second region 42. The height of the Schottky barrier is controlled by the voltage applied to the control electrode 13, and the carrier concentration in the second region 42 is controlled. When the voltage of the control electrode 13 is equal to or lower than the threshold, no current flows between the first electrode 11 and the second electrode 12 via the second region 42, i.e., the semiconductor device 10 is in an off state. When the voltage of the control electrode 13 exceeds the threshold, a current flows between the first electrode 11 and the second electrode 12 via the second region 42, i.e., the semiconductor device 10 is in an on state.

[0029] Fig. 2 is an enlarged view of region B in Fig. 1. Fig. 2 illustrates the control electrode 13, the first insulating portion 21, the second insulating portion 22, the protrusion 23 of the second electrode 12, and the pillar portion 40 of the semiconductor layer 30.

[0030] As shown in FIG. 2, the interface A3 between the first region 41 and the second region 42 is located closer to the first surface A1 (ie, lower in FIG. 2) than the interface A4 between the control electrode 13 and the first insulating portion 21.

[0031] 2, the first region 41 has a width d1 in the second direction Y of a portion (region 43) facing the second insulating portion 22 that is wider than the width d2 of the second region 42. This allows the Schottky barrier b1 generated at the interface between the first region 41 and the first metal layer 14 to be lower than the Schottky barrier b2 generated at the interface between the second region 42 and the first metal layer 14.

[0032] The above-mentioned region 43 can be formed, for example, by making the width d3 of the control electrode 11 in the second direction Y larger than the width d4 of at least a portion of the second insulating portion 22 facing the second electrode 12 in the second direction Y; in other words, by forming a cylindrical shape with the control electrode 11 and a portion of the second insulating portion 22.

[0033] By increasing the Schottky barrier b2 in the second region 42, the threshold voltage of the semiconductor element 10 can be increased. This allows the semiconductor element 10 to be configured as a normally-off MOSFET. On the other hand, by decreasing the Schottky barrier b1 in the first region 41, the source contact resistance of the semiconductor element 10 can be reduced, and the on-resistance of the semiconductor element 10 can be reduced. This allows for faster switching of the semiconductor element 10, and suppression of turn-on loss and turn-off loss.

[0034] That is, as shown in FIG. 2, by making the width d1 of the first region 41 wider than the width d2 of the second region 42, the Schottky barriers b1 and b2 can be adjusted, thereby achieving both an increase in the threshold voltage of the semiconductor element 10 and a reduction in the on-resistance.

[0035] The Schottky barriers b1 and b2 can also be adjusted by the impurities doped into the first region 41 and the second region 42.

[0036] The first region 41 and the second region 42 are each doped with an impurity (donor). The impurity doped into the first region 41 and the second region 42 is, for example, at least one of As, P, Sb, and Mg (for example, As). Note that when the semiconductor layer 30 is a p-type semiconductor, the semiconductor layer 30 may be doped with an acceptor (for example, B, In, Al, or Be) as the impurity.

[0037] By making the impurity concentration of the first region 41 higher than that of the second region 42, the Schottky barrier b1 can be made lower than the Schottky barrier b2. The first region 41 and the second region 42 may be doped with different impurities. For example, the first region 41 may be doped with the above-mentioned donor, and the second region 42 may be doped with the above-mentioned acceptor.

[0038] 1 may be electrically connected to the first metal layer 14 and the second metal layer 15 by a conductive portion (wiring or the like) not shown. Alternatively, a switching element or the like may be used to switch whether or not the conductive portion 16 is electrically connected to the first metal layer 14 and the second metal layer 15. The conductive portion 16 in FIG. 1 is used, for example, as a field plate, and suppresses local concentration of the electric field in the semiconductor element 10, stabilizing the operation of the semiconductor element 10.

[0039] The interlayer film 17 is made of, for example, SiO2.

[0040] 3 is a schematic diagram of a three-dimensional structure of a semiconductor device 1 according to an embodiment of the present disclosure. A third direction X intersecting the first direction Z and the second direction Y is illustrated in FIG. 3. The semiconductor device 1 may have, for example, a stripe structure in which the semiconductor elements 10 extend in the third direction X. Alternatively, the semiconductor device 1 may have a dot structure in which multiple semiconductor elements 10 are arranged in the third direction X.

[0041] 4A to 4Z are diagrams illustrating a manufacturing process of a semiconductor device 10 according to an embodiment of the present disclosure. FIG. 4A is a diagram illustrating a process of forming a field plate. In FIG. 4A, the semiconductor layer 30 is etched from the surface A5 side to form a trench (first trench) 51. Furthermore, a first insulating portion 21, a conductive portion 16, and an interlayer film 17 are buried in a portion of the trench 51. The sidewall portion of the trench 51 corresponds to the pillar portion 40 in FIG. 1.

[0042] 4B is a diagram showing a step of oxidizing the semiconductor layer 30. In FIG. 4B, a part of the semiconductor layer 30 is oxidized, and insulating portions 21a are formed on the surface A5 of the semiconductor layer 30 and on the side walls of the trenches 51.

[0043] Fig. 4C is a diagram showing a film formation step of the insulating film 61. In Fig. 4C, the insulating film 61 is formed on the surface A5 of the semiconductor layer 30 and on the sidewall of the trench 51. The insulating film 61 is made of, for example, SiN.

[0044] Fig. 4D is a diagram showing a process of forming the insulating film 62. In Fig. 4D, the insulating film 62 is formed so as to fill up the trench 51. The insulating film 62 is made of, for example, SiO2.

[0045] 4E is a diagram showing an etching back step of the insulating film 62. In Fig. 4E, a part of the insulating film 62 is removed from the surface A5 side of the semiconductor layer 30 by wet etching or the like to form a trench 51a. As a result, a part of the insulating film 61 is exposed on the surface.

[0046] 4F is a diagram showing a step of removing the insulating film 61. In FIG. 4F, the portion of the insulating film 61 that is not protected by the insulating film 62 is removed by wet etching or the like. As a result, a part of the insulating portion 21a is exposed on the surface.

[0047] 4G is a diagram showing a step of removing the insulating film 62 and the first insulating portion 21. In FIG. 4G, the insulating film 62 that was not removed in FIG. 4E is removed. In addition, the portion of the first insulating portion 21 that is not protected by the insulating film 61 is removed. As a result, the insulating portion 21a is disposed on part of the sidewall of the trench 51.

[0048] 4H is a diagram showing an oxidation step of the semiconductor layer 30. In FIG. 4H, a portion of the semiconductor layer 30 is oxidized, and insulating portion 21b is formed on surface A5 of the semiconductor layer 30 and on portions of the sidewalls of trench 51 that are not protected by insulating film 61. In FIG. 4H, the semiconductor layer 30 is oxidized sufficiently so that insulating portion 21b is thicker than insulating portion 21a.

[0049] Fig. 4I is a diagram showing a step of removing the insulating film 61. In Fig. 4I, the insulating film 61 is removed in Fig. 4F. As a result, the insulating portion 21a is exposed on the surface.

[0050] 4J is a diagram showing an etch-back process of insulating portions 21a and 21b. In FIG. 4J, insulating portions 21a and 21b are etched back to such an extent that a portion of insulating portion 21b remains. In this specification, the process of FIG. 4J is also referred to as half etch-back.

[0051] FIG. 4K is a diagram showing a step of forming the body region 52. In FIG. 4K, a portion of the semiconductor layer 30 that is not protected by the insulating portion 21b (i.e., the sidewall on the bottom side of the trench 51) is etched by CDE (Chemical Dry Etching) or the like. As a result, a cylindrical body region 52 is formed in the trench 51. The body region 52 is a region that bulges in the planar direction of the semiconductor layer 30. Furthermore, a first region 41a and a second region 42a that is narrower than the first region 41a are formed in the pillar portion 40.

[0052] 4L is a diagram showing a step of oxidizing the semiconductor layer 30. In FIG. 4L, the body region 52 is oxidized, and the first insulating portion 21 is formed so as to cover the trench 51.

[0053] Fig. 4M is a diagram showing a process of forming the control electrode 13. In Fig. 4M, the conductive member 13a is formed so as to fill up the trench 51. The conductive member 13a is made of, for example, polysilicon.

[0054] 4N is a diagram showing the etch-back process of the control electrode 13. In FIG. 4N, a part of the conductive member 13a is etched to form a trench 51b. As a result, the control electrode 13 is formed so as to fill up a part of the body region 52 (so as to contact the first insulating portion 21).

[0055] Fig. 4O is a diagram showing a step of forming the second insulating portion 22. In Fig. 4O, the second insulating portion 22 is formed so as to fill up the trench 51b (so as to be disposed above the control electrode 13).

[0056] Fig. 4P is a diagram showing an etch-back step of the first insulating portion 21 and the second insulating portion 22. In Fig. 4P, parts of the first insulating portion 21 and the second insulating portion 22 are etched.

[0057] 4Q is a diagram showing a first step of forming a mesa shape. In FIG. 4Q, the semiconductor layer 30 is etched from the surface A5 side by RIE (Reactive Ion Etching) or the like. As a result, a mesa portion 53 is formed on the surface A5 side.

[0058] 4R is a diagram showing a second mesa-shape forming step, in which the side surface of the mesa portion 53 in the semiconductor layer 30 is etched by CDE or the like.

[0059] Fig. 4S is a diagram showing an oxidation step of the semiconductor layer 30. In Fig. 4S, the surface A5 of the semiconductor layer 30 is oxidized.

[0060] 4T is a diagram showing the impurity doping and thermal diffusion process. In FIG. 4T, impurity ions (e.g., As) are doped into the semiconductor layer 30 from the oxidized surface A5 side. The doped impurities are then thermally diffused in the first region 41a and the second region 42a. As a result, the first region 41 is formed in the pillar portion 40 so as to face the control electrode 13 and the second insulating portion 22 with the first insulating portion 21 interposed therebetween. The second region 42 is also formed so as to face the control electrode 13 with the first insulating portion 21 interposed therebetween.

[0061] Fig. 4U is a diagram showing a process of forming the insulating film 63. In Fig. 4U, the insulating film 63 is formed by CVD (Chemical Vapor Deposition) or the like so as to cover the mesa portion 53. The insulating film 63 is made of, for example, SiO2.

[0062] 4V is a diagram showing an etch-back process of the insulating film 63. In FIG. 4V, a part of the insulating film 63 is removed by RIE or the like.

[0063] 4W is a diagram showing a Trecon (Trench-Contact) formation process. Portions of the semiconductor layer 30 and the first insulating portion 21 that are not protected by the insulating film 63 are etched to form trenches (second trenches) 54. The trenches 54 are trenches for contact with the source electrode.

[0064] Fig. 4X is a diagram showing an etching step of the first insulating portion 21 etc. In Fig. 4X, the insulating film 63 is removed and part of the first insulating portion 21 is etched. Note that part of the second insulating portion 22 may also be etched.

[0065] 4Y is a diagram showing a metal deposition step of the first metal layer 14. In FIG. 4Y, the first metal layer 14 is deposited on the surfaces of the first insulating portion 21 and the semiconductor layer 30 so as to cover the sidewalls of the trenches 54.

[0066] 4Z is a diagram showing a metal deposition process for the second metal layer 15. In FIG. 4Z, the second metal layer 15 is deposited so as to overlap the first metal layer 14. This completes the formation of the semiconductor element 10. The first electrode 11 may be formed, for example, in a process before the process shown in FIG. 4A or in a process after the process shown in FIG. 4Z.

[0067] 4K are merely examples. The semiconductor element 10 according to the present disclosure only needs to have a wide first region 41 on the first surface A1 side of the pillar portion 40 and a narrow second region 42 on the second surface A2 side, and the shapes of the control electrode 13 and the like are not limited to the example in FIG.

[0068] 5A and 5B are diagrams showing the configuration of a semiconductor device 100 according to a comparative example. Similar to FIG. 2, FIG. 5B is an enlarged view of the region between the control electrode 13 and the second electrode 12. FIG. 5A is a diagram showing a stage before the second electrode 12 is formed. The semiconductor device 100 is used as a MOSFET.

[0069] The semiconductor device 100 in Fig. 5B has a pillar portion 101 and a first insulating portion 102, which correspond to the pillar portion 40 and the first insulating portion 21 in Fig. 2, respectively. The pillar portion 101 in Fig. 5B differs from the pillar portion 40 in Fig. 2 in that it does not have the wide first region 41 on the first surface A1 side (i.e., on the upper side in Fig. 5B). The width of the pillar portion 101 in Fig. 5B monotonically narrows as it approaches the first surface A1 side.

[0070] Therefore, in the semiconductor device 100 according to the comparative example, the width to the source contact region becomes narrow, and the source contact resistance increases.

[0071] 5A shows the impurity concentration doped in the pillar portion 101a in the process of FIG. 4T. In FIG. 5A, the darker the color, the higher the impurity concentration. As shown in FIG. 5A, the impurity concentration of the pillar portion 101a becomes higher toward the upper side of FIG. 5A, and also becomes higher toward the center of the pillar portion 101a.

[0072] 5A also illustrates a region 103 where a trench 54 is formed in the process of FIG. 4W. As shown in FIG. 5A, the trench 54 is formed in the center of the pillar portion 101a. To increase the threshold voltage of the semiconductor device 100, the width of the pillar portion 101 needs to be sufficiently small, and therefore, a large portion of the pillar portion 101a is removed by the trench 54. As a result, many of the portions of the pillar portion 101a with a high impurity concentration are removed.

[0073] 5B shows the pillar portion 101b after the region 103 has been removed. As shown in FIG. 5B, the impurity concentration in the pillar portion 101b is significantly reduced compared to the pillar portion 101a. This significantly increases the source contact resistance.

[0074] Compared to the semiconductor device 100 according to the comparative example, the semiconductor device 1 according to the present disclosure has a sufficiently wide first region 41. As a result, even when the trench 54 is formed by removing a portion of the first region 41 and the second region 42, a portion with a high impurity concentration can be left in the pillar portion 40, and the semiconductor device 1 can have a lower source contact resistance than the semiconductor device 100.

[0075] As described above, first region 41 can maintain a high impurity concentration even if it is doped with impurities before forming trench 54. This makes it possible to provide an impurity doping step (i.e., FIG. 4T) as a pre-step for forming trench 54 (i.e., FIG. 4W), thereby simplifying the manufacturing process.

[0076] Thus, the semiconductor device 1 according to the present disclosure has the first region 41 on the second surface A2 side where the second electrode 12 is disposed. The first region 41 has a sufficiently wide interface with the first metal layer 14, which allows the source contact resistance to be reduced.

[0077] 4K, the first region 41 is formed by forming the body region 52 into a cylindrical shape. This allows the width of the first region 41 to be widened even when the width of the pillar portion 40 is narrowed to increase the threshold voltage of the semiconductor device 1.

[0078] Furthermore, the first region 41 can maintain a high impurity concentration even when the trench 54 is formed after the doping of the impurity. This allows the source contact resistance of the first region 41 to be reduced, and also allows the first region 41 to be doped with the impurity in a step prior to the formation of the trench 54, thereby simplifying the manufacturing process.

[0079] That is, the semiconductor device 1 can achieve both an increase in threshold voltage and a reduction in source contact resistance.

[0080] Although several embodiments of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These embodiments and examples can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and examples and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents.

[0081] (Appendix 1) A first electrode; a second electrode disposed spaced apart from the first electrode in a first direction; a control electrode disposed opposite the second electrode in a second direction intersecting the first direction; a first insulating portion provided between the second electrode and the control electrode; a semiconductor layer provided between the first electrode and the second electrode; a first region provided between the second electrode and the first insulating portion in the semiconductor layer and connected to the second electrode by a Schottky junction; a second region joined to the first region and disposed on the first electrode side, connected to the second electrode by a Schottky junction, and having a width in the second direction narrower than at least a portion of the first region, Semiconductor device. (Appendix 2) The first region has a higher impurity concentration than the second region. 2. The semiconductor device according to claim 1. (Appendix 3) The semiconductor layer has a first surface on which the first electrode is disposed; the second electrode is disposed on a second surface opposite the first surface; the second electrode has a protrusion extending from the second surface toward the first surface and connected to the first region and the second region by a Schottky junction. 3. The semiconductor device according to claim 1 or 2. (Appendix 4) a second insulating portion disposed adjacent to the control electrode and on the second surface side from the control electrode; the first region is disposed from the second surface side to a position at least reaching an interface between the control electrode and the second insulating portion. 4. The semiconductor device according to claim 3. (Appendix 5) a width in the second direction of the control electrode is larger than a width in the second direction of at least a part of a portion of the second insulating portion facing the second electrode; 5. The semiconductor device according to claim 4. (Appendix 6) a width in the second direction of at least a part of a portion of the first region facing the second insulating portion being larger than a width in the second direction of the second region; 6. The semiconductor device according to claim 4 or 5. (Appendix 7) The second electrode includes a first metal layer and a second metal layer provided between the first metal layer and the semiconductor layer, having a work function higher than that of the first metal layer, and connected to the first region and the second region by a Schottky junction; 7. The semiconductor device according to claim 1. (Appendix 8) a field plate disposed between the control electrode and the first electrode; 8. The semiconductor device according to claim 1. (Appendix 9) the first electrode is a drain electrode, the second electrode is a source electrode, and the control electrode is a gate electrode that controls a current flowing between the source electrode and the drain electrode; 9. The semiconductor device according to any one of claims 1 to 8. (Appendix 10) forming a first trench from one main surface of the semiconductor layer; a sidewall on the bottom side of the first trench is etched to form a body portion that bulges in a planar direction; forming a first insulating portion on a surface of the body portion; forming a control electrode in contact with the first insulating portion; forming a second insulating portion on the control electrode; forming a first region by implanting impurity ions into the semiconductor layer so as to face the control electrode and the second insulating portion across the first insulating portion; forming a second region between the semiconductor layer and the first region, and a first metal layer connected to the first region by a Schottky junction; A method for manufacturing a semiconductor device. (Appendix 11) removing a portion of the first region and the second region to form a second trench; the first metal layer is formed to cover a sidewall of the second trench; forming a second metal layer on the first metal layer; The manufacturing method described in Appendix 10. [Explanation of symbols]

[0082] 1, 100 semiconductor device, 10 semiconductor element, 11 first electrode, 12 second electrode, 13 control electrode, 13a conductive member, 14 first metal layer, 15 second metal layer, 16 conductive portion, 17 interlayer film, 21, 102 first insulating portion, 21a insulating portion, 21b insulating portion, 22 second insulating portion, 23 protrusion portion, 30 semiconductor layer, 40, 101, 101a, 101b pillar portion, 41, 41a first region, 42, 42a second region, 43 region, 51, 51a, 51b, 54 trench, 52 body region, 53 mesa portion, 61, 62, 63 insulating film, 103 region

Claims

1. A first electrode; a second electrode disposed spaced apart from the first electrode in a first direction; a control electrode disposed opposite the second electrode in a second direction intersecting the first direction; a first insulating portion provided between the second electrode and the control electrode; a semiconductor layer provided between the first electrode and the second electrode; a first region provided between the second electrode and the first insulating portion in the semiconductor layer and connected to the second electrode by a Schottky junction; a second region joined to the first region and disposed on the first electrode side, connected to the second electrode by a Schottky junction, and having a width in the second direction narrower than at least a portion of the first region; Semiconductor device.

2. The first region has a higher impurity concentration than the second region. The semiconductor device according to claim 1 .

3. The semiconductor layer has a first surface on which the first electrode is disposed; the second electrode is disposed on a second surface opposite the first surface; the second electrode has a protrusion extending from the second surface toward the first surface and connected to the first region and the second region by a Schottky junction. The semiconductor device according to claim 1 .

4. a second insulating portion disposed adjacent to the control electrode and on the second surface side from the control electrode; the first region is disposed from the second surface side to a position at least reaching an interface between the control electrode and the second insulating portion. The semiconductor device according to claim 3 .

5. a width in the second direction of the control electrode is larger than a width in the second direction of at least a part of a portion of the second insulating portion facing the second electrode; The semiconductor device according to claim 4 .

6. a width in the second direction of at least a part of a portion of the first region facing the second insulating portion being larger than a width in the second direction of the second region; The semiconductor device according to claim 4 .

7. The second electrode includes a first metal layer and a second metal layer provided between the first metal layer and the semiconductor layer, having a work function higher than that of the first metal layer, and connected to the first region and the second region by a Schottky junction; The semiconductor device according to claim 1 .

8. a field plate disposed between the control electrode and the first electrode; The semiconductor device according to claim 1 .

9. the first electrode is a drain electrode, the second electrode is a source electrode, and the control electrode is a gate electrode that controls a current flowing between the source electrode and the drain electrode; The semiconductor device according to claim 1 .

10. forming a first trench from one main surface of the semiconductor layer; a sidewall on the bottom side of the first trench is etched to form a body portion that bulges in a planar direction; forming a first insulating portion on a surface of the body portion; forming a control electrode in contact with the first insulating portion; forming a second insulating portion on the control electrode; impurity ions are implanted into the semiconductor layer to form a first region facing the control electrode and the second insulating portion across the first insulating portion; forming a second region between the semiconductor layer and the first region, and a first metal layer connected to the first region by a Schottky junction; A method for manufacturing a semiconductor device.

11. removing a portion of the first region and the second region to form a second trench; the first metal layer is formed to cover a sidewall of the second trench; forming a second metal layer on the first metal layer; The method of claim 10.

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