Power conversion device and method for controlling the same

Abstract

To suppress a cross current flowing between a plurality of power supply devices without adding a configuration for suppressing a high-frequency cross current.SOLUTION: A power conversion device includes a plurality of power supply devices each including a plurality of switching elements and having output terminals connected in parallel. Each of the power supply devices includes a control device that controls the plurality of switching elements. The control device calculates a plurality of sampling signals by sampling an output current of the power supply device a plurality of times within a switching cycle of the switching element, calculates a difference signal between the plurality of sampling signals, calculates a high-frequency cross current signal flowing between an own power supply device and another power supply device among the plurality of power supply devices based on the difference signal, and controls the switching element of the own power supply device based on the high-frequency cross current signal to synchronize operation of the own power supply device and that of the other power supply device.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a power conversion device and a control method for a power conversion device. [Background technology]

[0002] Patent Document 1 discloses a technique for suppressing cross currents between multiple inverters by performing virtual impedance control when multiple inverters are operated in parallel. Patent Document 2 discloses a technique for performing synchronous control of inverters connected in parallel using a dedicated circuit common to the multiple inverters. Patent Document 3 discloses a technique for detecting high-frequency components of the output current from the inverters using a bypass filter and suppressing the occurrence of cross currents between multiple inverters. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2017-225214 [Patent Document 2] U.S. Patent No. 9,800,187 [Patent Document 3] Japanese Patent Application Publication No. 2019-68559 Summary of the Invention [Problem to be solved by the invention]

[0004] The technology disclosed in Patent Document 1 can suppress the occurrence of low-frequency cross currents, but if the PWM (Pulse Width Modulation) signals between multiple inverters are not synchronized, high-frequency cross currents may flow between the multiple inverters. The technology disclosed in Patent Document 2 can synchronize the PWM signals between multiple inverters, but requires the addition of a dedicated circuit for synchronizing the PWM signals, which may increase costs and the size of the device. The technology disclosed in Patent Document 3 requires that the current switching frequency adjustment amount be determined based on the current detection value of the high-frequency component of the output current, the previous detection value, and the previous switching frequency adjustment amount. In this case, a significant change in the high-frequency detection result requires a large change in the switching frequency, which poses a challenge in stabilizing the switching frequency. Furthermore, when load fluctuations occur in multiple inverters, the switching frequencies of the multiple inverters may increase or decrease in the same direction, which may result in unstable switching frequency control.

[0005] The present disclosure aims to suppress high-frequency cross currents that flow between multiple power supply devices without adding any configuration for suppressing high-frequency cross currents. [Means for solving the problem]

[0006] A power conversion device according to one embodiment of the present disclosure includes a plurality of power supply units each having a plurality of switching elements and whose output terminals are connected in parallel, and each of the power supply units includes a control device that controls the plurality of switching elements, and the control device samples the output current of the power supply unit multiple times within the switching period of the switching elements to calculate multiple sampling signals, calculates a differential signal between the multiple sampling signals, and calculates a high-frequency cross-current signal flowing between the own power supply unit and another power supply unit among the plurality of power supply units based on the differential signal, and controls the switching elements of the own power supply unit based on the high-frequency cross-current signal to synchronize the operation of the own power supply unit with the operation of the other power supply unit.

[0007] In the power conversion device of the present disclosure, the control device performs three-phase / two-phase conversion and rotational coordinate conversion on the differential signal to calculate the high-frequency cross current signal.

[0008] In the power conversion device of the present disclosure, the control device applies a predetermined gain to the high-frequency cross current signal to adjust at least one of the switching frequency and the switching period of the plurality of switching elements.

[0009] In the power conversion device of the present disclosure, the control device applies a predetermined low-pass filter to the high-frequency cross current signal and performs proportional-integral calculations to adjust at least one of the switching frequency and switching period of the multiple switching elements.

[0010] In the power conversion device of the present disclosure, when adjusting the switching period, the control device records the decimal part of the adjustment amount of the switching period and adds the decimal part to the adjustment amount of the next switching period to control the switching period.

[0011] A control method for a power conversion device according to one aspect of the present disclosure is a control method for a power conversion device that includes a plurality of power supply devices each having a plurality of switching elements and whose output terminals are connected in parallel, and includes the steps of sampling the output current of the power supply devices a plurality of times within the switching period of the switching elements to calculate a plurality of sampling signals, calculating a differential signal between the plurality of sampling signals, calculating a high-frequency cross-current signal flowing between a local power supply device and another power supply device among the plurality of power supply devices based on the differential signal, and controlling the switching elements of the local power supply devices based on the high-frequency cross-current signal to synchronize the operation of the local power supply device and the operation of the other power supply device. [Effects of the Invention]

[0012] According to the present disclosure, it is possible to suppress cross currents that flow between multiple power supply devices without adding any configuration for suppressing high-frequency cross currents. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a power conversion system according to the first embodiment. [Figure 2] FIG. 2 is a diagram for explaining the output current of the power conversion device according to the comparative example. [Figure 3] FIG. 3 is a block diagram showing an example of the configuration of the control device according to the first embodiment. [Figure 4] FIG. 4 is a diagram for explaining a method for sampling an output current and a method for calculating a differential signal according to the first embodiment. [Figure 5] FIG. 5 is a diagram for explaining output waveforms of the three-phase / two-phase converter and the rotating coordinate converter according to the first embodiment. [Figure 6] FIG. 6 is a diagram showing the simulation results of the cross current suppression method according to the first embodiment. [Figure 7] FIG. 7 is a diagram illustrating an example of the configuration of a control device according to the second embodiment. [Figure 8] FIG. 8 is a diagram for explaining the low-pass filter processing according to the second embodiment. [Figure 9] FIG. 9 is a diagram illustrating an example of the configuration of the PI calculation unit according to the second embodiment. [Figure 10] FIG. 10 is a diagram illustrating an example of the configuration of the decimal point processing unit according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that the present disclosure is not limited to these embodiments, and in the following embodiments, the same components are designated by the same reference numerals, and redundant description will be omitted.

[0015] [First embodiment] An example of the configuration of the power conversion system according to the first embodiment will be described with reference to Fig. 1. Fig. 1 is a diagram showing an example of the configuration of the power conversion system according to the first embodiment.

[0016] 1, the power conversion system 1 includes power conversion devices 10-1 to 10-n (n is an integer of 2 or more). The power conversion devices 10-1 to 10-n are connected in parallel. When there is no need to distinguish between the power conversion devices 10-1 to 10-n, they will be collectively referred to as the power conversion devices 10.

[0017] (inverter) The power conversion device 10 includes a converter 20, a bridge circuit 30, a reactor circuit 40, a capacitor circuit 50, a voltage detection circuit 60, and a current detection circuit 70. The power conversion device 10 is, for example, a three-phase inverter. The power conversion device 10 is configured to convert a DC voltage output by the converter 20 into a three-phase AC voltage and output the three-phase AC voltage to a load 11.

[0018] The converter 20 is configured to output a DC voltage Vdc to the bridge circuit 30.

[0019] The bridge circuit 30 includes a first arm 31, a second arm 32, and a third arm 33. The first arm 31 is a U-phase arm. The second arm 32 is a V-phase arm. The third arm 33 is a W-phase arm. The phase difference between the first arm 31 and the second arm 32 is 120 degrees. The phase difference between the second arm 32 and the third arm 33 is 120 degrees. The phase difference between the third arm 33 and the first arm 31 is 120 degrees.

[0020] The first arm 31 includes a transistor Q1 and a transistor Q2. The control device 100 controls the on / off states of the transistor Q1 and the transistor Q2.

[0021] The drain of transistor Q1 is electrically connected to one output terminal of converter 20. The source of transistor Q1 is electrically connected to the drain of transistor Q2. The source of transistor Q2 is electrically connected to the other output terminal of converter 20.

[0022] The second arm 32 includes a transistor Q3 and a transistor Q4. The control device 100 controls the on / off states of the transistors Q3 and Q4.

[0023] The drain of transistor Q3 is electrically connected to one output terminal of converter 20. The source of transistor Q3 is electrically connected to the drain of transistor Q4. The source of transistor Q3 is electrically connected to the other output terminal of converter 20.

[0024] The third arm 33 includes a transistor Q5 and a transistor Q6. The control device 100 controls the on / off states of the transistors Q5 and Q6.

[0025] The drain of transistor Q5 is electrically connected to one output terminal of converter 20. The source of transistor Q5 is electrically connected to the drain of transistor Q6. The source of transistor Q6 is electrically connected to the other output terminal of converter 20.

[0026] Transistors Q1 to Q6 are a type of switching element of the present disclosure. In the embodiment, each transistor is an IGBT (Insulated Gate Bipolar Transistor), but the present disclosure is not limited to this. Each transistor may be a silicon power device, a GaN power device, a SiC power device (e.g., a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)), or the like.

[0027] Each transistor has a parasitic diode (body diode) that can actively pass current, or has a diode connected in anti-parallel.

[0028] The reactor circuit 40 includes a reactor 41, a reactor 42, and a reactor 43. The capacitor circuit 50 includes a capacitor 51, a capacitor 52, and a capacitor 53. The voltage detection circuit 60 includes a voltage detector 61 and a voltage detector 62. The voltage detection circuit 60 detects the voltage between each phase. The current detection circuit 70 includes a current detector 71 and a current detector 72. The current detection circuit 70 detects the current flowing through each phase.

[0029] One end of the reactor 41 is electrically connected to the source of the transistor Q1 and the drain of the transistor Q2, and the other end of the reactor 41 is electrically connected to one end of the capacitor 51, one end of the capacitor 52, and one end of the current detector 71.

[0030] One end of the reactor 42 is electrically connected to the source of the transistor Q3 and the drain of the transistor Q4, and the other end of the reactor 42 is electrically connected to the other end of the capacitor 51, one end of the capacitor 53, and the load 11.

[0031] One end of the reactor 43 is electrically connected to the source of the transistor Q5 and the drain of the transistor Q6, and the other end of the reactor 43 is electrically connected to the other end of the capacitor 52, the other end of the capacitor 53, and one end of the current detector 72.

[0032] One input terminal of the voltage detector 61 is electrically connected to the other end of the reactor 41. The other input terminal of the voltage detector 61 is electrically connected to the other end of the reactor 42. The voltage detector 61 detects the voltage between the U phase and the V phase. The voltage detector 61 outputs a voltage detection signal S1 to the control device 100. The voltage detection signal S1 indicates the detection result of the voltage between the U phase and the V phase.

[0033] The voltage detector 62 has one input terminal electrically connected to the other end of the reactor 43. The other input terminal of the voltage detector 62 is electrically connected to the other end of the reactor 42. The voltage detector 62 detects the voltage between the V phase and the W phase. The voltage detector 62 outputs a voltage detection signal S2 to the control device 100. The voltage detection signal S2 indicates the detection result of the voltage between the V phase and the W phase.

[0034] The other end of the current detector 71 is electrically connected to the load 11. The current detector 71 detects a U-phase current i out_u The current detector 71 outputs a current detection signal S3 to the control device 100. The current detection signal S3 is a signal representing the current i out_u Represents the detection result.

[0035] The other end of the current detector 72 is electrically connected to the load 11. A W-phase current i flows from the connection point of the current detector 72, the source of the transistor Q5, and the drain of the transistor Q6 to the load 11. out_W The current detector 72 outputs a current detection signal S4 to the control device 100. The current detection signal S4 is a signal representing the current i out_W Represents the detection result.

[0036] The control device 100 outputs a control signal S5 to the bridge circuit 30 to control the on / off of transistors Q1 to Q6. The control signal S5 may be a PWM signal. The control device 100 controls the on / off of transistors Q1 to Q3 based on voltage detection signals S1, S2, current detection signals S3, and S4. The control device 100 includes an information processing device such as a DSP (Digital Signal Processor) with a built-in digital PWM (Pulse Width Modulation) circuit, a CPU (Central Processing Unit), or an MPU (Micro Processing Unit), and a storage device such as a RAM (Random Access Memory) or a ROM (Read Only Memory). The control device 100 may be implemented by an integrated circuit such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). The control device 100 may be implemented by a combination of hardware and software.

[0037] (Output current according to the comparative example) 2 is a diagram illustrating the output current of a power conversion device according to a comparative example. In the comparative example, when multiple power conversion devices are connected in parallel, the PWM signals output by each power conversion device are asynchronous, so that a high-frequency cross current flows into a power conversion device 10 from the other power conversion devices 10. Waveform 201 represents the output current of each phase of the power conversion device 10 according to the comparative example. As shown by waveform 201, a high-frequency cross current flows into a power conversion device 10 from the other power conversion devices 10, and therefore the output current of each phase includes a high-frequency cross current.

[0038] In the present disclosure, the control device 100 suppresses cross currents flowing between multiple power conversion devices 10 by controlling each transistor included in the bridge circuit 30 without adding any configuration to suppress high-frequency cross currents.

[0039] [Control device] An example of the configuration of the control device according to the first embodiment will be described with reference to Fig. 3. Fig. 3 is a block diagram showing an example of the configuration of the control device according to the first embodiment.

[0040] In the example shown in FIG. 3, the power conversion device 10 includes a capacitor 80 between the converter 20 and the bridge circuit 30, which smoothes the voltage output from the converter 20.

[0041] As shown in FIG. 3, the control device 100 includes a sampling unit 101, a difference calculation unit 102, a cross current calculation unit 103, a gain control unit 106, an adder 107, an output control unit 108, and a switching control unit 109.

[0042] The control device 100 performs a process of suppressing high-frequency cross currents that flow between the power conversion device 10 and another power conversion device 10.

[0043] The sampling unit 101 samples the output currents of the U phase, V phase, and W phase multiple times within the switching period of each transistor to calculate multiple sampling signals. The sampling unit 101 calculates the calculated U phase sampling signal i u , V-phase sampling signal i v and W-phase sampling signal i w is output to the difference calculation unit 102.

[0044] The difference calculation unit 102 receives the sampling signal i from the sampling unit 101. u , sampling signal i v and sampling signal i w The difference calculation unit 102 receives the sampling signal i from the sampling unit 101. u , sampling signal i v and sampling signal i w The difference between the sampled signals is calculated based on the above.

[0045] 4 is a diagram for explaining a method for sampling an output current and a method for calculating a differential signal according to the first embodiment. The horizontal axis of FIG. 4 represents time. A waveform 211 represents a switching period signal. A waveform 212 represents a U-phase output current of the power conversion device 10. A waveform 213 represents a V-phase output current of the power conversion device 10. A waveform 214 represents a W-phase output current of the power conversion device 10.

[0046] In the example shown in Fig. 4, the sampling unit 101 samples the output current value of each phase at timing t1, timing t2, timing t3, timing t4, timing t5, and timing t6. Specifically, the sampling unit 101 samples the output current value at a plurality of points within each same switching period. For example, the sampling unit 101 samples the output current value at a plurality of points within the same switching period T c The sampling unit 101 samples the output current value of each phase at two points, timing t3 and timing t4, in the time series. u , the sampling signal i representing the V-phase output current value at timing t3 and timing t4 v , the sampling signal i representing the output current value of the W phase at timing t3 and timing t4 w to the difference calculation unit 102. Note that the sampling unit 101 may sample the output current value of each phase at three or more locations for each switching period Tc.

[0047] 4, the difference calculation unit 102 calculates the difference between the output current value of each phase sampled at timing t3 and the output current value of each phase sampled at timing t4, and calculates a difference signal. For example, the difference signal of the U phase is u , V phase differential signal did v , W phase differential signal did w The difference calculation unit 102 calculates the difference signal did u , the difference signal did v and the differential signal did w is output to the cross current calculation unit 103.

[0048] In the example shown in FIG. 4, the sampling unit 101 is shown sampling the output current values ​​of the U phase, the V phase, and the W phase, but the present disclosure is not limited to this. For example, the sampling unit 101 may sample the output current values ​​of two phases, the U phase and the W phase. In this case, the sampling unit 101 may calculate the output current value of the V phase based on the sampling results of the output current values ​​of the U phase and the W phase. In this case, the output current value of the V phase is calculated as i v =-(i u +i w ), can be calculated as follows.

[0049] The cross current calculation unit 103 calculates the differential signal did u , the difference signal did v and the differential signal did w Based on this, the cross current calculation unit 103 calculates a high frequency cross current flowing between the power conversion device 10 and another power conversion device 10. The cross current calculation unit 103 includes a three-phase / two-phase conversion unit 104 and a rotational coordinate conversion unit 105.

[0050] The three-phase / two-phase conversion unit 104 converts the differential signal did from the differential calculation unit 102 into u , the difference signal did v and the differential signal did w The three-phase / two-phase conversion unit 104 receives the differential signal did u , the difference signal did v and the differential signal did w To generate a three-phase / two-phase converted current, the three-phase / two-phase conversion unit 104 performs three-phase / two-phase conversion processing on the α-coordinate signal di α and β coordinate signal di β Calculate.

[0051]

number

[0052] The three-phase / two-phase converter 104 converts the α coordinate signal di α and β coordinate signal di βis output to the rotation coordinate transformation unit 105.

[0053] The rotation coordinate conversion unit 105 converts the α coordinate signal di α and β coordinate signal di β The rotational coordinate conversion unit 105 receives the AC voltage reference phase φ ref AC voltage reference phase φ ref is generated by, for example, a PLL (Phase Locked Loop) oscillator (not shown). The rotational coordinate conversion unit 105 converts the AC voltage reference phase φ ref Based on the α coordinate signal di α and β coordinate signal di β Specifically, the rotational coordinate conversion unit 105 converts the d-axis current di d and the reactive current, q-axis current di q Generates the d-axis current di d is the cross current detection signal di d It is also called.

[0054]

number

[0055] The rotational coordinate conversion unit 105 combines the equations (1) and (2) to obtain the d-axis current di d and q-axis current di q may be generated.

[0056]

number

[0057] The rotation coordinate conversion unit 105 converts the cross current detection signal di d is output to the gain control unit 106.

[0058] 5 is a diagram for explaining the output waveforms of the three-phase / two-phase converter and the rotational coordinate converter according to the first embodiment. In FIG. 5, the horizontal axis represents time. A waveform 221 represents the α coordinate signal di output from the three-phase / two-phase converter 104. α The waveform 222 represents the β coordinate signal di β The waveform 223 represents the cross current detection signal di output by the rotation coordinate conversion unit 105. d Represents.

[0059] As shown by the waveforms 221 and 222, the difference signal calculated by the difference calculation unit 102 changes periodically. α and β coordinate signal di β also changes periodically.

[0060] As shown in waveform 223, the AC voltage reference phase φ ref As a result of the dq conversion using the reference phase as the reference phase, a stable cross current detection signal di d The cross current detection signal di d changes in proportion to the sine function of the phase difference of the PWM signals between the power converters 10. By adjusting the switching period in proportion to the stable detection signal, synchronization of the PWM signals between the power converters 10 can be achieved. d is 0 when the phase difference of the PWM signals between the power converters 10 is 180°, but due to errors in the crystal oscillators and fluctuations in the cross current detection signal, it is controlled in the positive or negative direction. Therefore, stable control can be obtained regardless of the value of the phase difference of the power converters 10.

[0061] Returning to FIG. 3, the gain control unit 106 receives the cross current detection signal di d The gain control section 106 receives the cross current detection signal di d Based on this, the gain control unit 106 calculates a frequency compensation value Δf, which is a correction amount for the switching frequency of each transistor included in the bridge circuit 30, in order to suppress cross currents that flow between the power conversion device 10 and another power conversion device 10. The gain control unit 106 outputs the calculated frequency compensation value Δf to the adder 107.

[0062] The adder 107 calculates a switching frequency reference value f ref and a frequency compensation value Δf from the gain control unit 106. The adder 107 calculates the switching frequency reference value f ref The frequency compensation value Δf is added to the frequency setting value f, which is the switching frequency set for each transistor. sw The adder 107 calculates the calculated frequency setting value f sw is output to the switching control section 109.

[0063] The output control unit 108 generates voltage command values ​​and current command values ​​such that the power conversion device 10 outputs three-phase AC voltages and three-phase AC currents of desired values. The output control unit 108 outputs the generated voltage command values ​​and current command values ​​to the switching control unit 109.

[0064] The switching control unit 109 receives the frequency setting value f from the adder 107. sw The switching control unit 109 receives the PWM duty ratio signal of each arm from the output control unit 108. The switching control unit 109 receives the PWM duty ratio signal of each arm from the output control unit 108. sw The switching control unit 109 generates a switching signal for controlling the on / off of each transistor based on the PWM duty ratio signal of the arm. The switching control unit 109 outputs the switching signal to each transistor and synchronizes the switching frequency of each transistor with the switching frequency of another power conversion device 10, thereby suppressing cross currents that flow between the power conversion device 10 and another power conversion device 10.

[0065] (Simulation results) The simulation results of the cross current suppression method according to the first embodiment will be described with reference to Fig. 6. Fig. 6 is a diagram showing the simulation results of the cross current suppression method according to the first embodiment.

[0066] In Figure 6, the horizontal axis represents time. Waveform 231 represents the U-phase output voltage. Waveform 232 represents the V-phase output voltage. Waveform 233 represents the W-phase output voltage. Waveform 234 represents the U-phase output current. Waveform 235 represents the V-phase output current. Waveform 236 represents the W-phase output current.

[0067] In the example shown in Figure 6, the section from time t10 to time t11 is a high-frequency cross current processing stop section where high-frequency cross current suppression processing is not performed, and the section from time t11 to time t12 is a high-frequency cross current suppression processing execution section where high-frequency cross current suppression processing is performed.

[0068] As shown by waveforms 234 to 236, in the high frequency suppression processing stop section, a cross current flows between the power conversion device 10 and another power conversion device 10, and therefore the waveform of the output current of each phase is disturbed due to the influence of the high frequency cross current. In contrast, in the high frequency suppression processing execution section, the cross current flowing between the power conversion device 10 and another power conversion device 10 is suppressed, and therefore the waveform of the output current of each phase is stable.

[0069] As described above, in the first embodiment, a high-frequency detection signal flowing between the power conversion device 10 and another power conversion device 10 is calculated, and the switching frequency of each transistor is controlled based on the calculated high-frequency detection signal. In this way, the first embodiment can suppress high-frequency cross currents flowing between the power conversion device 10 and another power conversion device 10.

[0070] [Second embodiment] (Control device) An example of the configuration of the control device according to the second embodiment will be described with reference to Fig. 7. Fig. 7 is a diagram for explaining an example of the configuration of the control device according to the second embodiment.

[0071] 7, the power conversion system 1A includes power conversion devices 10A-1 to 10A-n. The power conversion devices 10A-1 to 10A-n are connected in parallel. When there is no need to distinguish between the power conversion devices 10A-1 to 10A-n, they will be collectively referred to as the power conversion device 10A.

[0072] The control device 100A of the power conversion device 10A includes a sampling unit 101, a difference calculation unit 102, a cross current calculation unit 103, an adder 107A, an output control unit 108, a switching control unit 109A, a filter unit 110, a PI calculation unit 111, and a decimal point processing unit 112. The control device 100A differs from the control device 100 shown in FIG. 3 in that it does not include the gain control unit 106, but includes the filter unit 110, the PI calculation unit 111, and the decimal point processing unit 112.

[0073] The filter unit 110 receives the cross current detection signal di from the rotation coordinate conversion unit 105. d The filter unit 110 receives, for example, a cross current detection signal di d The cross current detection signal di d 5. The filter unit 110 removes noise components (fluctuations) included in the cross current detection signal di. FIG. 8 is a diagram for explaining the low-pass filter processing according to the second embodiment. In FIG. 8, the horizontal axis represents time and the vertical axis represents signal level. A waveform 241 is obtained by performing low-pass filter processing on the waveform 223 shown in FIG. 5 by the filter unit 110. d As shown in the waveform 241, the noise component included in the waveform 223 is removed. d By performing low-pass filtering on the cross current detection signal di, it is possible to accurately suppress cross currents that flow between the power conversion device 10 and another power conversion device 10. The filter unit 110 performs low-pass filtering on the cross current detection signal di d is output to the PI calculation unit 111.

[0074] The PI calculation unit 111 receives the cross current detection signal di that has been subjected to filtering (for example, low-pass filtering) from the filter unit 110.d The PI calculation unit 111 receives the cross current detection signal di d Based on this, PI (proportional integral) calculations are performed to calculate the gain to be applied to the switching period of the switching frequency.

[0075] An example of the configuration of the PI calculation unit according to the second embodiment will be described with reference to Fig. 9. Fig. 9 is a diagram for explaining an example of the configuration of the PI calculation unit according to the second embodiment.

[0076] As shown in FIG. 9, the PI calculation unit 111 includes a proportional gain unit 120, an integrator 121, an integral gain unit 122, and an adder 123.

[0077] The proportional gain unit 120 receives the cross current detection signal di from the filter unit 110. d The proportional gain unit 120 receives the cross current detection signal di d The proportional gain unit 120 sets the proportional gain Kp based on the cross current detection signal di d The signal obtained by multiplying the signal by the set proportional gain Kp is output to the adder 123.

[0078] The integrator 121 receives the cross current detection signal di from the filter 110. d The integration unit 121 receives the cross current detection signal di d The integrating unit 121 outputs the calculated integral value to the integral gain unit 122.

[0079] The integral gain unit 122 receives the cross current detection signal di from the integrator 121. d The integral gain unit 122 receives the integral value of the cross current detection signal di d The integral gain unit 122 sets an integral gain Ki based on the integral value of the cross current detection signal di d is multiplied by the integral gain Ki that has been set, and output to the adder 123.

[0080] The adder 123 receives the proportional gain Kp from the proportional gain unit 120. The adder 123 receives the integral gain Ki from the integral gain unit 122. The adder 123 adds the proportional gain Kp and the integral gain Ki to calculate a switching period addition value, which is an adjustment amount of the switching period to be added to the switching period of the switching frequency of each transistor. The switching period addition value here is a value that includes a decimal point value of the digital PWM resolution. The adder 123 outputs the calculated switching period addition value to the decimal point processing unit 112.

[0081] The decimal point processing unit 112 receives the switching period sum from the PI calculation unit 111. The decimal point processing unit 112 removes the decimal point from the switching period sum to calculate an integer switching period sum.

[0082] An example of the configuration of the decimal point processing unit according to the second embodiment will be described with reference to Fig. 10. Fig. 10 is a diagram for explaining an example of the configuration of the decimal point processing unit according to the second embodiment.

[0083] As shown in FIG. 10, the decimal point processing unit 112 includes an adder 130, an integer conversion unit 131, a subtractor 132, and a delay unit 133.

[0084] The adder 130 receives a switching period addition value including a decimal point from the PI calculation unit 111. In an initial state, the adder 130 outputs the switching period addition value received from the PI calculation unit 111 to the integer conversion unit 131 and the subtractor 132. When the adder 130 receives a delay signal from the delay unit 133, the adder 130 outputs a switching period addition value obtained by adding the switching period addition value received from the PI calculation unit 111 and the delay signal received from the delay unit 133 to the integer conversion unit 131 and the subtractor 132.

[0085] The integer conversion unit 131 receives the switching period addition value from the adder 130. The integer conversion unit 131 rounds off the switching period addition value received from the adder 130 to generate an integer switching period addition value. The integer conversion unit 131 rounds off the integer switching period addition value ΔT cis output to adder 107A.

[0086] The subtractor 132 subtracts the switching period sum including the decimal point received from the adder 130 from the integer conversion unit 131. c The subtractor 132 subtracts the integer switching period addition value from the switching period addition value including the decimal point to calculate the decimal part of the switching period addition value. The subtractor 132 outputs the calculated decimal part of the switching period addition value to the delay unit 133.

[0087] The delay unit 133 receives the calculation result of the decimal point part of the switching period sum from the subtractor 132. The delay unit 133 delays, by one sample, the calculation result of the decimal point part of the switching period received from the subtractor 132. The delay unit 133 outputs, to the adder 130, the calculation result of the decimal point part of the switching period sum that has been delayed by one sample.

[0088] That is, the decimal point processor 112 records the decimal point part of the switching sum and performs feedback control to add the previous decimal point part to the next switching sum, thereby calculating the switching cycle sum.

[0089] Returning to Fig. 7, the adder 107A calculates a switching period reference value T ref and the decimal point processing unit 112 outputs the switching period addition value ΔT c The adder 107A receives the switching period reference value T ref Add the switching period ΔT c The switching period set for each transistor is calculated by adding the above. c The adder 107A calculates the calculated switching cycle setting value T c is output to the switching control section 109A.

[0090] The switching control unit 109A receives the switching cycle set value T cThe switching control unit 109A receives the PWM duty ratio signal of each arm from the output control unit 108. ... c Based on the PWM duty ratio signal of each arm, a switching control unit 109 generates a switching signal for controlling the on / off of each transistor. The switching control unit 109 outputs a switching signal to each transistor to synchronize the switching period of each transistor with the switching period of another power conversion device 10A, thereby suppressing cross currents that flow between the power conversion device 10A and another power conversion device 10A.

[0091] As described above, in the second embodiment, a high-frequency detection signal flowing between the power conversion device 10A and another power conversion device 10A is calculated, and the switching period of each transistor is controlled based on the calculated high-frequency detection signal. This makes it possible to suppress high-frequency cross currents flowing between the power conversion device 10A and another power conversion device 10A. [Explanation of symbols]

[0092] 1 Power Conversion System 10 Power conversion device 11 Load 20 Converter 30 Bridge Circuit 31 First Arm 32 Second Arm 33 Third Arm 40 Reactor circuit 41, 42, 43 Reactor 50 Capacitor Circuit 51, 52, 53, 80 Capacitors 60 Voltage detection circuit 61,62 Voltage detector 70 Current detection circuit 71,72 Current detector 100,100A control device 101 Sampling section 102 Difference calculation section 103 Cross flow calculation section 104 Three-phase / two-phase conversion unit 105 Rotational coordinate transformation unit 106 Gain control section 107, 107A, 123, 130 Adder 108 Output control section 109,109A Switching control section 110 Filter section 111 PI calculation section 112 Decimal point processing section 120 Proportional gain section 121 Integration Department 122 Integral gain section 131 Integer conversion part 132 Subtractor 133 Delay Section Q1, Q2, Q3, Q4, Q5, Q6 transistors

Claims

1. a plurality of power supply devices each including a plurality of switching elements and having output terminals connected in parallel; Each of the power supply devices includes a control device that controls a plurality of the switching elements, The control device sampling the output current of the power supply device a plurality of times within a switching period of the switching element to calculate a plurality of sampling signals; Calculating a difference signal between the plurality of sampling signals; calculating a high-frequency cross current signal flowing between the power supply device itself and another power supply device among the plurality of power supply devices based on the differential signal; controlling the switching element of the own power supply device based on the high frequency cross current signal to synchronize the operation of the own power supply device with the operation of the other power supply device; Power conversion device.

2. The control device The differential signal is subjected to three-phase / two-phase transformation and rotational coordinate transformation to calculate the high-frequency cross current signal. The power conversion device according to claim 1 .

3. The control device a predetermined gain is applied to the high-frequency cross current signal to adjust at least one of the switching frequency and the switching period of the plurality of switching elements; The power conversion device according to claim 2 .

4. The control device a predetermined low-pass filter is applied to the high-frequency cross current signal, and a proportional-plus-integral operation is performed to adjust at least one of the switching frequency and the switching period of the plurality of switching elements; The power conversion device according to claim 2 .

5. The control device When adjusting the switching period, a decimal part of an adjustment amount of the switching period is recorded, and the decimal part is added to the adjustment amount of the next switching period to control the switching period. The power conversion device according to claim 3 .

6. A control method for a power conversion device including a plurality of power supply devices each including a plurality of switching elements and having output terminals connected in parallel, comprising: sampling the output current of the power supply device a plurality of times within a switching period of the switching element to calculate a plurality of sampling signals; calculating a difference signal between a plurality of said sampled signals; calculating a high-frequency cross current signal flowing between a power supply device and another power supply device among the plurality of power supply devices based on the differential signal; controlling the switching element of the own power supply device based on the high frequency cross current signal to synchronize the operation of the own power supply device with the operation of the other power supply device; A method for controlling a power conversion device, comprising:

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