Semiconductor module, semiconductor device, and manufacturing method of semiconductor module

Abstract

To inspect the insulating properties of a sealing member positioned between opposing wiring layers while preventing damage to a semiconductor chip.SOLUTION: At least one of a wiring layer 111 for a first wiring portion and a wiring layer 121 for a second wiring portion, which are connected to semiconductor chips 31 and 32, is arranged within a sealing member 50 and has portions that are arranged opposite each other across the sealing member 50, and an inspection wiring layer 141, which is not connected to the semiconductor chips, is arranged between the wiring layer 111 for the first wiring portion and the wiring layer 121 for the second wiring portion.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor module, a semiconductor device, and a method for manufacturing a semiconductor module. [Background technology]

[0002] Conventionally, semiconductor modules have been proposed that are manufactured by performing an insulation inspection process (see, for example, Patent Document 1). Specifically, in this semiconductor module, a first heat transfer layer, a measurement electrode, and a second heat transfer layer are arranged in this order on a metal plate, and a semiconductor chip such as an electronic component is arranged on the second heat transfer layer.

[0003] Such a semiconductor module is manufactured after the insulation of the first and second heat transfer layers is inspected as follows: That is, a measuring jig is placed on the second heat transfer layer before placing electronic components. Next, in this semiconductor device, the insulation of the first heat transfer layer is inspected by applying a voltage between the metal plate and the measurement electrode, and the insulation of the second heat transfer layer is inspected by applying a voltage between the measurement electrode and the measuring jig. That is, by applying a voltage to two conductors, the insulation of the component placed between the two conductors is inspected. Thereafter, for those whose insulation of the first and second heat transfer layers is normal, the measuring jig is removed and a semiconductor chip is placed thereon, thereby manufacturing the above semiconductor device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-4731 Summary of the Invention [Problem to be solved by the invention]

[0005] The present inventors have been studying a semiconductor device in which a semiconductor chip is sealed with a sealing member made of resin or the like, and which includes multiple wiring layers connected to the semiconductor chip. In this semiconductor device, the wiring layers may be arranged opposite each other, and it is desirable to inspect the insulation of the sealing member located between the opposing wiring layers.

[0006] However, if the wiring layers connected to the semiconductor chip are used as they are and a high voltage is applied to each wiring layer to inspect the insulation of the sealing material located between opposing wiring layers, the semiconductor chip will also be subjected to a high voltage, which could destroy the semiconductor chip.

[0007] The present disclosure aims to provide a semiconductor module, a semiconductor device, and a method for manufacturing a semiconductor module that can inspect the insulation of a sealing member located between opposing wiring layers while preventing damage to a semiconductor chip. [Means for solving the problem]

[0008] According to one aspect of the present disclosure, a semiconductor module comprises semiconductor chips (31, 32), a sealing member (50) that seals the semiconductor chips, a wiring layer (111) for a first wiring portion connected to the semiconductor chip, a first terminal portion (112) arranged on the sealing member and electrically connected to the wiring layer for the first wiring portion, a wiring layer (121) for a second wiring portion connected to the semiconductor chip, and a second terminal portion (122) arranged on the sealing member and electrically connected to the wiring layer for the second wiring portion, at least one of the wiring layer for the first wiring portion and the wiring layer for the second wiring portion is arranged within the sealing member and has portions that are arranged opposite each other across the sealing member, and a wiring layer for inspection (141) that is not connected to the semiconductor chip is arranged between the wiring layer for the first wiring portion and the wiring layer for the second wiring portion.

[0009] According to this, the inspection wiring layer is disposed between the first wiring portion wiring layer and the second wiring portion wiring layer. Therefore, in order to inspect the insulation of the sealing member disposed between the first wiring portion wiring layer and the second wiring portion wiring layer, it is sufficient to apply a high voltage between the inspection wiring layer and the first wiring portion wiring layer and between the inspection wiring layer and the second wiring portion wiring layer. Therefore, a high voltage is not applied to the semiconductor chip, and the insulation of the sealing member can be inspected while suppressing damage to the semiconductor chip.

[0010] According to another aspect of the present disclosure, the method for manufacturing the semiconductor module includes preparing a component (200) including a module formation area (210) having a semiconductor chip, a wiring layer for a first wiring portion, a first terminal portion, a wiring layer for a second wiring portion, a second terminal portion, an inspection wiring layer, and a sealing member, and an inspection terminal portion (142) electrically connected to the inspection wiring layer, and inspecting the insulation of the sealing member disposed between the wiring layer for the first wiring portion and the wiring layer for the second wiring portion by applying a voltage to the inspection terminal portion and at least one of the first terminal portion and the second terminal portion.

[0011] This makes it possible to manufacture a semiconductor module by inspecting the insulating properties of the sealing member while preventing the semiconductor chip from being damaged.

[0012] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view of a semiconductor module according to a first embodiment. [Figure 2] FIG. 2 is a plan view of the semiconductor module according to the first embodiment. [Figure 3] FIG. 2 is a diagram illustrating a circuit configuration of a semiconductor module. [Figure 4] FIG. 2 is a plan view showing components for manufacturing a semiconductor module. [Figure 5] FIG. 10 is a plan view of a semiconductor module according to a second embodiment. [Figure 6] FIG. 10 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 7] FIG. 11 is a cross-sectional view of a semiconductor module according to a modified example of the third embodiment. [Figure 8] FIG. 2 is a plan view illustrating an exposed portion configured in the semiconductor module. [Figure 9] FIG. 10 is a plan view showing a semiconductor device according to a fourth embodiment. [Figure 10] FIG. 11 is a plan view showing a semiconductor device according to a modified example of the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0015] (First embodiment) A semiconductor module 1 according to a first embodiment will be described with reference to the drawings. The semiconductor module 1 according to this embodiment is suitable for use, for example, in a vehicle to control various electronic components.

[0016] 1 and 2, the semiconductor module 1 has a substantially rectangular planar shape in this embodiment. The semiconductor module 1 includes an external connection heat sink 10, a first heat sink 21, a second heat sink 22, a first semiconductor chip 31, a second semiconductor chip 32, a sealing member 50, first to third wiring portions 101 to 103, an inspection wiring layer 141, and the like. Note that FIG. 1 corresponds to a cross-sectional view taken along line II in FIG. 2.

[0017] 1, the heat sink 10 for external connection has a main heat sink 11 made of a copper plate or the like having one surface 11a and another surface 11b, and an insulating sheet 12 arranged on the one surface 11a side of the main heat sink 11. When the semiconductor module 1 is mounted on a mounting member such as a vehicle, the other surface 11b side of the main heat sink 11 is joined to the mounting member. The main heat sink 11 is made of, for example, a copper plate, and the insulating sheet 12 is made of, for example, an epoxy resin.

[0018] The first and second heat sinks 21, 22 are each a block made of copper or the like. In this embodiment, they are each a rectangular shape in plan view, have the same size, and are made equal in thickness. Note that "equal" here includes slight manufacturing errors. The first and second heat sinks 21, 22 are arranged side by side on the insulating sheet 12 of the external connection heat sink 10.

[0019] The first semiconductor chip 31 and the second semiconductor chip 32 are configured by forming semiconductor elements such as switching elements such as MOSFET elements and IGBT elements, and freewheeling diode elements, etc. Note that MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor, and IGBT is an abbreviation for Insulated Gate Bipolar Transistor.

[0020] In this embodiment, the first semiconductor chip 31 has a first electrode 311 formed on one surface 31a and a second electrode 312 formed on the other surface 31b, and a semiconductor element formed to allow current to flow between the first electrode 311 and the second electrode 312. Although not particularly shown, the first semiconductor chip 31 has a plurality of pad portions formed on the one surface 31a, including gate pads connected to gate electrodes in MOSFET elements and IGBT elements.

[0021] Similarly, the second semiconductor chip 32 has a first electrode 321 formed on one surface 32a and a second electrode 322 formed on the other surface 32b, and a semiconductor element formed to allow current to flow between the first electrode 321 and the second electrode 322. Although not particularly shown, the second semiconductor chip 32 has a plurality of pad portions formed on the one surface 32a, including gate pads connected to gate electrodes in MOSFET elements and IGBT elements.

[0022] The first semiconductor chip 31 is disposed on the first heat sink 21 with the second electrode 312 being disposed via the first bonding member 41. The second semiconductor chip 32 is disposed on the second heat sink 22 with the second electrode 322 being disposed via the second bonding member 42.

[0023] The first bonding member 41 is made of a material that electrically and thermally connects the first semiconductor chip 31 and the first heat sink 21, such as solder or sintered silver. The second bonding member 42 is made of a material that electrically and thermally connects the second semiconductor chip 32 and the second heat sink 22, such as solder or sintered silver. By placing the first semiconductor chip 31 on the first heat sink 21 in this manner, heat from the first semiconductor chip 31 is dissipated from the first heat sink 21 to the external connection heat sink 10. By placing the second semiconductor chip 32 on the second heat sink 22, heat from the second semiconductor chip 32 is dissipated from the second heat sink 22 to the external connection heat sink 10.

[0024] Here, in this embodiment, the first semiconductor chip 31 and the second semiconductor chip 32 are connected in series to form an upper arm UA and a lower arm LA of an inverter circuit or the like. Specifically, as shown in FIG. 3 , the first semiconductor chip 31 is used to form the upper arm UA, with the second electrode 312 connected to the first wiring portion 101 and the first electrode 311 connected to the third wiring portion 103. The second semiconductor chip 32 is used to form the lower arm LA, with the second electrode 322 connected to the third wiring portion 103 and the first electrode 321 connected to the second wiring portion 102. Therefore, in this embodiment, the first semiconductor chip 31 is connected to the first wiring portion 101 and the third wiring portion 103, and is connected to the second wiring portion 102 via the second semiconductor chip 32. The second semiconductor chip 32 is connected to the second wiring portion 102 and the third wiring portion 103, and can be said to be connected to the first wiring portion 101 via the first semiconductor chip 31. The first wiring portion 101 is what is called a P wiring, the second wiring portion 102 is what is called an N wiring, and the third wiring portion 103 is what is called an O wiring, and the first to third wiring portions 101 are at different potentials. As will be described later, the first wiring portion 101 is configured to include a first wiring portion wiring layer 111 and a first terminal portion 112, the second wiring portion 102 is configured to include a second wiring portion wiring layer 121 and a second terminal portion 122, and the third wiring portion 103 is configured to include a third wiring portion wiring layer 131 and a third terminal portion 132. The third wiring portion 103 is connected to an external load or the like, although not particularly shown. In this circuit configuration, the switching elements of the first semiconductor chip 31 and the second semiconductor chip 32 are alternately turned on.

[0025] 1, the sealing member 50 is disposed on the external connection heat sink 10 so as to seal the first semiconductor chip 31, the second semiconductor chip 32, the first heat sink 21, the second heat sink 22, etc. In this embodiment, the sealing member 50 is formed by laminating multiple film members made of resin such as prepreg, and integrating them by applying heat and pressure. Note that the sealing member 50 disposed between the first heat sink 21 and the second heat sink 22 is disposed by the resin material constituting the film members flowing in when the film members are integrated by applying heat and pressure.

[0026] Hereinafter, in this embodiment, the portion of the sealing member 50 that is disposed on the insulating sheet 12 and seals the first and second semiconductor chips 31, 32, the first and second heat sinks 21, 22, etc. will be described as the first sealing member 51, and the portions that are disposed on the first sealing member 51 will be described as the second and third sealing members 52, 53. The second sealing member 52 is the portion that is disposed on the first sealing member 51, and the third sealing member 53 is the portion that is disposed on the opposite side of the second sealing member 52 from the first sealing member 51.

[0027] The first to third wiring portions 101 to 103 are appropriately arranged on the first sealing member 51 or the third sealing member 53 so that the first semiconductor chip 31 and the second semiconductor chip 32 form an upper arm UA and a lower arm LA. That is, the first to third wiring portions 101 to 103 of this embodiment are arranged together on the same side (i.e., the upper side of the paper in FIG. 1) with respect to the first semiconductor chip 31 and the second semiconductor chip 32. The first to third wiring portions 101 to 103 are made of, for example, aluminum wiring or copper wiring.

[0028] Specifically, first chip via holes 511 are formed in the first sealing member 51 to expose the first electrodes 311 of the first semiconductor chip 31. Second chip via holes 512 are formed in the first sealing member 51 to expose the first electrodes 321 of the second semiconductor chip 32. Second heat sink via holes 513 are formed in the first sealing member 51 to expose the portion of the second heat sink 22 on the first heat sink 21 side. Note that each of the via holes 511 to 513 is formed in plurality.

[0029] The third wiring section 103 has a third wiring section wiring layer 131 disposed on the first sealing member 51 so as to face the portion of the first heat sink 21, the first semiconductor chip 31, and the second heat sink 22 that is closer to the first heat sink 21. The third wiring section wiring layer 131 is connected to the first electrode 311 of the first semiconductor chip 31 through the first chip via 511a disposed in the first chip via hole 511. The third wiring section wiring layer 131 is also connected to the second heat sink 22 through the second heat sink via 513a disposed in the second heat sink via hole 513, and is connected to the second electrode 322 of the second semiconductor chip 32 through the second heat sink 22. The first chip via 511a and the second heat sink via 513a are formed of, for example, copper vias. Similarly, each via described below is also formed of, for example, copper vias.

[0030] The second wiring portion 102 has a wiring layer 121 for the second wiring portion disposed on the first sealing member 51 so as to face the second heat sink 22 and the second semiconductor chip 32. The wiring layer 121 for the second wiring portion is connected to the first electrode 321 of the second semiconductor chip 32 through the second chip via 512a disposed in the second chip via hole 512.

[0031] The second sealing member 52 is disposed on the first sealing member 51 so as to cover the third wiring portion wiring layer 131 and the second wiring portion wiring layer 121. An inspection wiring layer 141 is disposed on the second sealing member 52 so as to face the second wiring portion wiring layer 121 and the third wiring portion wiring layer 131. The inspection wiring layer 141 is not connected to the first semiconductor chip 31 and the second semiconductor chip 32 and is in a floating state.

[0032] The third sealing member 53 is disposed on the second sealing member 52 so as to cover the inspection wiring layer 141. The second sealing member 52 and the third sealing member 53 have formed therein a third wiring portion via hole 523 that exposes the third wiring portion wiring layer 131. The second sealing member 52 and the third sealing member 53 also have formed therein a second wiring portion via hole 522 that exposes the second wiring portion wiring layer 121.

[0033] First heat sink via holes 531 are formed in the first sealing member 51, the second sealing member 52, and the third sealing member 53, exposing the portion of the first heat sink 21 that faces the second heat sink 22. Note that a plurality of each of the via holes 522, 523, and 531 are formed.

[0034] The first wiring portion 101 has a first wiring portion wiring layer 111 disposed on the second sealing member 52 so as to face the second semiconductor chip 32 and a portion of the first heat sink 21 facing the second heat sink 22. Specifically, the first wiring portion wiring layer 111 is disposed so as to have a portion facing the second wiring portion wiring layer 121 and the third wiring portion wiring layer 131. The inspection wiring layer 141 is disposed so as to face the first wiring portion wiring layer 111 and the second wiring portion wiring layer 121, and also so as to face the first wiring portion wiring layer 111 and the third wiring portion wiring layer 131. In other words, the inspection wiring layer 141 is disposed between the first wiring portion wiring layer 111 and the second wiring portion wiring layer 121 with the sealing member 50 interposed therebetween, and is also disposed between the first wiring portion wiring layer 111 and the third wiring portion wiring layer 131 with the sealing member 50 interposed therebetween.

[0035] The first wiring portion wiring layer 111 has a non-overlapping portion that does not face the third wiring portion wiring layer 131 in a portion facing the first heat sink 21. The first wiring portion wiring layer 111 is connected to the first heat sink 21 in this non-overlapping portion through the first heat sink via 531a arranged in the first heat sink via hole 531, and is connected to the second electrode 312 of the first semiconductor chip 31 through the first heat sink 21.

[0036] A first terminal 112 constituting the first wiring portion 101, a second terminal 122 constituting the second wiring portion 102, and a third terminal 132 constituting the third wiring portion 103 are arranged on the third sealing member 53. The third terminal 132 is connected to the third wiring portion wiring layer 131 through a third wiring portion via 523a arranged in a third wiring portion via hole 523 formed in the second sealing member 52 and the third sealing member 53.

[0037] The second terminal portion 122 is connected to the second wiring portion wiring layer 121 through a second wiring portion via 522 a arranged in a second wiring portion via hole 522 formed in the second sealing member 52 and the third sealing member 53 .

[0038] The first terminal portion 112 is configured as a part of the wiring layer 111 for the first wiring portion. In this embodiment, the first terminal portion 112, the second terminal portion 122, and the third terminal portion 132 are arranged side by side in the arrangement direction of the first semiconductor chip 31 and the second semiconductor chip 32, such that the first terminal portion 112 is located between the third terminal portion 132 and the second terminal portion 122. In FIG. 2, for example, the left-right direction on the paper surface corresponds to the arrangement direction. In this embodiment, the semiconductor module 1 is not provided with a terminal portion for inspection connected to the wiring layer 141 for inspection.

[0039] A protective film 60 made of solder resist or the like is formed on the third sealing member 53. The protective film 60 is formed with a contact hole 61 exposing the first terminal portion 112, a contact hole 62 exposing the second terminal portion 122, and a contact hole 63 exposing the third terminal portion 132.

[0040] Although not shown, signal terminal portions that are electrically connected to the pad portions of the first semiconductor chip 31 and the pad portions of the second semiconductor chip 32 are also formed on the third sealing member 43. In addition, contact holes that expose the signal terminal portions are also formed in the protective film 60.

[0041] The above is the configuration of the semiconductor module 1 in this embodiment. Next, a manufacturing method including an inspection step for such a semiconductor module 1 will be described.

[0042] In this embodiment, first, as shown in FIG. 4, a component 200 is prepared, which has a module formation region 210 and an inspection terminal portion region 220 connected to this module formation region 210. The module formation region 210 is a region in which the semiconductor module 1 described with reference to FIG. 1 is formed, and is configured to have an inspection wiring layer 141. The component 200 may be configured to have only one module formation region 210 and one inspection terminal portion region 220, or may be in the form of a wafer having a plurality of module formation regions 210 and a plurality of inspection terminal portion regions 220. In this embodiment, the inspection wiring layer 141 extends to the inspection terminal portion region 220 and is electrically connected to the inspection terminal portions 142 arranged in the inspection terminal portion region 220.

[0043] Next, a step of inspecting the insulation of the sealing member 50 located between the first wiring portion wiring layer 111 and the second wiring portion wiring layer 121, which are arranged opposite to each other, and a step of inspecting the insulation of the sealing member 50 located between the first wiring portion wiring layer 111 and the third wiring portion wiring layer 131, which are arranged opposite to each other, are performed. In this embodiment, a voltage is applied between the first terminal portion 112 (i.e., the first wiring portion wiring layer 111) and the inspection terminal portion 142 (i.e., the inspection wiring layer 141) to inspect the insulation of the third sealing member 53 located between the first wiring portion wiring layer 111 and the inspection wiring layer 141. Furthermore, a voltage is applied between the second terminal portion 122 (i.e., the second wiring portion wiring layer 121) and the inspection terminal portion 142 (i.e., the inspection wiring layer 141) to inspect the insulation of the second sealing member 52 located between the second wiring portion wiring layer 121 and the inspection wiring layer 141. Furthermore, by applying a voltage between the third terminal portion 132 (i.e., the wiring layer 131 for the third wiring portion) and the inspection terminal portion 142 (i.e., the wiring layer 141 for the inspection), the insulation of the second sealing member 52 located between the wiring layer 131 for the third wiring portion and the wiring layer 141 for the inspection is inspected.

[0044] In this embodiment, the insulation of the third sealing member 53 located between the first wiring portion wiring layer 111 and the inspection wiring layer 141 and the second sealing member 52 located between the second wiring portion wiring layer 121 and the inspection wiring layer 141 are inspected. However, the insulation between the first wiring portion wiring layer 111 and the second wiring portion wiring layer 121 is ensured as a whole if the insulation of at least one of the second sealing member 52 and the third sealing member 53 is ensured. Therefore, the insulation of the third sealing member 53 located between the first wiring portion wiring layer 111 and the inspection wiring layer 141 and the second sealing member 52 located between the second wiring portion wiring layer 121 and the inspection wiring layer 141 may be inspected by inspecting only one of them.

[0045] Furthermore, when the insulation of the second sealing member 52 located between the second wiring portion wiring layer 121 and the inspection wiring layer 141 is inspected, it is expected that the same result will be obtained for the insulation of the second sealing member 52 located between the third wiring portion wiring layer 131 and the inspection wiring layer 141. For this reason, when the insulation of the second sealing member 52 located between the second wiring portion wiring layer 121 and the inspection wiring layer 141 is inspected, the inspection of the second sealing member 52 located between the third wiring portion wiring layer 131 and the inspection wiring layer 141 may be omitted.

[0046] Thereafter, by separating terminal portion area 220 for inspection from module formation area 210 determined to have normal insulation, semiconductor module 1 is manufactured in which wiring layer 141 for inspection is disposed between first wiring portion wiring layer 111 and second wiring portion wiring layer 121. For this reason, semiconductor module 1 of the present embodiment is configured not to include terminal portion 142 for inspection, as described above with reference to FIG.

[0047] According to the present embodiment described above, the inspection wiring layer 141 is disposed between the first wiring portion wiring layer 111 and the second wiring portion wiring layer 121. When inspecting the insulation of the sealing member 50 disposed between the first wiring portion wiring layer 111 and the second wiring portion wiring layer 121, a high voltage may be applied to at least one of between the inspection wiring layer 141 and the first wiring portion wiring layer 111 and between the inspection wiring layer 141 and the second wiring portion wiring layer 121. Therefore, when inspecting the insulation of the sealing member 50 disposed between the first wiring portion wiring layer 111 and the second wiring portion wiring layer 121, a high voltage is not applied to the first semiconductor chip 31 and the second semiconductor chip 32, and damage to the first semiconductor chip 31 and the second semiconductor chip 32 can be suppressed.

[0048] Similarly, the inspection wiring layer 141 is arranged between the first wiring portion wiring layer 111 and the third wiring portion wiring layer 131. Therefore, when inspecting the insulation of the sealing member 50 arranged between the first wiring portion wiring layer 111 and the third wiring portion wiring layer 131, it is sufficient to apply a high voltage to at least one of between the inspection wiring layer 141 and the first wiring portion wiring layer 111 and between the inspection wiring layer 141 and the third wiring portion wiring layer 131. Therefore, when inspecting the insulation of the sealing member 50 arranged between the first wiring portion wiring layer 111 and the third wiring portion wiring layer 131, a high voltage is not applied to the first semiconductor chip 31 and the second semiconductor chip 32, and damage to the first semiconductor chip 31 and the second semiconductor chip 32 can be suppressed.

[0049] (1) In this embodiment, when manufacturing semiconductor module 1, component 200 is prepared by connecting inspection terminal portion area 220 to module formation area 210. Therefore, when semiconductor module 1 is manufactured, an area for arranging inspection terminal portion 142 is not required in semiconductor module 1, and miniaturization can be achieved.

[0050] (Second embodiment) A second embodiment will be described. In contrast to the first embodiment, this embodiment is configured such that a terminal portion for inspection 142 is arranged on semiconductor module 1. As the rest of the configuration is the same as that of the first embodiment, a description thereof will be omitted here.

[0051] 5, semiconductor module 1 of the present embodiment has inspection terminal portion 142 arranged therein. In the present embodiment, inspection terminal portion 142 is arranged between first terminal portion 112 and third terminal portion 132. Although details are omitted, inspection terminal portion 142 is electrically connected to inspection wiring layer 141 through an inspection via that is arranged in an inspection via hole that exposes inspection wiring layer 141. In addition, protective film 60 has a contact hole that exposes inspection terminal portion 142.

[0052] The above is the configuration of semiconductor module 1 in this embodiment. When manufacturing semiconductor module 1 in this embodiment, component 200 having module formation area 210 is prepared. Note that component 200 in this embodiment has inspection terminal portion 142 arranged in module formation area 210, and is not provided with inspection terminal portion area 220.

[0053] Then, similarly to the first embodiment, a step of inspecting the insulation of sealing member 50 is performed. At this time, in this embodiment, terminal for inspection 142 is disposed in semiconductor module 1 (i.e., module formation region 210). Therefore, when inspection is performed by applying a voltage between first terminal 112 (i.e., first wiring portion wiring layer 111) and terminal for inspection 142 (i.e., inspection wiring layer 141), the insulation of protective film 60 located between first terminal 112 and terminal for inspection 142 can also be inspected. Similarly, when inspection is performed by applying a voltage between third terminal 132 (i.e., third wiring portion wiring layer 131) and terminal for inspection 142 (i.e., inspection wiring layer 141), the insulation of protective film 60 located between third terminal 132 and terminal for inspection 142 can also be inspected.

[0054] 6, the semiconductor module 1 of this embodiment is connected to a wiring substrate 300 to form a semiconductor device. Although details are omitted, lands, wiring, and the like are appropriately formed on the wiring substrate 300. Specifically, the wiring substrate 300 is electrically connected to the semiconductor module 1 via connection members 410 arranged on the first terminal portion 112, the second terminal portion 122, and the third terminal portion 132, respectively. An insulating member 420 made of an underfill, potting resin, or the like is arranged between the semiconductor module 1 and the wiring substrate 300, and the inspection terminal portion 142 is covered with the insulating member 420. The connection member 410 is made of, for example, solder.

[0055] According to the present embodiment described above, the semiconductor module 1 is configured to include the inspection wiring layer 141, and therefore, the same effects as those of the first embodiment can be obtained.

[0056] (1) In the semiconductor module 1 of this embodiment, the semiconductor module 1 is configured to include the terminal for inspection 142. Therefore, compared to the first embodiment, there is no need to provide the terminal for inspection region 220 when manufacturing the semiconductor module 1, and the area of ​​the component 200 can be used effectively.

[0057] (2) In the semiconductor device of the present embodiment, terminal for inspection 142 is covered with insulating member 420. This makes it possible to suppress fluctuations in the potential of terminal for inspection 142 (i.e., wiring layer for inspection 141), and to suppress malfunctions of first semiconductor chip 31 and second semiconductor chip 32.

[0058] (Modification of the second embodiment) A modification of the second embodiment will be described. In the second embodiment, an example has been described in which terminal for inspection 142 is covered with insulating member 420 disposed between semiconductor module 1 and wiring board 300. However, as shown in Fig. 7 , semiconductor module 1 may be configured by disposing insulating member 430 so as to cover terminal for inspection 142, and then connected to wiring board 300. Note that while Fig. 7 shows insulating member 430 that covers only terminal for inspection 142, insulating member 430 may be a secondary molded product made of a resin material, or may be configured to entirely cover sealing member 50 so that terminals 112, 122, and 132 are exposed.

[0059] Furthermore, in the second embodiment described above, the location of terminal for inspection 142 can be changed as appropriate. For example, terminal for inspection 142 may be arranged between first terminal 112 and second terminal 122. In this way, when an inspection is performed by applying a voltage between second terminal 122 (i.e., wiring layer 121 for second wiring portion) and terminal for inspection 142 (i.e., wiring layer 141 for inspection), the insulation of protective film 60 located between second terminal 122 and terminal for inspection 142 can also be inspected.

[0060] (Third embodiment) A third embodiment will be described. In contrast to the first embodiment, this embodiment is configured such that a semiconductor device is constructed by accommodating a semiconductor module 1 in a frame portion. As other aspects are the same as those of the first embodiment, a description thereof will be omitted here.

[0061] First, in the above-described first embodiment, a manufacturing method has been described in which, when manufacturing the semiconductor module 1, a component 200 is prepared in which the inspection wiring layer 141 extends from the module formation region 210 to the inspection terminal portion region 220, and the inspection terminal portion region 220 is separated from the module formation region 210. In this case, as shown in Fig. 8, the semiconductor module 1 has an exposed portion 141a in which the inspection wiring layer 141 is exposed from the side surface 1a from which the inspection terminal portion region 220 is separated. Note that, in Fig. 8, for ease of understanding, the portion of the inspection wiring layer 141 exposed from the side surface 1a is exaggerated and shown as the exposed portion 141a.

[0062] 9, the semiconductor device of this embodiment is configured by arranging three semiconductor modules 1 in a frame portion 500. Specifically, the frame portion 500 is configured to have housing portions 510 formed therein that correspond to the outer shapes of the semiconductor modules 1. In this embodiment, three housing portions 510 are formed in the frame portion 500. The semiconductor modules 1 are housed in the housing portions 510, respectively. Therefore, the exposed portion 141a exposed from the side surface 1a of the semiconductor module 1 faces the inner wall surface of the frame portion 500 and is unlikely to be exposed to the outside. Therefore, the exposed portion 141a of the inspection wiring layer 141 is easily insulated, and malfunction of the semiconductor module 1 due to fluctuations in the potential of the inspection wiring layer 141 can be suppressed.

[0063] In the semiconductor device, in order to further ensure the insulation of the exposed portion 141a in the inspection wiring layer 141 while firmly fixing the frame portion 500 to the semiconductor module 1, a potting resin or the like may be placed in a minute gap between the frame portion 500 and the semiconductor module 1. In this case, when the wiring board 300 is placed as in the second embodiment, the insulating member 420 placed between the frame portion 500 and the wiring board 300 may be poured into the minute gap between the frame portion 500 and the semiconductor module 1.

[0064] In the semiconductor device of this embodiment, three semiconductor modules 1 are housed in a frame 500. The three semiconductor modules 1 extend along the arrangement direction of the three semiconductor modules 1. If a virtual line intersecting with the first terminal 112 of one semiconductor module 1 is defined as a first virtual line K1, the first terminal 112 of each semiconductor module 1 is arranged so as to intersect with the first virtual line K1. The three semiconductor modules 1 extend along the arrangement direction of the three semiconductor modules 1. If a virtual line intersecting with the second terminal 122 of one semiconductor module 1 is defined as a second virtual line K2, the second terminal 122 of each semiconductor module 1 is arranged so as to intersect with the second virtual line K2. The three semiconductor modules 1 extend along the arrangement direction of the three semiconductor modules 1. If a virtual line intersecting with the third terminal 132 of one semiconductor module 1 is defined as a third virtual line K3, the third terminal 132 of each semiconductor module 1 is arranged so as to intersect with the third virtual line K3. That is, the three semiconductor modules 1 are arranged so as to face in the same direction.

[0065] According to the present embodiment described above, the semiconductor module 1 is configured to include the inspection wiring layer 141, and therefore, the same effects as those of the first embodiment can be obtained.

[0066] (1) In the semiconductor device of this embodiment, the semiconductor module 1 is housed in a frame 500, and the exposed portion 141a of the inspection wiring layer 141 faces the inner wall surface of the frame 500. This makes it easier for the exposed portion 141a of the inspection wiring layer 141 to be insulated, and it is possible to prevent malfunction of the semiconductor module 1 due to fluctuations in the potential of the inspection wiring layer 141.

[0067] (2) The semiconductor device of this embodiment includes a plurality of semiconductor modules 1, and the first terminal portion 112, the second terminal portion 122, and the third terminal portion 132 of each semiconductor module 1 are arranged so as to intersect with the imaginary lines K1 to K3 extending along the arrangement direction of the semiconductor modules 1. Therefore, when connecting the semiconductor module 1 to the wiring board 300, it is easy to design the lands and wiring on the wiring board 300 side.

[0068] (Fourth embodiment) A fourth embodiment will be described. In this embodiment, a semiconductor device is configured using the semiconductor module 1 of the first embodiment. As other aspects are the same as those of the first embodiment, a description thereof will be omitted here.

[0069] 10, the semiconductor device of this embodiment includes three semiconductor modules 1. Although not specifically shown, similar to the second embodiment, the semiconductor device is configured such that the first terminal portion 112, the second terminal portion 122, and the third terminal portion 132 of each semiconductor module 1 are electrically connected to the wiring substrate 400 via the connecting member 410.

[0070] In this embodiment, the semiconductor modules 1 are arranged side by side with gaps between them. In this embodiment, the insulating member 420 arranged between the semiconductor module 1 and the wiring substrate 400 described in the second embodiment is also arranged between adjacent semiconductor modules 1. More specifically, the insulating member 420 is arranged so as to cover the exposed portion 141a on the side surface 1a of each semiconductor module 1.

[0071] According to the present embodiment described above, the semiconductor module 1 is configured to include the inspection wiring layer 141, and therefore, the same effects as those of the first embodiment can be obtained.

[0072] (1) The semiconductor device of this embodiment includes multiple semiconductor modules 1, and the insulating member 420 disposed between the semiconductor modules 1 and the wiring substrate 300 is disposed so as to cover the exposed portion 141a of each semiconductor module 1. Therefore, there is no need to prepare a separate member to cover the exposed portion 141a, and an increase in the number of members can be suppressed.

[0073] (Other embodiments) Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0074] In the above embodiments, the semiconductor module 1 has been described as including a first semiconductor chip 31 and a second semiconductor chip 32. However, the semiconductor module 1 may have one semiconductor chip, or may have three or more semiconductor chips. Furthermore, the number of wiring layers connected to the semiconductor chips can be changed as appropriate, as long as there are two wiring layers facing each other across the sealing member 50, and the inspection wiring layer 141 is disposed between these two wiring layers.

[0075] In addition, in each of the above embodiments, the semiconductor module 1 is described as having the first to third wiring portions 101 to 103. However, the number of wiring portions provided in the semiconductor module 1 can be changed as appropriate. In the third and fourth embodiments, the number of semiconductor modules 1 can be changed as appropriate. [Explanation of symbols]

[0076] 31, 32 Semiconductor chips 50 Sealing member 111 Wiring layer for first wiring part 112 1st terminal section 121 Wiring layer for second wiring section 122 2nd terminal section 141 Inspection wiring layer

Claims

1. A semiconductor module, Semiconductor chips (31, 32); a sealing member (50) that seals the semiconductor chip; a wiring layer (111) for a first wiring portion connected to the semiconductor chip; a first terminal portion (112) disposed on the sealing member and electrically connected to the first wiring portion wiring layer; a wiring layer (121) for a second wiring portion connected to the semiconductor chip; a second terminal portion (122) disposed on the sealing member and electrically connected to the second wiring portion wiring layer; at least one of the first wiring portion wiring layer and the second wiring portion wiring layer is disposed within the sealing member and has portions disposed opposite to each other across the sealing member; A semiconductor module in which an inspection wiring layer (141) that is not connected to the semiconductor chip is disposed between the wiring layer for the first wiring portion and the wiring layer for the second wiring portion.

2. 2. The semiconductor module according to claim 1, wherein a terminal for inspection (141) electrically connected to the wiring layer for inspection is disposed on the sealing member.

3. 3. The semiconductor module according to claim 2, wherein a protective film (60) is disposed on the sealing member, the protective film having formed therein contact holes (61) that expose the first terminal portion, contact holes (62) that expose the second terminal portion, and contact holes that expose the inspection terminal portion.

4. 4. The semiconductor module according to claim 2, wherein the terminal for inspection is covered with an insulating member (430).

5. A semiconductor device, The semiconductor module according to claim 2; a wiring substrate (300) disposed opposite the semiconductor module and electrically connected to the first terminal portion and the second terminal portion of the semiconductor chip; The semiconductor device further comprises an insulating member (420) disposed between the semiconductor module and the wiring board, the insulating member covering the terminals for inspection.

6. A semiconductor device, The semiconductor module according to claim 1 ; a frame portion (500) in which a housing portion (510) for housing the semiconductor module is formed, The semiconductor module has an exposed portion (141a) in which the inspection wiring layer is exposed from one side surface (1a) of the sealing member, and is a semiconductor device accommodated in the accommodation portion so that the exposed portion faces the inner wall surface of the frame portion.

7. A semiconductor device, The semiconductor module according to claim 1 ; a wiring substrate (300) disposed opposite the semiconductor module and electrically connected to the first terminal portion and the second terminal portion of the semiconductor chip; the semiconductor module has an exposed portion (141a) where the inspection wiring layer is exposed from one side surface (1a) of the sealing member, An insulating member (420) is disposed between the semiconductor module and the wiring board, The insulating member is disposed so as to cover the exposed portion.

8. Semiconductor chips (31, 32); a sealing member (50) that seals the semiconductor chip; a wiring layer (111) for a first wiring portion connected to the semiconductor chip; a first terminal portion (112) disposed on the sealing member and electrically connected to the first wiring portion wiring layer; a wiring layer (121) for a second wiring portion connected to the semiconductor chip; a second terminal portion (122) disposed on the sealing member and electrically connected to the second wiring portion wiring layer; at least one of the first wiring portion wiring layer and the second wiring portion wiring layer is disposed within the sealing member and has portions disposed opposite to each other across the sealing member; A method for manufacturing a semiconductor module, wherein an inspection wiring layer (141) that is not connected to the semiconductor chip is disposed between the first wiring portion wiring layer and the second wiring portion wiring layer, preparing a component (200) including: a module formation area (210) having the semiconductor chip, the wiring layer for the first wiring portion, the first terminal portion, the wiring layer for the second wiring portion, the second terminal portion, the wiring layer for inspection, and the sealing member; and a terminal portion for inspection (142) electrically connected to the wiring layer for inspection; and inspecting the insulation of the sealing member disposed between the wiring layer for the first wiring portion and the wiring layer for the second wiring portion by applying a voltage to the inspection terminal portion and at least one of the first terminal portion and the second terminal portion.

9. The preparation of the component includes preparing a component having the module formation area and a terminal for inspection area (220) connected to the module formation area and in which the terminal for inspection is arranged, 9. The method for manufacturing a semiconductor module according to claim 8, wherein the module formation area and the terminal area for inspection are separated after inspecting the insulation.

10. 9. The method for manufacturing a semiconductor module according to claim 8, wherein preparing the component includes preparing a component in which the terminals for inspection are arranged in the module formation region.

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