Semiconductor device

Abstract

To provide a semiconductor device capable of improving reliability.SOLUTION: A semiconductor device comprises: a semiconductor layer including a first principal surface and a second principal surface on an opposite side of the first principal surface; a first conductive part which is provided on the first principal surface of the semiconductor layer; a second conductive part which is provided on the second principal surface of the semiconductor layer and joined to a metal piece via a joint material having conductivity; and a damming part which is provided on the first principal surface outside of the first conductive part and electrically insulated from the first conductive part and the second conductive part. The joint material is not in contact with the first conductive part.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] In a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the drift electrode is bonded to the die pad via a conductive bonding material such as solder. The source electrode and drift electrode of a MOSFET are connected to different potentials during use, creating a potential difference between the source electrode and the drift electrode. This potential difference can cause the bonding material to flow toward the source electrode or the source wiring layer electrically connected to the source electrode. If the bonding material comes into contact with the source electrode or the source wiring layer, a short circuit may occur between the source electrode or the source wiring layer and the drift electrode via the bonding material. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-77674 [Patent Document 2] Patent No. 7175095 [Patent Document 3] Japanese Patent Publication No. 2022-110431 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present invention provide a semiconductor device that can improve reliability. [Means for solving the problem]

[0005] The semiconductor device according to this embodiment includes a semiconductor layer having a first main surface and a second main surface opposite to the first main surface, a first conductive portion provided on the first main surface of the semiconductor layer, a second conductive portion provided on the second main surface of the semiconductor layer and joined to a metal piece via a conductive bonding material, and a dam portion provided on the first main surface outside the first conductive portion and electrically insulated from the first conductive portion and the second conductive portion. The bonding material is not in contact with the first conductive portion. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a plan view of a semiconductor device according to an embodiment; [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] 2 is an enlarged cross-sectional view of a peripheral region of the semiconductor device according to the embodiment; [Figure 4] 2 is a cross-sectional view taken along the line AA in FIG. 1, illustrating the blocking of the bonding material by the blocking portion. FIG. [Figure 5A] 1A to 1C are cross-sectional views for explaining an example of a manufacturing process of a semiconductor device according to an embodiment. [Figure 5B] 5B is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the embodiment, following FIG. 5A. [Figure 5C] 5C is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the embodiment, following FIG. 5B. [Figure 5D] 5D is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the embodiment, following FIG. 5C. [Figure 6] FIG. 10 is a plan view of a semiconductor device according to a first modified example of the embodiment. [Figure 7] FIG. 10 is a plan view of a semiconductor device according to a second modification of the embodiment. [Figure 8] FIG. 10 is a plan view of a semiconductor device according to a third modification of the embodiment. [Figure 9] FIG. 10 is an enlarged cross-sectional view of a peripheral region in a semiconductor device according to a fourth modification of the embodiment. [Figure 10]FIG. 11 is an enlarged cross-sectional view of a peripheral region in a semiconductor device according to a fifth modification of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments do not limit the present invention. The drawings are schematic or conceptual, and the proportions of each part are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0008] For convenience of explanation, the source electrode side in the stacking direction (thickness direction) of the semiconductor device is also referred to as "upper" and the drain electrode side as "lower." However, these expressions are for convenience only and have no relation to the direction of gravity.

[0009] In the following description, n is used to indicate the relative level of impurity concentration in each conductivity type. + , n, n - , and ,p + , p, p - In some cases, the notation n + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than p. When both p-type and n-type impurities are contained in each region, these notations represent the relative high and low net impurity concentrations after the impurities compensate for each other. Note that in the following explanation, n-type and p-type may be reversed.

[0010] The impurity concentration of a semiconductor region can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS), and the relative level of the impurity concentration can be determined from the carrier concentration determined by, for example, Scanning Capacitance Microscopy (SCM).

[0011] Furthermore, dimensions such as the width of the damming portion can be measured by surface and / or cross-sectional analysis using, for example, a transmission electron microscope (TEM), energy dispersive X-ray spectroscopy (EDX), or a scanning electron microscope (SEM).

[0012] A semiconductor device 1 according to one embodiment will be described with reference to Figures 1 to 3. Figure 1 is a plan view of the semiconductor device 1 according to this embodiment. Figure 2 is a cross-sectional view of the semiconductor device 1 according to this embodiment taken along line AA in Figure 1. Figure 3 is an enlarged cross-sectional view of a peripheral region ER in the semiconductor device 1 according to this embodiment.

[0013] The semiconductor device 1 is, for example, a diode or a vertical transistor such as a bipolar transistor, a MOSFET, an IGBT (Insulated Gate Bipolar Transistor), etc. In the following, an example will be described in which the semiconductor device 1 is a vertical MOSFET.

[0014] 1 and 2, the semiconductor device 1 according to this embodiment includes a semiconductor layer 2, a source wiring layer 3, a drain electrode 4, a bonding material 5, a die pad 6, a blocking portion 7, an insulating protection portion 8, and a sealing portion 9. Note that the sealing portion 9 is omitted in FIG.

[0015] The semiconductor layer 2 is provided with a drift region 21, which will be described later. The semiconductor layer 2 may be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate with an epitaxial layer disposed thereon. In this embodiment, the semiconductor layer 2 is silicon (Si). In this case, for example, arsenic (As), phosphorus (P), or antimony (Sb) is used as the n-type impurity, and for example, boron (B) is used as the p-type impurity. The material of the semiconductor layer 2 is not particularly limited. The semiconductor layer 2 may be made of a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN).

[0016] 2, the semiconductor layer 2 has an upper surface (first main surface) 2a, a lower surface (second main surface) 2b opposite to the upper surface 2a, and a side surface 2c which is a dicing surface. A source wiring layer 3 is provided on the upper surface 2a of the semiconductor layer 2, and a drain electrode 4 is provided on the lower surface 2b of the semiconductor layer 2.

[0017] The source wiring layer 3 is a wiring layer electrically connected to a source electrode (not shown). In this embodiment, the source wiring layer 3 is a wiring layer electrically connected to the source electrode and located at an end (terminal) on the upper surface 2a of the semiconductor layer 2. The source wiring layer 3 is made of, for example, aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), or the like. The source wiring layer 3 is an example of a first conductive portion in the claims.

[0018] The drain electrode 4 functions as a drain electrode of the MOSFET. When the semiconductor device 1 is in use, the drain electrode 4 is connected to a different potential from that of the source wiring layer 3. That is, when the semiconductor device 1 is in use, a potential difference occurs between the source wiring layer 3 and the drain electrode 4. The drain electrode 4 is made of, for example, aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), or the like. The drain electrode 4 is an example of a second conductive portion in the claims.

[0019] Next, an example of the internal structure of the semiconductor layer 2 will be described.

[0020] As shown in FIGS. 2 and 3, the semiconductor layer 2 includes a cell region (current region) CR and a peripheral region (termination region) ER.

[0021] The cell region CR is connected to the source wiring layer 3 and the drain electrode 4, and is a region through which a current flows between the source wiring layer 3 and the drain electrode 4. As shown in Fig. 3, the cell region CR is provided with a drift region 21, an insulating region 22, and a field plate electrode (FP electrode) 23.

[0022] The drift region 21 functions as a drift region of the MOSFET. The drift region 21 is, for example, - The n-type impurity concentration of the drift region 21 is, for example, 1×10 15 cm -3 Over 2×10 16 cm -3 The following is the result.

[0023] The insulating region 22 is an insulating film that covers the sidewalls of a trench provided in the upper surface 2a of the semiconductor layer 2. The insulating region 22 includes, for example, silicon oxide or silicon nitride.

[0024] The FP electrode 23 is provided in the semiconductor layer 2 via an insulating region 22. The FP electrode 23 is made of, for example, polysilicon containing p-type or n-type impurities. The FP electrode 23 is electrically connected to the source electrode. By providing such an FP electrode 23, the concentration of the reverse electric field between the source wiring layer 3 and the drain electrode 4 is alleviated, and the breakdown voltage of the semiconductor device 1 is improved.

[0025] Although not shown, the cell region CR is provided with n-type semiconductor regions such as a drain region and a source region, and p-type semiconductor regions such as a base region, etc. In this embodiment, the source wiring layer 3 is provided on the cell region CR.

[0026] The peripheral region ER is a region provided around the cell region CR. The peripheral region ER is located between the cell region CR and the side surface 2c of the semiconductor layer 2. The peripheral region ER is electrically insulated from the cell region CR. In other words, when a current flows through the cell region CR, no current flows through the peripheral region ER.

[0027] 3 is merely an example, and the present embodiment is not limited to this. For example, in the example of FIG. 3, six FP electrodes 23 are provided. However, the present invention is not limited to this, and more or less than six FP electrodes 23 may be provided, or no FP electrodes 23 may be provided.

[0028] 2, the drain electrode 4 is bonded to a metal piece such as a die pad 6 that is part of a lead frame via a bonding material 5. The bonding material 5 is a bonding material having conductivity such as solder or conductive paste.

[0029] The damming portion 7 is provided on the upper surface 2a outside (on the dicing surface side of) the source wiring layer 3, and spaced apart from the source wiring layer 3. More specifically, as shown in FIG. 3, the damming portion 7 is provided on the upper surface 2a of the semiconductor layer 2, at a position closer to the side portion S1 of the upper surface 2a than the source wiring layer 3. In this embodiment, the damming portion 7 is provided on a portion of the upper surface 2a that is exposed in the peripheral region ER and not covered by the insulating protection portion 8. Also, as shown in FIG. 3, the height H1 of the damming portion 7 is equal to the height H2 of the source wiring layer 3.

[0030] The blocking portion 7 is made of a conductive material such as a metal material. This metal material may be a material that does not form a passive state and bonds with the bonding material 5. Such a metal material includes, for example, at least one of copper, titanium, tungsten, and platinum. This allows the bonding material 5 to adhere to the blocking portion 7, improving the effect of blocking the contact of the bonding material 5 with the source wiring layer 3 (hereinafter referred to as the "blocking effect").

[0031] Alternatively, when the damming portion 7 includes a metal material, the metal material may be a material that forms a passive state and repels the bonding material 5. Such a metal material includes, for example, at least one of aluminum, nickel, iron, chromium, and cobalt. This allows the bonding material 5 to be repelled by the damming portion 7, thereby improving the damming effect of the damming portion 7.

[0032] Alternatively, the damming portion 7 may be made of the same material as the source wiring layer 3. This allows the damming portion 7 to be formed simultaneously with the source wiring layer 3. The damming portion 7 may contain an insulating material that is stronger than the material of the insulating protection portion 8.

[0033] The blocking portion 7 is electrically insulated from the source wiring layer 3, the drain electrode 4, and other wirings and electrodes in the semiconductor device 1, and is configured to block contact of the bonding material 5 with the source wiring layer 3.

[0034] The insulating protection portion 8 is provided to protect the source wiring layer 3. The insulating protection portion 8 is provided on the upper surface 2a of the semiconductor layer 2, and covers the source wiring layer 3. The insulating protection portion 8 is made of, for example, polyimide.

[0035] In this embodiment, the insulating protective portion 8 does not cover the blocking portion 7. That is, the blocking portion 7 is provided at a distance from the insulating protective portion 8. In this embodiment, the portion of the upper surface 2a of the semiconductor layer 2 that is not covered by the insulating protective portion 8 serves as a dicing line when manufacturing the semiconductor device 1. The blocking portion 7 is provided on the dicing line.

[0036] As shown in Fig. 2, the sealing portion 9 seals the semiconductor layer 2, the source wiring layer 3, the drain electrode 4, the bonding material 5, the die pad 6, the blocking portion 7, and the insulating protection portion 8. The sealing portion 9 is made of, for example, epoxy resin. Note that in Fig. 2, the sealing portion 9 does not cover the underside of the die pad 6 opposite the bonding material 5. However, the present invention is not limited to this, and the sealing portion 9 may cover the underside of the die pad 6.

[0037] Here, the blocking of the bonding material 5 by the blocking portion 7 will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view of the semiconductor device 1 according to this embodiment during operation, taken along line AA in Fig. 1.

[0038] As shown in Fig. 4, when the semiconductor device 1 is in use, the potential difference between the source wiring layer 3 and the drain electrode 4 causes the bonding material 5 to gradually flow from the drain electrode 4 toward the source wiring layer 3. In the example of Fig. 4, the bonding material 5 creeps up along the side surface 2c of the semiconductor layer 2 to the upper surface 2a of the semiconductor layer 2 and flows toward the source wiring layer 3. However, as shown in Fig. 4, the blocking portion 7 blocks the bonding material 5, thereby preventing the bonding material 5 from contacting the source wiring layer 3. That is, in this embodiment, the bonding material 5 does not contact the source wiring layer 3 even when the semiconductor device 1 is in use.

[0039] As described above, the semiconductor device 1 according to this embodiment includes a semiconductor layer 2 having an upper surface 2a and a lower surface 2b, a source wiring layer 3 provided on the upper surface 2a of the semiconductor layer 2, a drain electrode 4 provided on the lower surface 2b of the semiconductor layer 2 and bonded to a die pad 6 via a conductive bonding material 5, and a dam portion 7 provided on the upper surface 2a outside the source wiring layer 3, electrically insulated from the source wiring layer 3 and the drain electrode 4, and blocking contact of the bonding material 5 with the source wiring layer 3.

[0040] As described above, in this embodiment, when the semiconductor device 1 is in use, the potential difference between the source wiring layer 3 and the drain electrode 4 causes the bonding material 5 to flow toward the source wiring layer 3, and the dam portion 7 is provided to prevent the bonding material 5 from coming into contact with the source wiring layer 3. Therefore, according to this embodiment, it is possible to prevent the source wiring layer 3 and the drain electrode 4 from shorting out via the bonding material 5. As a result, the reliability of the semiconductor device 1 can be improved.

[0041] In this embodiment, the source wiring layer 3 is provided on the cell region CR, and the blocking portion 7 is provided on the peripheral region ER. However, the present invention is not limited to this, and the source wiring layer 3 may be provided in the peripheral region ER as long as it is provided inside the blocking portion 7 (opposite the dicing surface). Alternatively, the blocking portion 7 may be provided on the cell region CR as long as it is provided outside the source wiring layer 3 and electrically insulated from the cell region CR by an interlayer insulating film or the like.

[0042] 1, the semiconductor layer 2 according to this embodiment has a rectangular planar shape, and the damming portion 7 is provided on the upper surface 2a of the semiconductor layer 2 so as to surround the source wiring layer 3 provided on the cell region CR. In other words, the damming portion 7 according to this embodiment forms a closed curve that surrounds the source wiring layer 3 on the upper surface 2a of the semiconductor layer 2. The semiconductor layer 2 may have a planar shape other than a rectangle, such as a circle or a polygon. In such a case, the damming portion 7 may have a shape that follows the shape of the side of the semiconductor device 1.

[0043] Furthermore, in this embodiment, as described above, the height H1 of the damming portion 7 is equal to the height H2 of the source wiring layer 3. However, this is not limiting, and the height H1 and width W1 of the damming portion 7 are arbitrary. For example, the width W1 of the damming portion 7 may be equal to or greater than the height H1 of the damming portion 7. This increases the strength of the damming portion 7 and the processing stability during manufacturing of the semiconductor device 1, thereby improving the reliability of the semiconductor device 1.

[0044] <Method of Manufacturing Semiconductor Device 1> Next, an example of a method for manufacturing the semiconductor device 1 will be described with reference to Figures 5A to 5D. Figures 5A to 5D are cross-sectional views for explaining an example of a manufacturing process for the semiconductor device according to this embodiment.

[0045] First, as shown in FIG. 5A, a semiconductor member having a semiconductor wafer 20, a conductive layer 30 provided on the upper surface 2a of the semiconductor wafer 20, and a resist pattern 40 provided on the conductive layer 30 is prepared.

[0046] Such a semiconductor component can be obtained, for example, as follows. First, a semiconductor wafer 20 is prepared. The semiconductor wafer 20 is provided with a drift region 21, an insulating region 22, an FP electrode 23, and the like. Next, a conductive layer 30 is formed on the upper surface 2a of the semiconductor wafer 20. The conductive layer 30 is formed, for example, by depositing aluminum on the upper surface 2a by sputtering. Thereafter, a resist is applied onto the conductive layer 30 to form a resist film, and the resist film is patterned by photolithography or the like to form a resist pattern 40. This results in the semiconductor component shown in FIG. 5A.

[0047] 5B, the conductive layer 30 that is not covered by the resist pattern 40 is removed by isotropic or anisotropic etching such as wet etching or reactive ion etching (RIE). This results in patterning of the conductive layer 30, and the source wiring layer 3 and the blocking portion 7 are formed. In this example, the blocking portion 7 is formed on the dicing line.

[0048] Next, as shown in FIG. 5C, the resist pattern 40 is removed.

[0049] 5D, an insulating material such as polyimide is applied to form an insulating protection portion 8 that covers the source wiring layer 3. For example, after polyimide is applied to the entire upper surface 2a and cured, the cured insulating film that covers the blocking portion 7 is removed by photolithography.

[0050] Thereafter, although not shown, a drain electrode 4 is formed on the lower surface of the semiconductor wafer 20. Thereafter, the semiconductor wafer 20 is diced so that the dam portion 7 remains.

[0051] Thereafter, the drain electrode 4 is bonded to the die pad 6 via the bonding material 5, and sealed with the sealing portion 9. Through the above steps, the semiconductor device 1 is manufactured.

[0052] According to the manufacturing method of this embodiment, it is possible to form the source wiring layer 3 and the blocking portion 7 at the same time, and therefore it is possible to easily manufacture the semiconductor device 1 including the blocking portion 7 at low cost.

[0053] Modifications of this embodiment will be described below. Any of the modifications can provide the same effects as this embodiment.

[0054] (Variation 1) A semiconductor device 1A according to a first modification of the embodiment will be described with reference to Fig. 6. Fig. 6 is a plan view of the semiconductor device 1A according to this modification. Note that the source wiring layer 3 and the insulating protection portion 8 are omitted in Fig. 6. One of the differences between the above-described embodiment and this modification is the planar shape of the blocking portion.

[0055] As shown in FIG. 6, unlike the damming portions 7 of the embodiment, the damming portions 7A of this modification are not provided at the corners of the semiconductor layer 2. In the example of FIG. 6, the semiconductor layer 2 has a rectangular planar shape, and the damming portions 7A are not provided on lines connecting the center of the upper surface 2a (the center of the cell region CR) to each of the four corners of the upper surface 2a. More specifically, the damming portions 7A include a damming portion 7a provided on the upper surface 2a between the cell region CR and the side S1, a damming portion 7b provided between the cell region CR and the side S2, a damming portion 7c provided between the cell region CR and the side S3, and a damming portion 7d provided between the cell region CR and the side S4. The damming portions 7a to 7d each block the bonding material 5 that creeps up from the side portions S1 to S4 and flows toward the source wiring layer 3. In the example of FIG. 6, the blocking portions 7a and 7c are equal to the length of the source wiring layer 3 in the vertical direction in the figure, and the blocking portions 7b and 7d are equal to the length of the source wiring layer 3 in the horizontal direction in the figure.

[0056] When the bonding material 5 flows toward the source wiring layer 3 due to a potential difference generated between the source wiring layer 3 and the drain electrode 4, the bonding material 5 is more likely to flow onto the upper surface 2a through the side portions S1 to S4 of the semiconductor layer 2 than through the corner portions of the semiconductor layer 2. Therefore, there is less need to provide the dam portion 7A at the corner portions of the semiconductor layer 2 compared to the side portions S1 to S4 of the semiconductor layer 2.

[0057] This allows for greater freedom in designing the damming portion 7A.

[0058] The semiconductor layer 2 may have a planar shape other than a rectangle, such as a polygon. In such a case, the damming portion 7A may be configured by the same number of damming portions as the number of sides of the semiconductor device 1.

[0059] (Variation 2) Next, a semiconductor device 1B according to a second modification of the embodiment will be described with reference to Fig. 7. Fig. 7 is a plan view of the semiconductor device 1B according to the second modification of the embodiment. Note that the source wiring layer 3 and the insulating protection portion 8 are omitted in Fig. 7. One of the differences between the above-described embodiment and this modification is the planar shape of the blocking portion.

[0060] 7, the damming portion 7B of this modification has a bent planar shape on the upper surface 2a of the semiconductor layer 2. In this manner, the damming portion 7B may have a plurality of curved and / or linear portions.

[0061] According to this modification, the area of ​​the side surface of the damming portion increases, and more of the damming portion 7B faces the bonding material 5 that has crawled up to the upper surface 2a of the semiconductor layer 2. This improves the damming effect of the damming portion 7B. Note that if the damming portion 7B does not form a passivation state or contains a metal material that forms a passivation state, the damming portion 7B will bond more closely with or repel more strongly from the bonding material 5, thereby further improving the damming effect.

[0062] (Variation 3) Next, a semiconductor device 1C according to a third modification of the embodiment will be described with reference to Fig. 8. Fig. 8 is a plan view of the semiconductor device 1C according to the third modification of the embodiment. Note that the source wiring layer 3 and the insulating protection portion 8 are omitted in Fig. 8. One of the differences between the above-described embodiment and this modification is the number of blocking portions.

[0063] 8, the damming portion 7C of this modification surrounds the cell region CR, i.e., includes a damming portion 7e (inner damming portion) surrounding the source wiring layer 3, and a damming portion 7f (outer damming portion) surrounding the damming portion 7e. In this manner, in this modification, a plurality of damming portions 7e, 7f are provided on the upper surface 2a (main surface) of the semiconductor layer 2 between the source wiring layer 3 and the side portions S1 to S4 of the semiconductor layer 2. This can improve the damming effect of the damming portion 7C.

[0064] In addition, on the upper surface 2a (main surface) of the semiconductor layer 2, a plurality of damming portions 7e, 7f may be provided between the source wiring layer 3 and at least one of the sides S1 to S4 of the semiconductor layer 2.

[0065] 8, two damming portions 7e and 7f are provided, but a damming portion (not shown) surrounding damming portion 7f may be further provided. More generally, depending on the distance between source wiring layer 3 and at least one of sides S1 to S4 of semiconductor layer 2, three or more damming portions may be provided between source wiring layer 3 and at least one of sides S1 to S4.

[0066] Furthermore, the planar shape of the blocking portion 7C of this modification is not particularly limited. For example, in the blocking portion 7C, the inner blocking portion 7e may have a notch only between it and the side portion S1, and the outer blocking portion 7d may have a notch only between it and the side portion S3. By adopting such a shape, the flow path of the bonding material 5 from the drain electrode 4 to the source wiring layer 3 becomes longer, thereby improving the blocking effect of the blocking portion 7C.

[0067] Furthermore, the multiple damming portions 7e, 7f of the damming portion 7C may contain different materials. For example, the damming portion 7e may contain a metal material that bonds with the bonding material 5, and the damming portion 7f may contain a metal material that repels the bonding material 5. Conversely, the damming portion 7e may contain a metal material that repels the bonding material 5, and the damming portion 7f may contain a metal material that bonds with the bonding material 5. This combines the different properties, thereby improving the damming effect of the damming portion 7C.

[0068] (Variation 4) Next, a semiconductor device 1D according to a fourth modification of the embodiment will be described with reference to Fig. 9. Fig. 9 is an enlarged cross-sectional view of a peripheral region ER in the semiconductor device 1D according to the fourth modification of the embodiment. One of the differences between the above-described embodiment and this modification is that the blocking portion is plated.

[0069] 9, the blocking portion 7D of this modification has a main body portion 71 and a plating portion 72 that covers the main body portion 71. The main body portion 71 corresponds to the blocking portion 7 of the embodiment. The height H3 of the blocking portion 7D, which is the combination of the main body portion 71 and the plating portion 72, is greater than the height H2 of the source wiring layer 3. Furthermore, the width W2 of the blocking portion 7D, which is the combination of the main body portion 71 and the plating portion 72, is greater than the width W1 of the main body portion 71. This improves the blocking effect of the blocking portion 7D.

[0070] The main body portion 71 may be made of the same material as the source wiring layer 3. This allows the main body portion 71 and the source wiring layer 3 to be formed simultaneously.

[0071] Furthermore, the plating portion 72 may be made of the same material as the main body portion 71, or may be made of a different material. If the plating portion 72 is made of a different material from the main body portion 71, for example, when the main body portion 71 is formed simultaneously with the source wiring layer 3, the metal material for the surface of the damming portion 7D can be selected more freely. For example, the main body portion 71 may be made of a metal material that bonds with the bonding material 5, and the plating portion 72 may be made of a metal material that repels the bonding material 5. Conversely, the main body portion 71 may be made of a metal material that repels the bonding material 5, and the plating portion 72 may be made of a metal material that bonds with the bonding material 5.

[0072] (Variation 5) Next, a semiconductor device 1E according to a fifth modification of the embodiment will be described with reference to Fig. 10. Fig. 10 is an enlarged cross-sectional view of a peripheral region ER in the semiconductor device 1E according to the fifth modification of the embodiment. One of the differences between the above-described embodiment and this modification is that the blocking portion 7 is covered with an insulating protection portion 8A.

[0073] As shown in FIG. 10, the blocking portion 7 of this modification is covered with an insulating protective portion 8A provided on the upper surface 2a of the semiconductor layer 2.

[0074] This eliminates the need for a photolithography process for the insulating protection portion, and allows for easy manufacturing of the semiconductor device 1 E. Furthermore, when sealing with the sealing portion 9, the blocking portion 7 E can be protected.

[0075] In the example of FIG. 10, the entire blocking portion 7 is covered with the insulating protective portion 8A, but a portion of the blocking portion 7 may not be covered with the insulating protective portion 8A.

[0076] The above describes the embodiments and modifications. In the above-described embodiments and modifications, the source wiring layer 3 corresponds to the first conductive portion and the drain electrode 4 corresponds to the second conductive portion. However, this does not necessarily apply to the first conductive portion and the second conductive portion, as long as they are connected to different potentials during operation of the semiconductor device 1. For example, the first conductive portion in the claims may be a source electrode disposed at the end (terminal) of the semiconductor device 1, or another conductive portion electrically connected to the source electrode and located at the end of the semiconductor device 1, such as a source pad. As another example, the first conductive portion in the claims may be a gate electrode disposed at the end of the semiconductor device 1, or another conductive portion electrically connected to the gate electrode and located at the end of the semiconductor device 1, such as a gate wiring layer or a gate pad. As yet another example, the first conductive portion may be a drain electrode disposed at the end of the semiconductor device 1, or another conductive portion electrically connected to the drain electrode, and the second conductive portion may be a source electrode or a gate electrode. In these examples, the blocking portion blocks contact of the bonding material with the source electrode, source pad, gate wiring layer, gate electrode, gate pad, drain electrode, or the like.

[0077] Although the embodiments of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These embodiments and examples can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and examples and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims.

[0078] (Appendix 1) a semiconductor layer having a first major surface and a second major surface opposite the first major surface; a first conductive portion provided on the first main surface of the semiconductor layer; a second conductive portion provided on the second main surface of the semiconductor layer and bonded to a metal piece via a conductive bonding material; a dam portion provided on the first main surface outside the first conductive portion and electrically insulated from the first conductive portion and the second conductive portion, The bonding material is not in contact with the first conductive portion. Semiconductor device. (Appendix 2) 2. The semiconductor device according to claim 1, wherein the blocking portion blocks contact of the bonding material with the first conductive portion. (Appendix 3) a current region provided in the semiconductor layer, connected to the first conductive portion and the second conductive portion, through which a current flows between the first conductive portion and the second conductive portion; a peripheral region provided in the semiconductor layer around the current region and electrically insulated from the current region; Furthermore, 3. The semiconductor device according to claim 1, wherein the blocking portion is provided on the first main surface in the peripheral region. (Appendix 4) 4. The semiconductor device according to claim 1, wherein the blocking portion is provided so as to surround the first conductive portion. (Appendix 5) the semiconductor layer has a rectangular planar shape, 5. The semiconductor device according to claim 4, wherein the blocking portion is not provided on a line connecting a center of the first main surface and a corner of the first main surface. (Appendix 6) 4. The semiconductor device according to any one of claims 1 to 3, wherein the blocking portion has a bent planar shape. (Appendix 7) 4. The semiconductor device according to any one of claims 1 to 3, wherein a plurality of the blocking portions are provided between the first conductive portion and the side portion of the semiconductor layer. (Appendix 8) 8. The semiconductor device according to any one of claims 1 to 7, wherein the blocking portion has a main body made of the same material as the first conductive portion. (Appendix 9) 9. The semiconductor device according to claim 8, wherein the blocking portion further includes a plating portion that covers the main body portion and is made of a material different from that of the first conductive portion. (Appendix 10) 8. The semiconductor device according to any one of claims 1 to 7, wherein the blocking portion has a main body portion and a plating portion that covers the main body portion. (Appendix 11) further comprising an insulating protection part that covers the first conductive part; 11. The semiconductor device according to claim 9, wherein the blocking portion is provided at a distance from the insulating protection portion. (Appendix 12) 12. The semiconductor device according to any one of claims 1 to 11, wherein the blocking portion includes a metal material. (Appendix 13) 13. The semiconductor device according to claim 12, wherein the metal material of the blocking portion is a material that bonds with the bonding material. (Appendix 14) 14. The semiconductor device of claim 13, wherein the metal material of the blocking portion includes at least one of copper, titanium, tungsten, and platinum. (Appendix 15) 13. The semiconductor device according to claim 12, wherein the metal material of the blocking portion is a material that repels the bonding material. (Appendix 16) 16. The semiconductor device according to claim 15, wherein the metal material of the blocking portion includes at least one of aluminum, nickel, iron, chromium, and cobalt. (Appendix 17) further comprising an insulating protection part that covers the first conductive part; The semiconductor device according to any one of claims 1 to 10 and claims 12 to 16 depending from claims 1 to 10, wherein the blocking portion is covered with the protective layer. (Appendix 18) 18. The semiconductor device according to any one of claims 1 to 17, wherein the width of the blocking portion is equal to or greater than the height of the blocking portion. (Appendix 19) 19. The semiconductor device according to any one of claims 1 to 18, further comprising a sealing portion that seals the semiconductor layer, the second conductive portion, the insulating protection portion, the blocking portion, and the die pad. (Appendix 20) 20. The semiconductor device according to any one of claims 1 to 19, wherein the semiconductor device is a diode or a transistor. [Explanation of symbols]

[0079] 1, 1A, 1B, 1C, 1D, 1E Semiconductor device 2. Semiconductor layer 2a Top side 2b Bottom side 2c side 21 Drift Region 22 Insulation Area 23 FP electrode 3 Source wiring layer 4. Drain electrode 5 Bonding material 6 die pad 7,7A,7B,7C,7D,7E Dam part 71 Main body 72 Plating Department 8,8A Insulation protection part 9 Sealing part 30 Conductive layer 40 Resist Pattern CR Cell Area ER peripheral area S1,S2,S3,S4 side

Claims

1. a semiconductor layer having a first major surface and a second major surface opposite the first major surface; a first conductive portion provided on the first main surface of the semiconductor layer; a second conductive portion provided on the second main surface of the semiconductor layer and bonded to a metal piece via a conductive bonding material; a dam portion provided on the first main surface outside the first conductive portion and electrically insulated from the first conductive portion and the second conductive portion, The bonding material is not in contact with the first conductive portion. Semiconductor device.

2. The semiconductor device according to claim 1 , wherein the blocking portion blocks contact of the bonding material with the first conductive portion.

3. The semiconductor device according to claim 1 , wherein the blocking portion is provided so as to surround the first conductive portion.

4. the semiconductor layer has a rectangular planar shape, The semiconductor device according to claim 3 , wherein the damming portion is not provided on a line connecting a center of the first main surface and a corner of the first main surface.

5. The semiconductor device according to claim 1 , wherein said damming portion has a bent planar shape.

6. The semiconductor device according to claim 1 , wherein a plurality of the damming portions are provided between the first conductive portion and the side portion of the semiconductor layer.

7. The semiconductor device according to claim 1 , wherein the blocking portion has a main body made of the same material as the first conductive portion.

8. The semiconductor device according to claim 1 , wherein the blocking portion has a main body portion and a plating portion covering the main body portion.

9. further comprising an insulating protection part covering the first conductive part; The semiconductor device according to claim 8 , wherein the blocking portion is provided spaced apart from the insulating protection portion.

10. 10. The semiconductor device according to claim 1, wherein the blocking portion includes a metal material.

11. The semiconductor device according to claim 10 , wherein the metal material of the blocking portion is a material that bonds with the bonding material.

12. The semiconductor device according to claim 10 , wherein the metal material of the blocking portion is a material that repels the bonding material.

13. further comprising an insulating protection part covering the first conductive part; The semiconductor device according to claim 1 , wherein the damming portion is covered with the protective layer.

14. 10. The semiconductor device according to claim 1, wherein the width of said damming portion is equal to or greater than the height of said damming portion.

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