Semiconductor device

Abstract

To provide a semiconductor device having improved electrical characteristics and reliability.SOLUTION: A semiconductor device according to the present invention includes a first channel region, a first dielectric structure on the first channel region, a first metal pattern spaced apart from the first dielectric structure, and a first dipole structure between the first metal pattern and the first dielectric structure. The first dipole structure includes a first dipole film and a second dipole film. The first dipole film includes a first dipole element. The second dipole film includes a second dipole element different from the first dipole element. The maximum oxidation number of the first dipole element is different from the maximum oxidation number of the second dipole element.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor devices including dipole structures. [Background technology]

[0002] Due to their small size, multi-functionality, and / or low manufacturing cost, semiconductor devices are gaining attention as important elements in the electronics industry. Semiconductor devices are classified into semiconductor memory devices that store logical data, semiconductor logic devices that process logical data, and hybrid semiconductor devices that include both memory and logic elements.

[0003] Recently, as electronic devices become faster and consume less power, the semiconductor devices incorporated therein are also required to have faster operating speeds and / or lower operating voltages. To meet these requirements, semiconductor devices with higher integration levels are required. However, as the integration level of semiconductor devices increases, the electrical characteristics and production yield of the semiconductor devices decrease. Therefore, much research is being conducted to improve the electrical characteristics and production yield of semiconductor devices. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 10,896,966 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a semiconductor device with improved electrical characteristics and reliability. [Means for solving the problem]

[0006] In order to achieve the above object, one aspect of the present invention provides a semiconductor device comprising: a first channel region; a first insulating structure on the first channel region; a first metal pattern spaced apart from the first insulating structure; and a first dipole structure between the first metal pattern and the first insulating structure, wherein the first dipole structure comprises a first dipole film and a second dipole film, the first dipole film comprising a first dipole element, the second dipole film comprising a second dipole element different from the first dipole element, and the maximum oxidation number of the first dipole element being different from the maximum oxidation number of the second dipole element.

[0007] In order to achieve the above object, according to another aspect of the present invention, a semiconductor device includes a channel region, a gate insulating film on the channel region, a high dielectric film on the gate insulating film, a first metal pattern spaced apart from the high dielectric film, and a dipole structure between the first metal pattern and the high dielectric film, wherein the first metal pattern includes a metal compound, and the dipole structure includes a first dipole film including a first dipole element and a second dipole film including a second dipole element, and the first dipole element and the second dipole element are different from each other.

[0008] In order to achieve the above object, according to yet another aspect of the present invention, a semiconductor device includes a channel region, a gate insulating film on the channel region, a high dielectric film on the gate insulating film, a first metal pattern spaced apart from the high dielectric film, a dipole structure between the first metal pattern and the high dielectric film, and a conductive structure on the first metal pattern, wherein the conductive structure includes polysilicon, the first metal pattern includes a metal compound, and the dipole structure includes a first dipole film including a first dipole element and a second dipole film including a second dipole element, and the maximum oxidation number of the first dipole element is different from the maximum oxidation number of the second dipole element. [Effects of the Invention]

[0009] The semiconductor device according to the present invention includes a dipole structure, which allows the threshold voltage of the transistor to be adjusted and the size of the transistor to be reduced. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to some embodiments. [Figure 2A] FIG. 2 is an enlarged view of the E1 region of FIG. [Figure 2B] FIG. 2B shows an energy band diagram of the semiconductor device according to FIG. 2A. [Figure 3A] 1 is an enlarged cross-sectional view of a semiconductor device according to some embodiments. [Figure 3B] FIG. 3B is a diagram showing an energy band diagram of the semiconductor device of FIG. 3A. [Figure 4] 1 is a cross-sectional view of a semiconductor device according to some embodiments. [Figure 5] FIG. 5 is an enlarged view of region E2 in FIG. [Figure 6] 1 is an enlarged cross-sectional view of a semiconductor device according to some embodiments. [Figure 7] 1 is a cross-sectional view of a semiconductor device according to some embodiments. [Figure 8] 1 is a cross-sectional view of a semiconductor device according to some embodiments. [Figure 9] 1 is a cross-sectional view of a semiconductor device according to some embodiments. [Figure 10] 1 is a cross-sectional view of a semiconductor device according to some embodiments. [Figure 11A] 1 is a cross-sectional view of a semiconductor device according to some embodiments. [Figure 11B] 1 is a cross-sectional view of a semiconductor device according to some embodiments. [Figure 11C] FIG. 11B is an enlarged view of the E3 region of FIG. [Figure 12A] 1 is a cross-sectional view of a semiconductor device according to some embodiments. [Figure 12B] 1 is a cross-sectional view of a semiconductor device according to some embodiments. [Figure 12C]FIG. 12B is an enlarged view of the E4 region of FIG. 12B. DETAILED DESCRIPTION OF THE INVENTION

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method for manufacturing the same according to an embodiment of the present invention will be described in detail below with reference to the drawings.

[0012] Figure 1 is a cross-sectional view of a semiconductor device according to some embodiments, Figure 2A is an enlarged view of region E1 of Figure 1, and Figure 2B is an energy band diagram of the semiconductor device according to Figure 2A.

[0013] Referring to FIG. 1 , the semiconductor device includes a substrate 100. The top surface of the substrate 100 is parallel to a first direction D1. In some embodiments, the substrate 100 is a semiconductor substrate. For example, the substrate 100 includes silicon, germanium, silicon-germanium, GaP, or GaAs. In some embodiments, the substrate 100 may be a semiconductor-on-insulator (SOI) substrate. The substrate 100 is doped with impurities of a first conductivity type. For example, the substrate 100 is doped with N-type impurities.

[0014] An isolation layer 101 is provided on a substrate 100. The isolation layer 101 includes an insulating material.

[0015] A transistor TR is provided on a substrate 100. The transistor TR is provided between isolation layers 101. The transistor TR includes a portion of the substrate 100, a semiconductor layer 120, an insulating structure 130, a first metal pattern 140, a dipole structure 150, a second metal pattern 160, a conductive structure 170, a gate spacer GS, and a gate capping pattern GP. In some embodiments, the transistor TR is a PMOSFET.

[0016] The semiconductor film 120, the insulating structure 130, the first metal pattern 140, the dipole structure 150, the second metal pattern 160, the conductive structure 170, and the gate capping pattern GP are sequentially stacked on the substrate 100 along a second direction D2. The second direction D2 intersects with the first direction D1. For example, the first direction D1 and the second direction D2 are horizontal and vertical directions that are perpendicular to each other.

[0017] The transistor TR includes a first source / drain region 111, a second source / drain region 112, and a channel region CH. The channel region CH is disposed between the first source / drain region 111 and the second source / drain region 112. Each of the first source / drain region 111, the second source / drain region 112, and the channel region CH includes a portion of the substrate 100 and a portion of the semiconductor film 120.

[0018] The first source / drain region 111 and the second source / drain region 112 are doped with impurities of a second conductivity type different from the first conductivity type. For example, the first source / drain region 111 and the second source / drain region 112 are doped with P-type impurities.

[0019] Semiconductor film 120 comprises a different semiconductor material than substrate 100. For example, substrate 100 comprises silicon and semiconductor film 120 comprises silicon-germanium. In some embodiments, semiconductor film 120 is a single-crystal semiconductor film. In some embodiments, the lattice constant of semiconductor film 120 is larger than the lattice constant of substrate 100.

[0020] The insulating structure 130 includes a gate insulating film 131 on the semiconductor film 120 and a high-k film 132 on the gate insulating film 131. The gate insulating film 131 includes an insulating material. For example, the gate insulating film 131 is a compound containing at least one of Si, Hf, Zr, In, Ga, and Zn, and at least one of O and N. For example, the gate insulating film 131 is a silicon oxide film.

[0021] The high dielectric film 132 contains a material different from the gate insulating film 131. The high dielectric film 132 has a higher dielectric constant than the gate insulating film 131. The high dielectric film 132 contains a material having a higher dielectric constant than silicon oxide. For example, the high dielectric film 132 is a compound containing at least one of Si, Hf, Zr, In, Ga, and Zn, and at least one of O and N. As an example, the high dielectric film 132 is an HfSiON film.

[0022] The first metal pattern 140 includes a metal compound. For example, the first metal pattern 140 includes at least one of Ti, Mo, Al, and W, and at least one of C, O, and N. For example, the first metal pattern 140 is a TiN film.

[0023] The first metal pattern 140 has a work function that allows the transistor TR to operate. For example, if the transistor TR is a PMOSFET, the first metal pattern 140 has a P-type work function compatible with the PMOSFET. In some embodiments, the work function of the first metal pattern 140 is greater than the electron affinity of the channel region CH and less than the sum of the electron affinity and bandgap energy of the channel region CH. In some embodiments, the work function of the first metal pattern 140 is greater than the mid-gap work function of the channel region CH.

[0024] The second metal pattern 160 is spaced apart from the high-k dielectric film 132 of the insulating structure 130. The second metal pattern 160 includes a metal compound. For example, the second metal pattern 160 includes at least one of Ti, Mo, Al, and W, and at least one of C, O, and N. For example, the second metal pattern 160 is a TiN film. In some embodiments, the work function of the second metal pattern 160 is greater than the electron affinity of the channel region CH and less than the sum of the electron affinity and band gap energy of the channel region CH.

[0025] In some embodiments, the work function of the second metal pattern 160 is smaller than the work function of the first metal pattern 140. In some embodiments, the work function of the second metal pattern 160 is smaller than the mid-gap work function of the channel region CH. In some embodiments, the second metal pattern 160 and the first metal pattern 140 include different materials. In some embodiments, the second metal pattern 160 and the first metal pattern 140 include the same material but have different compositions.

[0026] The conductive structure 170 includes a first conductive film 171, a second conductive film 172 on the first conductive film 171, and a third conductive film 173 on the second conductive film 172. The first conductive film 171 is spaced apart from the dipole structure 150. A second metal pattern 160 is disposed between the first conductive film 171 and the dipole structure 150.

[0027] The first conductive layer 171 includes a different conductive material from the dipole structure 150, the first metal pattern 140, the second metal pattern 160, the second conductive layer 172, and the third conductive layer 173. The first conductive layer 171 includes polysilicon. For example, the first conductive layer 171 includes polysilicon doped with impurities (e.g., N-type impurities).

[0028] The second conductive film 172 is a barrier film, and is, for example, a TiSiN film. The third conductive film 173 is, for example, a W film.

[0029] A gate capping pattern GP is provided on the third conductive layer 173 of the conductive structure 170. The gate capping pattern GP includes an insulating material.

[0030] Gate spacers GS are provided on both sidewalls of the insulating structure 130, the first metal pattern 140, the dipole structure 150, the second metal pattern 160, and the conductive structure 170. The gate spacers GS include an insulating material.

[0031] 2A and 2B, the dipole structure 150 is disposed between the first metal pattern 140 and the second metal pattern 160. The dipole structure 150 includes a first dipole film 151 and a second dipole film 152. The second dipole film 152 is provided on the first metal pattern 140. The first dipole film 151 is provided on the second dipole film 152. The upper surface of the first dipole film 151 contacts the lower surface of the second metal pattern 160. The lower surface of the second dipole film 152 contacts the upper surface of the first metal pattern 140. The first dipole film 151 includes a different material from the first metal pattern 140 and the second metal pattern 160. The second dipole film 152 includes a different material from the first metal pattern 140 and the second metal pattern 160. The first dipole film 151 includes a different material from the second dipole film 152.

[0032] The first dipole film 151 includes a first dipole element. The first dipole element is a dipole-inducing or dipole-forming material. The first dipole element is a metal or metalloid. For example, the first dipole element is Ti, Al, Zr, Hf, Mg, Y, La, Lu, Sr, Si, or Ge. The first dipole film 151 is a single film including the first dipole element or a compound including the first dipole element. The compound includes O or N. For example, the first dipole film 151 is a Ti film, a TiSiN film, a SiN film, a SiO film, or a TiO film. In some embodiments, the first dipole element is different from the metal included in the first metal pattern 140 and the second metal pattern 160.

[0033] The second dipole film 152 includes a second dipole element. The second dipole element is a dipole-inducing or dipole-forming material. The second dipole element is a metal or a metalloid. The second dipole element is an N-type dipole element. The N-type dipole element forms a dipole to lower the threshold voltage of an NMOSFET and increase the threshold voltage of a PMOSFET. The second dipole element is different from the first dipole element. The maximum oxidation number of the second dipole element is smaller than the maximum oxidation number of the first dipole element. For example, if the first dipole element is Ti, Zr, Hf, Si, or Ge, which has a maximum oxidation number of 4, the second dipole element is Al, Mg, Y, La, Lu, or Sr, which has a maximum oxidation number of 3 or less. For example, if the first dipole element is Al, Y, La, or Lu, which has a maximum oxidation number of 3, the second dipole element is Mg or Sr, which has a maximum oxidation number of 2. The second dipole film 152 is a single film containing the second dipole element or a compound containing the second dipole element. The compound contains O or N. For example, the second dipole film 152 is a La film or LaO film. In some embodiments, the dielectric constants of the first dipole film 151 and the second dipole film 152 are higher than that of silicon oxide. In some embodiments, the second dipole element is different from the metal contained in the first metal pattern 140 and the second metal pattern 160.

[0034] Because the maximum oxidation number of the second dipole element is smaller than the maximum oxidation number of the first dipole element, an interface dipole 153 is formed between the first dipole film 151 and the second dipole film 152. The interface dipole 153 is formed so that positive charges face the first dipole film 151. The interface dipole 153 increases the effective work function eW1 of the structure including the first metal pattern 140, the second dipole film 152, the first dipole film 151, and the second metal pattern 160 by about a first level L1. The interface dipole 153 adjusts the threshold voltage of the transistor TR.

[0035] The thickness T1 of the first metal pattern 140 in the second direction D2 is smaller than the thickness T2 of the second metal pattern 160 in the second direction D2. The thickness T3 of the second dipole film 152 in the second direction D2 and the thickness T4 of the first dipole film 151 in the second direction D2 are smaller than the thickness T1 of the first metal pattern 140 in the second direction D2 and the thickness T2 of the second metal pattern 160 in the second direction D2. The interface dipole 153 adjusts the threshold voltage of the transistor TR, thereby allowing the thickness of the first metal pattern 140 to be relatively thin, and the size of the transistor TR to be relatively small.

[0036] In some embodiments, the maximum oxidation number of the second dipole element of the second dipole film 152 is greater than the maximum oxidation number of the first dipole element of the first dipole film 151. As an example, when the second dipole element is Ti, Zr, Hf, Si, or Ge, which has a maximum oxidation number of 4, the first dipole element is Al, Mg, Y, La, Lu, or Sr, which has a maximum oxidation number of 3 or less. As an example, when the second dipole element is Al, Y, La, or Lu, which has a maximum oxidation number of 3, the first dipole element is Mg or Sr, which has a maximum oxidation number of 2.

[0037] Because the maximum oxidation number of the second dipole element in the second dipole film 152 is greater than the maximum oxidation number of the first dipole element in the first dipole film 151, an interface dipole is formed such that positive charges are directed toward the second dipole film 152. The interface dipole reduces the effective work function of the structure including the first metal pattern 140, the second dipole film 152, the first dipole film 151, and the second metal pattern 160, thereby adjusting the threshold voltage of the transistor TR.

[0038] A semiconductor device according to some embodiments includes a dipole structure 150 including a first dipole film 151 and a second dipole film 152, thereby adjusting the threshold voltage of a transistor TR.

[0039] In some embodiments, the semiconductor device includes the first dipole film 151, which limits or prevents the second dipole element of the second dipole film 152 from diffusing below the first metal pattern 140. Therefore, the increase in the threshold voltage of the transistor TR due to the diffusion of the second dipole element of the second dipole film 152 is limited or prevented.

[0040] Figure 3A is an enlarged cross-sectional view of a semiconductor device according to some embodiments. Figure 3B is an energy band diagram of the semiconductor device of Figure 3A. The semiconductor device according to Figure 3A is similar to the semiconductor devices according to Figures 1 and 2A, except as described below.

[0041] 3A and 3B, the dipole structure 250 includes a first dipole film 251 on the first metal pattern 140 and a second dipole film 252 on the first dipole film 251. The lower surface of the first dipole film 251 contacts the upper surface of the first metal pattern 140. The upper surface of the second dipole film 252 contacts the lower surface of the second metal pattern 160.

[0042] The first dipole film 251 includes a first dipole element. The first dipole element is a metal or a semimetal. For example, the first dipole element is Ti, Al, Zr, Hf, Mg, Y, La, Lu, Sr, Si, or Ge. The first dipole film 251 is a single film including the first dipole element or a compound film including the first dipole element. For example, the first dipole film 251 is a Ti film, a TiSiN film, a SiN film, a SiO film, or a TiO film.

[0043] The second dipole film 152 includes a second dipole element. The second dipole element is a metal or a metalloid. The second dipole element is an N-type dipole element. The second dipole element is different from the first dipole element. The maximum oxidation number of the second dipole element is smaller than the maximum oxidation number of the first dipole element. The second dipole film 152 is a single film including the second dipole element or a compound including the second dipole element. As an example, the second dipole film 152 is a La film or a LaO film.

[0044] Because the maximum oxidation number of the second dipole element is smaller than the maximum oxidation number of the first dipole element, an interface dipole 253 is formed between the first dipole film 251 and the second dipole film 252. The interface dipole 253 is formed so that positive charges are directed toward the first dipole film 251. The interface dipole 253 reduces the effective work function eW2 of the structure including the first metal pattern 140, the first dipole film 251, the second dipole film 252, and the second metal pattern 160 by about a second level L2. The interface dipole 253 adjusts the threshold voltage of the transistor TR.

[0045] In some embodiments, the maximum oxidation number of the second dipole element of the second dipole film 252 is greater than the maximum oxidation number of the first dipole element of the first dipole film 251. Because the maximum oxidation number of the second dipole element of the second dipole film 252 is greater than the maximum oxidation number of the first dipole element of the first dipole film 251, an interface dipole is formed such that positive charges are directed toward the second dipole film 252. The interface dipole increases the effective work function of the structure including the first metal pattern 140, the second dipole film 252, the first dipole film 251, and the second metal pattern 160, thereby adjusting the threshold voltage of the transistor TR.

[0046] Figure 4 is a cross-sectional view of a semiconductor device according to some embodiments. Figure 5 is an enlarged view of region E2 of Figure 4. The semiconductor device according to Figures 4 and 5 is similar to the semiconductor device according to Figures 1 and 2A, except as described below.

[0047] 4, a substrate 300 is doped with impurities of a first conductivity type. For example, the substrate 300 is doped with P-type impurities. A transistor TRa is provided on the substrate 300. The transistor TRa includes a portion of the substrate 300, an insulating structure 130, a dipole structure 350, a metal pattern 360, a conductive structure 170, a gate spacer GS, and a gate capping pattern GP. In some embodiments, the transistor TRa is an NMOSFET.

[0048] The transistor TRa includes a first source / drain region 311, a second source / drain region 312, and a channel region CHa. Each of the first source / drain region 311, the second source / drain region 312, and the channel region CHa includes a portion of the substrate 300.

[0049] The first source / drain region 311 and the second source / drain region 312 are doped with impurities of a second conductivity type different from the first conductivity type. For example, the first source / drain region 311 and the second source / drain region 312 are doped with N-type impurities.

[0050] The insulating structure 130 includes a gate insulating film 131 on the substrate 300 and a high dielectric film 132 on the gate insulating film 131 .

[0051] The metal pattern 360 includes a metal compound. For example, the metal pattern 360 includes at least one of Ti, Mo, Al, and W, and at least one of C, O, and N. For example, the metal pattern 360 is a TiN film.

[0052] The metal pattern 360 has a work function that allows the transistor TRa to operate. For example, if the transistor TRa is an NMOSFET, the metal pattern 360 has an N-type work function compatible with the NMOSFET. In some embodiments, the work function of the metal pattern 360 is greater than the electron affinity of the channel region CHa and less than the sum of the electron affinity and bandgap energy of the channel region CHa. In some embodiments, the work function of the metal pattern 360 is less than the mid-gap work function of the channel region CHa.

[0053] 5, the dipole structure 350 includes a first dipole film 351 on the high dielectric film 132 of the insulating structure 130 and a second dipole film 352 on the first dipole film 351. The lower surface of the first dipole film 351 contacts the upper surface of the high dielectric film 132 of the insulating structure 130. The upper surface of the second dipole film 352 contacts the lower surface of the metal pattern 360.

[0054] The first dipole film 351 includes a first dipole element. The first dipole element is a metal or a metalloid. For example, the first dipole element is Ti, Al, Zr, Hf, Mg, Y, La, Lu, Sr, Si, or Ge. The first dipole film 351 is a single film including the first dipole element or a compound film including the first dipole element. For example, the first dipole film 351 is a Ti film, a TiSiN film, a SiN film, a SiO film, or a TiO film.

[0055] The second dipole film 352 includes a second dipole element. The second dipole element is a metal or a metalloid. The second dipole element is an N-type dipole element. The second dipole element is different from the first dipole element. The maximum oxidation number of the second dipole element is smaller than the maximum oxidation number of the first dipole element. The second dipole film 352 is a single film including the second dipole element or a compound including the second dipole element. As an example, the second dipole film 352 is a La film or a LaO film.

[0056] Because the maximum oxidation number of the second dipole element is smaller than the maximum oxidation number of the first dipole element, an interface dipole is formed between the first dipole film 351 and the second dipole film 352, and the threshold voltage of the transistor TRa is adjusted. In some embodiments, the maximum oxidation number of the second dipole element of the second dipole film 352 is larger than the maximum oxidation number of the first dipole element of the first dipole film 351.

[0057] Figure 6 is an enlarged cross-sectional view of a semiconductor device according to some embodiments. The semiconductor device according to Figure 6 is similar to the semiconductor device according to Figures 4 and 5, except as described below.

[0058] 6, the dipole structure 450 includes a first dipole film 451 and a second dipole film 452. The second dipole film 452 is provided on the high dielectric film 132 of the insulating structure 130. The first dipole film 451 is provided on the second dipole film 452. The lower surface of the second dipole film 452 contacts the upper surface of the high dielectric film 132 of the insulating structure 130. The upper surface of the first dipole film 451 contacts the lower surface of the metal pattern 360.

[0059] The first dipole film 451 includes a first dipole element. The first dipole element is a metal or a metalloid. For example, the first dipole element is Ti, Al, Zr, Hf, Mg, Y, La, Lu, Sr, Si, or Ge. The first dipole film 451 is a single film including the first dipole element or a compound film including the first dipole element. For example, the first dipole film 451 is a Ti film, a TiSiN film, a SiN film, a SiO film, or a TiO film.

[0060] The second dipole film 452 includes a second dipole element. The second dipole element is a metal or a metalloid. The second dipole element is an N-type dipole element. The second dipole element is different from the first dipole element. The maximum oxidation number of the second dipole element is smaller than the maximum oxidation number of the first dipole element. The second dipole film 452 is a single film including the second dipole element or a compound including the second dipole element. As an example, the second dipole film 452 is a La film or a LaO film.

[0061] Since the maximum oxidation number of the second dipole element is smaller than the maximum oxidation number of the first dipole element, an interface dipole is formed between the first dipole film 451 and the second dipole film 452, and the threshold voltage of the transistor TRa is adjusted. In some embodiments, the maximum oxidation number of the second dipole element of the second dipole film 452 is larger than the maximum oxidation number of the first dipole element of the first dipole film 451.

[0062] Figure 7 is a cross-sectional view of a semiconductor device according to some embodiments. The semiconductor device according to Figure 7 is similar to the semiconductor device according to Figures 1 and 2A, except as described below.

[0063] 7, a transistor TRb is provided on a substrate 100. The transistor TRb includes a portion of the substrate 100, a semiconductor film 120, an insulating structure 130, a dipole structure 550, a metal pattern 560, a conductive structure 170, a gate spacer GS, and a gate capping pattern GP. In some embodiments, the transistor TRb is a PMOSFET.

[0064] The metal pattern 560 includes a metal compound. The metal pattern 560 has a work function that allows the transistor TRb to operate. For example, the transistor TRb is a PMOSFET, and the metal pattern 560 has a P-type work function that is compatible with the PMOSFET.

[0065] The dipole structure 550 includes a first dipole film and a second dipole film. The first dipole film includes a first dipole element. The first dipole element is a metal or a semimetal. For example, the first dipole element is Ti, Al, Zr, Hf, Mg, Y, La, Lu, Sr, Si, or Ge. The first dipole film is a single film including the first dipole element or a compound including the first dipole element. For example, the first dipole film is a Ti film, a TiSiN film, a SiN film, a SiO film, or a TiO film.

[0066] The second dipole film includes a second dipole element. The second dipole element is a metal or a semimetal. The second dipole element is a P-type dipole element. The P-type dipole element forms a dipole to lower the threshold voltage of a PMOSFET and increase the threshold voltage of an NMOSFET. The second dipole element is different from the first dipole element. For example, the second dipole element is one of Ti, Al, Zr, Hf, Mg, Y, La, Lu, Sr, Si, or Ge, different from the first dipole element. For example, the second dipole film is an Al film or an AlO film. The maximum oxidation number of the second dipole element is different from the maximum oxidation number of the first dipole element. The maximum oxidation number of the second dipole element is greater than or less than the maximum oxidation number of the first dipole element.

[0067] In some embodiments, the first dipole film contacts the high dielectric film 132 of the insulating structure 130, and the second dipole film contacts the metal pattern 560. In some embodiments, the second dipole film contacts the high dielectric film 132 of the insulating structure 130, and the first dipole film contacts the metal pattern 560.

[0068] An interface dipole is formed between the first dipole film and the second dipole film, and the threshold voltage of the transistor TRb is adjusted.

[0069] Figure 8 is a cross-sectional view of a semiconductor device according to some embodiments. The semiconductor device according to Figure 8 is similar to the semiconductor device according to Figures 4 and 5, except as described below.

[0070] 8, a transistor TRc is provided on a substrate 300. The transistor TRc includes a portion of the substrate 300, an insulating structure 130, a dipole structure 650, a first metal pattern 640, a second metal pattern 660, a conductive structure 170, a gate spacer GS, and a gate capping pattern GP. In some embodiments, the transistor TRc is an NMOSFET.

[0071] A dipole structure 650 is provided on the high dielectric film 132 of the insulating structure 130. A first metal pattern 640 is provided on the dipole structure 650. A second metal pattern 660 is provided on the first metal pattern 640. The lower surface of the dipole structure 650 contacts the upper surface of the high dielectric film 132 of the insulating structure 130. The upper surface of the dipole structure 650 contacts the lower surface of the first metal pattern 640. The upper surface of the first metal pattern 640 contacts the lower surface of the second metal pattern 660.

[0072] The first metal pattern 640 includes a metal compound and has a work function that allows the transistor TRc to operate. For example, if the transistor TRc is an NMOSFET, the first metal pattern 640 has an N-type work function suitable for the NMOSFET.

[0073] The second metal pattern 660 includes a metal compound and has a work function greater than that of the first metal pattern 640 .

[0074] The dipole structure 650 includes a first dipole film and a second dipole film. The first dipole film includes a first dipole element. The first dipole element is a metal or a semimetal. For example, the first dipole element is Ti, Al, Zr, Hf, Mg, Y, La, Lu, Sr, Si, or Ge. The first dipole film is a single film including the first dipole element or a compound including the first dipole element. For example, the first dipole film 151 is a Ti film, a TiSiN film, a SiN film, a SiO film, or a TiO film.

[0075] The second dipole film includes a second dipole element. The second dipole element is a metal or a metalloid. The second dipole element is a p-type dipole element. The second dipole element is different from the first dipole element. For example, the second dipole element is one of Ti, Al, Zr, Hf, Mg, Y, La, Lu, Sr, Si, or Ge, which is different from the first dipole element. For example, the second dipole film is an Al film or an AlO film. The maximum oxidation number of the second dipole element is different from the maximum oxidation number of the first dipole element. The maximum oxidation number of the second dipole element is greater than or less than the maximum oxidation number of the first dipole element.

[0076] In some embodiments, the first dipole film contacts the high dielectric film 132 of the insulating structure 130, and the second dipole film contacts the first metal pattern 640. In some embodiments, the second dipole film contacts the high dielectric film 132 of the insulating structure 130, and the first dipole film contacts the first metal pattern 640.

[0077] An interface dipole is formed between the first dipole film and the second dipole film, and the threshold voltage of the transistor TRc is adjusted.

[0078] Figure 9 is a cross-sectional view of a semiconductor device according to some embodiments. The semiconductor device according to Figure 9 is similar to the semiconductor device according to Figures 1 and 2A, except as described below.

[0079] 9, transistor TRd includes a portion of substrate 100, semiconductor film 120, insulating structure 130, first metal pattern 740, dipole structure 750, second metal pattern 760, conductive structure 170, gate spacer GS, and gate capping pattern GP. In some embodiments, transistor TRd is a PMOSFET.

[0080] Dipole structure 750 has a similar structure to dipole structure 150 described in FIG. 2A or dipole structure 250 described in FIG. 3A.

[0081] The first metal pattern 740 includes a first metal film 741, a second metal film 742 on the first metal film 741, and a third metal film 743 on the second metal film 742. The second metal film 742 includes a different material from the first metal film 741 and the third metal film 743. As an example, the first metal film 741 and the third metal film 743 are TiN films, and the second metal film 742 is an Al film.

[0082] FIG. 10 is a cross-sectional view of a semiconductor device according to some embodiments.

[0083] 10, the semiconductor device includes a substrate 800. An isolation layer 801 is provided on the substrate 800.

[0084] A first transistor TR1 and a second transistor TR2 are provided on a substrate 800. The first transistor TR1 includes a portion of the substrate 800, a first insulating structure 830, a first dipole structure 850, a first metal pattern 860, a first conductive structure 870, a first gate spacer GS1, and a first gate capping pattern GP1. In some embodiments, the first transistor TR1 is an NMOSFET. The second transistor TR2 includes a portion of the substrate 800, a semiconductor film 820, a second insulating structure 835, a second metal pattern 845, a second dipole structure 855, a third metal pattern 865, a second conductive structure 875, a second gate spacer GS2, and a second gate capping pattern GP2. In some embodiments, the second transistor TR2 is a PMOSFET.

[0085] The first transistor TR1 includes a first channel region CH1, a first source / drain region 811, and a second source / drain region 812. The first channel region CH1 is doped with, for example, P-type impurities. The second transistor TR2 includes a second channel region CH2, a third source / drain region 813, and a fourth source / drain region 814. The second channel region CH2 is doped with, for example, N-type impurities.

[0086] The first insulating structure 830 includes a first gate insulating film 831 and a first high-k dielectric film 832. The second insulating structure 835 includes a second gate insulating film 836 and a second high-k dielectric film 837.

[0087] The first conductive structure 870 includes a first conductive film 871, a second conductive film 872, and a third conductive film 873. The second conductive structure 875 includes a fourth conductive film 876, a fifth conductive film 877, and a sixth conductive film 878.

[0088] The first dipole structure 850 has a structure similar to the dipole structure 350 described in Figure 5 or the dipole structure 450 described in Figure 6. The second dipole structure 855 has a structure similar to the dipole structure 150 described in Figure 2A or the dipole structure 250 described in Figure 3A.

[0089] The first dipole structure 850 includes a first dipole film and a second dipole film. The second dipole structure 855 includes a third dipole film and a fourth dipole film. The first and third dipole films include a first dipole element. The second and fourth dipole films include a second dipole element.

[0090] The second transistor TR2 includes the second dipole structure 855, which adjusts the threshold voltage of the second transistor TR2 and eliminates the need for a film for adjusting the threshold voltage of the second transistor TR2. Therefore, the height of the second transistor TR2 is relatively low, and the height difference between the first and second transistors TR1 and TR2 is minimized, improving the stability of subsequent processes.

[0091] In some embodiments, the first transistor TR1 has a structure similar to the transistor TRc described in FIG. 8. In some embodiments, the second transistor TR2 has a structure similar to the transistor TRb described in FIG. 7 or the transistor TRd described in FIG. 9.

[0092] 11A and 11B are cross-sectional views of a semiconductor device according to some embodiments, and FIG. 11C is an enlarged view of region E3 of FIG. 11B.

[0093] 11A and 11B, the semiconductor device includes a substrate 10, an active pattern 11, a cell isolation film 12, a cell insulating film 13, a bit line contact 15, a first bit line conductive film 14, a second bit line conductive film 16, a third bit line conductive film 17, a bit line capping film 19, a bit line spacer 20, a node contact 21, a landing pad 22, a landing pad isolation film 23, a first cell capacitor electrode 24, a cell capacitor insulating film 25, a second cell capacitor electrode 26, a cell gate electrode 27, a cell gate insulating film 28, a cell gate capping film 29, and an insulating fence 30.

[0094] The upper portions of the substrate 10 protruding in the second direction D2 are defined as active patterns 11. The active patterns 11 are spaced apart from each other.

[0095] A cell isolation layer 12 is provided in a space provided between the active patterns 11. The active patterns 11 are defined by the cell isolation layer 12. The cell isolation layer 12 includes an insulating material.

[0096] A gate structure including a cell gate electrode 27, a cell gate insulating film 28, and a cell gate capping film 29 is provided. The gate structure extends in a first direction D1. The gate structure is arranged in a third direction D3. The third direction D3 intersects with the first direction D1 and the second direction D2. For example, the third direction D3 is a horizontal direction perpendicular to the first direction D1 and the second direction D2.

[0097] The gate structure is a buried gate structure buried within the active pattern 11 and the cell isolation layer 12. The cell gate capping layer 29 includes an insulating material.

[0098] A cell insulating film 13 is provided on the gate structure and the cell isolation film 12. The cell insulating film 13 comprises an insulating material. In some embodiments, the cell insulating film 13 comprises multiple insulating films.

[0099] Bit line structures extending in a third direction D3 are provided and arranged in the first direction D1. The bit line structures include bit line contacts 15, a first bit line conductive layer 14, a second bit line conductive layer 16, a third bit line conductive layer 17, a bit line capping layer 19, and bit line spacers 20.

[0100] The bit line contacts 15 of the bit line structures and the first bit line conductive layers 14 are alternately arranged along the third direction D3. The bit line contacts 15 are connected to the active patterns 11. The first bit line conductive layers 14 are provided on the cell insulating layer 13.

[0101] A second bit line conductive layer 16 is provided on the bit line contact 15 and the first bit line conductive layer 14. A third bit line conductive layer 17 is provided on the second bit line conductive layer 16. A bit line capping layer 19 is provided on the third bit line conductive layer 17. The bit line contact 15, the first bit line conductive layer 14, the second bit line conductive layer 16, and the third bit line conductive layer 17 include conductive materials. The bit line capping layer 19 includes an insulating material.

[0102] The bit line spacers 20 cover the top surface and sidewalls of the bit line capping layer 19, the sidewalls of the first to third bit line conductive layers 14, 16, and 17, and the sidewalls of the bit line contacts 15. The bit line spacers 20 include an insulating material. In some embodiments, the bit line spacers 20 include a plurality of insulating layers.

[0103] The node contacts 21 are connected to the active patterns 11. The node contacts 21 are provided between adjacent bit line structures. The node contacts 21 include a conductive material. For example, the node contacts 21 include polysilicon.

[0104] A landing pad 22 is provided on the node contact 21. The landing pad 22 includes a conductive material. In some embodiments, a metal silicide film and a barrier film are provided between the node contact 21 and the landing pad 22.

[0105] An insulating fence 30 is provided on the cell gate capping film 29. The insulating fence 30 is provided between adjacent node contacts 21. The insulating fence 30 includes an insulating material.

[0106] A landing pad isolation film 23 is provided on the insulating fence 30. The landing pad isolation film 23 separates the landing pads 22 from each other. The landing pad isolation film 23 surrounds the landing pads 22. The landing pad isolation film 23 includes an insulating material.

[0107] The first cell capacitor electrode 24, the cell capacitor insulating film 25, and the second cell capacitor electrode 26 constitute a cell capacitor. The cell capacitor insulating film 25 is provided between the first cell capacitor electrode 24 and the second cell capacitor electrode 26. The first and second cell capacitor electrodes 24 and 26 include a conductive material. The cell capacitor insulating film 25 includes an insulating material. The semiconductor device is a dynamic random access memory (DRAM) including a cell capacitor.

[0108] In some embodiments, the memory cell structure includes a magnetic tunnel junction pattern instead of a cell capacitor. In this case, the semiconductor device is a magnetic tunnel junction pattern (MRAM). In some embodiments, the memory cell structure includes a phase-change material or a variable resistance material instead of a cell capacitor. In this case, the semiconductor device is a phase-change random access memory (PRAM) or a resistive random access memory (ReRAM). In some embodiments, various structures and / or materials are provided for storing data instead of the cell capacitor.

[0109] 11C, the cell gate insulating film 28 includes a gate insulating film 28a and a high-k dielectric film 28b. The cell gate electrode 27 includes a dipole structure 27a, a metal pattern 27b, a first conductive film 27c, a second conductive film 27d, and a third conductive film 27e. The dipole structure 27a includes a first dipole film and a second dipole film, and the first dipole element of the first dipole film has a different maximum oxidation number from the second dipole element of the second dipole film.

[0110] In some embodiments, a metal pattern having a work function different from that of the metal pattern 27b is provided between the dipole structure 27a and the high dielectric film 28b.

[0111] 12A and 12B are cross-sectional views of a semiconductor device according to some embodiments, and FIG. 12C is an enlarged view of region E4 of FIG. 12B.

[0112] 12A and 12B, the semiconductor device includes a substrate 50. Logic transistors that constitute a logic circuit are disposed on the substrate 50.

[0113] The substrate 50 includes a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 and the second active pattern AP2 are defined by trenches TR on the substrate 50. The first and second active patterns AP1 and AP2 extend in a first direction D1. The first and second active patterns AP1 and AP2 are protruding portions in a second direction D2.

[0114] An isolation layer ST is provided on the substrate 50. The isolation layer ST fills the trench TR. The isolation layer ST includes an insulating material.

[0115] A channel pattern CA is provided on each of the first and second active patterns AP1 and AP2. The channel pattern CA includes a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 that are sequentially arranged in the second direction D2. The first to third semiconductor patterns SP1, SP2, and SP3 are spaced apart from each other in the third direction D3.

[0116] In some embodiments, the first to third semiconductor patterns SP1, SP2, and SP3 include silicon (Si). For example, each of the first to third semiconductor patterns SP1, SP2, and SP3 includes crystalline silicon. In some embodiments, the first to third semiconductor patterns SP1, SP2, and SP3 include silicon-germanium (SiGe).

[0117] A plurality of source / drain patterns SD1 are provided on each of the first active pattern AP1 and the second active pattern AP2. A plurality of recesses RS1 are formed on each of the first active pattern AP1 and the second active pattern AP2. A source / drain pattern SD1 is provided in each of the recesses RS1. A channel pattern CA is interposed between adjacent source / drain patterns SD1. The source / drain patterns SD1 are epitaxial patterns formed by a selective epitaxial growth (SEG) process.

[0118] A gate electrode GE is provided extending in a third direction D3 and includes a first portion PO1 interposed between the active pattern AP1 or AP2 and the first semiconductor pattern SP1, a second portion PO2 interposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third portion PO3 interposed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth portion PO4 on the third semiconductor pattern SP3.

[0119] The gate electrode GE and the first to third semiconductor patterns SP1, SP2, and SP3 three-dimensionally surrounded by the gate electrode GE constitute a three-dimensional field effect transistor (for example, an MBCFET or a GAAFET).

[0120] A pair of gate spacers GA are disposed on both sidewalls of the gate electrode GE, and a gate capping pattern GC is provided on the gate electrode GE.

[0121] A cell gate insulating film GI is provided. The cell gate insulating film GI separates the gate electrode GE from the channel pattern CA. The cell gate insulating film GI three-dimensionally surrounds the first to third semiconductor patterns SP1, SP2, and SP3. The cell gate insulating film GI covers the isolation film ST. The cell gate insulating film GI includes an insulating material. For example, the cell gate insulating film GI includes an oxide.

[0122] A first interlayer insulating film 51 is provided to cover the gate spacer GA and the source / drain pattern SD1. A second interlayer insulating film 52 is provided on the first interlayer insulating film 51 and the gate capping pattern GC. The first and second interlayer insulating films 51 and 52 include an insulating material.

[0123] Isolation structures DB are provided, the isolation structures DB extend in a third direction D3, and gate electrodes GE are disposed between the isolation structures DB.

[0124] The isolation structure DB extends into the first and second active patterns AP1 and AP2 through the first and second interlayer insulating films 51 and 52. The lower portion of the isolation structure DB penetrates the upper portions of the first and second active patterns AP1 and AP2 in the third direction D3.

[0125] Active contacts AC are provided to be electrically connected to the source / drain patterns SD1 through the first and second interlayer insulating layers 51 and 52. Gate electrodes GE are provided between adjacent active contacts AC.

[0126] A metal-semiconductor compound film SC is provided, which is interposed between the active contact AC and the source / drain pattern SD1.

[0127] The active contact AC is electrically connected to the source / drain pattern SD1 through a metal-semiconductor compound layer SC, which may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0128] The active contact AC includes a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM includes at least one of aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM covers the sidewalls and bottom surface of the conductive pattern FM. The barrier pattern BM includes at least one of a metal film and a metal nitride film. The metal film includes at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride film includes at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0129] 12C, the cell gate insulating film GI includes a gate insulating film Gia and a high-dielectric film GIb. The gate electrode GE includes a dipole structure GEa, a metal pattern GEb, a first conductive film Gec, a second conductive film GEd, and a third conductive film GEe. The dipole structure GEa includes a first dipole film and a second dipole film, and the first dipole element of the first dipole film has a different maximum oxidation number from the second dipole element of the second dipole film.

[0130] In some embodiments, a metal pattern having a work function different from that of the metal pattern GEb is provided between the dipole structure GEa and the high dielectric film GIb.

[0131] Although the embodiments of the present invention have been described above with reference to the drawings, those skilled in the art will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and are not limiting. Furthermore, the above-described embodiments may be combined with each other as necessary. [Explanation of symbols]

[0132] 100, 300, 800 boards 101, 801 Element isolation film 111, 311, 811 First source / drain region 112, 312, 812 Second source / drain region 120, 820 Semiconductor film 130 Insulation structure 131 Gate insulating film 132 High dielectric film 140, 640, 740, 860 First metal pattern 150, 250, 350, 450, 550, 650, 750 dipole structure 160, 660, 760, 845 Second metal pattern 170 Conductive Structure 360, 560 metal pattern 813 Third Source / Drain Region 814 4th source / drain region 830 First insulating structure 835 Second insulating structure 850 First dipole structure 855 Second Dipole Structure 865 3rd metal pattern 870 First conductive structure 875 Second conductive structure CH, CHa channel region CH1 1st channel area CH2 Second channel area GP Gate Capping Pattern GP1 First gate capping pattern GP2 Second gate capping pattern GS Gate Spacer GS1 1st Gate Spacer GS2 Second Gate Spacer

Claims

1. a first channel region; a first insulating structure on the first channel; a first metal pattern spaced apart from the first insulating structure; a first dipole structure between the first metal pattern and the first insulating structure; the first dipole structure includes a first dipole film and a second dipole film; the first dipole film includes a first dipole element; the second dipole film includes a second dipole element different from the first dipole element, A semiconductor device, wherein the maximum oxidation number of the first dipole element is different from the maximum oxidation number of the second dipole element.

2. the first dipole film is in contact with the first metal pattern, 2. The semiconductor device according to claim 1, wherein the second dipole film is in contact with the first insulating structure.

3. 3. The semiconductor device according to claim 2, wherein the maximum oxidation number of the first dipole element is greater than the maximum oxidation number of the second dipole element.

4. 3. The semiconductor device according to claim 2, wherein the maximum oxidation number of the second dipole element is greater than the maximum oxidation number of the first dipole element.

5. 2. The semiconductor device of claim 1, further comprising a second metal pattern between the first insulating structure and the first dipole structure.

6. 6. The semiconductor device according to claim 5, wherein the thickness of the second metal pattern is smaller than the thickness of the first metal pattern.

7. a second channel region; a second insulating structure over the second channel region; a second metal pattern spaced apart from the second insulating structure; and a second dipole structure between the second metal pattern and the second insulating structure; the first channel region includes impurities of a first conductivity type; the second channel region includes impurities of a second conductivity type different from the first conductivity type; 2. The semiconductor device according to claim 1, wherein the second dipole structure includes a third dipole film including the first dipole element and a fourth dipole film including the second dipole element.

8. the first dipole structure is in contact with the first insulating structure; the second dipole structure is spaced apart from the second insulating structure; 8. The semiconductor device of claim 7, further comprising a third metal pattern between the second dipole structure and the second insulating structure.

9. 9. The semiconductor device according to claim 8, wherein the work function of the second metal pattern is smaller than the work function of the third metal pattern.

10. a work function of the second metal pattern that is less than a mid-gap work function of the second channel region; 9. The semiconductor device of claim 8, wherein the work function of the third metal pattern is greater than the mid-gap work function of the second channel region.

11. a channel region; a gate insulating film on the channel region; a high dielectric film on the gate insulating film; a first metal pattern spaced apart from the high dielectric layer; a dipole structure between the first metal pattern and the high dielectric film, the first metal pattern includes a metal compound; the dipole structure includes a first dipole film including a first dipole element and a second dipole film including a second dipole element; The semiconductor device is characterized in that the first dipole element and the second dipole element are different from each other.

12. a conductive film spaced apart from the dipole structure; the first metal pattern is disposed between the dipole structure and the conductive film; 12. The semiconductor device according to claim 11, wherein the conductive film contains polysilicon.

13. 12. The semiconductor device of claim 11, further comprising a second metal pattern between the dipole structure and the high dielectric film.

14. 14. The semiconductor device according to claim 13, wherein the work function of the second metal pattern is greater than the work function of the first metal pattern.

15. a second metal pattern on the first metal pattern; a conductive structure on the second metal pattern; The semiconductor device of claim 11 , further comprising: a gate capping pattern on the conductive structure.

16. 16. The semiconductor device of claim 15, wherein the work function of the second metal pattern is greater than the work function of the first metal pattern.

17. A substrate; a semiconductor film on the substrate; the semiconductor film is disposed between the gate insulating film and the substrate, The semiconductor device of claim 11 , wherein the substrate and the semiconductor film comprise different semiconductor materials.

18. 12. The semiconductor device of claim 11, wherein the dipole structure increases an effective work function of the first metal pattern.

19. a channel region; a gate insulating film on the channel region; a high dielectric film on the gate insulating film; a first metal pattern spaced apart from the high dielectric layer; a dipole structure between the first metal pattern and the high dielectric film; a conductive structure on the first metal pattern; the conductive structure comprises polysilicon; the first metal pattern includes a metal compound; the dipole structure includes a first dipole film including a first dipole element and a second dipole film including a second dipole element; A semiconductor device, wherein the maximum oxidation number of the first dipole element is different from the maximum oxidation number of the second dipole element.

20. the first dipole element is Ti, Al, Zr, Hf, Mg, Y, La, Lu, Sr, Si, or Ge; 20. The semiconductor device of claim 19, wherein the second dipole element is one of Ti, Al, Zr, Hf, Mg, Y, La, Lu, Sr, Si, or Ge that is different from the first dipole element.

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