Field effect transistor

Abstract

To achieve low on resistance in a field effect transistor with a plurality of p-type deep layers.SOLUTION: A field effect transistor (10) includes a plurality of p-type deep layers (36) and a plurality of n-type deep layers (37). Each p-type deep layer protrudes downward from the body layer, extends in a first direction intersecting with the trench when the semiconductor substrate is viewed from above, and is disposed with a gap part in a second direction orthogonal to the first direction when the semiconductor substrate is viewed from above. Each n-type deep layer is disposed in the corresponding gap part. A drift layer has n-type impurity concentration that is lower than that of each n-type deep layer. A size of the n-type deep layer in a thickness direction of the semiconductor substrate is larger than a size of the n-type deep layer in the second direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a field effect transistor.

[0002] Patent Document 1 discloses a trench-gate field-effect transistor. This field-effect transistor has multiple p-type deep layers protruding downward from a body layer. Each p-type deep layer extends so as to intersect with the trench when viewed from above the semiconductor substrate. The multiple p-type deep layers are arranged with gaps in their width direction. Each p-type deep layer extends from the body layer to below the bottom of the trench. In one example of a field-effect transistor disclosed in Patent Document 1, each p-type deep layer contacts a gate insulating film on the side and bottom of the trench located below the body layer. The field-effect transistor also has an n-type drift layer contacting the body layer and each p-type deep layer. When this field-effect transistor is turned off, a depletion layer extends from the body layer into the drift layer. The depletion layer extending in the drift layer maintains the source-drain voltage. When this field-effect transistor is turned off, a depletion layer also extends from each deep p-layer into the drift layer. Since each deep p layer contacts the gate insulating film at the bottom of the trench, the depletion layer extending from each deep p layer depletes the drift layer around the bottom of the trench. In this way, the depletion layer extending from each deep p layer to the periphery of the bottom of the trench suppresses electric field concentration in the gate insulating film and drift layer around the bottom of the trench. Therefore, this field effect transistor has a high breakdown voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-194065 Summary of the Invention [Problem to be solved by the invention]

[0004] When the field-effect transistor of Patent Document 1 is turned on, a channel is formed in the body layer. Then, electrons flow from the source layer to the channel. Because multiple p-type deep layers exist below the body layer, electrons passing through the channel flow into the drift layer located in the gap between the p-type deep layers. Electrons passing through the gap flow into the drift layer below the gap. In this way, electrons flow from the source layer through the channel and the drift layer in the gap to the drift layer below the gap. The drift layer in the gap is sandwiched between the p-type deep layers. When the field-effect transistor is in the on state, a depletion layer extends from each p-type deep layer to the drift layer in the gap. This expanding depletion layer narrows the path through which electrons flow in the drift layer in the gap. As a result, the resistance of the gap increases. Therefore, the field-effect transistor of Patent Document 1 has a high on-resistance. This specification proposes a technology for achieving low on-resistance in a field-effect transistor with multiple p-type deep layers. [Means for solving the problem]

[0005] The field-effect transistor disclosed in this specification includes a semiconductor substrate having a trench on its upper surface, a gate insulating film covering the inner surface of the trench, and a gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate includes an n-type source layer in contact with the gate insulating film on a side surface of the trench, a p-type body layer located below the source layer in contact with the gate insulating film on the side surface of the trench, multiple p-type deep layers, multiple n-type deep layers, and a drift layer (38). Each of the p-type deep layers protrudes downward from the body layer and extends from the body layer below the bottom surface of the trench. The p-type deep layers extend along a first direction intersecting the trench when viewed from above, and are spaced apart in a second direction perpendicular to the first direction when viewed from above. The p-type deep layers contact the gate insulating film at the side surface of the trench located below the body layer and at the bottom surface of the trench. Each of the n-type deep layers is disposed in the corresponding gap and contacts the gate insulating film at the side of the trench located below the body layer. The drift layer is n-type with a lower n-type impurity concentration than each of the n-type deep layers and contacts the lower surfaces of the multiple n-type deep layers. Each of the p-type deep layers has a shape in which its dimension in the thickness direction of the semiconductor substrate is larger than its dimension in the second direction. Each of the n-type deep layers has a shape in which its dimension in the thickness direction of the semiconductor substrate is larger than its dimension in the second direction.

[0006] The "dimension in the second direction" of the p-type deep layer refers to the distance between both side surfaces of the p-type deep layer in the second direction. The "dimension in the thickness direction of the semiconductor substrate" of the p-type deep layer refers to the distance in the thickness direction of the semiconductor substrate from the lower surface of the body layer (i.e., the upper surface of the p-type deep layer) to the lower surface of the p-type deep layer. The "dimension in the second direction" of the n-type deep layer refers to the distance between both side surfaces of the n-type deep layer in the second direction. The "dimension in the thickness direction of the semiconductor substrate" of the n-type deep layer refers to the distance in the thickness direction of the semiconductor substrate from the lower surface of the body layer (i.e., the upper surface of the n-type deep layer) to the lower surface of the n-type deep layer.

[0007] This field-effect transistor has multiple p-type deep layers, which can suppress electric field concentration around the bottom of the trench when the field-effect transistor is turned off. Therefore, this field-effect transistor has a high breakdown voltage. In addition, in this field-effect transistor, an n-type deep layer having a higher n-type impurity concentration than the drift layer is provided in the gap between the multiple p-type deep layers. The dimension of the n-type deep layer in the thickness direction of the semiconductor substrate is larger than the dimension of the n-type deep layer in the second direction. That is, the n-type deep layer has a long shape in the vertical direction (i.e., the thickness direction of the semiconductor substrate). Therefore, a wide area of ​​the gap is composed of the n-type deep layer. When this field-effect transistor is turned on, electrons flow from the source layer through the channel and the n-type deep layer to the drift layer. Because the n-type deep layer is disposed in the gap, a depletion layer extends from the p-type deep layers on both sides of the n-type deep layer. However, because the n-type deep layer has a high n-type impurity concentration, the width of the depletion layer extending from the p-type deep layer to the n-type deep layer is narrow. This ensures a wide electron flow path within the n-type deep layer, making it possible to lower the resistance of the gap compared to conventional techniques. This field-effect transistor configuration therefore achieves a low on-resistance. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional perspective view of a MOSFET 10 (a view showing an xz cross section not including a p-type deep layer 36). [Figure 2] FIG. 2 is a cross-sectional perspective view of the MOSFET 10, with the source electrode 22 and the interlayer insulating film 20 omitted. [Figure 3] FIG. 2 is a plan view showing the arrangement of trenches 14 and p-type deep layers 36 when the semiconductor substrate 12 is viewed from above. [Figure 4] 3 is an enlarged cross-sectional view of a p-type deep layer 36 and an n-type deep layer 37. FIG. [Figure 5] FIG. 1 is a cross-sectional perspective view of a MOSFET 10 (a view showing an xz cross section including a p-type deep layer 36). [Figure 6] 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10. [Figure 7] 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10. [Figure 8] 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10. [Figure 9] FIG. 10 is a diagram showing the distribution of a depletion layer in an n-type deep layer 37 when the MOSFET 10 is on. [Figure 10] 1 is a graph showing the relationship between the standard value Dn / Dp and the characteristics of the MOSFET 10. [Figure 11] FIG. 3 is an enlarged cross-sectional view of a p-type deep layer 36 and an n-type deep layer 37 of a MOSFET according to a first modified example. [Figure 12] FIG. 10 is an enlarged cross-sectional view of a p-type deep layer 36 and an n-type deep layer 37 of a MOSFET according to a second modification. [Figure 13] FIG. 10 is an enlarged cross-sectional view of a p-type deep layer 36 and an n-type deep layer 37 of a MOSFET according to a third modified example. DETAILED DESCRIPTION OF THE INVENTION

[0009] In the field-effect transistor disclosed in the present specification, the n-type deep layers may extend from the lower surface of the body layer to a depth equal to the lower surfaces of the p-type deep layers. In this case, the n-type deep layers may extend from the lower surface of the body layer to a depth lower than the lower surfaces of the p-type deep layers.

[0010] With these configurations, the entire gap can be made of an n-type deep layer with a high concentration of n-type impurities, thereby further reducing the on-resistance of the field-effect transistor.

[0011] In the field effect transistor disclosed in the present specification as an example, the plurality of n-type deep layers may be connected to each other via a region below the lower surfaces of the plurality of p-type deep layers.

[0012] In one example field effect transistor disclosed in this specification, the dimension of the n-type deep layer in the thickness direction of the semiconductor substrate may be 1.07 times or less the dimension of the p-type deep layer in the thickness direction of the semiconductor substrate.

[0013] This configuration makes it possible to achieve a higher breakdown voltage in the field effect transistor.

[0014] A MOSFET (metal-oxide-semiconductor field effect transistor) 10 according to an embodiment shown in FIGS. 1 and 2 includes a semiconductor substrate 12. Hereinafter, the thickness direction of the semiconductor substrate 12 is referred to as the z-direction, a direction parallel to the upper surface 12a of the semiconductor substrate 12 (a direction perpendicular to the z-direction) is referred to as the x-direction, and a direction perpendicular to the x-direction and z-direction is referred to as the y-direction. The semiconductor substrate 12 is made of silicon carbide (i.e., SiC). The semiconductor substrate 12 may also be made of other semiconductor materials such as silicon or gallium nitride. A plurality of trenches 14 are provided in the upper surface 12a of the semiconductor substrate 12. As shown in FIG. 2, the plurality of trenches 14 extend elongatedly along the y-direction on the upper surface 12a. The plurality of trenches 14 are spaced apart in the x-direction.

[0015] As shown in FIGS. 1 and 2, the inner surface (i.e., the side and bottom surfaces) of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is disposed in each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. As shown in FIG. 1, the upper surface of each gate electrode 18 is covered with an interlayer insulating film 20. A source electrode 22 is provided on the upper part of the semiconductor substrate 12. The source electrode 22 covers each interlayer insulating film 20. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. The source electrode 22 is in contact with the upper surface 12a of the semiconductor substrate 12 at a position where the interlayer insulating film 20 is not present. A drain electrode 24 is disposed on the lower part of the semiconductor substrate 12. The drain electrode 24 is in contact with the entire lower surface 12b of the semiconductor substrate 12.

[0016] As shown in Figures 1 and 2, the semiconductor substrate 12 has a plurality of source layers 30, a plurality of contact layers 32, a body layer 34, a plurality of p-type deep layers 36, a plurality of n-type deep layers 37, a drift layer 38, and a drain layer 40.

[0017] Each source layer 30 is an n-type layer having a high concentration of n-type impurities. Each source layer 30 is disposed in an area that partially includes the upper surface 12a of the semiconductor substrate 12. Each source layer 30 is in ohmic contact with the source electrode 22. Each source layer 30 is in contact with the gate insulating film 16 at the top of the side surface of the trench 14. Each source layer 30 faces the gate electrode 18 via the gate insulating film 16. Each source layer 30 extends long in the y direction along the side surface of the trench 14.

[0018] Each contact layer 32 is a p-type layer having a high p-type impurity concentration. Each contact layer 32 is disposed in an area that partially includes the upper surface 12a of the semiconductor substrate 12. Each contact layer 32 is disposed between two corresponding source layers 30. Each contact layer 32 is in ohmic contact with the source electrode 22. Each contact layer 32 extends longitudinally in the y direction.

[0019] The body layer 34 is a p-type layer having a lower p-type impurity concentration than the contact layer 32. The body layer 34 is disposed below the source layers 30 and the contact layers 32. The body layer 34 contacts the source layers 30 and the contact layers 32 from below. The body layer 34 contacts the gate insulating film 16 on the side surface of the trench 14 located below the source layer 30. The body layer 34 faces the gate electrode 18 with the gate insulating film 16 interposed therebetween.

[0020] Each p-type deep layer 36 is a p-type layer that protrudes downward from the lower surface of the body layer 34. The p-type impurity concentration of each p-type deep layer 36 is higher than that of the body layer 34 and lower than that of the contact layer 32. When the semiconductor substrate 12 is viewed from above as shown in FIG. 3, each p-type deep layer 36 extends elongately in the x direction and is perpendicular to the trench 14. The multiple p-type deep layers 36 are arranged at intervals in the y direction. Hereinafter, the portions between the multiple p-type deep layers 36 are referred to as intervals 39. As shown in FIG. 4, the p-type deep layer 36 has a shape that is elongated in the z direction in the y-z cross section. That is, the dimension of the p-type deep layer 36 in the z direction (hereinafter referred to as depth Dp) is larger than the dimension of the p-type deep layer 36 in the y direction (hereinafter referred to as width Wp). For example, the depth Dp can be 1 to 4 times the width Wp. 5, each p-type deep layer 36 extends from the lower surface of the body layer 34 to a depth below the bottom surface of each trench 14. Each p-type deep layer 36 contacts the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34. Each p-type deep layer 36 also contacts the gate insulating film 16 on the bottom surface of the trench 14. Each p-type deep layer 36 faces the gate electrode 18 with the gate insulating film 16 interposed therebetween.

[0021] Each n-type deep layer 37 is an n-type layer having a higher n-type impurity concentration than the drift layer 38. The n-type impurity concentration of each n-type deep layer 37 is lower than the p-type impurity concentration of each p-type deep layer 36. As shown in FIGS. 1 and 2, each n-type deep layer 37 is disposed in a corresponding gap 39. Each n-type deep layer 37 is in contact with the lower surface of the body layer 34. Each n-type deep layer 37 is in contact with the side surfaces of the p-type deep layers 36 on both sides. Each n-type deep layer 37 extends from the lower surface of the body layer 34 to a position lower than the bottom surface of each trench 14 and the lower surface of each p-type deep layer 36. As shown in FIG. 4, the n-type deep layer 37 in the gap 39 has a shape that is elongated in the z direction in the y-z cross section. That is, the dimension of the n-type deep layer 37 in the z direction (hereinafter referred to as depth Dn) is greater than the dimension of the n-type deep layer 37 in the gap 39 in the y direction (hereinafter referred to as width Wn). For example, the depth Dn can be set to 1 to 4 times the width Wn. In this embodiment, the width Wn of the n-type deep layer 37 is approximately equal to the width Wp of the p-type deep layer 36. Each n-type deep layer 37 has a connection region 37a extending to just below the lower surface of the adjacent p-type deep layer 36. Each connection region 37a contacts the lower surface of the corresponding p-type deep layer 36. The n-type deep layers 37 are connected to each other via their connection regions 37a. The thickness T1 of the portion of the n-type deep layer 37 that protrudes below the lower surface of the p-type deep layer 36 (i.e., the distance in the z direction from the lower surface of the p-type deep layer 36 to the lower surface of the n-type deep layer 37) is approximately 0.1 μm, which is extremely thin. As shown in FIGS. 1 and 2 , each n-type deep layer 37 contacts the gate insulating film 16 within each gap 39. That is, each n-type deep layer 37 contacts the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34 and on the bottom surface of the trench 14 .

[0022] The drift layer 38 is an n-type layer having a lower n-type impurity concentration than the source layer 30. The drift layer 38 is disposed below the n-type deep layer 37. The drift layer 38 contacts the n-type deep layer 37 from below.

[0023] The drain layer 40 is an n-type layer having a higher n-type impurity concentration than the drift layer 38 and the n-type deep layer 37. The drain layer 40 is in contact with the drift layer 38 from below. The drain layer 40 is disposed in an area including the lower surface 12b of the semiconductor substrate 12. The drain layer 40 is in ohmic contact with the drain electrode 24.

[0024] Next, a method for manufacturing the MOSFET 10 will be described. The MOSFET 10 is manufactured from a semiconductor substrate entirely composed of a drain layer 40. First, as shown in FIG. 6, a drift layer 38 is formed on the drain layer 40 by epitaxial growth, and an n-type deep layer 37 is formed by ion-implanting n-type impurities into the surface portion of the formed drift layer 38. Next, as shown in FIG. 7, a plurality of p-type deep layers 36 are formed in the n-type deep layer 37 by selectively ion-implanting p-type impurities into the n-type deep layer 37. Next, as shown in FIG. 8, a body layer 34 is formed on the n-type deep layer 37 and the p-type deep layer 36 by epitaxial growth. Note that the step of forming the p-type deep layer 36 may be performed after the step of forming the body layer 34. Next, a source layer 30 and a contact layer 32 are formed by selectively ion-implanting n-type impurities and p-type impurities into the body layer 34. Thereafter, the trench 14, the gate insulating film 16, the gate electrode 18, the interlayer insulating film 20, the source electrode 22, and the drain electrode 24 are formed, thereby completing the MOSFET 10.

[0025] The MOSFET 10 is used with a higher potential applied to the drain electrode 24 than to the source electrode 22. When a potential equal to or greater than the gate threshold is applied to each gate electrode 18, a channel is formed in the body layer 34 near the gate insulating film 16. The channel connects the source layer 30 and the n-type deep layer 37. As a result, electrons flow from the source layer 30 to the channel, the n-type deep layer 37, and the drift layer 38, as indicated by arrow 100 in FIG. 1 , to the drain layer 40. In other words, the MOSFET 10 is turned on. When the potential of each gate electrode 18 is reduced from a value equal to or greater than the gate threshold to a value less than the gate threshold, the channel disappears and the flow of electrons stops. In other words, the MOSFET 10 is turned off.

[0026] Next, the operation when the MOSFET 10 is turned off will be described in more detail. When the channel disappears, a reverse voltage is applied to the pn junction at the interface between the body layer 34 and each n-type deep layer 37. Therefore, a depletion layer spreads from the body layer 34 to each n-type deep layer 37. Furthermore, each p-type deep layer 36 is connected to the body layer 34 and has approximately the same potential as the body layer 34. Therefore, when the channel disappears, a reverse voltage is also applied to the pn junction at the interface between each p-type deep layer 36 and each n-type deep layer 37. Therefore, a depletion layer also spreads from each p-type deep layer 36 to each n-type deep layer 37. As shown in FIG. 5 , at the intersection of each p-type deep layer 36 and the trench 14, the p-type deep layer 36 is present directly below the trench 14. Therefore, a depletion layer spreads from the p-type deep layer 36 directly below the trench 14 to the n-type deep layer 37 around the bottom of the trench 14. In this way, the depletion layer spreading from the p-type deep layer 36 quickly depletes the n-type deep layer 37 around the bottom of the trench 14. This suppresses electric field concentration near the bottom of the trench 14. Furthermore, the depletion layer spreading from the body layer 34 and each p-type deep layer 36 depletes each n-type deep layer 37 entirely. Note that because each n-type deep layer 37 has a lower n-type impurity concentration than the drift layer 38, the depletion layer is less likely to spread within each n-type deep layer 37 than within the drift layer 38. However, because each n-type deep layer 37 is sandwiched between the p-type deep layers 36 and each n-type deep layer 37 has a narrow width Wn, each n-type deep layer 37 is entirely depleted. Furthermore, the depletion layer spreads into the drift layer 38 via each n-type deep layer 37. Because the n-type impurity concentration of the drift layer 38 is low, almost the entire drift layer 38 is depleted. The depleted drift layer 38 and each n-type deep layer 37 support a high voltage applied between the drain electrode 24 and the source electrode 22. Therefore, the MOSFET 10 has a high breakdown voltage.

[0027] Next, the operation when the MOSFET 10 is turned on will be described in more detail. As described above, when the MOSFET 10 is turned on, electrons flow from the source layer 30 to the drift layer 38 through the channel and the n-type deep layer 37, as indicated by the arrow 100 in FIG. 1 . FIG. 9 shows the distribution of the depletion layer 90 in the n-type deep layer 37 when the MOSFET 10 is on. In FIG. 9 , the region hatched with diagonal lines represents the depletion layer 90. When the MOSFET 10 is on, no reverse voltage is applied to the pn junction (hereinafter referred to as the pn junction 70) at the interface between the n-type deep layer 37 and the p-type deep layer 36. However, even in this state, the depletion layer 90 exists in the pn junction 70 due to the built-in potential. In this embodiment, the n-type impurity concentration in the n-type deep layer 37 is high, so the width Wd of the depletion layer 90 extending from the pn junction 70 into the n-type deep layer 37 is narrow. Therefore, the width We of the electron flow path (i.e., the non-depleted n-type deep layer 37) in the gap 39 is wide. Therefore, when the MOSFET 10 is on, the resistance of the n-type deep layer 37 is low. Therefore, the MOSFET 10 has a low on-resistance.

[0028] As described above, the structure of the MOSFET 10 according to the embodiment can achieve both a high breakdown voltage and a low on-resistance. FIG. 10 shows the results of a simulation of the on-resistance and breakdown voltage of a MOSFET when the depth Dn of the n-type deep layer 37 is changed. The horizontal axis shows the normalized value Dn / Dp, which is the depth Dn of the n-type deep layer 37 divided by the depth Dp of the p-type deep layer 36. When Dn / Dp > 1.00, the n-type deep layer 37 extends below the p-type deep layer 36, as shown in FIG. 4. When Dn / Dp = 1.00, the bottom ends of the n-type deep layer 37 and the p-type deep layer 36 coincide with each other, as shown in FIG. 11. When Dn / Dp < 1.00, the bottom end of the n-type deep layer 37 is located above the bottom end of the p-type deep layer 36, as shown in FIG. 12, and the drift layer 38 extends into the gap 39 below the n-type deep layer 37 (i.e., region 39a in FIG. 12). As shown in FIG. 10, the larger the standard value Dn / Dp, the lower the on-resistance. The reason why the on-resistance is high when the standard value Dn / Dp is small is thought to be that the n-type impurity concentration in region 39a (i.e., the drift layer 38 in the gap 39) in FIG. 12 is low, resulting in a wide depletion layer extending from the p-type deep layer 36 to region 39a when the MOSFET is on, narrowing the electron flow path in region 39a. As shown in FIG. 10, the on-resistance can be relatively reduced when the standard value Dn / Dp is 0.67 or greater, and the on-resistance can be more effectively reduced when the standard value Dn / Dp is 1.0 or greater. Furthermore, a large standard value Dn / Dp reduces the breakdown voltage of the MOSFET. This is thought to be because an electric field is more likely to concentrate in the drift layer 38 when the thickness T1 of the portion of the n-type deep layer 37 that protrudes downward from the bottom surface of the p-type deep layer 36 is large. When the standard value Dn / Dp is 1.07 or less, a high withstand voltage is obtained, and when the standard value Dn / Dp is 1.03 or less, the withstand voltage becomes more stable.

[0029] As described above, in the MOSFET 10 of this embodiment, each n-type deep layer 37 and each p-type deep layer 36 has a vertically elongated shape. When each n-type deep layer 37 and each p-type deep layer 36 are configured in this manner, the electrostatic capacitance (i.e., feedback capacitance) between the gate electrode 18 and the drain electrode 24 is reduced. This allows the switching speed of the MOSFET 10 to be improved.

[0030] 1 to 5, the depth of the n-type deep layer 37 is deeper than the depth of the p-type deep layer 36. However, as shown in FIG. 11 above, the depth of the n-type deep layer 37 may be equal to the depth of the p-type deep layer 36. Alternatively, as shown in FIG. 12 above, the depth of the p-type deep layer 36 may be deeper than the depth of the n-type deep layer 37.

[0031] 1 to 5, each n-type deep layer 37 has a connection region 37a extending to just below the p-type deep layer 36. However, as shown in FIG. 13, the n-type deep layer 37 does not necessarily have to have the connection region 37a.

[0032] Furthermore, in the above-described embodiment, each p-type deep layer 36 is perpendicular to each trench 14, but each p-type deep layer 36 may also intersect each trench 14 obliquely.

[0033] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0034] 10: MOSFET, 12: semiconductor substrate, 14: trench, 16: gate insulating film, 18: gate electrode, 20: interlayer insulating film, 22: source electrode, 24: drain electrode, 30: source layer, 32: contact layer, 34: body layer, 36: p-type deep layer, 37: n-type deep layer, 38: drift layer, 40: drain layer

Claims

1. A field effect transistor (10), a semiconductor substrate (12) having a trench (14) formed on its upper surface; a gate insulating film (16) covering the inner surface of the trench; a gate electrode (18) disposed in the trench and insulated from the semiconductor substrate by the gate insulating film; and The semiconductor substrate is an n-type source layer (30) in contact with the gate insulating film on the side surface of the trench; a p-type body layer (34) in contact with the gate insulating film on the side surface of the trench located below the source layer; a plurality of p-type deep layers (36); a plurality of n-type deep layers (37); a drift layer (38); and each of the p-type deep layers protrudes downward from the body layer, extends from the body layer to a position lower than the bottom surface of the trench, extends along a first direction intersecting the trench when the semiconductor substrate is viewed from above, is arranged with intervals in a second direction perpendicular to the first direction when the semiconductor substrate is viewed from above, and is in contact with the gate insulating film at the side surface of the trench located below the body layer and at the bottom surface of the trench; each n-type deep layer is disposed in the corresponding gap and is in contact with the gate insulating film at the side surface of the trench located below the body layer; the drift layer is an n-type layer having an n-type impurity concentration lower than that of each of the n-type deep layers, and is in contact with lower surfaces of the plurality of n-type deep layers; each of the p-type deep layers has a shape in which a dimension in a thickness direction of the semiconductor substrate is larger than a dimension in the second direction; each of the n-type deep layers has a shape in which a dimension in the thickness direction of the semiconductor substrate is larger than a dimension in the second direction; Field effect transistor.

2. 2. The field effect transistor of claim 1, wherein the plurality of n-type deep layers extend from the lower surface of the body layer to a depth of the lower surfaces of the plurality of p-type deep layers.

3. The field effect transistor according to claim 2 , wherein the plurality of n-type deep layers extend from the lower surface of the body layer to a position lower than the lower surfaces of the plurality of p-type deep layers.

4. The field effect transistor according to claim 3 , wherein the plurality of n-type deep layers are connected to each other via a region below the lower surface of the plurality of p-type deep layers.

5. 5. The field effect transistor according to claim 3, wherein the dimension of said n-type deep layer in said thickness direction of said semiconductor substrate is 1.07 times or less the dimension of said p-type deep layer in said thickness direction of said semiconductor substrate.

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