Semiconductor device and manufacturing method of the same

Abstract

To provide a highly reliable semiconductor device.SOLUTION: A semiconductor device includes: a first electrode; a first semiconductor layer of a first conductivity type provided on the first electrode; a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and having an impurity concentration of the first conductivity type lower than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type provided on the third semiconductor layer; a fifth semiconductor layer of the first conductivity type or the second conductivity type, which is provided on a first semiconductor layer and around the second semiconductor layer and has an impurity concentration of the first conductivity type lower than that of the second semiconductor layer; a second electrode provided in the third semiconductor layer; a third electrode provided in the second semiconductor layer and the third semiconductor layer via the second semiconductor layer, the third semiconductor layer, and a first insulating film; and a fourth electrode provided in the fifth semiconductor layer adjacent to the second semiconductor layer, separated from the first insulating film, with the fifth semiconductor layer and a second insulating film interposed therebetween.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used for applications such as power conversion, etc. High reliability is desirable for such semiconductor devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-227237 [Patent Document 2] Japanese Patent Publication No. 2020-174170 [Patent Document 3] Japanese Patent Application Laid-Open No. 2012-199444 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a highly reliable semiconductor device. [Means for solving the problem]

[0005] a fourth semiconductor layer of the first conductivity type provided on the third semiconductor layer; a fifth semiconductor layer of the first conductivity type or the second conductivity type provided on the first semiconductor layer around the second semiconductor layer and having a lower first conductivity type impurity concentration than the second semiconductor layer; a second electrode provided in the third semiconductor layer; a third electrode provided in the second semiconductor layer and the third semiconductor layer, with a first insulating film interposed between the second semiconductor layer and the third semiconductor layer; and a fourth electrode provided in the fifth semiconductor layer adjacent to the second semiconductor layer, spaced apart from the first insulating film, with the fifth semiconductor layer interposed between the second insulating film and the fifth semiconductor layer. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic top view of a main part of a semiconductor device according to a first embodiment. [Figure 2] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 3] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to another aspect of the first embodiment. [Figure 4] 2A to 2C are schematic cross-sectional views illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 5] 2A to 2C are schematic cross-sectional views illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 6] FIG. 2 is a schematic top view of a semiconductor device as a comparative example of the first embodiment. [Figure 7] FIG. 2 is a schematic cross-sectional view of a semiconductor device as a comparative example of the first embodiment. [Figure 8] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 9] 5A to 5C are schematic cross-sectional views illustrating a manufacturing process of the semiconductor device according to the second embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. [Figure 11] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to another aspect of the third embodiment. [Figure 12] 10A to 10C are schematic cross-sectional views illustrating a manufacturing process of the semiconductor device according to the third embodiment. [Figure 13] 10A to 10C are schematic cross-sectional views illustrating a manufacturing process of the semiconductor device according to the third embodiment. [Figure 14] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same components will be denoted by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0008] In this specification, in order to indicate the positional relationship of parts, etc., the upward direction of the drawing will be described as "up" and the downward direction of the drawing will be described as "down." In this specification, the concepts of "up" and "down" do not necessarily refer to the direction of gravity.

[0009] The following description will be given taking as an example a case where the first conductivity type is n-type and the second conductivity type is p-type.

[0010] In the following description, n + , n, n - and p + , p, p - The notation indicates the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The type is simply n-type, p + type, p - The type is sometimes simply referred to as p-type.

[0011] (First embodiment) The semiconductor device of this embodiment includes a first electrode, a first semiconductor layer of a first conductivity type provided on the first electrode, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and having a lower first conductivity type impurity concentration than the first semiconductor layer, a third semiconductor layer of a second conductivity type provided on the second semiconductor layer, a fourth semiconductor layer of the first conductivity type provided on the third semiconductor layer, a fifth semiconductor layer of the first conductivity type or the second conductivity type provided around the second semiconductor layer on the first semiconductor layer and having a lower first conductivity type impurity concentration than the second semiconductor layer, a second electrode provided in the third semiconductor layer, a third electrode provided in the second semiconductor layer and the third semiconductor layer with a first insulating film interposed between them, and a fourth electrode provided in the fifth semiconductor layer adjacent to the second semiconductor layer, spaced apart from the first insulating film, with the fifth semiconductor layer interposed between them and the second insulating film.

[0012] FIG. 1 is a schematic top view of a semiconductor device 100 according to this embodiment.

[0013] Fig. 2 is a schematic cross-sectional view of the semiconductor device 100 of this embodiment. Fig. 2(a) is a schematic view of the A-A' cross section shown in Fig. 1. Fig. 2(b) is a schematic view of the B-B' cross section shown in Fig. 1. Fig. 2(c) is a schematic view of the C-C' cross section shown in Fig. 1.

[0014] In FIG. 1, the source wiring 20, the gate wiring 22, the first insulating layer 34, the third wiring 26, the extension portion of the gate electrode (a part of the gate electrode) 16c, etc. are omitted.

[0015] A semiconductor device 100 of this embodiment will be described with reference to FIGS.

[0016] The semiconductor device 100 is, for example, a vertical MOSFET.

[0017] The drain electrode 2 (an example of a first electrode) is an electrode that functions as a drain electrode of a MOSFET. The drain electrode 2 includes a conductive material such as aluminum (Al).

[0018] The drain layer 4 (an example of a first semiconductor layer) is provided on the drain electrode 2. The drain layer 4 is electrically connected to the drain electrode 2. The drain layer 4 is a layer that functions as the drain of the MOSFET. The drain layer 4 is, for example, an n + The present invention includes semiconductor materials of the type.

[0019] The drift layer 6 (an example of a second semiconductor layer) is provided on the drain layer 4. The drift layer 6 is a layer that functions as a drift layer of the MOSFET. The drift layer 6 is, for example, - The drift layer 6 contains an n-type semiconductor material. The n-type impurity concentration of the drift layer 6 is lower than the n-type impurity concentration of the drain layer 4.

[0020] Here, the X direction, the Y direction perpendicular to the X direction, and the Z direction perpendicular to the X and Y directions are defined. The drain electrode 2, the drain layer 4, and the drift layer 6 are layers provided parallel to the XY plane. The Z direction is the direction from the drain electrode 2 toward the drift layer 6.

[0021] The base layer 32 (an example of a third semiconductor layer) is provided on the drift layer 6. A portion of the base layer 32 is provided on, for example, a termination layer 8 described later. The base layer 32 is a layer that functions as the base of the MOSFET. The base layer 32 is a layer that forms a channel when charge is applied to a gate electrode 16 described later, and allows carriers to flow between a source layer 36 and a drain layer 4 described later. The base layer 32 includes, for example, a p-type semiconductor material.

[0022] The source layer 36 (an example of a fourth semiconductor layer) is provided on the base layer 32. The source layer 36 is a region that functions as the source of the MOSFET. When an appropriate voltage is applied to the gate electrode 16, carriers flow between the source layer 36 and the drain layer 4. The source layer 36 is, for example, an n + The present invention includes semiconductor materials of the type.

[0023] The termination layer 8 (an example of a fifth semiconductor layer) is provided on the drain layer 4 and around the drift layer 6. The termination layer 8 is, for example, - The n-type impurity concentration of the termination layer 8 is lower than the n-type impurity concentration of the drift layer 6.

[0024] The RESURF layer 30 (an example of a sixth semiconductor layer) is provided on the termination layer 8 and is connected to the base layer 32. The RESURF layer 30 is connected to, for example, the base layer 32 provided on the termination layer 8. The RESURF layer 30 includes, for example, a p-type semiconductor material. The p-type impurity concentration of the RESURF layer 30 is lower than the p-type impurity concentration of the base layer 32.

[0025] The first trench 11a and the first trench 11b are provided so as to extend from above the base layer 32 to the drift layer 6. The first trench 11b is provided so as to extend from above the source layer 36 to the drift layer 6. On the other hand, the source layer 36 is not provided in the region where the first trench 11a is provided.

[0026] The first field plate electrode 12b (an example of a third electrode) is provided in the first trench 11b, with the drift layer 6, the base layer 32, and the source layer 36 interposed therebetween, and with the first insulating film 10b interposed therebetween. The first field plate electrode 12a (an example of a third electrode) is provided in the first trench 11a, with the drift layer 6, the base layer 32, and the first insulating film 10 interposed therebetween. The first field plate electrode 12 is provided, for example, to reduce the concentration of a reverse electric field between the gate electrode 16 and the drain electrode 2, thereby increasing the breakdown voltage of the MOSFET. The first field plate electrode 12 includes a conductive material such as polysilicon containing impurities.

[0027] The second trench 51a is provided in the termination layer 8 adjacent to the drift layer 6 and spaced apart from the first trench 11. For example, the second trench 51a is provided from above the base layer 32 and the RESURF layer 30 provided on the termination layer 8 to reach the termination layer 8.

[0028] The second field plate electrode 52a (an example of a fourth electrode) is provided in the second trench 51a, with the termination layer 8, the RESURF layer 30, and the base layer 32, with the second insulating film 50a interposed therebetween. The second insulating film 50a is provided apart from the first insulating film 10. The second field plate electrode 52a is provided, for example, to reduce the concentration of a reverse electric field between the gate electrode 16 and the drain electrode 2, thereby increasing the breakdown voltage of the MOSFET. The second field plate electrode 52 includes a conductive material such as polysilicon containing impurities.

[0029] In the semiconductor device 100 of this embodiment, as shown in FIG. 1(a), the field plate electrodes (first field plate electrode 12 and second field plate electrode 52) are arranged separately in the X and Y directions.

[0030] The first insulating layer 34 is provided on the drift layer 6, the termination layer 8, the base layer 32, and the source layer 36. The first insulating layer 34 includes an insulating material such as silicon oxide.

[0031] The source wiring 20 (an example of a first wiring) is provided, for example, on a first insulating layer 34 on the base layer 32. The source wiring 20 includes, for example, a conductive material such as Al.

[0032] The gate wiring 22 (an example of a second wiring) is provided, for example, on the first insulating layer 34 on the termination layer 8. The gate wiring 22 includes, for example, a conductive material such as Al.

[0033] The connection wiring 18a is provided, for example, around the first trench 11a when viewed from above. The connection wiring 18a electrically connects the base layer 32 and the source wiring 20.

[0034] The connection wiring 18b is provided, for example, around the first trench 11b when viewed from above. The connection wiring 18b electrically connects the base layer 32 and the source wiring 20.

[0035] The connection wiring 14a electrically connects the first field plate electrode 12a and the source wiring 20. The connection wiring 14b electrically connects the first field plate electrode 12b and the source wiring 20. The connection wiring 54 electrically connects the second field plate electrode 52 and the source wiring 20.

[0036] The gate electrode 16a is provided in the base layer 32 between the first insulating film 10a and the first insulating film 10b. The gate electrode 16b is provided in the base layer 32. The gate electrodes 16a and 16b are electrically connected to the gate wiring 22 via, for example, an extension portion (part of the gate electrode) 16c ( FIG. 2(b) ) of the gate electrode provided in the base layer 32 and a third wiring 26 provided in the first insulating layer 34 on the termination layer 8. The gate electrode 16 includes, for example, a conductive material such as polysilicon containing impurities. The gate electrode 16 is an example of a second electrode. As shown in FIG. 3(b), a gate insulating film 17 is provided between the gate electrode 16 and the drift layer 6, the base layer 32, and the source layer 36.

[0037] 3 is a schematic cross-sectional view of a semiconductor device 105 according to another aspect of this embodiment. FIG. 3(a) corresponds to a schematic cross-sectional view taken along the line CC' of the schematic top view shown in FIG. - Instead of the termination layer 8, p - A mold termination layer 9 is provided. FIG. 3(b) is a schematic enlarged view of the gate electrode 16, the gate insulating film 17, and the vicinity thereof.

[0038] 2 and 3 also show the depletion layer edge E when a reverse electric field is applied.

[0039] When Si is used as the semiconductor material, for example, arsenic (As), phosphorus (P) or antimony (Sb) can be used as the n-type impurity, and for example, B (boron) can be used as the p-type impurity.

[0040] 4 and 5 are schematic cross-sectional views showing the manufacturing process of the semiconductor device of this embodiment.

[0041] The method for manufacturing a semiconductor device of this embodiment includes forming a tenth semiconductor layer of the second conductivity type in a layer of the second semiconductor layer of the first conductivity type that will become the fifth semiconductor layer, forming a first trench in the second semiconductor layer where the tenth semiconductor layer is not formed, forming a second trench in the second semiconductor layer where the tenth semiconductor layer is formed, forming a fourth insulating film on the second semiconductor layer, inside the first trench, and inside the second trench, and diffusing the second conductivity type impurities contained in the tenth semiconductor layer into the second semiconductor layer where the tenth semiconductor layer is formed, thereby forming a fifth semiconductor layer of the first conductivity type or the second conductivity type that has a lower first conductivity type impurity concentration than the second semiconductor layer.

[0042] First, a resist mask R is used to form a p-type semiconductor layer 62 (an example of a tenth semiconductor layer) and a p-type semiconductor layer 60 (an example of a tenth semiconductor layer) on the semiconductor layer 62, which is provided on the layer that will become the termination layer 8 of the drift layer 6 above the drain layer 4 and on the portion where the termination layer 8 will not be formed.

[0043] Next, the resist mask R is removed by, for example, ashing. Next, a first trench 11 is formed in the drift layer 6 where the semiconductor layer 62 and the semiconductor layer 60 are not formed. Furthermore, a second trench 51 is formed in the drift layer 6 where the semiconductor layer 62 and the semiconductor layer 60 are formed and adjacent to the first trench 11 (FIG. 4(b)).

[0044] Next, an insulating film 64 containing, for example, silicon oxide is formed on the drift layer 6 and inside the first trench 11 and the second trench 51 by, for example, thermal oxidation. Here, when the insulating film 64 is formed, for example, p-type impurities in the semiconductor layer 60 and the semiconductor layer 62 are thermally diffused to form n - A mould termination layer 8 is formed.

[0045] Although the p-type semiconductor layer 60 and the p-type semiconductor layer 62 are formed here, the number and form of the p-type semiconductor layers to be formed are not particularly limited to those shown in Figures 4(a) and 4(b). In addition, by increasing the amount of p-type impurities to be implanted, it is possible to form p-type semiconductor layers around the drift layer 6. - It is also possible to form a mould termination layer 9 .

[0046] Next, for example, by using a CVD (Chemical Vapor Deposition) method, a first field plate electrode 12 is formed in the first trench 11. Also, a second field plate electrode 52 is formed in the second trench 51 (FIG. 5(a)).

[0047] Next, an insulating film 66 is formed on the first field plate electrode 12 and the second field plate electrode 52 using, for example, thermal oxidation or CVD. Next, a gate trench 68 is formed between the first field plate electrode 12 and the second field plate electrode 52. The depth of the gate trench 68 is shallower than the depth of the first trench 11 and the depth of the second trench 51.

[0048] Next, the insulating film 66 and part of the insulating film 64 are removed by, for example, etching (FIG. 5(c)).

[0049] Next, the gate electrode 16 is formed in the gate trench 68. An extension portion 16c of the gate electrode is formed on the insulating film 64. Next, a RESURF layer 30 is formed on the drift layer 6 and on the termination layer 8 adjacent to the drift layer 6, for example, by ion implantation. A base layer 32 is formed on the drift layer 6, for example, by ion implantation. Next, a source layer 36 is formed on the base layer 32, for example, by ion implantation.

[0050] Next, the third wiring 26, the connection wiring 18a, the connection wiring 18b, the connection wiring 14a, the connection wiring 14b, the connection wiring 54, the first insulating layer 34, the source wiring 20 and the gate wiring 22 are formed as appropriate to obtain the semiconductor device 100 of this embodiment.

[0051] Next, the effects of the semiconductor device of this embodiment will be described.

[0052] In a MOSFET with a field plate electrode, the drift layer is depleted by the electric field from the field plate electrode, which allows for both high breakdown voltage and low on-resistance, even in a drift layer with a high concentration of n-type impurities, compared to one-dimensional junctions such as pn junctions.

[0053] However, when the n-type impurity concentration in the drift layer is high, the termination layer, where the field plate electrode is not located, is less susceptible to depletion than the FET cell section where the field plate electrode is located, which has led to problems such as a decrease in breakdown voltage during reliability evaluation tests such as the high-temperature reverse bias (HTRB) test.

[0054] In addition, in a MOSFET with a field plate electrode, it is necessary to place the gate electrode only inside the region where the field plate electrode connected to the source wiring is located. This is because if the gate electrode is located in a region that is not depleted because there is no field plate electrode, the drain voltage will be applied to the gate insulating film, which may cause dielectric breakdown of the gate insulating film.

[0055] Fig. 6 is a schematic top view of a comparative semiconductor device 1000. Fig. 6 is a schematic top view showing the connection between the first field plate electrode 12 and the source wiring 20 and the connection between the gate electrode 16 and the gate wiring 22 in the semiconductor device 1000 in which the first field plate electrode 12 extends in the X direction.

[0056] The gate electrode 16 can be connected to a gate wiring (not shown) provided on the source layer 36 via the third wiring 26. Furthermore, the first field plate electrode 12 can be connected to a source wiring (not shown) provided on the connection wiring 14 via the connection wiring 14. In this way, in a semiconductor device in which the field plate electrode is provided extending in the X direction, there is a large degree of freedom in the connection between the gate electrode and the gate wiring, and the connection between the field plate electrode and the source wiring in the X direction. Therefore, it is possible to place the gate electrode in a depleted region.

[0057] FIG. 7 is a schematic diagram of a semiconductor device 1100 as a comparative example. By arranging the field plate electrodes separated in the X and Y directions as in the semiconductor device 1100, a low on-resistance and a small output capacitance Coss can be obtained. Meanwhile, since the gate electrode 16 cannot be arranged in a non-depleted region, the connection between the gate electrode 16 and the gate wiring 22 is achieved by providing wiring 27 (wiring 27a, wiring 27b, and wiring 27c) between the drift layer 6 and the source wiring 20. This results in a two-layer wiring structure in which wiring 27b and the source wiring 20 are stacked. This complicates the manufacturing process.

[0058] Therefore, the semiconductor device of this embodiment includes a first electrode, a first semiconductor layer of a first conductivity type provided on the first electrode, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and having a lower first conductivity type impurity concentration than the first semiconductor layer, a third semiconductor layer of a second conductivity type provided on the second semiconductor layer, a fourth semiconductor layer of the first conductivity type provided on the third semiconductor layer, a fifth semiconductor layer of the first conductivity type or the second conductivity type provided around the second semiconductor layer on the first semiconductor layer and having a lower first conductivity type impurity concentration than the second semiconductor layer, a second electrode provided in the third semiconductor layer, a third electrode provided in the second semiconductor layer and the third semiconductor layer with the second semiconductor layer and the third semiconductor layer interposed between them and a first insulating film, and a fourth electrode provided in the fifth semiconductor layer adjacent to the second semiconductor layer, spaced apart from the first insulating film, with the fifth semiconductor layer and the second insulating film interposed between them.

[0059] In the semiconductor device 100, n - Type termination layer 8 or p - A termination layer 9 is provided. - Type termination layer 8 or p - Even if a field plate electrode is not provided in termination layer 9, the depletion layer tends to spread outside termination layer 8 or termination layer 9. This avoids the problem described above that "if the gate electrode is placed in a region that is not depleted, the drain voltage is applied to the gate insulating film, causing dielectric breakdown of the gate insulating film." This makes it possible to provide a highly reliable semiconductor device.

[0060] Furthermore, by providing RESURF layer 30, the depletion layer is more likely to extend outside termination layer 8 or 9.

[0061] Furthermore, by using third wiring 26 provided in first insulating layer 34 on termination layer 8 and electrically connecting gate electrode 16 and gate wiring 22, it is possible to reduce the film thickness of first insulating layer 34 between termination layer 8 and the portion where gate electrode 16 extends to termination layer 8. This makes it possible to reduce the step on the surface when forming first insulating layer 34, facilitating processing of the wiring formed in first insulating layer 34.

[0062] According to the semiconductor device of this embodiment, it is possible to provide a highly reliable semiconductor device.

[0063] (Second embodiment) The semiconductor device of this embodiment differs from the semiconductor device of the first embodiment in that it further includes a fifth electrode provided in the fifth semiconductor layer via a third insulating film that is spaced from the fifth semiconductor layer and the second insulating film, and the fourth electrode is provided between the third electrode and the fifth electrode. Here, a description of the content that overlaps with the first embodiment will be omitted.

[0064] FIG. 8 is a schematic diagram of a semiconductor device 110 of this embodiment.

[0065] In semiconductor device 105, in addition to second trench 51a, for example, second trench 51b, second trench 51c, second trench 51d, and second trench 51e are provided in termination layer 8. Note that the number of second trenches provided in termination layer 8 is not limited to that shown in FIG.

[0066] The second field plate electrode 52b is provided in the termination layer 8 via a second insulating film 50b that is spaced apart from the termination layer 8 and the second insulating film 50a. The second field plate electrode 52c is provided in the termination layer 8 via a second insulating film 50c that is spaced apart from the termination layer 8 and the second insulating film 50b. The second field plate electrode 52d is provided in the termination layer 8 via a second insulating film 50d that is spaced apart from the termination layer 8 and the second insulating film 50c. The second field plate electrode 52e is provided in the termination layer 8 via a second insulating film 50e that is spaced apart from the termination layer 8 and the second insulating film 50d.

[0067] The second field plate electrode 52b, the second field plate electrode 52c, the second field plate electrode 52d, and the second field plate electrode 52e are not electrically connected to the source wiring 20.

[0068] In the semiconductor device 110 of this embodiment, the second insulating film 50a is an example of a second insulating film, the second insulating film 50b is an example of a third insulating film, and the second field plate electrode 52b is an example of a fifth electrode.

[0069] FIG. 9 is a schematic diagram showing the manufacturing process of the semiconductor device 110 of this embodiment.

[0070] As shown in FIG. 9(a), second trenches 51b, 51c, 51d, and 51e are also formed in the layer of the drift layer 6 in which the termination layer 8 is formed.

[0071] Next, a resist mask R is formed inside the first trenches 11a and 11b. Next, p-type impurity ions are implanted from above the layer on which the termination layer 8 is to be formed (FIG. 9(b)).

[0072] Next, the resist mask R is removed by, for example, ashing. Next, an insulating film 64 containing, for example, silicon oxide is formed on the drift layer 6 and inside the first trench 11 and the second trench 51 by, for example, thermal oxidation. Here, when the insulating film 64 is formed, p-type impurities in the semiconductor layers 60 and 62 are thermally diffused to form n-type impurities around the drift layer 6. - A mold termination layer 8 is formed (FIG. 9(c)). After this, the process is the same as the process from FIG. 5 onwards in the manufacturing process of the semiconductor device 100 of the first embodiment.

[0073] In the case of semiconductor device 110 of this embodiment, termination layer 8 is formed by ion implantation of p-type impurities using second trenches 51b, 51c, 51d, and 51e provided in the portion where termination layer 8 will be formed. Because second trenches 51b, 51c, 51d, and 51e exist, ion implantation can be easily performed throughout drift layer 6 to form termination layer 8 without using high-energy ion implantation. This is particularly advantageous when using a thick drift layer 6 to manufacture a high-voltage MOSFET.

[0074] The semiconductor device 110 of this embodiment also makes it possible to provide a highly reliable semiconductor device.

[0075] (Third embodiment) The semiconductor device of this embodiment includes a first electrode, a first semiconductor layer of a first conductivity type provided on the first electrode, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and having a lower first conductivity type impurity concentration than the first semiconductor layer, a third semiconductor layer of a second conductivity type provided on the second semiconductor layer, a fourth semiconductor layer of the first conductivity type provided on the third semiconductor layer, and a seventh semiconductor layer of the second conductivity type provided on the second semiconductor layer around the third semiconductor layer, connected to the third semiconductor layer, and having a lower second conductivity type impurity concentration than the third semiconductor layer. an eighth semiconductor layer of the second conductivity type provided in the second semiconductor layer below the seventh semiconductor layer and having a lower second conductivity type impurity concentration than the third semiconductor layer, a second electrode provided in the third semiconductor layer, a third electrode provided in the second semiconductor layer and the third semiconductor layer with the second semiconductor layer and the third semiconductor layer and a first insulating film interposed therebetween, and a fourth electrode provided in the seventh semiconductor layer, in the eighth semiconductor layer and in the second semiconductor layer between the seventh and eighth semiconductor layers and the seventh semiconductor layer, the eighth semiconductor layer and the second semiconductor layer and a second insulating film interposed therebetween. Here, description of content that overlaps with the first and second embodiments will be omitted.

[0076] Fig. 10 is a schematic cross-sectional view of a semiconductor device 120 of this embodiment. Fig. 10 is a schematic cross-sectional view corresponding to the CC' cross-sectional view of Fig. 1(a).

[0077] In the semiconductor device 120, the termination layer 8 or the termination layer 9 is not provided.

[0078] The p-type seventh semiconductor layer 33 is provided on the drift layer 6 around the base layer 32. The seventh semiconductor layer 33 is connected to the base layer 32. The p-type impurity concentration of the seventh semiconductor layer 33 is lower than the p-type impurity concentration of the base layer 32.

[0079] The p-type eighth semiconductor layer 31 is provided in the drift layer 6 below the seventh semiconductor layer 33. The p-type impurity concentration of the eighth semiconductor layer 31 is lower than the p-type impurity concentration of the base layer 32.

[0080] In the semiconductor device 120, the second trench 51a is provided, for example, spaced apart from the first trench 11a and extending from above the base layer 32 and the seventh semiconductor layer 33 to the drift layer 6 below the eighth semiconductor layer 31.

[0081] The second field plate electrode 52a (an example of a fourth electrode) is provided in the second trench 51a via the drift layer 6, the seventh semiconductor layer 33, the eighth semiconductor layer 31, and the base layer 32, with a second insulating film 50a interposed between them. The second insulating film 50a is provided apart from the first insulating film 10a.

[0082] The third wiring 26 is provided in the first insulating layer 34 on the seventh semiconductor layer 33.

[0083] FIG. 11 is a schematic cross-sectional view of a semiconductor device 125 according to another aspect of this embodiment.

[0084] The p-type ninth semiconductor layer 29 is provided between the seventh semiconductor layer 33 and the eighth semiconductor layer 31 and is connected to the seventh semiconductor layer 33 and the eighth semiconductor layer 31. The p-type impurity concentration of the ninth semiconductor layer 29 is lower than the p-type impurity concentration of the base layer 32.

[0085] 12 and 13 are schematic cross-sectional views showing the manufacturing process of the semiconductor device 120 of this embodiment.

[0086] The method for manufacturing a semiconductor device of this embodiment includes forming a tenth semiconductor layer of the second conductivity type in a layer of the second semiconductor layer of the first conductivity type that will become the fifth semiconductor layer, forming a first trench in the second semiconductor layer where the tenth semiconductor layer is not formed, forming a second trench in the second semiconductor layer adjacent to the first trench where the tenth semiconductor layer is formed, forming a fourth insulating film on the second semiconductor layer, inside the first trench, and inside the second trench, and diffusing the second conductivity type impurities contained in the tenth semiconductor layer into the second semiconductor layer in which the tenth semiconductor layer has been formed, thereby forming a fifth semiconductor layer of the first conductivity type or the second conductivity type that has a lower first conductivity type impurity concentration than the second semiconductor layer.

[0087] Unlike the semiconductor device 100 of the first embodiment, the semiconductor device 120 of the present embodiment does not form the semiconductor layers 60 and 62, but instead forms the first trench 11a, the first trench 11b, and the second trench 51a in the drift layer 6 (FIG. 12(a)). Next, an insulating film 64 containing, for example, silicon oxide is formed on the drift layer 6 and inside the first trench 11 and the second trench 51 by, for example, thermal oxidation (FIG. 12(b)). Next, a first field plate electrode 12 is formed in the first trench 11 by, for example, CVD (Chemical Vapor Deposition). Furthermore, a second field plate electrode 52 is formed in the second trench 51 (FIG. 12(c)).

[0088] Next, using the resist mask R provided on the first field plate electrode 12 as a mask, ions of a p-type impurity concentration are implanted from above the second field plate electrode 52 and the drift layer 6 to form the seventh semiconductor layer 33 and the eighth semiconductor layer 31 (FIG. 13(a)). The subsequent steps are the same as those in the first and second embodiments and will therefore not be described.

[0089] In the semiconductor device 120 of this embodiment, by providing the seventh semiconductor layer 33 and the eighth semiconductor layer 31, it is possible to extend the depletion layer from the first insulating layer 34 side to the drain layer 4 side.

[0090] The semiconductor device of this embodiment also makes it possible to provide a highly reliable semiconductor device.

[0091] (Fourth embodiment) The semiconductor device of this embodiment differs from the semiconductor devices of the first to third embodiments in that the width of the fifth electrode in a plane intersecting the direction from the first semiconductor layer to the second semiconductor layer is smaller than the widths of the third electrode and the fourth electrode in a plane intersecting the direction from the first semiconductor layer to the second semiconductor layer.

[0092] The semiconductor device of this embodiment also differs from the semiconductor devices of the first to third embodiments in that it further includes a plurality of third insulating films and a plurality of fifth electrodes, and the plurality of third insulating films and the plurality of fifth electrodes are arranged at intervals different from the intervals between the first insulating films and the first field plate electrodes so that, in a plane intersecting the direction from the first semiconductor layer to the second semiconductor layer, the sum of the areas of the plurality of third insulating films and the plurality of fifth electrodes is 0.5 to 2 times the area of ​​the fifth semiconductor layer on which the areas of the plurality of third insulating films and the plurality of fifth electrodes are not provided.

[0093] Here, the description of the contents that overlap with the first to third embodiments will be omitted.

[0094] FIG. 14 is a schematic cross-sectional view of a semiconductor device 130 of this embodiment.

[0095] Unlike the semiconductor device of the second embodiment, in semiconductor device 130, the widths in the XY plane of second field plate electrode 52b, second field plate electrode 52c, second field plate electrode 52d, second field plate electrode 52e, second field plate electrode 52f, second field plate electrode 52g, second field plate electrode 52h and second field plate electrode 52i are smaller than the widths in the XY plane of second field plate electrode 52a, first field plate electrode 12a and first field plate electrode 12b.

[0096] It should be noted that second field plate electrode 52b, second field plate electrode 52c, second field plate electrode 52d, second field plate electrode 52e, second field plate electrode 52f, second field plate electrode 52g, second field plate electrode 52h and second field plate electrode 52i are not electrically connected to source wiring 20.

[0097] Furthermore, the sum of the areas of second insulating film 50b, second insulating film 50c, second insulating film 50d, second insulating film 50e, second insulating film 50f, second insulating film 50g, second insulating film 50h, and second insulating film 50i and the areas of second field plate electrode 52b, second field plate electrode 52c, second field plate electrode 52d, second field plate electrode 52e, second field plate electrode 52f, second field plate electrode 52g, second field plate electrode 52h, and second field plate electrode 52i in a plane parallel to the XY plane is The area of ​​the second insulating film 50b, the second insulating film 50c, the second insulating film 50d, the second insulating film 50e, the second insulating film 50f, the second insulating film 50g, the second insulating film 50h, the second insulating film 50i, the second field plate electrode 52b, the second field plate electrode 52c, the second field plate electrode 52d, the second field plate electrode 52e, the second field plate electrode 52f, the second field plate electrode 52g, the second field plate electrode 52h, and the second field plate electrode 52i are not provided. This is because, in the manufacturing process of the semiconductor device 130 of this embodiment, p-type impurities are implanted into the upper surface of the termination layer 8 and the bottom of the second trench 51 and diffused therein, thereby increasing the n-type impurity concentration of the termination layer 8. - This is because it is appropriate from the viewpoint of making the mold impurity concentration uniform.

[0098] In the semiconductor device 130 of this embodiment, the second insulating film 50a is an example of a second insulating film. The second insulating films 50b, 50c, 50d, 50e, 50f, 50g, 50h, and 50i are examples of a plurality of third insulating films. The second field plate electrode 52b, 52c, 52d, 52e, 52f, 52g, 52h, and 52i are examples of a plurality of fifth electrodes.

[0099] By appropriately adjusting the depths and opening sizes of the second trenches 51b, 51c, 51d, 51e, 51f, 51g, 51h, and 51i, it is possible to process the trenches collectively, including the first trench 11a, 11b, and 51a.

[0100] Furthermore, by appropriately adjusting the depths and opening sizes of second trenches 51b, 51c, 51d, 51e, 51f, 51g, 51h, and 51i, p-type impurities can be easily diffused throughout drift layer 6 by implanting ions into the surface of drift layer 6 and the bottoms of second trenches 51b to 51i, without using high-energy ion implantation, and termination layer 8 can be formed.

[0101] The semiconductor device of this embodiment also makes it possible to provide a highly reliable semiconductor device.

[0102] Although several embodiments and examples of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0103] The above-described embodiment can be summarized as the following technical proposal. (Technical proposal 1) A first electrode; a first semiconductor layer of a first conductivity type provided on the first electrode; a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and having a lower first conductivity type impurity concentration than the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type provided on the third semiconductor layer; a fifth semiconductor layer of the first conductivity type or the second conductivity type provided on the first semiconductor layer and around the second semiconductor layer, the fifth semiconductor layer having a lower first conductivity type impurity concentration than the second semiconductor layer; a second electrode provided in the third semiconductor layer; a third electrode provided in the second semiconductor layer and the third semiconductor layer with a first insulating film interposed between the second semiconductor layer and the third semiconductor layer; a fourth electrode provided in the fifth semiconductor layer adjacent to the second semiconductor layer, spaced apart from the first insulating film, with the fifth semiconductor layer and the second insulating film interposed therebetween; A semiconductor device comprising: (Technical proposal 2) The semiconductor device according to Technical Solution 1 further comprises a sixth semiconductor layer of the second conductivity type provided on the fifth semiconductor layer, connected to the third semiconductor layer, and having a lower second conductivity type impurity concentration than the third semiconductor layer. (Technical proposal 3) a fifth electrode provided in the fifth semiconductor layer via a third insulating film that is spaced apart from the fifth semiconductor layer and the second insulating film; The fourth electrode is provided between the third electrode and the fifth electrode. The semiconductor device according to Technical Proposal 1. (Technical proposal 4) a width of the fifth electrode in a plane intersecting a direction from the first semiconductor layer toward the second semiconductor layer is smaller than widths of the third electrode and the fourth electrode in the plane intersecting a direction from the first semiconductor layer toward the second semiconductor layer; A semiconductor device according to Technical Proposal 3. (Technical proposal 5) Further comprising a plurality of the third insulating films and a plurality of the fifth electrodes, In a plane intersecting a direction from the first semiconductor layer toward the second semiconductor layer, the sum of the areas of the third insulating films and the fifth electrodes is 0.5 to 2 times the area of ​​the fifth semiconductor layer where the areas of the third insulating films and the fifth electrodes are not provided. A semiconductor device according to Technical Proposal 4. (Technical proposal 6) a first insulating layer provided on the third semiconductor layer and the fifth semiconductor layer; a first wiring provided on the first insulating layer above the third semiconductor layer and electrically connected to the third electrode and the fourth electrode; a second wiring provided on the first insulating layer above the fifth semiconductor layer; a third wiring provided in the first insulating layer on the fifth semiconductor layer and electrically connecting the second electrode and the second wiring; The semiconductor device according to Technical Solution 1 further comprises: (Technical proposal 7) A first electrode; a first semiconductor layer of a first conductivity type provided on the first electrode; a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and having a lower first conductivity type impurity concentration than the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type provided on the third semiconductor layer; a seventh semiconductor layer of a second conductivity type provided on the second semiconductor layer around the third semiconductor layer, connected to the third semiconductor layer, and having a second conductivity type impurity concentration lower than that of the third semiconductor layer; an eighth semiconductor layer of a second conductivity type provided in the second semiconductor layer below the seventh semiconductor layer and having a second conductivity type impurity concentration lower than that of the third semiconductor layer; a second electrode provided in the third semiconductor layer; a third electrode provided in the second semiconductor layer and the third semiconductor layer with a first insulating film interposed between the second semiconductor layer and the third semiconductor layer; a fourth electrode provided in the seventh semiconductor layer, the eighth semiconductor layer, and the second semiconductor layer between the seventh semiconductor layer and the eighth semiconductor layer, with a second insulating film interposed between the seventh semiconductor layer, the eighth semiconductor layer, and the second semiconductor layer; A semiconductor device comprising: (Technical proposal 8) a ninth semiconductor layer of a second conductivity type provided between the seventh semiconductor layer and the eighth semiconductor layer, connected to the seventh semiconductor layer and the eighth semiconductor layer, and having a second conductivity type impurity concentration lower than that of the third semiconductor layer; The semiconductor device according to Technical Solution 7 further comprises: (Technical proposal 9) a first insulating layer provided on the third semiconductor layer and the seventh semiconductor layer; a first wiring provided on the first insulating layer above the third semiconductor layer and electrically connected to the third electrode and the fourth electrode; a second wiring provided on the first insulating layer above the seventh semiconductor layer; a third wiring provided in the first insulating layer on the seventh semiconductor layer and electrically connecting the second electrode and the second wiring; The semiconductor device according to Technical Solution 7, comprising: (Technical proposal 10) forming a tenth semiconductor layer of the second conductivity type on a layer of the second semiconductor layer of the first conductivity type that will become a fifth semiconductor layer; forming a first trench in the second semiconductor layer where the tenth semiconductor layer is not formed; forming a second trench in the second semiconductor layer adjacent to the first trench in which the tenth semiconductor layer is formed; forming a fourth insulating film on the second semiconductor layer, inside the first trench, and inside the second trench; forming a fifth semiconductor layer of the first conductivity type or the second conductivity type having a lower first conductivity type impurity concentration than the second semiconductor layer by diffusing the second conductivity type impurity contained in the tenth semiconductor layer into the second semiconductor layer in which the tenth semiconductor layer is formed; A method for manufacturing a semiconductor device. [Explanation of symbols]

[0104] 2: Drain electrode (first electrode) 4: Drain layer (first semiconductor layer) 6: Drift layer (second semiconductor layer) 8: Termination layer (fifth semiconductor layer) 9: Termination layer (fifth semiconductor layer) 10: First insulating film 11: First trench 12: First field plate electrode (third electrode) 16: Gate electrode (second electrode) 17: Gate insulating film 20: Source wiring (first wiring) 22: Gate wiring (second wiring) 26: 3rd wiring 29: 9th semiconductor layer 30: RESURF layer (6th semiconductor layer) 31: Eighth semiconductor layer 32: Base layer (third semiconductor layer) 33: Seventh semiconductor layer 34: First insulating layer 36: Source layer (fourth semiconductor layer) 50a: Second insulating film 51: Second trench 52: Second field plate electrode (fourth electrode) 60: Semiconductor layer 62: Semiconductor layer (10th semiconductor layer) 64: insulating film 66: Insulating film 100: Semiconductor device 105: Semiconductor device 110: Semiconductor device 120: Semiconductor device 125: Semiconductor devices 130: Semiconductor device

Claims

1. A first electrode; a first semiconductor layer of a first conductivity type provided on the first electrode; a second semiconductor layer of a first conductivity type provided on the first semiconductor layer and having a lower first conductivity type impurity concentration than the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type provided on the third semiconductor layer; a fifth semiconductor layer of the first conductivity type or the second conductivity type provided on the first semiconductor layer and around the second semiconductor layer, the fifth semiconductor layer having a lower first conductivity type impurity concentration than the second semiconductor layer; a second electrode provided in the third semiconductor layer; a third electrode provided in the second semiconductor layer and the third semiconductor layer with a first insulating film interposed between the second semiconductor layer and the third semiconductor layer; a fourth electrode provided in the fifth semiconductor layer adjacent to the second semiconductor layer, spaced apart from the first insulating film, with the fifth semiconductor layer and the second insulating film interposed therebetween; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, further comprising a sixth semiconductor layer of the second conductivity type provided on the fifth semiconductor layer, connected to the third semiconductor layer, and having a lower second conductivity type impurity concentration than the third semiconductor layer.

3. a fifth electrode provided in the fifth semiconductor layer via a third insulating film that is spaced apart from the fifth semiconductor layer and the second insulating film; The fourth electrode is provided between the third electrode and the fifth electrode. The semiconductor device according to claim 1.

4. a width of the fifth electrode in a plane intersecting a direction from the first semiconductor layer toward the second semiconductor layer is smaller than widths of the third electrode and the fourth electrode in the plane intersecting a direction from the first semiconductor layer toward the second semiconductor layer; 4. The semiconductor device according to claim 3.

5. a plurality of the third insulating films and a plurality of the fifth electrodes; In a plane intersecting a direction from the first semiconductor layer toward the second semiconductor layer, a sum of an area of ​​the third insulating films and an area of ​​the fifth electrodes is 0.5 to 2 times an area of ​​the fifth semiconductor layer where the area of ​​the third insulating films and the area of ​​the fifth electrodes are not provided.

5. The semiconductor device according to claim 4.

6. a first insulating layer provided on the third semiconductor layer and the fifth semiconductor layer; a first wiring provided on the first insulating layer above the third semiconductor layer and electrically connected to the third electrode and the fourth electrode; a second wiring provided on the first insulating layer above the fifth semiconductor layer; a third wiring provided in the first insulating layer on the fifth semiconductor layer and electrically connecting the second electrode and the second wiring; The semiconductor device according to claim 1 , further comprising:

7. A first electrode; a first semiconductor layer of a first conductivity type provided on the first electrode; a second semiconductor layer of a first conductivity type provided on the first semiconductor layer and having a lower first conductivity type impurity concentration than the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type provided on the third semiconductor layer; a seventh semiconductor layer of the second conductivity type provided on the second semiconductor layer around the third semiconductor layer, connected to the third semiconductor layer, and having a second conductivity type impurity concentration lower than that of the third semiconductor layer; an eighth semiconductor layer of a second conductivity type provided in the second semiconductor layer below the seventh semiconductor layer and having a second conductivity type impurity concentration lower than that of the third semiconductor layer; a second electrode provided in the third semiconductor layer; a third electrode provided in the second semiconductor layer and the third semiconductor layer with a first insulating film interposed between the second semiconductor layer and the third semiconductor layer; a fourth electrode provided in the seventh semiconductor layer, the eighth semiconductor layer, and the second semiconductor layer between the seventh semiconductor layer and the eighth semiconductor layer, with a second insulating film interposed between the seventh semiconductor layer, the eighth semiconductor layer, and the second semiconductor layer; A semiconductor device comprising:

8. a ninth semiconductor layer of a second conductivity type provided between the seventh semiconductor layer and the eighth semiconductor layer, connected to the seventh semiconductor layer and the eighth semiconductor layer, and having a second conductivity type impurity concentration lower than that of the third semiconductor layer; The semiconductor device according to claim 7 , further comprising:

9. a first insulating layer provided on the third semiconductor layer and the seventh semiconductor layer; a first wiring provided on the first insulating layer above the third semiconductor layer and electrically connected to the third electrode and the fourth electrode; a second wiring provided on the first insulating layer above the seventh semiconductor layer; a third wiring provided in the first insulating layer on the seventh semiconductor layer and electrically connecting the second electrode and the second wiring; The semiconductor device according to claim 7 , comprising:

10. forming a tenth semiconductor layer of the second conductivity type on a layer of the second semiconductor layer of the first conductivity type that will become a fifth semiconductor layer; forming a first trench in the second semiconductor layer where the tenth semiconductor layer is not formed; forming a second trench in the second semiconductor layer adjacent to the first trench in which the tenth semiconductor layer is formed; forming a fourth insulating film on the second semiconductor layer, inside the first trench, and inside the second trench; forming a fifth semiconductor layer of the first conductivity type or the second conductivity type having a lower first conductivity type impurity concentration than the second semiconductor layer by diffusing the second conductivity type impurity contained in the tenth semiconductor layer into the second semiconductor layer in which the tenth semiconductor layer is formed; A method for manufacturing a semiconductor device.

Images