Semiconductor device

Abstract

To provide a semiconductor device capable of reducing an oscillation amplitude of a voltage at the time of switching.SOLUTION: A semiconductor device according to an embodiment includes: a semiconductor substrate having a first main surface and a second main surface opposed to a first main surface in a first direction; a drift region; a buffer region having a plurality of concentration peaks in the first direction; a first electrode provided on the first main surface; a second electrode provided on the second main surface; and a transistor region in which a transistor having the first electrode as a collector electrode and the second electrode as an emitter electrode is formed. The plurality of concentration peaks includes a first concentration peak closest to the second main surface, a second concentration peak that is farther from the second main surface than the first concentration peak and has an impurity concentration higher than an impurity concentration of the first concentration peak, and a third concentration peak that is selectively provided between the first main surface and the second concentration peak in a plane intersecting the first direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art In semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), a structure is known in which a buffer region having a higher impurity concentration than the drift layer is provided between the drift layer and the collector electrode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6508372 [Patent Document 2] Patent No. 6144510 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device capable of reducing the oscillation amplitude of voltage during switching. [Means for solving the problem]

[0005] a first electrode provided on the first main surface; a second electrode provided on the second main surface; and a transistor region in which a transistor is formed, the transistor having the first electrode as a collector electrode and the second electrode as an emitter electrode. The plurality of concentration peaks include a first concentration peak closest to the second main surface, a second concentration peak farther from the second main surface than the first concentration peak and having an impurity concentration higher than the impurity concentration of the first concentration peak, and a third concentration peak selectively provided between the first main surface and the second concentration peak in a plane intersecting the first direction. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view of a semiconductor device 1 according to a first embodiment. [Figure 2A] FIG. 2 is a diagram showing the impurity concentration distribution along the line AA′ shown in FIG. [Figure 2B] FIG. 2 is a diagram showing the impurity concentration distribution along the line BB′ shown in FIG. [Figure 3A] FIG. 2 is a diagram showing a carrier lifetime distribution along the line AA′ shown in FIG. [Figure 3B] FIG. 2 is a diagram showing a carrier lifetime distribution along the line BB′ shown in FIG. [Figure 4A] 10A and 10B are cross-sectional views illustrating the operation of the semiconductor device when it is turned off. [Figure 4B] 10A and 10B are cross-sectional views illustrating the operation of the semiconductor device when it is turned off. [Figure 4C] 10A and 10B are cross-sectional views illustrating the operation of the semiconductor device when it is turned off. [Figure 5A] 4 is a diagram showing the oscillation of a voltage waveform when the semiconductor device according to the first embodiment is turned off. FIG. [Figure 5B]4 is a diagram showing the oscillation of a voltage waveform when the semiconductor device according to the first embodiment is turned off. FIG. [Figure 5C] 4 is a diagram showing the oscillation of a voltage waveform when the semiconductor device according to the first embodiment is turned off. FIG. [Figure 6] FIG. 10 is a diagram showing the relationship between the oscillation amplitude of a voltage waveform and the third carrier lifetime. [Figure 7A] FIG. 10 is a diagram showing the impurity concentration distribution of a semiconductor device according to a first modified example of the first embodiment. [Figure 7B] FIG. 10 is a diagram showing the impurity concentration distribution of a semiconductor device according to a first modified example of the first embodiment. [Figure 8A] FIG. 10 is a diagram showing a carrier lifetime distribution of a semiconductor device according to a first modified example of the first embodiment. [Figure 8B] FIG. 10 is a diagram showing a carrier lifetime distribution of a semiconductor device according to a first modified example of the first embodiment. [Figure 9] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 10] FIG. 10 is a diagram showing the impurity concentration distribution of the semiconductor device according to the second embodiment. [Figure 11A] FIG. 10 is a top view of a semiconductor device according to a third embodiment. [Figure 11B] FIG. 10 is a top view of a semiconductor device according to a third embodiment. [Figure 12] FIG. 10 is a top view of a semiconductor device according to a fourth embodiment. [Figure 13] FIG. 10 is a top view of a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0008] The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing.

[0009] For example, in the cross-sectional views shown in the present specification, some laminated structures are shown, but the thickness ratio of each layer in the laminated structure is not necessarily the same as that in reality. Even if one layer is shown thicker than another layer in the cross-sectional view, in reality, the thicknesses of one layer and the other layer may be approximately the same, or one layer may be thinner than the other layer. In other words, the dimensions such as thicknesses shown in the drawings in the present specification may differ from the actual dimensions.

[0010] In the following description, n + , n, n - and p + , p, p - The notation indicates the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + shape, n - The shape is simply n-type, p-type + shape, p - The shape is sometimes simply referred to as p-shape.

[0011] The direction from the first electrode 41 to the second electrode 42 is referred to as the Z direction (first direction). The direction perpendicular to the Z direction is referred to as the X direction (second direction), and the direction intersecting the X and Z directions is referred to as the Y direction (third direction). The semiconductor device 1 shown in FIG. 2 is a cross-sectional view taken along the XZ plane. Note that although the X, Y, and Z directions are shown orthogonal to each other in this embodiment, they are not limited to being orthogonal, and may intersect with each other. For ease of explanation, the positive direction of the Z direction is referred to as "up," and the negative direction of the Z direction is referred to as "down." However, the "up" and "down" directions are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0012] The length measured in the positive Z direction from the first main surface 10a is defined as the depth. That is, the farther away from the first main surface 10a in the positive Z direction, the deeper the depth. Conversely, the closer to the first main surface 10a in the positive Z direction, the shallower the depth.

[0013] In the present specification and the drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0014] (First embodiment) Fig. 1 is a cross-sectional view of a semiconductor device 1 according to a first embodiment. Fig. 2 is a diagram showing an impurity concentration distribution along line AA' shown in Fig. 1. Fig. 3 is a diagram showing an impurity concentration distribution along line BB' shown in Fig. 1.

[0015] First, a cross-sectional view of a semiconductor device 1 will be described with reference to FIG.

[0016] 1, semiconductor substrate 10 has first and second major surfaces 10a and 10b that face each other in the Z direction. Semiconductor substrate 10 has a drift region 11 of a first conductivity type and a buffer region 100 of the first conductivity type provided between drift region 11 and first major surface 10a. Buffer region 100 has regions R1, R2, R3, and R4. Regions R1 to R4 will be described later with reference to FIGS. 2 and 3.

[0017] The drift region 11 is, for example, an n-type drift region, and the buffer region 100 is, for example, an n-type buffer region.

[0018] A first electrode 41 is provided below the first major surface 10a. A second electrode 42 is provided on a second major surface 10b opposite to the first major surface 10a. The first electrode 41 and the second electrode 42 are made of a metal containing, for example, Al.

[0019] The semiconductor device 1 has a transistor region 50 in which a transistor is provided and a diode region 60 in which a diode is provided. The transistor provided in the transistor region 50 controls a current flowing between the first electrode 41 and the second electrode 42, with the first electrode 41 as a collector electrode and the second electrode 42 as an emitter electrode. The diode provided in the diode region 60 has the first electrode 41 as a cathode electrode and the second electrode 42 as an anode electrode, has a rectifying effect, and causes a current to flow from the second electrode 42 to the first electrode 41. The transistor region 50 and the diode region 60 are provided adjacent to each other, for example. Below, an example will be described in which the semiconductor device 1 has an RCIGBT (Reverse Conductive Insulated Gate Bipolar Transistor).

[0020] First, the transistor region 50 will be described. In the transistor region 50, the buffer region 100 has, in order of depth, a first region R1, a second region R2, and a third region R3. Furthermore, the transistor region 50 has a first semiconductor region 21 of the second conductivity type between the buffer region 100 and the first electrode 41.

[0021] The semiconductor device also includes a second semiconductor region 22 of the second conductivity type provided between the drift region 11 and the second electrode 42 and a third semiconductor region 23 of the first conductivity type selectively provided on the second semiconductor region 22.

[0022] A gate insulating film 32 is provided from the second main surface 10b to a position reaching the drift region 11 so as to be in contact with the second semiconductor region 22. The gate electrode 31 is covered with the gate insulating film 32. The gate electrode 31 and the second semiconductor region 22 face each other with the gate insulating film 32 interposed therebetween. An interlayer insulating film 33 is provided between the gate electrode 31 and the second electrode 42. The gate electrode 31 and the second electrode 42 are electrically insulated by the interlayer insulating film 33.

[0023] In the transistor region 50, the first electrode 41 is, for example, a collector electrode, and the second electrode 42 is, for example, an emitter electrode. + The second semiconductor region 22 is a p-type collector region, and the third semiconductor region 23 is an n-type base region. + The emitter area is of the shape.

[0024] Next, the diode region 60 will be described. The diode region 60 functions as, for example, an FWD (Free Wheeling Diode) for the transistor region 50. The diode region 60 has a drift region 11 and a buffer region 100. The buffer region 100 has, in order of depth, a first region R1, a second region R2, and a fourth region R4. The impurity concentration distribution of the fourth region R4 is different from the impurity concentration distribution of the third region R3 of the transistor region 50.

[0025] In the diode region 60, a fourth semiconductor region 24 of the first conductivity type is provided between the first electrode 41 and the buffer region 100. The fourth semiconductor region 24 is, for example, an n + The cathode region is shaped like a cathode.

[0026] A second semiconductor region 22 is provided on the drift region 11. The second semiconductor region 22 is, for example, a p-type anode region. The second semiconductor region 22 of the transistor region 50 and the diode region 60 may be formed in the same process. Furthermore, impurities may be further implanted into the second semiconductor region 22 of the diode region 60, so that the second semiconductor region 22 has a higher impurity concentration than the second semiconductor region 22 of the transistor region 50.

[0027] While FIG. 1 shows an example in which the third semiconductor region 23 is not formed in the diode region 60, the third semiconductor region 23 may be formed in the diode region 60 with the same structure as the transistor region 50.

[0028] In the diode region 60, the first electrode 41 is a cathode electrode of the diode, and the second electrode 42 is an anode electrode of the diode. By setting the second electrode 42 at a higher potential than the first electrode 41, a current can flow from the second electrode 42 to the first electrode 41.

[0029] Next, the operation of the semiconductor device 1 will be described.

[0030] First, a positive voltage is applied to the first electrode 41 with respect to the second electrode 42. Next, the voltage applied to the gate electrode 31 in the transistor region 50 is controlled. When the voltage applied to the gate electrode 31 exceeds the threshold voltage, an inversion layer is generated in the second semiconductor region 22 near the gate insulating film 32.

[0031] Electrons can flow from the second electrode 42 of the transistor region 50 to the first electrode 41 through the inversion layer, turning the transistor region 50 into an on state. Note that when the transistor region 50 is in an on state, the first semiconductor region 21 is, for example, a p-type semiconductor region, and holes are injected from the first semiconductor region 21 into the drift region 11.

[0032] Subsequently, when the voltage applied to the gate electrode 31 is controlled to be lower than the threshold voltage, the inversion layer in the second semiconductor region 22 near the gate insulating film 32 disappears, and the transistor region 50 is turned off. That is, in the transistor region 50, by controlling the potential of the gate electrode 31, the on and off states of the transistor formed in the transistor region 50 can be controlled.

[0033] Next, the operation of the diode region 60 will be described. When a positive voltage of a certain level or higher is applied to the second electrode 42 with the first electrode 41 as the reference, the diode region 60 passes a current from the second electrode 42 to the first electrode 41, turning on. Therefore, the diode region 60 can function as a FWD that passes a reverse current that occurs when an inductive load is connected, such as when the transistor region 50 is turned off.

[0034] Subsequently, when the potential of the second electrode 42 relative to the first electrode 41 in the diode region 60 decreases, the diode enters a recovery operation in which it transitions to an off state. Carriers remain in the semiconductor substrate 10 of the diode region 60, which was flowing a reverse current, and a tail current flows that discharges the carriers during recovery. When the tail current flows and the recovery operation is completed, switching of the semiconductor device 1 is completed. The operation of the diode region 60 during switching will be described in detail later with reference to FIGS. 6 and 7.

[0035] The cross-sectional view of the semiconductor device 1 according to the first embodiment has been described above with reference to FIG.

[0036] Next, the structure of the buffer region 100 will be described with reference to FIG. 2. FIG. 2A is a diagram showing an example of an impurity concentration distribution along line AA′ shown in FIG. 1. FIG. 2B is a diagram showing an example of an impurity concentration distribution along line BB′ shown in FIG. 1. Here, the impurity concentration distribution is measured by, for example, SRA (Spreading Resistance Analysis). Furthermore, the concentration distribution may be smoothed by, for example, a moving average, if necessary.

[0037] 2A, the impurity concentration distribution along line AA' will be described. Line AA' traverses the buffer region 100 formed in the transistor region 50 of the semiconductor substrate 10.

[0038] 2, the horizontal axis represents the distance (hereinafter referred to as depth) from the first main surface 10a of the semiconductor substrate 10. The vertical axis represents the impurity concentration of the semiconductor substrate 10. Here, the impurity concentration shown on the vertical axis represents the concentration of carriers generated by activation of the implanted impurities.

[0039] The impurity concentration distribution along line AA′ has at least three concentration peaks: a first concentration peak 101, a second concentration peak 102, and a third concentration peak 103. The first region R1 of the buffer region 100 has the first concentration peak 101. The second region R2 has the second concentration peak 102. The third region R3 has the third concentration peak 103.

[0040] Here, the peak of the impurity concentration distribution can be defined as the maximum value of the distribution obtained by smoothing the concentration distribution of impurities implanted and activated in the semiconductor substrate 10 in the Z direction, which is the thickness direction of the semiconductor substrate 10. Here, smoothing includes, for example, means such as calculating a moving average.

[0041] The drift region 11 is located deeper than the buffer region 100, and the drift region 11 has, for example, a flat impurity concentration distribution. Here, the flat impurity concentration of a certain region can be defined, for example, by the minimum and maximum values ​​of the impurity concentration distribution within the region. For example, a region is defined as flat when the maximum value of the impurity concentration after smoothing is less than 1.5 times the minimum value. Conversely, when the maximum value of the impurity concentration after smoothing is 1.5 times or more the minimum value, the region is said to have an impurity concentration peak.

[0042] The first concentration peak 101 is formed deeper than the second concentration peak 102. The second concentration peak 102 is formed deeper than the third concentration peak 103.

[0043] The first concentration peak 101 and the second concentration peak 102 are formed by, for example, protons and have n-type conductivity. The first concentration peak 101 and the second concentration peak 102 are formed by, for example, implanting impurities from the first main surface 10a and performing annealing.

[0044] The annealing temperature for diffusing protons is, for example, 300° C. or higher and 500° C. or lower. The annealing temperature for diffusing protons may desirably be 380° C. or higher and 400° C. or lower. The annealing is performed by, for example, hydrogen plasma annealing.

[0045] The first concentration peak 101 is formed at a depth of 10 μm or more and 30 μm or less, measured from the first major surface 10a toward the second major surface 10b, for example. By making the depth of the first concentration peak 101 10 μm or more, the buffer region 100 gently suppresses the expansion of the depletion layer and suppresses oscillation of the voltage waveform. Furthermore, by making the depth of the first concentration peak 101 30 μm or less, the depletion layer easily expands in the semiconductor substrate 10, thereby maintaining the breakdown voltage. Making the depth of the first concentration peak 101 20 μm or less is desirable because it further improves the breakdown voltage. The depth of the first concentration peak 101 is preferably 10 μm or more and 20 μm or less.

[0046] The impurity concentration of the first concentration peak 101 is lower than the impurity concentration of the second concentration peak 102. The first concentration peak 101 and the second concentration peak 102 suppress the expansion of the depletion layer in the direction from A to A'. By making the impurity concentration of the first concentration peak 101 lower than the impurity concentration of the second concentration peak 102, the expansion of the depletion layer can be made gentler, which is desirable, thereby making it possible to further stabilize the voltage waveform during switching.

[0047] In order to make the depletion layer spread slowly and ensure the breakdown voltage, the first concentration peak 101 is set to, for example, 1.0×10 14 cm ―3 Over 1.0 x 10 15 cm ―3The second concentration peak 102 has an impurity concentration of, for example, 1.0×10 15 cm ―3 Over 1.0 x 10 17 cm ―3 It has the following impurity concentrations:

[0048] The third concentration peak 103 is formed by, for example, protons. The third concentration peak 103 has, for example, an n-type conductivity. The depth of the third concentration peak 103 is, for example, greater than 0 μm and equal to or less than 10 μm.

[0049] The third concentration peak 103 has, for example, a lower impurity concentration than the second concentration peak 102. It is desirable for the third concentration peak to have a lower impurity concentration and for the amount of impurity implanted to form the third concentration peak 103 to be smaller in order to improve the efficiency of impurity implantation.

[0050] The impurity concentration distribution along the line AA' in Fig. 1 has been described above with reference to Fig. 2A. Next, the impurity concentration distribution along the line BB' in Fig. 1 will be described with reference to Fig. 2B.

[0051] 2B is a diagram showing the impurity concentration distribution along line BB' shown in FIG. 1. Line BB' cuts the buffer region 100 in the diode region 60 in the Z direction. Along line BB', there are at least a first concentration peak 101 and a second concentration peak 102. The first concentration peak 101 is formed at a deeper position than the second concentration peak 102.

[0052] In the diode region 60, the first region R1 has a first concentration peak 101. The second region R2 has a second concentration peak 102. The impurity concentration distributions of the first region R1 and the second region R2 may be the same as the impurity concentration distributions of the first region R1 and the second region R2 of the transistor region 50 shown in FIG.

[0053] The fourth region R4 has, for example, a flat impurity concentration distribution.

[0054] The first concentration peak 101 shown in Fig. 2B is formed, for example, by the same process as the first concentration peak 101 shown in Fig. 2A. The second concentration peak 102 shown in Fig. 2B is formed, for example, by the same process as the second concentration peak 102 shown in Fig. 2A. Forming at least a portion of the buffer regions of the transistor region 50 and the diode region 60 in the same process is desirable because it improves manufacturing efficiency.

[0055] Next, the distribution of carrier lifetime will be described with reference to FIG. 3. Hereinafter, the carrier lifetime is measured, for example, by the μ-PCD (Photo Conductive Decay) method. However, it is not necessary to obtain the continuous profile shown in FIG. 3; carrier lifetimes may be measured discretely in the depth direction and compared. FIG. 3A is a schematic diagram of the distribution of carrier lifetimes along line AA′ in FIG. 1. FIG. 3B is a schematic diagram of the distribution of carrier lifetimes along line BB′ in FIG. 1.

[0056] First, the entire surface of the semiconductor substrate 10 is irradiated with an electron beam, for example, to form crystal defects across the first region R1, the second region R2, the third region R3, the fourth region R4, and the drift region 11. The formed crystal defects promote carrier recombination, thereby uniformly reducing the carrier lifetime. The formed crystal defects can be repaired, for example, by proton injection. Next, the crystal defects are repaired, and the carrier lifetime is locally restored, for example, by injecting protons.

[0057] That is, by irradiating the electron beam, the carrier lifetime is reduced in the first region R1, the second region R2, the third region R3, and the fourth region R4, and then impurities such as protons are injected to restore the carrier lifetime, thereby obtaining the lifetime distribution shown in Figures 3A and 3B.

[0058] First, let us consider Figure 3A. In the distribution of carrier lifetimes shown in Figure 3A, the carrier lifetimes are restored at positions corresponding to a first concentration peak 101, a second concentration peak 102, and a third concentration peak 103 formed by implanting protons, for example.

[0059] The representative value of the carrier lifetime in the first region R1 is called the first carrier lifetime LT1. The representative value of the carrier lifetime in the second region R2 is called the second carrier lifetime LT2. The representative value of the carrier lifetime in the third region R3 is called the third carrier lifetime LT3. The representative value may be defined, for example, as the average value of the carrier lifetime in each region. Here, the average value is the average of the carrier lifetimes measured at two or more points in each region. Note that the carrier lifetime measured at one point in each region may also be used as the representative value. The same applies to the fourth carrier lifetime LT4 described below.

[0060] The second carrier lifetime LT2 is longer than the first carrier lifetime LT1 and the third carrier lifetime LT3. The first carrier lifetime LT1 and the second carrier lifetime LT2 are longer than the carrier lifetimes in the drift region 11.

[0061] Next, with reference to Fig. 3B, a schematic diagram of the distribution of carrier lifetimes along line BB' in Fig. 1 will be described. Fig. 3B illustrates drift region 11, first region R1, second region R2, and fourth region R4.

[0062] 3B, the representative value of the carrier lifetime in the fourth region R4 is referred to as the fourth carrier lifetime LT4. The fourth carrier lifetime LT4 is shorter than the first carrier lifetime LT1 in the first region R1 and the second carrier lifetime LT2 in the second region R2. The fourth carrier lifetime LT4 is shorter than the carrier lifetime in the drift region 11.

[0063] 2, when impurities are implanted from the first main surface 10a, defects occur in the crystal lattice due to the passing impurities at positions closer to the first main surface 10a than the second concentration peak 102. The resulting crystal defects promote carrier recombination, thereby reducing the carrier lifetime in the region through which the impurities have passed.

[0064] Impurities implanted from first main surface 10a to form first concentration peak 101 and second concentration peak 102 pass through fourth region R4. The passage of the impurities causes defects in the crystal of fourth region R4, reducing fourth carrier lifetime LT4. On the other hand, in third region R3 shown in FIG. 3A, the carrier lifetime is restored with the formation of third concentration peak 103. Therefore, in fourth region R4 shown in FIG. 3B, crystal defects are not repaired, and fourth region R4 has a fourth carrier lifetime LT4 that is shorter than the third carrier lifetime LT3 of third region R3 shown in FIG. 3A.

[0065] The carrier lifetime distribution in the first region R1 and the second region R2 of the diode region 60 may be the same as the carrier lifetime distribution in the first region R1 and the second region R2 of the transistor region 50 shown in, for example, FIG. 3A. The third concentration peak 103 is selectively provided in the XY plane between the first main surface 10a of the semiconductor substrate 10 and the second concentration peak 102 of the buffer region 100. That is, in the XY plane, a portion having the third concentration peak 103 (e.g., the third region R3) and a portion not having the third concentration peak 103 (e.g., the fourth region R4) are provided. The impurity concentration distribution and the carrier lifetime distribution have been described above with reference to FIGS. 2 and 3.

[0066] Next, with reference to FIG. 4, the switching operation of the semiconductor device 1 will be described in detail in association with the carrier lifetime distribution. FIG. 4 is a cross-sectional view showing the behavior of carriers when the transistor region 50 is turned off. FIG. 4A is a schematic diagram showing carriers (electrons e and holes h) remaining in the drift region 11. FIG. 4B is a schematic diagram showing the expansion of the depletion layer indicated by the dotted line. FIG. 4C is a schematic diagram showing the disappearance of remaining carriers while holes are injected from the first semiconductor region 21 into the diode region 60.

[0067] When the semiconductor device 1 is switched, for example, when the transistor region 50 is turned off, electrons and holes remain in the drift region 11 as shown in FIG. 4A. The electrons and holes remaining in the drift region 11 are carriers that were carrying current in the transistor region 50 and the diode region 60. To complete the turn-off operation of the semiconductor device 1 (including the recovery operation of the diode region 60), the electrons and holes must be discharged from the first electrode 41 or the second electrode 42, or the electrons and holes must disappear due to recombination.

[0068] As carriers are lost from drift region 11, the depletion layer expands in the direction indicated by the arrow in Fig. 4B. The depletion layer expands in drift region 11 from second major surface 10b toward first major surface 10a, and when carriers are discharged from drift region 11, the depletion layer reaches buffer region 100.

[0069] At least a part of the buffer region 100 has a higher impurity concentration than the drift region 11. Therefore, when the depletion layer reaches the buffer region 100, the expansion of the depletion layer becomes gentler.

[0070] 2 is lower than the impurity concentration of the second concentration peak 102, the depletion layer can be more gradually expanded toward the first major surface 10a. In this case, the gradual expansion of the depletion layer refers to gradually suppressing the expansion of the depletion layer by gradually increasing the impurity concentration from the second major surface 10b toward the first major surface 10a.

[0071] When the depletion layer reaches the buffer region 100, the carriers remaining between the depletion layer and the first major surface 10a are called residual carriers. The current flowing due to the discharged residual carriers is called a tail current.

[0072] The shorter the carrier lifetime of the residual carriers, the shorter the time it takes for the residual carriers to recombine. In other words, the time the tail current flows is shorter, making it possible to reduce switching loss. On the other hand, the shorter the carrier lifetime of the residual carriers, the more rapidly the residual carriers recombine, causing the depletion layer to rapidly expand toward the first main surface 10a, which may cause the voltage waveform during switching to become unstable and promote voltage oscillation.

[0073] On the other hand, the longer the carrier lifetime of the residual carriers, the slower the recombination of the residual carriers. Because the residual carriers recombine slowly, the tail current flows for a longer period of time than when the carrier lifetime is short, but the sudden recombination of carriers does not occur.

[0074] 4A, 4B, and 4C, the lifetime is restored in the third region R3 of the buffer region 100 (see FIG. 3A). Therefore, between FIG. 4B and FIG. 4C, the recombination of residual carriers in the transistor region 50 progresses more slowly in the third region R3 than in, for example, the fourth region R4.

[0075] The remaining carriers shown in the diode region 60 disappear due to recombination etc. from Figure 4B to Figure 4C. In the fourth region R4, the carrier lifetime is not restored as shown in Figure 3B, and the disappearance of carriers progresses more rapidly than in, for example, the third region R3.

[0076] 4C, holes are injected from the first semiconductor region 21 (p-type) of the transistor region 50 adjacent to the diode region 60 to compensate for the remaining carriers reduced by recombination. Here, the injection of holes is promoted as the n-type impurity concentration of the third region R3 decreases. This is because the recombination between holes flowing into the diode region 60 via the third region R3 and electrons in the third region R3 is suppressed.

[0077] That is, although the fourth carrier lifetime LT4 in the diode region 60 is shorter than the third carrier lifetime LT3 in the transistor region 50, the injection of carriers from the first semiconductor region 21 suppresses the rapid disappearance of remaining carriers in the diode region 60.

[0078] Next, the relationship between the carrier lifetime and the oscillation amplitude of the voltage waveform will be explained with reference to Figures 5 and 6. Figures 5A, 5B, and 5C show simulated voltage waveforms when the third carrier lifetime LT3 is 0.01 μs, 0.1 μs, and 10 μs, respectively. The horizontal axis represents time. The vertical axis represents the potential difference between the first electrode 41 and the second electrode 42. The vertical axis represents, for example, the collector-emitter voltage of an IGBT.

[0079] First, Figure 5A shows the case where LT3 = 0.01 μs. It shows how the voltage converges to V0 after switching. Here, V0 is the power supply voltage, for example 600 V. During the tail period when the tail current flows, residual carriers continue to be discharged, causing the voltage waveform to oscillate. When focusing on the behavior of the tail current due to residual carriers, the voltage waveform during the tail period is used to evaluate the oscillation amplitude.

[0080] The magnitude of the oscillation amplitude is evaluated based on the oscillation pattern of the voltage waveform as follows. The difference between the maximum and minimum values ​​of the oscillating voltage waveform during the tail period is divided by the power supply voltage. In other words, the larger the value (Vmax - Vmin) / V0 obtained by subtracting the minimum value Vmin from the maximum value Vmax in Figure 5A and dividing the result by V0, the larger the oscillation amplitude of the voltage waveform. In the following, when we say that the oscillation amplitude is large, we mean that (Vmax - Vmin) / V0 is large for the voltage waveform during the tail period.

[0081] Figure 5B shows the case where LT3 = 0.1 μs. That is, it shows a case where the carrier lifetime recovery amount in the third region R3 is greater than that shown in Figure 5A. In Figure 5B, the value of Vmax - Vmin is smaller than that shown in Figure 5A, and the oscillation amplitude of the voltage waveform shown in Figure 5B is smaller than that of the voltage waveform shown in Figure 5A. In other words, when LT3 = 0.1 μs, voltage oscillation in the tail period can be suppressed more effectively than when LT3 = 0.01 μs.

[0082] Figure 5C shows the voltage waveform when LT3 is further increased to LT3 = 10 μs. The oscillation amplitude of the voltage waveform in Figure 5C is smaller than that of the voltage waveform shown in Figure 5A. However, compared to the difference in oscillation amplitude between Figures 5A and 5B, the difference in oscillation amplitude between Figures 5B and 5C is not as significant.

[0083] The relationship between the third carrier lifetime LT3 and oscillation amplitude in Figures 5A, 5B, and 5C explained above is summarized in Figure 6. Figure 6 also includes the results for LT3 = 0.001 μs, which was not shown in Figure 5. The horizontal axis represents the first carrier lifetime LT1 on a log scale, and the vertical axis represents the oscillation amplitude as a percentage.

[0084] 6, the longer the third carrier lifetime LT3, the smaller the oscillation amplitude. That is, the more impurities such as protons are injected into the third region R3 to repair crystal defects, the more the oscillation amplitude can be reduced.

[0085] The carrier lifetime before the third carrier lifetime LT3 in the third region R3 is restored is, for example, shorter than 0.001 μs. The fourth carrier lifetime LT4 in the fourth region R4 of the diode region 60 is, for example, shorter than 0.001 μs. That is, the oscillation amplitude without the carrier lifetime restoration is greater than 120%.

[0086] By controlling the third carrier lifetime LT3 to be restored to 0.001 μs or more, the oscillation amplitude can be reduced to 120% or less.

[0087] Furthermore, by setting the third carrier lifetime LT3 to 0.01 μs or more, the oscillation amplitude can be reduced to 60%.

[0088] The slope of the approximation line shown in Figure 6, i.e., the rate of decrease in oscillation amplitude, differs between the range of LT3<0.1 μs and the range of LT3≧0.1 μs. The rate of decrease in oscillation amplitude is greater in the range of LT3<0.1 μs than in the range of LT3≧0.1 μs. In the range of LT3≧0.1 μs, the decrease in oscillation amplitude approaches saturation. By setting LT3 to 0.1 μs or more, the decrease in oscillation amplitude approaches saturation, and the oscillation amplitude can be sufficiently reduced. Furthermore, by setting LT3≧1 μs, the oscillation amplitude can be further reduced.

[0089] The third carrier lifetime LT3 is, for example, 100 μs or less in order to prevent switching loss from increasing, but may also be LT3≦50 μs or LT3≦10 μs.

[0090] In order to reduce the oscillation amplitude, the third carrier lifetime LT3 is, for example, 0.001 μs≦LT3≦100 μs, and preferably 0.1 μs≦LT3≦10 μs.

[0091] The carrier lifetime in the drift region 11 is typically several tens of μs, for example, about 10 μs. Here, the carrier lifetime in the drift region 11 is, for example, an average calculated within the region. The third carrier lifetime LT3 is, for example, 1 / 1000 times or more the carrier lifetime of the drift region 11. Preferably, it is 1 / 100 times or more the carrier lifetime of the drift region 11. More preferably, it is 1 / 10 times or more the carrier lifetime of the drift region 11.

[0092] 2A repairs crystal defects with the impurities contained in the third concentration peak 103, thereby restoring the third carrier lifetime LT3. Here, the total implantation amount Tin for the third concentration peak 103 is defined as follows: The impurity concentration values ​​are integrated from a depth corresponding to the minimum located between the second concentration peak 102 and the third concentration peak 103 in the impurity concentration distribution to the first main surface 10a, with the flat impurity concentration in the drift region 11 as the reference. The concentration per unit area in the XY plane obtained by the integration is regarded as the amount of impurities implanted to form the third concentration peak 103, and is defined as the total implantation amount Tin.

[0093] In order to recover the third carrier lifetime LT3 and reduce the oscillation amplitude, for example, the total injection amount Tin is 1×10 11 cm ―2 That's it, 1×10 16 cm ―2 It is less than 1 × 10 per unit area. 11 cm ―2 By implanting the above impurity concentration, the lifetime can be sufficiently restored. 16 cm ―2 Damage to the wafer can be suppressed by limiting the amount of impurities to the following: To satisfy LT3 ≥ 0.1 μs, the total implantation amount Tin must be 8 × 10 11 cm ―2 That's it, 1×10 16 cm ―2 To further reduce damage to the wafer, the total implantation dose Tin is preferably 1×10 14cm ―2 It is desirable that the following:

[0094] When the spread of the impurity concentration centered on the third concentration peak 103 is located over a depth of approximately 0 μm to 10 μm, the total implantation amount Tin is 1×10 11 cm ―2 Therefore, even if we assume a flat concentration distribution over the depth range of 0 μm to 10 μm, the concentration is 1×10 14 cm ―3 The impurity concentration of the third concentration peak 103 is higher than that of the surrounding area, so the impurity concentration of the third concentration peak 103 is 1×10 14 cm ―3 In order to recover the lifetime, the impurity concentration of the third concentration peak 103 is preferably 8×10 14 cm ―3 That's all.

[0095] The impurity concentration of the third concentration peak 103 is, for example, lower than the impurity concentration of the second concentration peak 102. In order to suppress damage to the wafer, the total implantation amount Tin is, for example, 1×10 14 cm ―2 The impurity concentration of the third concentration peak 103 is 1×10 17 cm ―3 The third concentration peak 103 is preferably a lower impurity concentration in order to suppress damage to the wafer, provided that the amount of impurities is sufficient to restore the third carrier lifetime LT3.

[0096] The semiconductor device 1 according to this embodiment includes a buffer region 100 having different impurity concentration distributions in the transistor region 50 and the diode region 60, and the third carrier lifetime LT3 is greater than the fourth carrier lifetime LT4. By suppressing the rapid loss of carriers, the oscillation amplitude of the voltage waveform during switching can be reduced. When the third carrier lifetime LT3 is, for example, 0.01 μs≦LT3≦100 μs, the oscillation amplitude can be further reduced.

[0097] Generally, there is a trade-off between reducing oscillation amplitude and reducing switching loss in terms of carrier lifetime. If the buffer region 100 is shared by the transistor region 50 and the diode region 60, it becomes necessary to prioritize either reducing oscillation amplitude or reducing switching loss over the other. For example, if lifetime recovery is performed uniformly in both the transistor region and the diode region, the switching time may become longer, which may increase switching loss.

[0098] According to the semiconductor device 1 of this embodiment, the trade-off between reduced oscillation amplitude and reduced switching loss can be improved by prioritizing the reduction of oscillation amplitude in some parts of the semiconductor device and the reduction of switching loss in other parts.

[0099] In the transistor region 50, the carrier lifetime is restored in the third region R3, thereby suppressing oscillation of the voltage waveform. The fourth carrier lifetime LT4 in the fourth region R4 of the diode region 60 is shorter than the third carrier lifetime LT3 of the transistor region 50, which promotes carrier recombination in the diode region 60, shortens the switching time, and enables to reduce switching loss. On the other hand, when the transistor region 50 and the diode region 60 are adjacent to each other, it is possible to suppress oscillation of the voltage waveform by injecting holes from the transistor region 50 into the diode region 60. Therefore, it is possible to reduce switching loss and oscillation amplitude.

[0100] When different buffer regions 100 are provided for the transistor region 50 and the diode region 60, it is desirable from the viewpoint of manufacturing efficiency to manufacture the common structure in the same process. According to the present embodiment shown in Fig. 1, the first region R1 and the second region R2 of the buffer region 100 have a common structure, and it is possible to form the transistor region 50 and the diode region 60 in the same process.

[0101] The first semiconductor region 21 and the fourth semiconductor region 24 may have different conductivity types and impurity concentrations. To form the first semiconductor region 21, it is necessary to mask the diode region 60 and implant impurities into the transistor region 50. The third region R3 can be selectively formed in the transistor region 50 within the XY plane using a mask provided in the step of masking the diode region 60 to form the first semiconductor region 21.

[0102] Furthermore, the second concentration peak 102 is, for example, 1.0×10 15 cm ―3 Over 1.0 x 10 17 cm ―3 The second region R2 has an impurity concentration below 102, which is higher than the first concentration peak 101 and the third concentration peak 103. The second concentration peak 102 stops the expansion of the depletion layer during switching in the second region R2, thereby making it possible to further stabilize the switching operation.

[0103] (Modification of the first embodiment) Next, a modified example of the first embodiment will be described with reference to Figures 7 and 8. Figure 7A shows the impurity concentration distribution along line AA' shown in Figure 1. Figure 7B shows the impurity concentration distribution along line BB' in Figure 1. Figure 8A shows the carrier lifetime distribution along line AA' shown in Figure 1. Figure 8B shows the carrier lifetime distribution along line BB' in Figure 1. Some descriptions of parts common to the first embodiment will be omitted.

[0104] In the first embodiment, control is performed to selectively restore the lifetime of the third region R3 of the transistor region 50, while in this modified example, control is performed to selectively restore the lifetime of the fourth region R4 of the diode region 60.

[0105] First, referring to FIG. 7A, the impurity concentration distribution of this modification along line A-A' in the transistor region 50 shown in FIG. 1 will be described. The first region R1 has a first concentration peak 101. The second region R2 has a second concentration peak 102. The third region R3 has, for example, a flat impurity concentration distribution. The impurity concentration distribution along line AA' in this modification is, for example, the same as the impurity concentration distribution shown in FIG. 2B.

[0106] Next, with reference to FIG. 7B, the impurity concentration distribution of this modification along line BB' in diode region 60 shown in FIG. 1 will be described. The first region R1 has a first concentration peak 101. The second region R2 has a second concentration peak 102. The fourth region R4 has a third concentration peak 103.

[0107] In this modification, the impurity concentration of the fourth region R4 of the diode region 60 is higher than the impurity concentration of the third region R3 of the transistor region 50 at the depth where the third concentration peak 103 is formed in the fourth region R4.

[0108] Next, with reference to Figure 8A, the carrier lifetime distribution of this modification along line AA' in the transistor region 50 shown in Figure 1 will be described. The first carrier lifetime LT1 in the first region R1 and the second carrier lifetime LT2 in the second region R2 are longer than the third carrier lifetime LT3 in the third region R3. The third carrier lifetime LT3 is shorter than the carrier lifetime in the drift region 11. The carrier lifetime distribution along line A-A' in this modification may be the same as the distribution shown in Figure 3B, for example.

[0109] 8B, the carrier lifetime distribution of this modification along line BB' in the diode region 60 shown in FIG. 1 will be described. The fourth carrier lifetime LT4 in the fourth region R4 in FIG. 8B is longer than the third carrier lifetime LT3 in the third region R3 shown in FIG. 8A. The carrier lifetime distribution along line BB' in this modification may be the same as the distribution shown in FIG. 3A, for example.

[0110] According to this modification, by restoring the fourth carrier lifetime LT4 in the diode region 60, the oscillation amplitude during recovery of the diode region 60 can be further reduced.

[0111] The longer fourth carrier lifetime LT4 slows the disappearance of remaining carriers during recovery operation. In the diode region 60, the injection of carriers from the first semiconductor region 21 of the transistor region 50 suppresses the rapid disappearance of carriers, but in this modification, the control of the carrier lifetime in the fourth region R4 further slows the disappearance of carriers.

[0112] The fourth carrier lifetime LT4 may be, for example, 0.001 μs≦LT4≦100 μs, 0.01 μs≦LT4≦10 μs, or 1 μs≦LT4≦10 μs.

[0113] Furthermore, since no process for restoring the lifetime is performed in the transistor region 50, crystal defects that occur in the third region R3 when the second concentration peak 102 and the third concentration peak 103 are formed are not restored, and the third carrier lifetime LT3 is shorter than the carrier lifetime in the drift region 11. The short third carrier lifetime LT3 shortens the switching time in the transistor region 50, enabling switching losses to be reduced.

[0114] Furthermore, the impurity concentration in the third region R3 of the transistor region 50 is approximately the same as the impurity concentration in the drift region 11, and the third region R3 is, for example, 1.0×10 14 cm ―3 Compared to when an impurity concentration peak of this magnitude or larger is formed, the injection of holes from the transistor region 50 to the diode region 60 during switching is promoted. This further suppresses the rapid loss of carriers in the diode region 60, and makes it possible to reduce the oscillation amplitude.

[0115] According to this modification, it is possible to improve the trade-off between reduction in oscillation amplitude and reduction in switching loss.

[0116] In the step of injecting impurities into the fourth region R4, the impurities must be injected selectively into the diode region 60 within the XY plane, but this can be done using the mask used in the step of forming the fourth semiconductor region 24. In other words, the manufacturing process can be shortened compared to when a new mask process is performed to form the buffer region 100.

[0117] Although the first embodiment has been described using an RCIGBT as an example, the semiconductor device only needs to have at least a transistor region 50. In this case, selectively forming the third concentration peak 103 in the transistor region 50 within the XY plane can reduce switching loss and suppress voltage oscillation during switching. This is because, compared to forming the third concentration peak 103 over the entire surface of the transistor region 50, providing a wide region with a short lifetime improves switching speed and reduces switching loss. On the other hand, compared to when the third concentration peak 103 is not present in the transistor region 50, carrier loss is slowed, suppressing the oscillation amplitude of the voltage waveform. Selectively restoring the lifetime to the transistor region 50 within the XY plane can improve the trade-off between reduced oscillation amplitude and reduced switching loss.

[0118] (Second embodiment) Next, a semiconductor device 2 according to a second embodiment will be described with reference to FIG. 9. Descriptions of some parts common to the semiconductor device 1 according to the first embodiment will be omitted. FIG. 9 shows a cross-sectional view of the semiconductor device 2 according to the second embodiment. The difference from the cross-sectional view shown in FIG. 1 is the structure of the third region R3 and the fourth region R4 of the buffer region 100.

[0119] Fig. 10 is a diagram showing the impurity concentration distribution along the line A2-A2' shown in Fig. 9. The impurity concentration distribution shown in Fig. 10 has, in order of depth, a first concentration peak 101, a second concentration peak 102, a third concentration peak 103, and a fourth concentration peak 104.

[0120] The third region R3 has at least two concentration peaks including a third concentration peak 103 and a fourth concentration peak 104.

[0121] The first concentration peak 101, the second concentration peak 102, and the third concentration peak 103 are formed by implanting, for example, protons, and the fourth concentration peak 104 is formed by implanting, for example, P (phosphorus).

[0122] The fourth concentration peak 104 is formed at a depth greater than 0 μm and equal to or less than 10 μm from the first main surface 10a. The depth of the fourth concentration peak 104 is equal to or less than the depth of the third concentration peak 103.

[0123] The impurity concentration of the fourth concentration peak 104 is, for example, 1.0×10 15 cm ―3 Over 1.0 x 10 17 cm ―3 The impurity concentration of the fourth concentration peak 104 is greater than the impurity concentration of the third concentration peak 103.

[0124] The impurity concentration of the first concentration peak 101 is, for example, 1.0×10 13 cm ―3 Over 1.0 x 10 15 cm ―3 The impurity concentration of the second concentration peak 102 is, for example, 1.0×10 14 cm ―3 Over 1.0 x 10 16 cm ―3 The impurity concentration of the third concentration peak 103 is, for example, 1.0×10 13 cm ―3 Over 1.0 x 10 15 cm ―3 The following is the result.

[0125] It is desirable to form the fourth concentration peak 104 in common with the fourth region R4 of the diode region 60 in order to improve manufacturing efficiency.

[0126] Furthermore, although FIG. 10 illustrates an example in which the third concentration peak 103 is formed in the transistor region 50, the third concentration peak 103 and the fourth concentration peak 104 may be formed in the diode region 60, as in the first modified example of the first embodiment.

[0127] In the semiconductor device 2 according to this embodiment, the buffer region 100 has the fourth concentration peak 104, which further prevents the depletion layer from reaching the first main surface 10a. Since the depletion layer is stopped at a position where it does not exceed the fourth concentration peak 104, the semiconductor device 2 has a stable voltage waveform during switching, and the switching characteristics can be improved.

[0128] Because the fourth concentration peak 104 can more reliably stop the depletion layer, the impurity concentrations of the first concentration peak 101 and the second concentration peak 102 can be made smaller than those of the semiconductor device 1 according to the first embodiment. Therefore, the amount of implantation of impurities such as protons required to form the first concentration peak 101 and the second concentration peak 102 can be reduced. In other words, the efficiency of impurity implantation can be improved.

[0129] The fourth concentration peak 104 can be a P (phosphorus) buffer. Generally, a P (phosphorus) buffer may require annealing at a temperature equal to or higher than the melting point of Al to diffuse the P (phosphorus). The structure on the first principal surface 10a side may be formed after the structure on the second principal surface 10b side, and high-temperature annealing may damage the structure already formed on the second principal surface 10b side. For example, an electrode containing Al may melt.

[0130] However, according to this embodiment, the P (phosphorus) buffer is distributed only near the first main surface 10a, and it is possible to perform annealing only near the first main surface 10a by, for example, irradiating a laser to heat it. Therefore, it is possible to prevent the influence of heat from reaching the second main surface 10b side during the annealing process for forming the fourth concentration peak 104. The P (phosphorus) buffer can be formed without damaging the structure on the second main surface 10b side.

[0131] Compared to forming the fourth concentration peak 104 with protons, forming it with P (phosphorus) eliminates the need to add a proton treatment step compared to the first embodiment. Therefore, the processing efficiency of proton injection can be improved compared to forming all concentration peaks by proton injection.

[0132] (Third embodiment) 11A shows a schematic top view of a semiconductor device 3 according to the third embodiment. A plurality of transistor regions 50 and a plurality of diode regions 60 are formed. The regions surrounded by dotted lines are the diode regions 60. FIG. 11A shows an example in which the transistor regions 50 and the diode regions 60 are arranged side by side in the X direction and extend in the Y direction.

[0133] First, the definition of the lifetime recovery region LTU will be explained. The lifetime recovery region LTU is a region where the third concentration peak 103 is selectively formed in the XY plane. The lifetime recovery region LTU has at least one impurity concentration peak between the second region R2 and the first main surface 10a, and the carrier lifetime is recovered. For example, in the semiconductor device 1 according to the first embodiment, the transistor region 50 corresponds to the lifetime recovery region LTU as shown in FIGS. 3A and 3B.

[0134] 11A, among a plurality of transistor regions 50 provided in the X direction, portions having lifetime recovery regions LTU are selectively provided. For example, the transistor regions 50 having lifetime recovery regions LTU are periodically arranged. FIG. 11 shows an example in which two rows of diode regions 60 are formed between the lifetime recovery regions LTU adjacent to each other in the X direction, and one row of transistor regions 50 is formed between the two rows of diode regions 60.

[0135] The semiconductor device 3 according to this embodiment can reduce switching loss at turn-off compared to when the lifetime recovery region LTU is formed over the entire transistor region 50. Lifetime recovery is not performed in at least a portion of the transistor region 50, promoting carrier loss and improving switching speed, thereby reducing loss. Meanwhile, the oscillation amplitude can be reduced by selectively providing the lifetime recovery region LTU.

[0136] Note that the transistor region 50 that does not have a lifetime recovery region LTU promotes the injection of holes into the adjacent diode region 60. During the recovery operation of the diode region 60, the smaller the area of ​​the lifetime recovery region LTU provided in the transistor region 50, the more the supply of holes from the transistor region 50 is promoted. This is because the increase in the donor concentration in the third region R3 of the buffer region 100 suppresses the injection of holes from the transistor region 50 into the diode region 60.

[0137] In other words, the smaller the area of ​​the lifetime recovery region LTU, the more it is possible to suppress the voltage oscillation during recovery in the diode region 60. Therefore, it is possible to suppress the sudden loss of carriers in the diode region 60 and reduce the oscillation amplitude.

[0138] Furthermore, the smaller the area of ​​the lifetime recovery region LTU, the shorter the switching time and the lower the switching loss. According to this embodiment, the trade-off between the reduction in oscillation amplitude and the reduction in switching loss can be improved.

[0139] Furthermore, according to this embodiment, the amount of implanted impurities such as protons can be reduced. Compared to forming the lifetime recovery region LTU over the entire transistor region 50, the amount of implanted impurities for recovering the carrier lifetime in the third region R3 can be reduced, and the implantation efficiency can be improved.

[0140] As shown in FIG. 11A, in an example in which two rows of diode regions 60 are formed between adjacent lifetime recovery regions LTU in the X direction, the amount of implantation of protons, etc. can be reduced to 50% compared to when lifetime recovery regions LTU are formed over the entire transistor region 50.

[0141] 11B, among a plurality of diode regions 60 provided in the X direction, portions having lifetime recovery regions LTU may be selectively provided in the XY plane. For example, the diode regions 60 having lifetime recovery regions LTU are periodically arranged. An arrangement may be such that two rows of transistor regions 50 and one row of diode regions 60 between the two rows of transistor regions 50 are formed between the lifetime recovery regions LTU (formed in the diode regions 60) adjacent to each other in the X direction.

[0142] 11B also improves the trade-off between reduced oscillation amplitude and reduced switching loss. In addition, the amount of implanted impurities such as protons can be reduced, improving the implantation efficiency.

[0143] (Fourth embodiment) 12 is a schematic top view of the semiconductor device 4 according to the fourth embodiment. Description of parts common to the semiconductor device 3 according to the third embodiment will be omitted.

[0144] In this embodiment, a plurality of diode regions 60 are formed in a dot pattern spaced apart in the X and Y directions. The diode regions 60 are formed inside the dotted lines shown in Fig. 12. The transistor regions 50 are arranged in a lattice pattern between the diode regions 60 so as to extend in the X and Y directions.

[0145] A plurality of lifetime recovery regions LTU are formed so as to extend in one direction (the Y direction in FIG. 12) in the lattice-shaped transistor region 50. A plurality of lifetime recovery regions LTU are arranged side by side in a direction intersecting the one direction (the X direction in FIG. 12).

[0146] According to the semiconductor device 4 of this embodiment, the amount of impurities injected can be reduced for the diode regions 60 arranged in a dot pattern compared to when a lifetime recovery region LTU is formed over the entire surface of the transistor region 50.

[0147] Furthermore, a lifetime recovery region LTU is not formed in the transistor region 50 adjacent to the diode region 60 in the Y direction, and the injection of holes from the transistor region 50 to the diode region 60 is promoted, which slows down the loss of carriers during recovery in the diode region 60 and reduces the voltage oscillation amplitude.

[0148] (Fifth embodiment) 13 is a schematic top view of a semiconductor device 5 according to the fifth embodiment. Description of parts common to the semiconductor device 4 according to the fourth embodiment will be omitted.

[0149] A lifetime recovery region LTU is selectively formed in a part of the plurality of diode regions 60 arranged in a dot pattern. A plurality of lifetime recovery regions LTU are formed at intervals in the X direction and the Y direction.

[0150] 14 shows an example in which one diode region 60 is formed between adjacent lifetime recovery regions LTU in the X direction and Y direction. Note that two or three diode regions 60 may be formed between adjacent lifetime recovery regions LTU.

[0151] Furthermore, the lifetime recovery region LTU may be provided so as to extend beyond the diode region 60 and reach the transistor region 50. Furthermore, the transistor region 50 does not necessarily need to have the lifetime recovery region LTU.

[0152] The semiconductor device 5 according to this embodiment can improve the trade-off between reduced oscillation amplitude and reduced switching loss.

[0153] In the region of the diode region 60 where the lifetime recovery region LTU is formed, the carrier lifetime is recovered, which slows down the recombination of carriers during recovery of the diode region 60 and reduces the oscillation amplitude of the voltage.

[0154] On the other hand, in the diode region 60 provided between the lifetime recovery regions LTU, the carrier lifetime is not recovered, improving the switching speed and reducing the loss during recovery. Furthermore, the injection of holes from the transistor region 50 adjacent to the diode region 60 is promoted, slowing down the recombination of carriers and reducing the oscillation amplitude of the voltage.

[0155] Furthermore, switching loss at turn-off can be reduced in the portion of the transistor region 50 where the lifetime recovery region LTU is not provided. When the lifetime recovery region LTU protrudes into the transistor region 50 as in the example of Fig. 13, the lifetime is also recovered in a portion of the transistor region 50, suppressing the oscillation amplitude of the voltage waveform at the time of switching.

[0156] According to at least one of the embodiments described above, the buffer region 100 is provided between the drift region 11 of the semiconductor substrate 10 and the first electrode 41, and the third concentration peak 103 is selectively formed in the XY plane, thereby reducing the oscillation amplitude of the voltage waveform during switching. Furthermore, the third carrier lifetime LT3 is preferably 0.1 μs or more and 10 μs or less.

[0157] The embodiments have been described above with reference to specific examples. However, the embodiments are not limited to these specific examples. In other words, designs that are appropriately modified by a person skilled in the art from these specific examples are also included within the scope of the embodiments as long as they have the characteristics of the embodiments. The elements, as well as their arrangement, materials, conditions, shapes, sizes, etc., of the above-mentioned specific examples are not limited to those exemplified and can be modified as appropriate.

[0158] Furthermore, the elements of each of the above-described embodiments can be combined to the extent technically possible, and combinations of these are also included within the scope of the embodiments as long as they include the features of the embodiments. In addition, within the scope of the concept of the embodiments, a person skilled in the art may conceive of various modifications and alterations, and it is understood that these modifications and alterations also fall within the scope of the embodiments.

[0159] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0160] 1, 2, 3, 4, 5, 6... Semiconductor device 10. Semiconductor substrate 10a... First principal surface 10b: Second principal surface 11. Drift region 21...First semiconductor region 22...Second semiconductor region 23. Third semiconductor region 24...Fourth semiconductor region 31 Gate electrode 32. Gate insulating film 41...1st electrode 42...2nd electrode 50 Transistor area 60...Diode area 100...Buffer area 101... First concentration peak 102...Second concentration peak 103...Third concentration peak 104...Fourth concentration peak R1, R2, R3, R4... area LT1, LT2, LT3, LT4, LT5, LT6... Carrier Lifetime

Claims

1. a semiconductor substrate having a first main surface and a second main surface facing the first main surface in a first direction; a drift region provided in the semiconductor substrate; a buffer region provided between the first main surface and the drift region, the buffer region having a plurality of concentration peaks in the first direction, the concentration peaks having an impurity concentration higher than that of the drift region; a first electrode provided on the first main surface; a second electrode provided on the second main surface; a transistor region in which a transistor is formed, the transistor having the first electrode as a collector electrode and the second electrode as an emitter electrode; and The plurality of concentration peaks are a first concentration peak closest to the second major surface; a second concentration peak that is farther from the second main surface than the first concentration peak and has an impurity concentration greater than the impurity concentration of the first concentration peak; a third concentration peak selectively provided between the first principal surface and the second concentration peak in a plane intersecting the first direction; A semiconductor device having:

2. the impurity concentration of the second concentration peak is greater than the impurity concentration of the third concentration peak; The semiconductor device according to claim 1 .

3. The semiconductor device further includes a diode region in which a diode is formed with the first electrode as a cathode electrode and the second electrode as an anode electrode. The semiconductor device according to claim 2 .

4. the number of concentration peaks in the first direction in the transistor region is different from the number of concentration peaks in the first direction in the diode region; The semiconductor device according to claim 3 .

5. the third concentration peak is selectively provided in the transistor region out of the transistor region and the diode region; The semiconductor device according to claim 3 .

6. the third concentration peak is selectively provided in the diode region out of the transistor region and the diode region; The semiconductor device according to claim 3 .

7. the first concentration peak is formed at a depth of 10 μm or more and 30 μm or less measured from the first main surface; The semiconductor device according to claim 1 .

8. The third concentration peak is 1.0×10 １４ cm ―３ Above 1.0 x 10 １７ cm ―３ having the following impurity concentrations: The semiconductor device according to claim 1 .

9. a carrier lifetime of a region of the buffer region including the third concentration peak is 0.001 μs or more and 100 μs or less; The semiconductor device according to claim 1 .

10. a fourth concentration peak closer to the first principal surface than the third concentration peak; the impurity concentration of the fourth concentration peak is greater than the impurity concentration of the third concentration peak; The semiconductor device according to claim 1 .

11. the impurities forming the first concentration peak, the second concentration peak, and the third concentration peak contain protons; the impurities forming the fourth concentration peak include phosphorus; The semiconductor device according to claim 10.

12. a plurality of the transistor regions and a plurality of the diode regions are provided, are aligned in a second direction intersecting the first direction, and extend in a third direction intersecting the first direction and the second direction; a lifetime recovery region in which the third concentration peak is formed is aligned in the second direction and extends in the third direction, and is selectively formed in a part of the plurality of transistor regions; At least two rows of the diode regions are provided between the lifetime recovery regions adjacent to each other in the second direction. The semiconductor device according to claim 3 .

13. the diode regions are provided in a dot pattern spaced apart from each other in a second direction intersecting the first direction and a third direction intersecting the first direction and the second direction, the transistor regions are provided in a lattice pattern between the diode regions, a plurality of lifetime recovery regions in which the third concentration peak is formed are formed in the transistor region, aligned in the second direction and extending in the third direction; The semiconductor device according to claim 3 .

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